SSD1306Z [ETC]
128 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller;
| 型号： | SSD1306Z |
| 厂家： | 
ETC |
| 描述： | 128 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 文件： | 总65页 (文件大小：1839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1306
Advance Information
128 x 64 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without
notice.
http://www.solomon-systech.com
SSD1306
Rev 1.1
P 1/59
Apr 2008
Copyright © 2008 Solomon Systech Limited
CONTENTS
1
GENERAL DESCRIPTION .......................................................................................................6
FEATURES...................................................................................................................................6
ORDERING INFORMATION...................................................................................................6
BLOCK DIAGRAM ....................................................................................................................7
DIE PAD FLOOR PLAN ............................................................................................................8
PIN ARRANGEMENT..............................................................................................................11
2
3
4
5
6
6.1
SSD1306TR1 PIN ASSIGNMENT.......................................................................................................................... 11
7
8
PIN DESCRIPTION ..................................................................................................................13
FUNCTIONAL BLOCK DESCRIPTIONS.............................................................................15
8.1
MCU INTERFACE SELECTION.............................................................................................................................. 15
MCU Parallel 6800-series Interface.......................................................................................................... 15
MCU Parallel 8080-series Interface.......................................................................................................... 16
MCU Serial Interface (4-wire SPI)............................................................................................................ 17
MCU Serial Interface (3-wire SPI)............................................................................................................ 18
MCU I2C Interface..................................................................................................................................... 19
COMMAND DECODER ......................................................................................................................................... 22
OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR..................................................................................... 22
FR SYNCHRONIZATION ....................................................................................................................................... 23
RESET CIRCUIT................................................................................................................................................... 23
SEGMENT DRIVERS / COMMON DRIVERS ............................................................................................................ 24
GRAPHIC DISPLAY DATA RAM (GDDRAM)..................................................................................................... 25
SEG/COM DRIVING BLOCK ............................................................................................................................... 26
POWER ON AND OFF SEQUENCE ........................................................................................................................ 27
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
COMMAND TABLE.................................................................................................................28
9.1
DATA READ / WRITE .......................................................................................................................................... 33
10
COMMAND DESCRIPTIONS .............................................................................................34
10.1 FUNDAMENTAL COMMAND ................................................................................................................................ 34
10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) .................................................34
10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) ................................................34
10.1.3 Set Memory Addressing Mode (20h).......................................................................................................... 34
10.1.4 Set Column Address (21h) ......................................................................................................................... 35
10.1.5 Set Page Address (22h).............................................................................................................................. 36
10.1.6 Set Display Start Line (40h~7Fh) .............................................................................................................. 36
10.1.7 Set Contrast Control for BANK0 (81h)...................................................................................................... 36
10.1.8 Set Segment Re-map (A0h/A1h) ................................................................................................................. 36
10.1.9 Entire Display ON (A4h/A5h).................................................................................................................. 37
10.1.10
10.1.11
10.1.12
10.1.13
10.1.14
10.1.15
10.1.16
10.1.17
10.1.18
10.1.19
Set Normal/Inverse Display (A6h/A7h).................................................................................................. 37
Set Multiplex Ratio (A8h)....................................................................................................................... 37
Set Display ON/OFF (AEh/AFh) ........................................................................................................... 37
Set Page Start Address for Page Addressing Mode (B0h~B7h)............................................................. 37
Set COM Output Scan Direction (C0h/C8h).......................................................................................... 37
Set Display Offset (D3h) ........................................................................................................................ 37
Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)............................................................... 40
Set Pre-charge Period (D9h) ................................................................................................................. 40
Set COM Pins Hardware Configuration (DAh)..................................................................................... 40
Set VCOMH Deselect Level (DBh) ........................................................................................................... 43
Solomon Systech
Apr 2008 P 2/59
Rev 1.1 SSD1306
10.1.20
10.1.21
NOP (E3h) ............................................................................................................................................. 43
Status register Read ............................................................................................................................... 43
10.2 GRAPHIC ACCELERATION COMMAND................................................................................................................. 44
10.2.1 Horizontal Scroll Setup (26h/27h) ............................................................................................................. 44
10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah).....................................................................45
10.2.3 Deactivate Scroll (2Eh).............................................................................................................................. 46
10.2.4 Activate Scroll (2Fh).................................................................................................................................. 46
10.2.5 Set Vertical Scroll Area(A3h) .................................................................................................................... 46
11
MAXIMUM RATINGS..........................................................................................................47
DC CHARACTERISTICS.....................................................................................................48
AC CHARACTERISTICS.....................................................................................................49
APPLICATION EXAMPLE..................................................................................................55
PACKAGE INFORMATION................................................................................................56
12
13
14
15
15.1 SSD1306TR1 DETAIL DIMENSION..................................................................................................................... 56
15.2 SSD1306Z DIE TRAY INFORMATION.................................................................................................................. 58
SSD1306
Rev 1.1
P 3/59
Apr 2008
Solomon Systech
TABLES
TABLE 5-1 : SSD1306Z BUMP DIE PAD COORDINATES...................................................................................................... 10
TABLE 6-1 : SSD1306TR1 PIN ASSIGNMENT TABLE.......................................................................................................... 12
TABLE 7-1 : MCU BUS INTERFACE PIN SELECTION............................................................................................................ 14
TABLE 8-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE ...................................................... 15
TABLE 8-2 : CONTROL PINS OF 6800 INTERFACE................................................................................................................. 15
TABLE 8-3 : CONTROL PINS OF 8080 INTERFACE................................................................................................................. 17
TABLE 8-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE................................................................................................. 17
TABLE 8-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE................................................................................................. 18
TABLE 9-1: COMMAND TABLE ........................................................................................................................................... 28
TABLE 9-2 : READ COMMAND TABLE................................................................................................................................. 33
TABLE 9-3 : ADDRESS INCREMENT TABLE (AUTOMATIC) ................................................................................................... 33
TABLE 10-1 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH NO REMAP.......................................... 38
TABLE 10-2 :EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP ................................................ 39
TABLE 10-3 : COM PINS HARDWARE CONFIGURATION ..................................................................................................... 40
TABLE 11-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS)................................................................................ 47
TABLE 12-1 : DC CHARACTERISTICS.................................................................................................................................. 48
TABLE 13-1 : AC CHARACTERISTICS.................................................................................................................................. 49
TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS......................................................... 50
TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS......................................................... 51
TABLE 13-4 : 4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS ................................................................................ 52
TABLE 13-5 : 3-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS ................................................................................ 53
TABLE 13-6 :I2C INTERFACE TIMING CHARACTERISTICS.................................................................................................... 54
Solomon Systech
Apr 2008 P 4/59
Rev 1.1 SSD1306
FIGURES
FIGURE 4-1 SSD1306 BLOCK DIAGRAM .............................................................................................................................. 7
FIGURE 5-1 : SSD1306Z DIE DRAWING ............................................................................................................................... 8
FIGURE 5-2 : SSD1306Z ALIGNMENT MARK DIMENSIONS .................................................................................................... 9
FIGURE 6-1 : SSD1306TR1 PIN ASSIGNMENT ................................................................................................................. 11
FIGURE 7-1 PIN DESCRIPTION............................................................................................................................................. 13
FIGURE 8-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ....................................................................... 16
FIGURE 8-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE......................................................... 16
FIGURE 8-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE .......................................................... 16
FIGURE 8-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ......................................................... 17
FIGURE 8-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE............................................................................... 18
FIGURE 8-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE............................................................................... 18
FIGURE 8-7 : I2C-BUS DATA FORMAT .................................................................................................................................. 20
FIGURE 8-8 : DEFINITION OF THE START AND STOP CONDITION ......................................................................................... 21
FIGURE 8-9 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION ................................................................................... 21
FIGURE 8-10 : DEFINITION OF THE DATA TRANSFER CONDITION ......................................................................................... 21
FIGURE 8-11 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR .............................................................................. 22
FIGURE 8-12 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES ....................................................................................... 24
FIGURE 8-13 : GDDRAM PAGES STRUCTURE OF SSD1306................................................................................................ 25
FIGURE 8-14 : ENLARGEMENT OF GDDRAM (NO ROW RE-MAPPING AND COLUMN-REMAPPING)...................................... 25
FIGURE 8-15 : IREF CURRENT SETTING BY RESISTOR VALUE ............................................................................................. 26
FIGURE 8-16 : THE POWER ON SEQUENCE.......................................................................................................................... 27
FIGURE 8-17 : THE POWER OFF SEQUENCE ........................................................................................................................ 27
FIGURE 10-1 : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE ..................................................................... 34
FIGURE 10-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETTING IN PAGE ADDRESSING MODE (NO ROW AND COLUMN-
REMAPPING) ............................................................................................................................................................... 34
FIGURE 10-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE ......................................................... 35
FIGURE 10-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE.............................................................. 35
FIGURE 10-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT .............................................................. 36
FIGURE 10-6 :TRANSITION BETWEEN DIFFERENT MODES.................................................................................................... 37
FIGURE 10-7 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY 1 COLUMN................................................................. 44
FIGURE 10-8 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY 1 COLUMN ................................................................... 44
FIGURE 10-9 : HORIZONTAL SCROLLING SETUP EXAMPLE................................................................................................... 44
FIGURE 10-10 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLE.................................................. 45
FIGURE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS...................................................................... 50
FIGURE 13-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS................................................................................ 51
FIGURE 13-3 : 4-WIRE SERIAL INTERFACE CHARACTERISTICS............................................................................................. 52
FIGURE 13-4 : 3-WIRE SERIAL INTERFACE CHARACTERISTICS............................................................................................. 53
FIGURE 13-5 : I2C INTERFACE TIMING CHARACTERISTICS.................................................................................................. 54
FIGURE 14-1 : APPLICATION EXAMPLE OF SSD1306Z ....................................................................................................... 55
FIGURE 15-1 SSD1306TR1 DETAIL DIMENSION ................................................................................................................ 56
FIGURE 15-2 : SSD1306Z DIE TRAY INFORMATION ............................................................................................................ 58
SSD1306
Rev 1.1
P 5/59
Apr 2008
Solomon Systech
1
GENERAL DESCRIPTION
SSD1306 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer light emitting
diode dot-matrix graphic display system. It consists of 128 segments and 64commons. This IC is
designed for Common Cathode type OLED panel.
The SSD1306 embeds with contrast control, display RAM and oscillator, which reduces the number of
external components and power consumption. It has 256-step brightness control. Data/Commands are
sent from general MCU through the hardware selectable 6800/8000 series compatible Parallel Interface,
I2C interface or Serial Peripheral Interface. It is suitable for many compact portable applications, such as
mobile phone sub-display, MP3 player and calculator, etc.
2
FEATURES
•
•
Resolution: 128 x 64 dot matrix panel
Power supply
o
V
DD = 1.65V to 3.3V for IC logic
CC = 7V to 15V for Panel driving
o
V
•
For matrix display
o
o
o
o
OLED driving output voltage, 15V maximum
Segment maximum source current: 100uA
Common maximum sink current: 15mA
256 step contrast brightness current control
•
•
Embedded 128 x 64 bit SRAM display buffer
Pin selectable MCU Interfaces:
o
o
o
8-bit 6800/8080-series parallel interface
3 /4 wire Serial Peripheral Interface
I2C Interface
•
•
•
•
•
•
•
Screen saving continuous scrolling function in both horizontal and vertical direction
RAM write synchronization signal
Programmable Frame Rate and Multiplexing Ratio
Row Re-mapping and Column Re-mapping
On-Chip Oscillator
Chip layout for COG & COF
Wide range of operating temperature: -40°C to 85°C
3
ORDERING INFORMATION
Table 3-1: Ordering Information
Ordering Part Number SEG COM Package Form Reference Remark
o
o
o
o
o
o
Min SEG pad pitch : 47um
Min COM pad pitch : 40um
Die thickness: 300 +/- 25um
35mm film, 4 sprocket hole, Folding TAB
8-bit 80 / 8-bit 68 / SPI / I2C interface
SEG, COM lead pitch 0.1mm x 0.997
=0.0997mm
SSD1306Z
128
104
8
64
48
COG
TAB
SSD1306TR1
11, 56
o
Die thickness: 457 +/- 25um
Solomon Systech
Apr 2008 P 6/59
Rev 1.1 SSD1306
4
BLOCK DIAGRAM
Figure 4-1 SSD1306 Block Diagram
RES#
CS#
D/C#
E (RD#)
R/W#(WR#)
BS2
BS1
BS0
COM62
COM60
|
|
COM2
COM0
D7
D6
D5
D4
D3
D2
D1
D0
SEG0
SEG1
|
|
SEG126
SEG127
VDD
VCC
VSS
VLSS
COM1
COM3
|
|
COM61
COM63
SSD1306
Rev 1.1
P 7/59
Apr 2008
Solomon Systech
5
DIE PAD FLOOR PLAN
Figure 5-1 : SSD1306Z Die Drawing
Pad 1
Die size
6.76mm x 0.86mm
Die thickness
300 +/- 25um
60um
Min I/O pad pitch
Min SEG pad pitch
Min COM pad pitch
47um
40um
Bump height
Nominal 15um
Bump size
Pad 1, 106, 124, 256
80um x 50um
Pad 2-18, 89-105, 107-123, 257-273
25ium x 80um
40um x 89um
31um x 59um
30um x 50um
Pad 19-88
Pad 125-255
Pad 274-281 (TR pads)
Alignment
mark
Position
Size
+ shape
+ shape
(-2973, 0)
(2973, 0)
75um x 75um
75um x 75um
R37.5um, inner 18um
-
Circle
(2466.665, 7.575)
(-2862.35, 144.82)
SSL Logo
(For details dimension please see p.9 )
Note
(1)
Diagram showing the Gold bumps face up.
(2)
(3)
(4)
Coordinates are referenced to center of the chip.
Coordinate units and size of all alignment marks are in um.
All alignment keys do not contain gold
Y
X
SSD1306
Pad 1,2,3,…->281
Gold Bumps face up
Solomon Systech
Apr 2008 P 8/59
Rev 1.1 SSD1306
Figure 5-2 : SSD1306Z alignment mark dimensions
T shape
+ shape
Circle
*All units are in um
SSD1306
Rev 1.1
P 9/59
Apr 2008
Solomon Systech
Table 5-1 : SSD1306Z Bump Die Pad Coordinates
Pad no. Pad Name X-pos
Y-pos
Pad no. Pad Name X-pos
Y-pos
Pad no. Pad Name X-pos Y-pos
Pad no. Pad Name X-pos Y-pos
1
2
NC
-3315
-377.5
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
VCOMH 1875.585 -352.83
161
162
163
164
165
166
167
168
169
170
171
SEG35
1364.5
356
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
SEG114 -2398.5
SEG115 -2445.5
SEG116 -2492.5
SEG117 -2539.5
SEG118 -2586.5
SEG119 -2633.5
SEG120 -2680.5
SEG121 -2727.5
SEG122 -2774.5
SEG123 -2821.5
SEG124 -2868.5
SEG125 -2915.5
SEG126 -2962.5
SEG127 -3009.5
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
VSS
-3084.77 -362.5
VCC
VCC
VLSS
VLSS
VLSS
NC
1967.185 -352.83
2027.185 -352.83
2109.185 -352.83
2169.185 -352.83
2254.185 -352.83
2314.185 -352.83
2374.185 -352.83
2444.77 -362.5
SEG36 1317.5 356
SEG37 1270.5 356
SEG38 1223.5 356
3
4
5
6
7
8
9
10
11
COM49 -3044.77 -362.5
COM50 -3004.77 -362.5
COM51 -2964.77 -362.5
COM52 -2924.77 -362.5
COM53 -2884.77 -362.5
COM54 -2844.77 -362.5
COM55 -2804.77 -362.5
COM56 -2764.77 -362.5
COM57 -2724.77 -362.5
SEG39
SEG40
1176.5
1129.5 356
356
SEG41 1082.5 356
SEG42 1035.5 356
NC
VSS
SEG43
SEG44
SEG45
988.5
941.5
894.5
356
356
356
356
356
356
356
356
356
356
COM31 2484.77 -362.5
COM30 2524.77 -362.5
12
13
14
15
16
17
18
COM58 -2684.77 -362.5
COM59 -2644.77 -362.5
COM60 -2604.77 -362.5
COM61 -2564.77 -362.5
COM62 -2524.77 -362.5
COM63 -2484.77 -362.5
VCOMH -2444.77 -362.5
COM29 2564.77 -362.5
COM28 2604.77 -362.5
COM27 2644.77 -362.5
COM26 2684.77 -362.5
COM25 2724.77 -362.5
COM24 2764.77 -362.5
172
173
174
175
176
177
178
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
847.5
800.5
753.5
706.5
659.5
612.5
565.5
NC
NC
-3056.5
-3315 367.5
COM32
COM33
-3315
-3315
315
275
COM23
2804.77 -362.5
19
20
21
22
23
24
25
NC
C2P
C2P
C2N
C2N
C1P
C1P
-2334.965 -352.83
-2278.265 -352.83
-2218.265 -352.83
-2136.715 -352.83
-2055.465 -352.83
-1995.465 -352.83
-1904.115 -352.83
99
COM22 2844.77 -362.5
179
180
181
182
183
184
185
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
518.5
471.5
424.5
377.5
330.5
283.5
236.5
356
356
356
356
356
356
356
259
260
261
262
263
264
265
COM34
COM35
COM36
COM37
COM38
COM39
COM40
-3315
-3315
-3315
-3315
-3315
-3315
-3315
235
195
155
115
75
100
101
102
103
104
105
COM21
COM20
COM19
COM18
COM17
VSS
2884.77 -362.5
2924.77 -362.5
2964.77 -362.5
3004.77 -362.5
3044.77 -362.5
3084.77 -362.5
35
-5
26
27
28
29
30
C1N
C1N
VBAT
VBAT
-1844.115 -352.83
-1762.865 -352.83
-1679.31 -352.83
-1619.31 -352.83
106
107
108
109
110
NC
3315
3315
3315
3315
3315
-377.5
-325
-285
-245
-205
186
187
188
189
190
SEG60
SEG61
SEG62
SEG63
SEG64
189.5
142.5
95.5
48.5
1.5
356
356
356
356
356
266
267
268
269
270
COM41
COM42
COM43
COM44
COM45
-3315
-3315
-3315
-3315
-3315
-45
-85
-125
-165
-205
COM16
COM15
COM14
COM13
VBREF -1537.51 -352.83
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
BGGND -1477.51 -352.83
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
NC
NC
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
3315
3315
3315
3315
3315
3315
3315
3315
3315
3315
3315
3315
3315
-165
-125
-85
-45
-5
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
NC
-45.5
-92.5
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
271
272
273
COM46
COM47
COM48
-3315
-3315
-3315
-245
-285
-325
VCC
VCC
-1416.01 -352.83
-1356.01 -352.83
-139.5
-186.5
-233.5
-280.5
-327.5
-374.5
-421.5
-468.5
-515.5
-562.5
-609.5
-656.5
-703.5
-750.5
-797.5
-844.5
-891.5
-940
VCOMH -1266.955 -352.83
VCOMH -1206.955 -352.83
Pad no. Pad Name X-pos Y-pos
VLSS
VLSS
VLSS
VSS
VSS
VSS
VDD
VDD
BS0
VSS
BS1
VDD
VDD
BS2
VSS
FR
-1125.155 -352.83
-1043.355 -352.83
-983.355 -352.83
35
75
Pin#
274
275
276
277
278
279
280
281
Pin name X-dir
Y-dir
TR0
TR1
TR2
TR3
VSS
TR4
TR5
TR6
2757.05 114.8
2697.05 114.8
2637.05 114.8
2577.05 114.8
2517.05 114.8
2457.05 114.8
2397.05 114.8
2337.05 114.8
115
155
195
235
275
315
367.5
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
356
-920
-856
-796
-352.83
-352.83
-352.83
-732.645 -352.83
-672.645 -352.83
-595.655 -352.83
-531.955 -352.83
-467.655 -352.83
-403.155 -352.83
-342.555 -352.83
-279.705 -352.83
-215.705 -352.83
-151.955 -352.83
-89.815 -352.83
-25.665 -352.83
38.635 -352.83
109.835 -352.83
182.425 -352.83
246.125 -352.83
310.425 -352.83
373.125 -352.83
457.175 -352.83
517.175 -352.83
609.275 -352.83
692.475 -352.83
765.675 -352.83
828.875 -352.83
890.325 -352.83
951.275 -352.83
1013.315 -352.83
1075.355 -352.83
1137.395 -352.83
1220.735 -352.83
1280.735 -352.83
1362.585 -352.83
1425.285 -352.83
1485.885 -352.83
1553.185 -352.83
1613.185 -352.83
1684.585 -352.83
1744.585 -352.83
3315
3055.5
3009.5
2962.5
2915.5
2868.5
2821.5
2774.5
2727.5
2680.5
2633.5
2586.5
2539.5
2492.5
2445.5
2398.5
2351.5
2304.5
2257.5
2210.5
2163.5
2116.5
2069.5
2022.5
1975.5
1928.5
1881.5
1834.5
1787.5
1740.5
1693.5
1646.5
1599.5
1552.5
1505.5
1458.5
1411.5
SEG84
-988.5
CL
SEG85 -1035.5 356
SEG86 -1082.5 356
SEG87 -1129.5 356
SEG88 -1176.5 356
SEG89 -1223.5 356
SEG90 -1270.5 356
SEG91 -1317.5 356
SEG92 -1364.5 356
SEG93 -1411.5 356
SEG94 -1458.5 356
SEG95 -1505.5 356
SEG96 -1552.5 356
SEG97 -1599.5 356
SEG98 -1646.5 356
SEG99 -1693.5 356
SEG100 -1740.5 356
SEG101 -1787.5 356
SEG102 -1834.5 356
SEG103 -1881.5 356
SEG104 -1928.5 356
SEG105 -1975.5 356
SEG106 -2022.5 356
SEG107 -2069.5 356
SEG108 -2116.5 356
SEG109 -2163.5 356
SEG110 -2210.5 356
SEG111 -2257.5 356
SEG112 -2304.5 356
SEG113 -2351.5 356
VSS
CS#
RES#
D/C#
VSS
R/W#
E
VDD
VDD
D0
D1
D2
D3
VSS
D4
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
D5
D6
D7
VSS
VSS
CLS
VDD
VDD
VDD
VDD
IREF
IREF
VCOMH 1815.585 -352.83
Solomon Systech
Apr 2008 P 10/59
Rev 1.1 SSD1306
6
PIN ARRANGEMENT
6.1 SSD1306TR1 pin assignment
Figure 6-1 : SSD1306TR1 Pin Assignment
Note:
(1) COM sequence (Split) is under command setting: DAh, 12h
SSD1306
Rev 1.1
P 11/59
Apr 2008
Solomon Systech
Table 6-1 : SSD1306TR1 Pin Assignment Table
Pin no.
Pin Name
Pin no.
Pin Name
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
Pin no.
Pin Name
SEG10
SEG9
SEG8
SEG7
1
2
3
4
5
6
NC
81
161
VCC
82
162
VCOMH
IREF
D7
83
84
85
163
164
165
SEG6
SEG5
D6
86
166
7
8
9
D5
D4
D3
D2
D1
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
SEG4
SEG3
SEG2
SEG1
SEG0
NC
NC
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
D0
E/RD#
R/W#
D/C#
RES#
CS#
NC
BS2
BS1
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COM0
COM2
COM4
COM6
COM8
COM10
COM12
COM14
COM16
COM18
COM20
COM22
COM24
COM26
COM28
COM30
COM32
COM34
COM36
COM38
COM40
COM42
COM44
COM46
NC
VSS
NC
NC
NC
COM47
COM45
COM43
COM41
COM39
COM37
COM35
COM33
COM31
COM29
COM27
COM25
COM23
COM21
NC
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
COM19
COM17
COM15
COM13
COM11
COM9
COM7
COM5
COM3
COM1
NC
NC
NC
NC
NC
NC
NC
NC
NC
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
NC
SEG103
SEG102
SEG101
71
72
73
74
75
76
77
78
79
80
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
151
152
153
154
155
156
157
158
159
160
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
Solomon Systech
Apr 2008 P 12/59
Rev 1.1 SSD1306
7
PIN DESCRIPTION
Key:
I = Input
O =Output
NC = Not Connected
Pull LOW= connect to Ground
I/O = Bi-directional (input/output) Pull HIGH= connect to VDD
P = Power pin
Figure 7-1 Pin Description
Pin Name
Type
Description
VDD
P
Power supply pin for core logic operation.
VCC
P
Power supply for panel driving voltage. This is also the most positive power voltage
supply pin.
VSS
P
P
O
This is a ground pin.
VLSS
VCOMH
This is an analog ground pin. It should be connected to VSS externally.
The pin for COM signal deselected voltage level.
A capacitor should be connected between this pin and VSS.
VBAT
P
P
I
Reserved pin. It should be connected to VDD.
BGGND
Reserved pin. It should be connected to ground.
Reserved pin. It should be kept NC.
C1P/C1N
C2P/C2N
VBREF
P
I
Reserved pin. It should be kept NC.
BS[2:0]
IREF
MCU bus interface selection pins. Please refer to Table 7-1 for the details of setting.
I
This is segment output current reference pin.
A resistor should be connected between this pin and VSS to maintain the IREF current at
12.5 uA. Please refer to Figure 8-15 for the details of resistor value.
FR
CL
O
I
This pin outputs RAM write synchronization signal. Proper timing between MCU data
writing and frame display timing can be achieved to prevent tearing effect.
It should be kept NC if it is not used. Please refer to Section 8.4 for details usage.
This is external clock input pin.
When internal clock is enabled (i.e. HIGH in CLS pin), this pin is not used and should be
connected to VSS. When internal clock is disabled (i.e. LOW in CLS pin), this pin is the
external clock source input pin.
CLS
I
This is internal clock enable pin. When it is pulled HIGH (i.e. connect to VDD), internal
clock is enabled. When it is pulled LOW, the internal clock is disabled; an external clock
source must be connected to the CL pin for normal operation.
RES#
CS#
This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is
executed. Keep this pin HIGH (i.e. connect to VDD) during normal operation.
I
I
This pin is the chip select input. (active LOW).
SSD1306
Rev 1.1
P 13/59
Apr 2008
Solomon Systech
Pin Name
Type
Description
D/C#
I
This is Data/Command control pin. When it is pulled HIGH (i.e. connect to VDD), the data
at D[7:0] is treated as data. When it is pulled LOW, the data at D[7:0] will be transferred
to the command register.
In I2C mode, this pin acts as SA0 for slave address selection.
When 3-wire serial interface is selected, this pin must be connected to VSS.
For detail relationship to MCU interface signals, please refer to the Timing Characteristics
Diagrams: Figure 13-1 to Figure 13-5.
E (RD#)
I
I
When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E)
signal. Read/write operation is initiated when this pin is pulled HIGH (i.e. connect to VDD
and the chip is selected.
)
When connecting to an 8080-series microprocessor, this pin receives the Read (RD#)
signal. Read operation is initiated when this pin is pulled LOW and the chip is selected.
When serial or I2C interface is selected, this pin must be connected to VSS.
R/W#(WR#)
This is read / write control input pin connecting to the MCU interface.
When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write
(R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH (i.e.
connect to VDD) and write mode when LOW.
When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write
operation is initiated when this pin is pulled LOW and the chip is selected.
When serial or I2C interface is selected, this pin must be connected to VSS.
D[7:0]
IO
These are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus.
When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will
be the serial data input: SDIN and D2 should be kept NC.
When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in
application and D0 is the serial clock input, SCL.
TR0-TR6
-
Testing reserved pins. It should be kept NC.
SEG0 ~
SEG127
O
These pins provide Segment switch signals to OLED panel. These pins are VSS state when
display is OFF.
COM0 ~
COM63
O
-
These pins provide Common switch signals to OLED panel. They are in high impedance
state when display is OFF.
NC
This is dummy pin. Do not group or short NC pins together.
Table 7-1 : MCU Bus Interface Pin Selection
I2C Interface 6800-parallel 8080-parallel 4-wire Serial
3-wire Serial
interface
SSD1306
Pin Name
interface
(8 bit)
0
interface
(8 bit)
0
interface
0
1
0
1
0
0
BS0
BS1
BS2
0
0
0
0
1
1
1
Note
(1) 0 is connected to VSS
(2) 1 is connected to VDD
Solomon Systech
Apr 2008 P 14/59
Rev 1.1 SSD1306
8
FUNCTIONAL BLOCK DESCRIPTIONS
8.1 MCU Interface selection
SSD1306 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface
mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[2:0] pins
(please refer to Table 7-1 for BS[2:0] setting).
Table 8-1 : MCU interface assignment under different bus interface mode
Pin Name Data/Command Interface
Bus
Control Signal
Interface
8-bit 8080
8-bit 6800
3-wire SPI
4-wire SPI
I2C
D7
D6
D5
D4
D3
D[7:0]
D[7:0]
D2
D1
D0
E
RD#
E
R/W# CS#
WR# CS#
R/W# CS#
D/C#
D/C#
D/C#
Tie LOW RES#
D/C#
SA0
RES#
RES#
RES#
Tie LOW
Tie LOW
Tie LOW
NC
NC
SDIN SCLK Tie LOW
SDIN SCLK Tie LOW
CS#
CS#
RES#
RES#
SDAOUT SDAIN SCL Tie LOW
8.1.1 MCU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#.
A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.
Table 8-2 : Control pins of 6800 interface
Function
E
↓
↓
↓
↓
R/W# CS#
D/C#
L
Write command
Read status
Write data
L
H
L
H
L
L
L
L
L
H
Read data
H
Note
(1) ↓ stands for falling edge of signal
H stands for HIGH in signal
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-1.
SSD1306
Rev 1.1
P 15/59
Apr 2008
Solomon Systech
Figure 8-1 : Data read back procedure - insertion of dummy read
R/W#
E
N
n
n+1
n+2
Databus
Write column
address
Dummy read
Read 1st data
Read 2nd data
Read 3rd data
8.1.2 MCU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
Figure 8-2 : Example of Write procedure in 8080 parallel interface mode
CS#
WR#
D[7:0]
D/C#
high
RD#
low
Figure 8-3 : Example of Read procedure in 8080 parallel interface mode
CS#
RD#
D[7:0]
D/C#
high
WR#
low
Solomon Systech
Apr 2008 P 16/59
Rev 1.1 SSD1306
Table 8-3 : Control pins of 8080 interface
Function
RD#
H
WR#
CS#
L
L
L
L
D/C#
L
L
H
H
Write command
Read status
Write data
Read data
↑
H
↑
H
↑
H
↑
Note
(1) ↑ stands for rising edge of signal
(2)
H stands for HIGH in signal
L stands for LOW in signal
(3)
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-4.
Figure 8-4 : Display data read back procedure - insertion of dummy read
WR#
RD#
Databus
N
n
n+1
n+2
Write column
address
Dummy read
Read 1st data
Read 2nd data
Read 3rd data
8.1.3 MCU Serial Interface (4-wire SPI)
The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode,
D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to
D7, E and R/W# (WR#)# can be connected to an external ground.
Table 8-4 : Control pins of 4-wire Serial interface
Function
Write command Tie LOW
Write data Tie LOW
E(RD#)
R/W#(WR#) CS# D/C# D0
Tie LOW
Tie LOW
L
L
L
↑
↑
H
Note
(1) H stands for HIGH in signal
(2) L stands for LOW in signal
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#
is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data
RAM (GDDRAM) or command register in the same clock.
Under serial mode, only write operations are allowed.
SSD1306
Rev 1.1
P 17/59
Apr 2008
Solomon Systech
Figure 8-5 : Write procedure in 4-wire Serial interface mode
CS#
D/C#
SDIN/
SCLK
DB1
DB2
DBn
SCLK
(D0)
D0
SDIN(D1)
D7
D6
D5
D4
D3
D2
D1
8.1.4
MCU Serial Interface (3-wire SPI)
The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#.
In 3-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open.
The pins from D3 to D7, R/W# (WR#)#, E and D/C# can be connected to an external ground.
The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9-bits will
be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit. The D/C# bit (first
bit of the sequential data) will determine the following data byte in the shift register is written to the Display
Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0). Under serial mode, only write operations
are allowed.
Table 8-5 : Control pins of 3-wire Serial interface
Function
E(RD#)
R/W#(WR#) CS# D/C#
D0
↑
Write command Tie LOW
Tie LOW
Tie LOW
L
L
Tie LOW
Tie LOW
Note
Write data
Tie LOW
↑
(1) L stands for LOW in signal
Figure 8-6 : Write procedure in 3-wire Serial interface mode
CS#
SDIN/
SCLK
DB1
DB2
DBn
SCLK
(D0)
D7
D6
D5
D4
D3
D2
D1
D0
D/C#
SDIN(D1)
Solomon Systech
Apr 2008 P 18/59
Rev 1.1 SSD1306
8.1.5 MCU I2C Interface
The I2C communication interface consists of slave address bit SA0, I2C-bus data signal SDA (SDAOUT/D2 for
output and SDAIN/D1 for input) and I2C-bus clock signal SCL (D0). Both the data and clock signals must be
connected to pull-up resistors. RES# is used for the initialization of device.
a) Slave address bit (SA0)
SSD1306 has to recognize the slave address before transmitting or receiving any information by the
I2C-bus. The device will respond to the slave address following by the slave address bit (“SA0” bit)
and the read/write select bit (“R/W#” bit) with the following byte format,
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1 1 0 SA0 R/W#
“SA0” bit provides an extension bit for the slave address. Either “0111100” or “0111101”, can be
selected as the slave address of SSD1306. D/C# pin acts as SA0 for slave address selection.
“R/W#” bit is used to determine the operation mode of the I2C-bus interface. R/W#=1, it is in read
mode. R/W#=0, it is in write mode.
b) I2C-bus data signal (SDA)
SDA acts as a communication channel between the transmitter and the receiver. The data and the
acknowledgement are sent through the SDA.
It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin becomes
a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid
logic 0 level in “SDA”.
“SDAIN” and “SDAOUT” are tied together and serve as SDA. The “SDAIN” pin must be connected to
act as SDA. The “SDAOUT” pin may be disconnected. When “SDAOUT” pin is disconnected, the
acknowledgement signal will be ignored in the I2C-bus.
c) I2C-bus clock signal (SCL)
The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission of
data bit is taken place during a single clock period of SCL.
SSD1306
Rev 1.1
P 19/59
Apr 2008
Solomon Systech
8.1.5.1 I2C-bus Write data
The I2C-bus interface gives access to write data and command into the device. Please refer to Figure 8-7 for
the write mode of I2C-bus in chronological order.
Figure 8-7 : I2C-bus data format
Note:
Co – Continuation bit
D/C# – Data / Command Selection bit
ACK – Acknowledgement
SA0 – Slave address bit
R/W# – Read / Write Selection bit
S – Start Condition / P – Stop Condition
Write mode
Control byte
Data byte
Control byte
Data byte
0 1 1 1 1 0
n ≥ 0 bytes
MSB ……………….LSB
Slave Address
1 byte
m ≥ 0 words
0 1 1 1 1 0
SSD1306
Slave Address
0 0 0 0 0 0
Control byte
8.1.5.2 Write mode for I2C
1) The master device initiates the data communication by a start condition. The definition of the start
condition is shown in Figure 8-8. The start condition is established by pulling the SDA from HIGH to
LOW while the SCL stays HIGH.
2) The slave address is following the start condition for recognition use. For the SSD1306, the slave
address is either “b0111100” or “b0111101” by changing the SA0 to LOW or HIGH (D/C pin acts as
SA0).
3) The write mode is established by setting the R/W# bit to logic “0”.
4) An acknowledgement signal will be generated after receiving one byte of data, including the slave
address and the R/W# bit. Please refer to the Figure 8-9 for the graphical representation of the
acknowledge signal. The acknowledge bit is defined as the SDA line is pulled down during the HIGH
period of the acknowledgement related clock pulse.
5) After the transmission of the slave address, either the control byte or the data byte may be sent across
the SDA. A control byte mainly consists of Co and D/C# bits following by six “0” ‘s.
a. If the Co bit is set as logic “0”, the transmission of the following information will contain
data bytes only.
b. The D/C# bit determines the next data byte is acted as a command or a data. If the D/C# bit is
set to logic “0”, it defines the following data byte as a command. If the D/C# bit is set to
logic “1”, it defines the following data byte as a data which will be stored at the GDDRAM.
The GDDRAM column address pointer will be increased by one automatically after each
data write.
6) Acknowledge bit will be generated after receiving each control byte or data byte.
7) The write mode will be finished when a stop condition is applied. The stop condition is also defined
in Figure 8-8. The stop condition is established by pulling the “SDA in” from LOW to HIGH while
the “SCL” stays HIGH.
Solomon Systech
Apr 2008 P 20/59
Rev 1.1 SSD1306
Figure 8-8 : Definition of the Start and Stop Condition
tSSTOP
tHSTART
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
Figure 8-9 : Definition of the acknowledgement condition
DATA OUTPUT
BY TRANSMITTER
Non-acknowledge
DATA OUTPUT
BY RECEIVER
Acknowledge
SCL FROM
MASTER
1
2
8
9
S
Clock pulse for acknowledgement
START
Condition
Please be noted that the transmission of the data bit has some limitations.
1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “HIGH”
period of the clock pulse. Please refer to the Figure 8-10 for graphical representations. Except in start or
stop conditions, the data line can be switched only when the SCL is LOW.
2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors.
Figure 8-10 : Definition of the data transfer condition
SDA
SCL
Data line is
stable
Change
of data
SSD1306
Rev 1.1
P 21/59
Apr 2008
Solomon Systech
8.2 Command Decoder
This module determines whether the input data is interpreted as data or command. Data is interpreted based
upon the input of the D/C# pin.
If D/C# pin is HIGH, D[7:0] is interpreted as display data written to Graphic Display Data RAM (GDDRAM).
If it is LOW, the input at D[7:0] is interpreted as a command. Then data input will be decoded and written to
the corresponding command register.
8.3 Oscillator Circuit and Display Time Generator
Figure 8-11 : Oscillator Circuit and Display Time Generator
Internal
Oscillator
Fosc
M
U
X
CLK
DCLK
Divider
Display
Clock
CL
CLS
This module is an on-chip LOW power RC oscillator circuitry. The operation clock (CLK) can be generated
either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is
pulled HIGH, internal oscillator is chosen and CL should be left open. Pulling CLS pin LOW disables
internal oscillator and external clock must be connected to CL pins for proper operation. When the internal
oscillator is selected, its output frequency Fosc can be changed by command D5h A[7:4].
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D”
can be programmed from 1 to 16 by command D5h
DCLK = FOSC / D
The frame frequency of display is determined by the following formula.
Fosc
FFRM
=
D× K × No.of Mux
where
•
D stands for clock divide ratio. It is set by command D5h A[3:0]. The divide ratio has the range from 1 to
16.
•
K is the number of display clocks per row. The value is derived by
K = Phase 1 period + Phase 2 period + BANK0 pulse width
= 2 + 2 + 50 = 54 at power on reset
(Please refer to Section 8.6 “Segment Drivers / Common Drivers” for the details of the “Phase”)
Number of multiplex ratio is set by command A8h. The power on reset value is 63 (i.e. 64MUX).
FOSC is the oscillator frequency. It can be changed by command D5h A[7:4]. The higher the register
setting results in higher frequency.
•
•
Solomon Systech
Apr 2008 P 22/59
Rev 1.1 SSD1306
8.4 FR synchronization
FR synchronization signal can be used to prevent tearing effect.
One frame
FR
100%
Memory
Access
Process
0%
Time
Fast write MCU
Slow write MCU
SSD1306 displaying memory updates to OLED screen
The starting time to write a new image to OLED driver is depended on the MCU writing speed. If MCU can
finish writing a frame image within one frame period, it is classified as fast write MCU. For MCU needs
longer writing time to complete (more than one frame but within two frames), it is a slow write one.
For fast write MCU: MCU should start to write new frame of ram data just after rising edge of FR pulse and
should be finished well before the rising edge of the next FR pulse.
For slow write MCU: MCU should start to write new frame ram data after the falling edge of the 1st FR
pulse and must be finished before the rising edge of the 3rd FR pulse.
8.5 Reset Circuit
When RES# input is LOW, the chip is initialized with the following status:
1. Display is OFF
2. 128 x 64 Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 mapped to
address 00h and COM0 mapped to address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 7Fh
9. Normal display mode (Equivalent to A4h command)
SSD1306
Rev 1.1
P 23/59
Apr 2008
Solomon Systech
8.6 Segment Drivers / Common Drivers
Segment drivers deliver 128 current sources to drive the OLED panel. The driving current can be adjusted
from 0 to 100uA with 256 steps. Common drivers generate voltage-scanning pulses.
The segment driving waveform is divided into three phases:
1. In phase 1, the OLED pixel charges of previous image are discharged in order to prepare for next
image content display.
2. In phase 2, the OLED pixel is driven to the targeted voltage. The pixel is driven to attain the
corresponding voltage level from VSS. The period of phase 2 can be programmed in length from 1 to
15 DCLKs. If the capacitance value of the pixel of OLED panel is larger, a longer period is required
to charge up the capacitor to reach the desired voltage.
3. In phase 3, the OLED driver switches to use current source to drive the OLED pixels and this is the
current drive stage.
Figure 8-12 : Segment Output Waveform in three phases
Segment
VSS
Time
Phase: 1 2
3
After finishing phase 3, the driver IC will go back to phase 1 to display the next row image data. This three-
step cycle is run continuously to refresh image display on OLED panel.
In phase 3, if the length of current drive pulse width is set to 50, after finishing 50 DCLKs in current drive
phase, the driver IC will go back to phase 1 for next row display.
Solomon Systech
Apr 2008 P 24/59
Rev 1.1 SSD1306
8.7 Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
128 x 64 bits and the RAM is divided into eight pages, from PAGE0 to PAGE7, which are used for
monochrome 128x64 dot matrix display, as shown in Figure 8-13.
Figure 8-13 : GDDRAM pages structure of SSD1306
Row re-mapping
PAGE0 (COM0-COM7)
PAGE1 (COM8-COM15)
PAGE2 (COM16-COM23)
PAGE3 (COM24-COM31)
PAGE4 (COM32-COM39)
PAGE5 (COM40-COM47)
PAGE6 (COM48–COM55)
PAGE7 (COM56-COM63)
PAGE0 (COM 63-COM56)
PAGE1 (COM 55-COM48)
PAGE2 (COM47-COM40)
PAGE3 (COM39-COM32)
PAGE4 (COM31-COM24)
PAGE5 (COM23-COM16)
PAGE6 (COM15-COM8)
PAGE7 (COM 7-COM0)
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
SEG0 ---------------------------------------------SEG127
SEG127 ---------------------------------------------SEG0
Column re-mapping
When one data byte is written into GDDRAM, all the rows image data of the same page of the current
column are filled (i.e. the whole column (8 bits) pointed by the column address pointer is filled.). Data bit D0
is written into the top row, while data bit D7 is written into bottom row as shown in Figure 8-14.
Figure 8-14 : Enlargement of GDDRAM (No row re-mapping and column-remapping)
....................
COM16
COM17
LSB D0
:
:
:
:
:
PAGE2
....................
COM23
MSB D7
Each box represents one bit of image data
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software as
shown in Figure 8-13.
For vertical shifting of the display, an internal register storing the display start line can be set to control the
portion of the RAM data to be mapped to the display (command D3h).
SSD1306
Rev 1.1
P 25/59
Apr 2008
Solomon Systech
8.8 SEG/COM Driving block
This block is used to derive the incoming power sources into the different levels of internal use voltage and
current.
•
•
•
•
VCC is the most positive voltage supply.
V
V
COMH is the Common deselected level. It is internally regulated.
LSS is the ground path of the analog and panel current.
I
REF is a reference current source for segment current drivers ISEG. The relationship between reference
current and segment current of a color is:
I
SEG = Contrast / 256 x IREF x scale factor
in which
the contrast (0~255) is set by Set Contrast command 81h; and
the scale factor is 8 by default.
The magnitude of IREF is controlled by the value of resistor, which is connected between IREF pin and
VSS as shown in Figure 8-15. It is recommended to set IREF to 12.5 ± 2uA so as to achieve ISEG
100uA at maximum contrast 255.
=
Figure 8-15 : IREF Current Setting by Resistor Value
SSD1306
I
REF (voltage at
IREF ~ 12.5uA
R1
this pin =
VCC – 2.5)
VSS
Since the voltage at IREF pin is VCC – 2.5V, the value of resistor R1 can be found as below:
For IREF = 12.5uA, VCC =12V:
R1 = (Voltage at IREF – VSS) / IREF
= (12 – 2.5) / 12.5uA
= 760KΩ
Solomon Systech
Apr 2008 P 26/59
Rev 1.1 SSD1306
8.9 Power ON and OFF sequence
The following figures illustrate the recommended power ON and power OFF sequence of SSD1306
Power ON sequence:
1. Power ON VDD
2. After VDD become stable, set RES# pin LOW (logic low) for at least 3us (t1) (4) and then HIGH (logic
high).
(1)
3. After set RES# pin LOW (logic low), wait for at least 3us (t2). Then Power ON VCC.
4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 100ms
(tAF).
Figure 8-16 : The Power ON sequence
ON VCC Send AFh command for Display ON
ON VDD RES#
VDD
OFF
t1
RES#
GND
t2
VCC
OFF
tAF
ON
SEG/COM
OFF
Power OFF sequence:
1. Send command AEh for display OFF.
(1), (2), (3)
2. Power OFF VCC.
3. Power OFF VDD after tOFF
.
(5) (Typical tOFF=100ms)
Figure 8-17 : The Power OFF sequence
Send command AEh for display OFF OFF VCC
VCC
OFF VDD
OFF
tOFF
VDD
OFF
Note:
(1) Since an ESD protection circuit is connected between VDD and VCC, VCC becomes lower than VDD whenever VDD is
ON and VCC is OFF as shown in the dotted line of VCC in Figure 8-16 and Figure 8-17.
(2)
V
should be kept float (i.e. disable) when it is OFF.
CC
(3) Power Pins (VDD , VCC) can never be pulled to ground under any circumstance.
(4) The register values are reset after t1.
(5)
V
should not be Power OFF before VCC Power OFF.
DD
SSD1306
Rev 1.1
P 27/59
Apr 2008
Solomon Systech
9
COMMAND TABLE
Table 9-1: Command Table
(D/C#=0, R/W#(WR#) = 0, E(RD#=1) unless specific setting is stated)
1. Fundamental Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
0
81
1
0
0
0
0
0
0
1
Set Contrast Control Double byte command to select 1 out of 256
contrast steps. Contrast increases as the value
increases.
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
(RESET = 7Fh )
A4h, X0=0b: Resume to RAM content display
(RESET)
0
0
A4/A5
A6/A7
1
1
0
0
1
1
0
0
0
0
1
1
0
1
X0 Entire Display ON
Output follows RAM content
A5h, X0=1b: Entire display ON
Output ignores RAM content
A6h, X[0]=0b: Normal display (RESET)
0 in RAM: OFF in display panel
1 in RAM: ON in display panel
A7h, X[0]=1b: Inverse display
0 in RAM: ON in display panel
1 in RAM: OFF in display panel
AEh, X[0]=0b:Display OFF (sleep mode)
(RESET)
X0 Set Normal/Inverse
Display
0
AE
AF
1
0
1
0
1
1
1
X0 Set Display ON/OFF
AFh X[0]=1b:Display ON in normal mode
2. Scrolling Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
26h, X[0]=0, Right Horizontal Scroll
27h, X[0]=1, Left Horizontal Scroll
(Horizontal scroll by 1 column)
A[7:0] : Dummy byte (Set as 00h)
B[2:0] : Define start page address
0
0
0
0
0
0
0
26/27
0
0
*
*
*
0
1
0
0
*
*
*
0
1
1
0
*
*
*
0
1
0
0
*
*
*
0
1
0
0
*
*
*
0
1
1
0
B2
C2
D2
0
1
0
B1
C1
D1
0
X0 Continuous
Horizontal Scroll
Setup
A[7:0]
B[2:0]
C[2:0]
D[2:0]
E[7:0]
F[7:0]
0
B0
C0
D0
0
000b – PAGE0 011b – PAGE3 110b – PAGE6
001b – PAGE1 100b – PAGE4 111b – PAGE7
010b – PAGE2 101b – PAGE5
1
1
1
C[2:0] : Set time interval between each scroll step in
terms of frame frequency
000b – 5 frames
001b – 64 frames
010b – 128 frames
011b – 256 frames
100b – 3 frames
101b – 4 frames
110b – 25 frame
111b – 2 frame
D[2:0] : Define end page address
000b – PAGE0 011b – PAGE3 110b – PAGE6
001b – PAGE1 100b – PAGE4 111b – PAGE7
010b – PAGE2 101b – PAGE5
The value of D[2:0] must be larger or equal
to B[2:0]
E[7:0] : Dummy byte (Set as 00h)
F[7:0] : Dummy byte (Set as FFh)
Solomon Systech
Apr 2008 P 28/59
Rev 1.1 SSD1306
2. Scrolling Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
0
0
0
0
0
29/2A
A[2:0]
B[2:0]
C[2:0]
D[2:0]
E[5:0]
0
0
*
*
*
*
0
0
*
*
*
*
1
0
*
*
*
0
0
*
*
*
1
0
*
*
*
0
0
B2
C2
D2
E2
X1
0
B1
C1
D1
E1
X0 Continuous
29h, X1X0=01b : Vertical and Right Horizontal Scroll
2Ah, X1X0=10b : Vertical and Left Horizontal Scroll
Vertical and
0
Horizontal Scroll (Horizontal scroll by 1 column)
Setup
B0
C0
D0
E0
A[7:0] : Dummy byte
B[2:0] : Define start page address
E5 E4 E3
000b – PAGE0 011b – PAGE3 110b – PAGE6
001b – PAGE1 100b – PAGE4 111b – PAGE7
010b – PAGE2 101b – PAGE5
C[2:0] : Set time interval between each scroll step in
terms of frame frequency
000b – 5 frames
001b – 64 frames
010b – 128 frames
011b – 256 frames
100b – 3 frames
101b – 4 frames
110b – 25 frame
111b – 2 frame
D[2:0] : Define end page address
000b – PAGE0 011b – PAGE3 110b – PAGE6
001b – PAGE1 100b – PAGE4 111b – PAGE7
010b – PAGE2 101b – PAGE5
The value of D[2:0] must be larger or equal
to B[2:0]
E[5:0] : Vertical scrolling offset
e.g. E[5:0]= 01h refer to offset =1 row
E[5:0] =3Fh refer to offset =63 rows
Note
(1)
No continuous vertical scrolling is available.
0
0
2E
2F
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
1
Deactivate scroll Stop scrolling that is configured by command
26h/27h/29h/2Ah.
Note
(1)
After sending 2Eh command to deactivate the scrolling
action, the ram data needs to be rewritten.
Activate scroll
Start scrolling that is configured by the scrolling setup
commands :26h/27h/29h/2Ah with the following valid
sequences:
Valid command sequence 1: 26h ;2Fh.
Valid command sequence 2: 27h ;2Fh.
Valid command sequence 3: 29h ;2Fh.
Valid command sequence 4: 2Ah ;2Fh.
For example, if “26h; 2Ah; 2Fh.” commands are
issued, the setting in the last scrolling setup command,
i.e. 2Ah in this case, will be executed. In other words,
setting in the last scrolling setup command overwrites
the setting in the previous scrolling setup commands.
SSD1306
Rev 1.1
P 29/59
Apr 2008
Solomon Systech
2. Scrolling Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
0
0
A3
A[5:0]
B[6:0]
1
*
*
0
*
1
0
0
0
A2
B2
1
A1
B1
1
A0
B0
Set Vertical ScrollA[5:0] : Set No. of rows in top fixed area. The No. of
Area
A5 A4 A3
rows in top fixed area is referenced to the
B6 B5 B4 B3
top of the GDDRAM (i.e. row 0).[RESET =
0]
B[6:0] : Set No. of rows in scroll area. This is the
number of rows to be used for vertical
scrolling. The scroll area starts in the first
row below the top fixed area. [RESET = 64]
Note
(1) A[5:0]+B[6:0] <= MUX ratio
(2)
B[6:0] <= MUX ratio
(3a) Vertical scrolling offset (E[5:0] in 29h/2Ah) <
B[6:0]
(3b) Set Display Start Line (X5X4X3X2X1X0 of
40h~7Fh) < B[6:0]
(4) The last row of the scroll area shifts to the first row
of the scroll area.
(5) For 64d MUX display
A[5:0] = 0, B[6:0]=64 : whole area scrolls
A[5:0]= 0, B[6:0] < 64 : top area scrolls
A[5:0] + B[6:0] < 64 : central area scrolls
A[5:0] + B[6:0] = 64 : bottom area scrolls
3. Addressing Setting Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
00~0F
0
0
0
0
X3 X2 X1 X0 Set Lower Column Set the lower nibble of the column start address
Start Address for
Page Addressing
Mode
register for Page Addressing Mode using X[3:0]
as data bits. The initial display line register is
reset to 0000b after RESET.
Note
(1) This command is only for page addressing mode
0
10~1F
0
0
0
1
X3 X2 X1 X0 Set Higher Column Set the higher nibble of the column start address
Start Address for
Page Addressing
Mode
register for Page Addressing Mode using X[3:0]
as data bits. The initial display line register is
reset to 0000b after RESET.
Note
(1) This command is only for page addressing mode
0
0
20
A[1:0]
0
*
0
*
1
*
0
*
0
*
0
*
0
0
Set Memory
A[1:0] = 00b, Horizontal Addressing Mode
A[1:0] = 01b, Vertical Addressing Mode
A[1:0] = 10b, Page Addressing Mode (RESET)
A[1:0] = 11b, Invalid
Addressing Mode
A1 A0
0
0
0
21
A[6:0]
B[6:0]
0
*
*
0
1
0
0
0
0
1
Set Column Address Setup column start and end address
A[6:0] : Column start address, range : 0-127d,
(RESET=0d)
A6 A5 A4 A3 A2 A1 A0
B6 B5 B4 B3 B2 B1 B0
B[6:0]: Column end address, range : 0-127d,
(RESET =127d)
Note
(1) This command is only for horizontal or vertical
addressing mode.
Solomon Systech
Apr 2008 P 30/59
Rev 1.1 SSD1306
3. Addressing Setting Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
0
0
22
A[2:0]
B[2:0]
0
*
*
0
*
*
1
*
*
0
*
*
0
*
*
0
1
0
Set Page Address
Setup page start and end address
A[2:0] : Page start Address, range : 0-7d,
(RESET = 0d)
B[2:0] : Page end Address, range : 0-7d,
(RESET = 7d)
A2 A1 A0
B2 B1 B0
Note
(1) This command is only for horizontal or vertical
addressing mode.
0
B0~B7
1
0
1
1
0
X2 X1 X0 Set Page Start
Address for Page
Set GDDRAM Page Start Address
(PAGE0~PAGE7) for Page Addressing Mode
using X[2:0].
Addressing Mode
Note
(1) This command is only for page addressing mode
4. Hardware Configuration (Panel resolution & layout related) Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
40~7F
0
1
X5 X4 X3 X2 X1 X0 Set Display Start LineSet display RAM display start line register from
0-63 using X5X3X2X1X0.
Display start line register is reset to 000000b
during RESET.
0
A0/A1
1
0
1
1
0
0
0
1
0
0
0
0
X0 Set Segment Re-map A0h, X[0]=0b: column address 0 is mapped to
SEG0 (RESET)
A1h, X[0]=1b: column address 127 is mapped to
SEG0
0
0
A8
A[5:0]
1
*
0
*
0
Set Multiplex Ratio Set MUX ratio to N+1 MUX
N=A[5:0] : from 16MUX to 64MUX, RESET=
A5 A4 A3 A2 A1 A0
111111b (i.e. 63d, 64MUX)
A[5:0] from 0 to 14 are invalid entry.
0
C0/C8
1
1
0
0
X3
0
0
0
Set COM Output
Scan Direction
C0h, X[3]=0b: normal mode (RESET) Scan from
COM0 to COM[N –1]
C8h, X[3]=1b: remapped mode. Scan from
COM[N-1] to COM0
Where N is the Multiplex ratio.
0
0
D3
A[5:0]
1
*
1
*
0
1
0
0
1
1
Set Display Offset
Set vertical shift by COM from 0d~63d
The value is reset to 00h after RESET.
A5 A4 A3 A2 A1 A0
0
0
DA
A[5:4]
1
0
1
0
0
1
1
0
0
0
1
1
0
0
Set COM Pins
Hardware
Configuration
A[4]=0b, Sequential COM pin configuration
A[4]=1b(RESET), Alternative COM pin
configuration
A5 A4
A[5]=0b(RESET), Disable COM Left/Right
remap
A[5]=1b, Enable COM Left/Right remap
SSD1306
Rev 1.1
P 31/59
Apr 2008
Solomon Systech
5. Timing & Driving Scheme Setting Command Table
D/C#Hex D7 D6 D5 D4 D3 D2 D1 D0 Command
Description
0
0
D5
1
1
0
1
0
1
0
1
Set Display Clock
Divide
Ratio/Oscillator
Frequency
A[3:0] : Define the divide ratio (D) of the
display clocks (DCLK):
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
Divide ratio= A[3:0] + 1, RESET is
0000b (divide ratio = 1)
A[7:4] : Set the Oscillator Frequency, FOSC
.
Oscillator Frequency increases with
the value of A[7:4] and vice versa.
RESET is 1000b
Range:0000b~1111b
Frequency increases as setting value
increases.
0
0
D9
1
1
0
1
1
0
0
1
Set Pre-charge Period A[3:0] : Phase 1 period of up to 15 DCLK
clocks 0 is invalid entry
(RESET=2h)
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
A[7:4] : Phase 2 period of up to 15 DCLK
clocks 0 is invalid entry
(RESET=2h )
Hex
code
00h
20h
30h
0
0
DB
1
0
1
0
1
1
0
0
0
1
0
1
0
Set VCOMH Deselect
Level
A[6:4]
V COMH deselect level
A[6:4]
A6 A5 A4
000b
010b
011b
~ 0.65 x VCC
~ 0.77 x VCC (RESET)
~ 0.83 x VCC
0
E3
1
1
1
0
0
0
1
1
NOP
Command for no operation
Note
(1) “*” stands for “Don’t care”.
Solomon Systech
Apr 2008 P 32/59
Rev 1.1 SSD1306
Table 9-2 : Read Command Table
Description
Bit Pattern
Command
D7D6D5D4D3D2D1D0
D[7] : Reserved
Status Register Read
D[6] : “1” for display OFF / “0” for display ON
D[5] : Reserved
D[4]
D[3]
D[2]
D[1]
D[0]
Reserved
Reserved
Reserved
Reserved
Reserved
:
:
:
:
:
Note
(1) Patterns other than those given in the Command Table are prohibited to enter the chip as a command; as unexpected
results can occur.
9.1 Data Read / Write
To read data from the GDDRAM, select HIGH for both the R/W# (WR#) pin and the D/C# pin for 6800-
series parallel mode and select LOW for the E (RD#) pin and HIGH for the D/C# pin for 8080-series parallel
mode. No data read is provided in serial mode operation.
In normal data read mode the GDDRAM column address pointer will be increased automatically by one after
each data read.
Also, a dummy read is required before the first data read.
To write data to the GDDRAM, select LOW for the R/W# (WR#) pin and HIGH for the D/C# pin for both
6800-series parallel mode and 8080-series parallel mode. The serial interface mode is always in write mode.
The GDDRAM column address pointer will be increased automatically by one after each data write.
Table 9-3 : Address increment table (Automatic)
D/C#
R/W# (WR#)
Comment
Address Increment
0
0
1
1
0
1
0
1
Write Command
Read Status
Write Data
No
No
Yes
Yes
Read Data
SSD1306
Rev 1.1
P 33/59
Apr 2008
Solomon Systech
10 COMMAND DESCRIPTIONS
10.1 Fundamental Command
10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh)
This command specifies the lower nibble of the 8-bit column start address for the display data RAM under
Page Addressing Mode. The column address will be incremented by each data access. Please refer to Section
Table 9-1 and Section 10.1.3 for details.
10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh)
This command specifies the higher nibble of the 8-bit column start address for the display data RAM under
Page Addressing Mode. The column address will be incremented by each data access. Please refer to Section
Table 9-1 and Section 10.1.3 for details.
10.1.3 Set Memory Addressing Mode (20h)
There are 3 different memory addressing mode in SSD1306: page addressing mode, horizontal addressing
mode and vertical addressing mode. This command sets the way of memory addressing into one of the above
three modes. In there, “COL” means the graphic display data RAM column.
Page addressing mode (A[1:0]=10xb)
In page addressing mode, after the display RAM is read/written, the column address pointer is increased
automatically by 1. If the column address pointer reaches column end address, the column address pointer is
reset to column start address and page address pointer is not changed. Users have to set the new page and
column addresses in order to access the next page RAM content. The sequence of movement of the PAGE
and column address point for page addressing mode is shown in Figure 10-1.
Figure 10-1 : Address Pointer Movement of Page addressing mode
COL0
:
COL 1
:
…..
:
COL 126 COL 127
PAGE0
PAGE1
:
:
:
PAGE6
PAGE7
In normal display data RAM read or write and page addressing mode, the following steps are required to
define the starting RAM access pointer location:
•
•
•
Set the page start address of the target display location by command B0h to B7h.
Set the lower start column address of pointer by command 00h~0Fh.
Set the upper start column address of pointer by command 10h~1Fh.
For example, if the page address is set to B2h, lower column address is 03h and upper column address is 10h,
then that means the starting column is SEG3 of PAGE2. The RAM access pointer is located as shown in
Figure 10-2. The input data byte will be written into RAM position of column 3.
Figure 10-2 : Example of GDDRAM access pointer setting in Page Addressing Mode (No row and column-
remapping)
SEG0
SEG3 (Starting column)
RAM access pointer
SEG127
COM16
COM17
LSB D0
MSB D7
Each lattice represents
one bit of image data
:
:
:
:
PAGE2
(Starting page)
....................
:
COM23
Solomon Systech
Apr 2008 P 34/59
Rev 1.1 SSD1306
Horizontal addressing mode (A[1:0]=00b)
In horizontal addressing mode, after the display RAM is read/written, the column address pointer is increased
automatically by 1. If the column address pointer reaches column end address, the column address pointer is
reset to column start address and page address pointer is increased by 1. The sequence of movement of the
page and column address point for horizontal addressing mode is shown in Figure 10-3. When both column
and page address pointers reach the end address, the pointers are reset to column start address and page start
address (Dotted line in Figure 10-3.)
Figure 10-3 : Address Pointer Movement of Horizontal addressing mode
COL0
COL 1
…..
COL 126 COL 127
PAGE0
PAGE1
:
:
:
:
:
:
PAGE6
PAGE7
Vertical addressing mode: (A[1:0]=01b)
In vertical addressing mode, after the display RAM is read/written, the page address pointer is increased
automatically by 1. If the page address pointer reaches the page end address, the page address pointer is reset
to page start address and column address pointer is increased by 1. The sequence of movement of the page
and column address point for vertical addressing mode is shown in Figure 10-4. When both column and page
address pointers reach the end address, the pointers are reset to column start address and page start address
(Dotted line in Figure 10-4.)
Figure 10-4 : Address Pointer Movement of Vertical addressing mode
COL0
COL 1
…..
…..
…..
:
COL 126 COL 127
PAGE0
PAGE1
:
PAGE6
PAGE7
…..
…..
In normal display data RAM read or write and horizontal / vertical addressing mode, the following steps are
required to define the RAM access pointer location:
•
•
Set the column start and end address of the target display location by command 21h.
Set the page start and end address of the target display location by command 22h.
Example is shown in Figure 10-5.
10.1.4 Set Column Address (21h)
This triple byte command specifies column start address and end address of the display data RAM. This
command also sets the column address pointer to column start address. This pointer is used to define the
current read/write column address in graphic display data RAM. If horizontal address increment mode is
enabled by command 20h, after finishing read/write one column data, it is incremented automatically to the
next column address. Whenever the column address pointer finishes accessing the end column address, it is
reset back to start column address and the row address is incremented to the next row.
SSD1306
Rev 1.1
P 35/59
Apr 2008
Solomon Systech
10.1.5 Set Page Address (22h)
This triple byte command specifies page start address and end address of the display data RAM. This
command also sets the page address pointer to page start address. This pointer is used to define the current
read/write page address in graphic display data RAM. If vertical address increment mode is enabled by
command 20h, after finishing read/write one page data, it is incremented automatically to the next page
address. Whenever the page address pointer finishes accessing the end page address, it is reset back to start
page address.
The figure below shows the way of column and page address pointer movement through the example: column
start address is set to 2 and column end address is set to 125, page start address is set to 1 and page end
address is set to 6; Horizontal address increment mode is enabled by command 20h. In this case, the graphic
display data RAM column accessible range is from column 2 to column 125 and from page 1 to page 6 only.
In addition, the column address pointer is set to 2 and page address pointer is set to 1. After finishing
read/write one pixel of data, the column address is increased automatically by 1 to access the next RAM
location for next read/write operation (solid line in Figure 10-5). Whenever the column address pointer
finishes accessing the end column 125, it is reset back to column 2 and page address is automatically
increased by 1 (solid line in Figure 10-5). While the end page 6 and end column 125 RAM location is
accessed, the page address is reset back to 1 and the column address is reset back to 2 (dotted line in Figure
10-5). .
Figure 10-5 : Example of Column and Row Address Pointer Movement
Col 0
Col 1
Col 2
…..
……. Col 125 Col 126 Col 127
PAGE0
PAGE1
:
:
:
PAGE6
PAGE7
10.1.6 Set Display Start Line (40h~7Fh)
This command sets the Display Start Line register to determine starting address of display RAM, by selecting
a value from 0 to 63. With value equal to 0, RAM row 0 is mapped to COM0. With value equal to 1, RAM
row 1 is mapped to COM0 and so on.
Refer to Table 10-1 for more illustrations.
10.1.7 Set Contrast Control for BANK0 (81h)
This command sets the Contrast Setting of the display. The chip has 256 contrast steps from 00h to FFh. The
segment output current increases as the contrast step value increases.
10.1.8 Set Segment Re-map (A0h/A1h)
This command changes the mapping between the display data column address and the segment driver. It
allows flexibility in OLED module design. Please refer to Table 9-1.
This command only affects subsequent data input. Data already stored in GDDRAM will have no changes.
Solomon Systech
Apr 2008 P 36/59
Rev 1.1 SSD1306
10.1.9 Entire Display ON (A4h/A5h)
A4h command enable display outputs according to the GDDRAM contents.
If A5h command is issued, then by using A4h command, the display will resume to the GDDRAM contents.
In other words, A4h command resumes the display from entire display “ON” stage.
A5h command forces the entire display to be “ON”, regardless of the contents of the display data RAM.
10.1.10 Set Normal/Inverse Display (A6h/A7h)
This command sets the display to be either normal or inverse. In normal display a RAM data of 1 indicates an
“ON” pixel while in inverse display a RAM data of 0 indicates an “ON” pixel.
10.1.11 Set Multiplex Ratio (A8h)
This command switches the default 63 multiplex mode to any multiplex ratio, ranging from 16 to 63. The
output pads COM0~COM63 will be switched to the corresponding COM signal.
10.1.12 Set Display ON/OFF (AEh/AFh)
These single byte commands are used to turn the OLED panel display ON or OFF.
When the display is ON, the selected circuits by Set Master Configuration command will be turned ON.
When the display is OFF, those circuits will be turned OFF and the segment and common output are in VSS
state and high impedance state, respectively. These commands set the display to one of the two states:
o
o
AEh : Display OFF
AFh : Display ON
Figure 10-6 :Transition between different modes
AFh
Normal mode
Sleep mode
AEh
10.1.13 Set Page Start Address for Page Addressing Mode (B0h~B7h)
This command positions the page start address from 0 to 7 in GDDRAM under Page Addressing Mode.
Please refer to Table 9-1 and Section 10.1.3 for details.
10.1.14 Set COM Output Scan Direction (C0h/C8h)
This command sets the scan direction of the COM output, allowing layout flexibility in the OLED module
design. Additionally, the display will show once this command is issued. For example, if this command is
sent during normal display then the graphic display will be vertically flipped immediately. Please refer to
Table 10-3 for details.
10.1.15 Set Display Offset (D3h)
This is a double byte command. The second command specifies the mapping of the display start line to one of
COM0~COM63 (assuming that COM0 is the display start line then the display start line register is equal to 0).
For example, to move the COM16 towards the COM0 direction by 16 lines the 6-bit data in the second byte
should be given as 010000b. To move in the opposite direction by 16 lines the 6-bit data should be given by
64 – 16, so the second byte would be 100000b. The following two tables (Table 10-1, Table 10-2) show the
example of setting the command C0h/C8h and D3h.
SSD1306
Rev 1.1
P 37/59
Apr 2008
Solomon Systech
Table 10-1 : Example of Set Display Offset and Display Start Line with no Remap
Output
64
64
64
56
56
56
Set MUX ratio(A8h)
Normal
0
0
Normal
8
0
Normal
0
8
Normal
0
0
Normal
8
0
Normal
0
8
COM Normal / Remapped (C0h / C8h)
Display offset (D3h)
Display start line (40h - 7Fh)
Hardware
pin name
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
Row0
RAM0
RAM1
RAM2
RAM3
RAM4
RAM5
RAM6
RAM7
RAM8
RAM9
Row8
Row9
RAM8
RAM9
Row0
Row1
RAM8
RAM9
Row0
Row1
RAM0
RAM1
RAM2
RAM3
RAM4
RAM5
RAM6
RAM7
RAM8
RAM9
Row8
Row9
RAM8
RAM9
Row0
Row1
RAM8
RAM9
Row1
Row2
Row3
Row4
Row5
Row6
Row7
Row8
Row9
Row10 RAM10 Row2
Row11 RAM11 Row3
Row12 RAM12 Row4
Row13 RAM13 Row5
Row14 RAM14 Row6
Row15 RAM15 Row7
Row16 RAM16 Row8
Row17 RAM17 Row9
RAM10 Row2
RAM11 Row3
RAM12 Row4
RAM13 Row5
RAM14 Row6
RAM15 Row7
RAM16 Row8
RAM17 Row9
Row10 RAM10 Row2 RAM10
Row11 RAM11 Row3 RAM11
Row12 RAM12 Row4 RAM12
Row13 RAM13 Row5 RAM13
Row14 RAM14 Row6 RAM14
Row15 RAM15 Row7 RAM15
Row16 RAM16 Row8 RAM16
Row17 RAM17 Row9 RAM17
COM10 Row10 RAM10 Row18 RAM18 Row10 RAM18 Row10 RAM10 Row18 RAM18 Row10 RAM18
COM11 Row11 RAM11 Row19 RAM19 Row11 RAM19 Row11 RAM11 Row19 RAM19 Row11 RAM19
COM12 Row12 RAM12 Row20 RAM20 Row12 RAM20 Row12 RAM12 Row20 RAM20 Row12 RAM20
COM13 Row13 RAM13 Row21 RAM21 Row13 RAM21 Row13 RAM13 Row21 RAM21 Row13 RAM21
COM14 Row14 RAM14 Row22 RAM22 Row14 RAM22 Row14 RAM14 Row22 RAM22 Row14 RAM22
COM15 Row15 RAM15 Row23 RAM23 Row15 RAM23 Row15 RAM15 Row23 RAM23 Row15 RAM23
COM16 Row16 RAM16 Row24 RAM24 Row16 RAM24 Row16 RAM16 Row24 RAM24 Row16 RAM24
COM17 Row17 RAM17 Row25 RAM25 Row17 RAM25 Row17 RAM17 Row25 RAM25 Row17 RAM25
COM18 Row18 RAM18 Row26 RAM26 Row18 RAM26 Row18 RAM18 Row26 RAM26 Row18 RAM26
COM19 Row19 RAM19 Row27 RAM27 Row19 RAM27 Row19 RAM19 Row27 RAM27 Row19 RAM27
COM20 Row20 RAM20 Row28 RAM28 Row20 RAM28 Row20 RAM20 Row28 RAM28 Row20 RAM28
COM21 Row21 RAM21 Row29 RAM29 Row21 RAM29 Row21 RAM21 Row29 RAM29 Row21 RAM29
COM22 Row22 RAM22 Row30 RAM30 Row22 RAM30 Row22 RAM22 Row30 RAM30 Row22 RAM30
COM23 Row23 RAM23 Row31 RAM31 Row23 RAM31 Row23 RAM23 Row31 RAM31 Row23 RAM31
COM24 Row24 RAM24 Row32 RAM32 Row24 RAM32 Row24 RAM24 Row32 RAM32 Row24 RAM32
COM25 Row25 RAM25 Row33 RAM33 Row25 RAM33 Row25 RAM25 Row33 RAM33 Row25 RAM33
COM26 Row26 RAM26 Row34 RAM34 Row26 RAM34 Row26 RAM26 Row34 RAM34 Row26 RAM34
COM27 Row27 RAM27 Row35 RAM35 Row27 RAM35 Row27 RAM27 Row35 RAM35 Row27 RAM35
COM28 Row28 RAM28 Row36 RAM36 Row28 RAM36 Row28 RAM28 Row36 RAM36 Row28 RAM36
COM29 Row29 RAM29 Row37 RAM37 Row29 RAM37 Row29 RAM29 Row37 RAM37 Row29 RAM37
COM30 Row30 RAM30 Row38 RAM38 Row30 RAM38 Row30 RAM30 Row38 RAM38 Row30 RAM38
COM31 Row31 RAM31 Row39 RAM39 Row31 RAM39 Row31 RAM31 Row39 RAM39 Row31 RAM39
COM32 Row32 RAM32 Row40 RAM40 Row32 RAM40 Row32 RAM32 Row40 RAM40 Row32 RAM40
COM33 Row33 RAM33 Row41 RAM41 Row33 RAM41 Row33 RAM33 Row41 RAM41 Row33 RAM41
COM34 Row34 RAM34 Row42 RAM42 Row34 RAM42 Row34 RAM34 Row42 RAM42 Row34 RAM42
COM35 Row35 RAM35 Row43 RAM43 Row35 RAM43 Row35 RAM35 Row43 RAM43 Row35 RAM43
COM36 Row36 RAM36 Row44 RAM44 Row36 RAM44 Row36 RAM36 Row44 RAM44 Row36 RAM44
COM37 Row37 RAM37 Row45 RAM45 Row37 RAM45 Row37 RAM37 Row45 RAM45 Row37 RAM45
COM38 Row38 RAM38 Row46 RAM46 Row38 RAM46 Row38 RAM38 Row46 RAM46 Row38 RAM46
COM39 Row39 RAM39 Row47 RAM47 Row39 RAM47 Row39 RAM39 Row47 RAM47 Row39 RAM47
COM40 Row40 RAM40 Row48 RAM48 Row40 RAM48 Row40 RAM40 Row48 RAM48 Row40 RAM48
COM41 Row41 RAM41 Row49 RAM49 Row41 RAM49 Row41 RAM41 Row49 RAM49 Row41 RAM49
COM42 Row42 RAM42 Row50 RAM50 Row42 RAM50 Row42 RAM42 Row50 RAM50 Row42 RAM50
COM43 Row43 RAM43 Row51 RAM51 Row43 RAM51 Row43 RAM43 Row51 RAM51 Row43 RAM51
COM44 Row44 RAM44 Row52 RAM52 Row44 RAM52 Row44 RAM44 Row52 RAM52 Row44 RAM52
COM45 Row45 RAM45 Row53 RAM53 Row45 RAM53 Row45 RAM45 Row53 RAM53 Row45 RAM53
COM46 Row46 RAM46 Row54 RAM54 Row46 RAM54 Row46 RAM46 Row54 RAM54 Row46 RAM54
COM47 Row47 RAM47 Row55 RAM55 Row47 RAM55 Row47 RAM47 Row55 RAM55 Row47 RAM55
COM48 Row48 RAM48 Row56 RAM56 Row48 RAM56 Row48 RAM48
COM49 Row49 RAM49 Row57 RAM57 Row49 RAM57 Row49 RAM49
COM50 Row50 RAM50 Row58 RAM58 Row50 RAM58 Row50 RAM50
COM51 Row51 RAM51 Row59 RAM59 Row51 RAM59 Row51 RAM51
COM52 Row52 RAM52 Row60 RAM60 Row52 RAM60 Row52 RAM52
COM53 Row53 RAM53 Row61 RAM61 Row53 RAM61 Row53 RAM53
COM54 Row54 RAM54 Row62 RAM62 Row54 RAM62 Row54 RAM54
COM55 Row55 RAM55 Row63 RAM63 Row55 RAM63 Row55 RAM55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Row48 RAM56
Row49 RAM57
Row50 RAM58
Row51 RAM59
Row52 RAM60
Row53 RAM61
Row54 RAM62
Row55 RAM63
COM56 Row56 RAM56
COM57 Row57 RAM57
COM58 Row58 RAM58
COM59 Row59 RAM59
COM60 Row60 RAM60
COM61 Row61 RAM61
COM62 Row62 RAM62
COM63 Row63 RAM63
Row0
Row1
Row2
Row3
Row4
Row5
Row6
Row7
RAM0
RAM1
RAM2
RAM3
RAM4
RAM5
RAM6
RAM7
Row56 RAM0
Row57 RAM1
Row58 RAM2
Row59 RAM3
Row60 RAM4
Row61 RAM5
Row62 RAM6
Row63 RAM7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Row0
Row1
Row2
Row3
Row4
Row5
Row6
Row7
RAM0
RAM1
RAM2
RAM3
RAM4
RAM5
RAM6
RAM7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Display
examples
(a)
(b)
(c)
(d)
(e)
(f)
(a)
(b)
(f)
(c)
(d)
(RAM)
(e)
Solomon Systech
Apr 2008 P 38/59
Rev 1.1 SSD1306
Table 10-2 :Example of Set Display Offset and Display Start Line with Remap
Output
64
Remap
0
0
64
Remap
8
0
64
Remap
0
8
48
Remap
0
0
48
Remap
8
0
48
Remap
0
8
48
Remap
8
Set MUX ratio(A8h)
COM Normal / Remapped (C0h / C8h)
Display offset (D3h)
Display start line (40h - 7Fh)
Hardware
pin name
COM0
COM1
COM2
COM3
COM4
COM5
COM6
16
Row63
RAM63
RAM62
RAM61
RAM60
RAM59
RAM58
RAM57
RAM56
RAM55
RAM54
RAM53
RAM52
RAM51
RAM50
RAM49
RAM48
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM9
Row7
Row6
Row5
Row4
Row3
Row2
Row1
Row0
RAM7
RAM6
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
Row63
RAM7
RAM6
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
Row47
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM9
RAM8
RAM7
RAM6
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Row47
RAM55
RAM54
RAM53
RAM52
RAM51
RAM50
RAM49
RAM48
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM9
RAM8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Row62
Row61
Row60
Row59
Row58
Row57
Row56
Row55
Row54
Row53
Row52
Row51
Row50
Row49
Row48
Row47
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
Row62
Row61
Row60
Row59
Row58
Row57
Row56
Row55
Row54
Row53
Row52
Row51
Row50
Row49
Row48
Row47
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
Row8
Row7
Row6
Row5
Row4
Row3
Row2
Row1
Row0
-
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
Row8
Row7
Row6
Row5
Row4
Row3
Row2
Row1
Row0
-
COM7
COM8
COM9
Row63
Row62
Row61
Row60
Row59
Row58
Row57
Row56
Row55
Row54
Row53
Row52
Row51
Row50
Row49
Row48
Row47
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
RAM63
RAM62
RAM61
RAM60
RAM59
RAM58
RAM57
RAM56
RAM55
RAM54
RAM53
RAM52
RAM51
RAM50
RAM49
RAM48
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM9
RAM63
RAM62
RAM61
RAM60
RAM59
RAM58
RAM57
RAM56
RAM55
RAM54
RAM53
RAM52
RAM51
RAM50
RAM49
RAM48
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM9
Row47
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
Row8
Row7
Row6
Row5
Row4
Row3
Row2
Row1
Row0
-
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM9
RAM8
RAM7
RAM6
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
-
Row47
Row46
Row45
Row44
Row43
Row42
Row41
Row40
Row39
Row38
Row37
Row36
Row35
Row34
Row33
Row32
Row31
Row30
Row29
Row28
Row27
Row26
Row25
Row24
Row23
Row22
Row21
Row20
Row19
Row18
Row17
Row16
Row15
Row14
Row13
Row12
Row11
Row10
Row9
Row8
Row7
Row6
Row5
Row4
Row3
Row2
Row1
Row0
-
RAM63
RAM62
RAM61
RAM60
RAM59
RAM58
RAM57
RAM56
RAM55
RAM54
RAM53
RAM52
RAM51
RAM50
RAM49
RAM48
RAM47
RAM46
RAM45
RAM44
RAM43
RAM42
RAM41
RAM40
RAM39
RAM38
RAM37
RAM36
RAM35
RAM34
RAM33
RAM32
RAM31
RAM30
RAM29
RAM28
RAM27
RAM26
RAM25
RAM24
RAM23
RAM22
RAM21
RAM20
RAM19
RAM18
RAM17
RAM16
-
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Row8
Row7
Row6
Row5
Row4
Row3
Row2
Row1
RAM8
RAM7
RAM6
RAM5
RAM4
RAM3
RAM2
RAM1
Row8
Row7
Row6
Row5
Row4
Row3
Row2
Row1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Row0
RAM0
Row8
RAM8
Row0
RAM8
Display
examples
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(a)
(b)
(f)
(c)
(g)
(d)
(e)
(RAM)
SSD1306
Rev 1.1
P 39/59
Apr 2008
Solomon Systech
10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)
This command consists of two functions:
•
•
Display Clock Divide Ratio (D)(A[3:0])
Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,
with reset value = 1. Please refer to section 8.3 for the details relationship of DCLK and CLK.
Oscillator Frequency (A[7:4])
Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit
value results in 16 different frequency settings available as shown below. The default setting is
1000b.
10.1.17 Set Pre-charge Period (D9h)
This command is used to set the duration of the pre-charge period. The interval is counted in number of
DCLK, where RESET equals 2 DCLKs.
10.1.18 Set COM Pins Hardware Configuration (DAh)
This command sets the COM signals pin configuration to match the OLED panel hardware layout. The table
below shows the COM pin configuration under different conditions (for MUX ratio =64):
Table 10-3 : COM Pins Hardware Configuration
Conditions
COM pins Configurations
ROW63
1 Sequential COM pin configuration (DAh A[4] =0)
COM output Scan direction: from COM0 to COM63 (C0h)
Disable COM Left/Right remap (DAh A[5] =0)
ROW32
ROW31
ROW0
128x 64
COM32
COM0
SSD1306Z
COM31
COM63
Pad 1,2,3,…->126
Gold Bumps face up
2 Sequential COM pin configuration (DAh A[4] =0)
COM output Scan direction: from COM0 to COM63 (C0h)
Enable COM Left/Right remap (DAh A[5] =1)
ROW63
ROW32
ROW31
ROW0
128 x 64
COM0
COM32
SSD1306Z
COM63
Pad 1,2,3,…->126
Gold Bumps face up
Solomon Systech
Apr 2008 P 40/59
Rev 1.1 SSD1306
Conditions
COM pins Configurations
ROW0
3 Sequential COM pin configuration (DAh A[4] =0)
COM output Scan direction: from COM63 to COM0 (C8h)
Disable COM Left/Right remap (DAh A[5] =0)
ROW31
ROW32
ROW63
128 x 64
COM32
COM0
SSD1306Z
COM31
COM63
Pad 1,2,3,…->126
Gold Bumps face up
4 Sequential COM pin configuration (DAh A[4] =0)
COM output Scan direction: from COM63 to COM0 (C8h)
Enable COM Left/Right remap (DAh A[5] =1)
ROW0
ROW32
ROW63
ROW31
128 x 64
COM0
COM32
SSD1306Z
COM63
COM31
Pad 1,2,3,…->126
Gold Bumps face up
ROW63
ROW61
5 Alternative COM pin configuration (DAh A[4] =1)
COM output Scan direction: from COM0 to COM63 (C0h)
Disable COM Left/Right remap (DAh A[5] =0)
ROW62
128 x 64
ROW2
ROW0
ROW1
COM32
COM0
COM1
SSD1306Z
COM62
COM63
COM31
Pad 1,2,3,…->126
Gold Bumps face up
SSD1306
Rev 1.1
P 41/59
Apr 2008
Solomon Systech
Conditions
COM pins Configurations
6 Alternative COM pin configuration (DAh A[4] =1)
COM output Scan direction: from COM0 to COM63 (C0h)
Enable COM Left/Right remap (DAh A[5] =1)
ROW63
ROW61
ROW62
128 x 64
ROW2
ROW0
COM32
ROW1
COM0
COM33
SSD1306Z
COM30
COM31
COM63
Pad 1,2,3,…->126
Gold Bumps face up
ROW0
ROW2
7 Alternative COM pin configuration (DAh A[4] =1)
COM output Scan direction: from COM63 to COM0(C8h)
Disable COM Left/Right remap (DAh A[5] =0)
ROW1
128 x 64
ROW61
ROW62
ROW63
COM32
COM0
COM1
SSD1306Z
COM62
COM63
COM31
Pad 1,2,3,…->126
Gold Bumps face up
ROW0
8 Alternative COM pin configuration (DAh A[4] =1)
COM output Scan direction: from COM63 to COM0(C8h)
Enable COM Left/Right remap (DAh A[5] =1)
ROW1
ROW2
128 x 64
ROW61
ROW62
ROW63
COM32
COM0
COM33
SSD1306Z
COM30
COM31
COM63
Pad 1,2,3,…->126
Gold Bumps face up
Solomon Systech
Apr 2008 P 42/59
Rev 1.1 SSD1306
10.1.19 Set VCOMH Deselect Level (DBh)
This command adjusts the VCOMH regulator output.
10.1.20 NOP (E3h)
No Operation Command
10.1.21 Status register Read
This command is issued by setting D/C# ON LOW during a data read (See Figure 13-1 to Figure 13-2 for
parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is
provided for serial mode.
SSD1306
Rev 1.1
P 43/59
Apr 2008
Solomon Systech
10.2 Graphic Acceleration Command
10.2.1 Horizontal Scroll Setup (26h/27h)
This command consists of consecutive bytes to set up the horizontal scroll parameters and determines the
scrolling start page, end page and scrolling speed.
Before issuing this command the horizontal scroll must be deactivated (2Eh). Otherwise, RAM content may
be corrupted.
The SSD1306 horizontal scroll is designed for 128 columns scrolling. The following two figures (Figure 10-7,
Figure 10-8, Figure 10-9) show the examples of using the horizontal scroll:
Figure 10-7 : Horizontal scroll example: Scroll RIGHT by 1 column
Original Setting
After one scroll
step
Figure 10-8 : Horizontal scroll example: Scroll LEFT by 1 column
Original
Setting
After one
scroll step
Figure 10-9 : Horizontal scrolling setup example
Solomon Systech
Apr 2008 P 44/59
Rev 1.1 SSD1306
10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)
This command consists of 6 consecutive bytes to set up the continuous vertical scroll parameters and
determines the scrolling start page, end page, scrolling speed and vertical scrolling offset.
The bytes B[2:0], C[2:0] and D[2:0] of command 29h/2Ah are for the setting of the continuous horizontal
scrolling. The byte E[5:0] is for the setting of the continuous vertical scrolling offset. All these bytes together
are for the setting of continuous diagonal (horizontal + vertical) scrolling. If the vertical scrolling offset byte
E[5:0] is set to zero, then only horizontal scrolling is performed (like command 26/27h).
Before issuing this command the scroll must be deactivated (2Eh). Otherwise, RAM content may be
corrupted. The following figure (Figure 10-10 ) show the example of using the continuous vertical and
horizontal scroll:
Figure 10-10 : Continuous Vertical and Horizontal scrolling setup example
SSD1306
Rev 1.1
P 45/59
Apr 2008
Solomon Systech
10.2.3 Deactivate Scroll (2Eh)
This command stops the motion of scrolling. After sending 2Eh command to deactivate the scrolling action,
the ram data needs to be rewritten.
10.2.4 Activate Scroll (2Fh)
This command starts the motion of scrolling and should only be issued after the scroll setup parameters have
been defined by the scrolling setup commands :26h/27h/29h/2Ah . The setting in the last scrolling setup
command overwrites the setting in the previous scrolling setup commands.
The following actions are prohibited after the scrolling is activated
1.
2.
RAM access (Data write or read)
Changing the horizontal scroll setup parameters
10.2.5 Set Vertical Scroll Area(A3h)
This command consists of 3 consecutive bytes to set up the vertical scroll area. For the continuous vertical
scroll function (command 29/2Ah), the number of rows that in vertical scrolling can be set smaller or equal to
the MUX ratio.
Solomon Systech
Apr 2008 P 46/59
Rev 1.1 SSD1306
11 MAXIMUM RATINGS
Table 11-1 : Maximum Ratings (Voltage Referenced to VSS)
Symbol
VDD
VCC
Parameter
Value
-0.3 to +4
0 to 16
Unit
V
V
Supply Voltage
VSEG
VCOM
Vin
TA
Tstg
SEG output voltage
COM output voltage
Input voltage
Operating Temperature
Storage Temperature Range
0 to VCC
V
V
V
ºC
ºC
0 to 0.9*VCC
VSS-0.3 to VDD+0.3
-40 to +85
-65 to +150
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the
limits in the Electrical Characteristics tables or Pin Description section
This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal
operation. This device is not radiation protected.
SSD1306
Rev 1.1
P 47/59
Apr 2008
Solomon Systech
12 DC CHARACTERISTICS
Condition (Unless otherwise specified):
Voltage referenced to VSS
VDD = 1.65 to 3.3V
TA = 25°C
Table 12-1 : DC Characteristics
Symbol Parameter
Test Condition
-
Min
7
Typ
-
Max
15
Unit
V
VCC
Operating Voltage
V
VDD
Logic Supply Voltage
-
1.65
-
3.3
VOH
VOL
VIH
VIL
High Logic Output Level
Low Logic Output Level
High Logic Input Level
Low Logic Input Level
ICC, Sleep mode Current
IOUT = 100uA, 3.3MHz
IOUT = 100uA, 3.3MHz
-
0.9 x VDD
-
0.8 x VDD
-
-
-
-
-
-
V
V
V
V
0.1 x VDD
-
0.2 x VDD
-
ICC, SLEEP
VDD = 1.65V~3.3V, VCC = 7V~15V
Display OFF, No panel attached
VDD = 1.65V~3.3V, VCC = 7V~15V
Display OFF, No panel attached
-
-
-
-
10
10
uA
uA
IDD, Sleep mode Current
IDD, SLEEP
VCC Supply Current
VDD = 2.8V, VCC = 12V,
IREF = 12.5uA
No loading, Display ON, All
ON
VDD Supply Current
VDD = 2.8V, VCC = 12V,
IREF = 12.5uA
No loading, Display ON, All
ON
ICC
-
-
430
50
780
150
uA
Contrast = FFh
IDD
uA
uA
Segment Output Current
Contrast=FFh
Contrast=AFh
Contrast=3Fh
-
-
-
100
69
-
-
-
ISEG
VDD=2.8V, VCC=12V,
IREF=12.5uA, Display ON.
25
Dev = (ISEG – IMID)/IMID
IMID = (IMAX + IMIN)/2
ISEG[0:131] = Segment current at
contrast = FFh
Adj Dev = (I[n]-I[n+1]) /
(I[n]+I[n+1])
Segment output current
uniformity
Dev
-3
-2
-
-
+3
+2
%
%
Adjacent pin output current
uniformity (contrast = FF)
Adj. Dev
Solomon Systech
Apr 2008 P 48/59
Rev 1.1 SSD1306
13 AC CHARACTERISTICS
Conditions:
Voltage referenced to VSS
VDD=1.65 to3.3V
TA = 25°C
Table 13-1 : AC Characteristics
Test Condition
Symbol Parameter
FOSC
Min Typ
Max Unit
(1)
Oscillation Frequency of Display VDD = 2.8V
Timing Generator
kHz
333 370
407
Frame Frequency for 64 MUX
Mode
128x64 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
FOSC x 1/(DxKx64)
Hz
FFRM
-
-
(2)
RES#
Reset low pulse width
us
3
-
-
Note
(1) FOSC stands for the frequency value of the internal oscillator and the value is measured when command D5h A[7:4] is
in default value.
(2) D: divide ratio (default value = 1)
K: number of display clocks (default value = 54)
Please refer to Table 9-1 (Set Display Clock Divide Ratio/Oscillator Frequency, D5h) for detailed description
SSD1306
Rev 1.1
P 49/59
Apr 2008
Solomon Systech
Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics
(VDD - VSS = 1.65V to 3.3V, TA = 25°C)
Symbol
Parameter
Min Typ
Max
Unit
tcycle
Clock Cycle Time
300
0
-
-
-
-
-
-
-
-
-
ns
tAS
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
-
ns
ns
ns
ns
ns
ns
ns
tAH
0
-
tDSW
tDHW
tDHR
tOH
40
7
-
-
20
-
-
70
140
tACC
-
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
120
60
60
PWCSL
PWCSH
-
-
-
-
ns
ns
60
tR
tF
Rise Time
Fall Time
-
-
-
-
40
40
ns
ns
Figure 13-1 : 6800-series MCU parallel interface characteristics
D/C#
tAS
tAH
R/W#
E
tcycle
PWCSH
PWCSL
tR
CS#
tF
tDHW
tDSW
D[7:0](WRITE)
Valid Data
tACC
tDHR
D[7:0](READ)
Valid Data
tOH
Solomon Systech
Apr 2008 P 50/59
Rev 1.1 SSD1306
Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics
(VDD - VSS = 1.65V to 3.3V, TA = 25°C)
Symbol
tcycle
tAS
Parameter
Min
300
10
0
Typ Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tAH
tDSW
tDHW
tDHR
tOH
40
7
20
-
-
70
140
-
-
-
tACC
tPWLR
tPWLW
tPWHR
tPWHW
tR
-
Read Low Time
Write Low Time
Read High Time
Write High Time
Rise Time
120
60
60
60
-
-
40
40
-
-
-
tF
Fall Time
-
tCS
tCSH
tCSF
Chip select setup time
Chip select hold time to read signal
Chip select hold time
0
0
20
Figure 13-2 : 8080-series parallel interface characteristics
Write Cycle
CS#
tCSF
tCS
D/C#
tAH
tAS
tR
tF
tcycle
tPWHW
tPWLW
tDSW
WR#
tDHW
D[7:0]
Read cycle
tCSH
CS#
tCS
D/C#
tAS
tAH
tR
tF
tcycle
tPWHR
tPWLR
RD#
tACC
tDHR
D[7:0]
tOH
SSD1306
Rev 1.1
P 51/59
Apr 2008
Solomon Systech
Table 13-4 : 4-wire Serial Interface Timing Characteristics
(VDD - VSS = 1.65V to 3.3V, TA = 25°C)
Symbol
tcycle
tAS
tAH
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
Parameter
Min
100
15
15
20
10
15
15
20
20
-
Typ
Max Unit
Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
40
40
tF
Fall Time
-
Figure 13-3 : 4-wire Serial interface characteristics
D/C#
CS#
tAS
t AH
tCSS
tCSH
tcycle
tCLKL
tCLKH
0)
1)
SCLK(D
SDIN(D
tF
tR
tDSW
Valid Data
tDHW
CS#
SCLK(D0)
D7
D6
D5
D4
D3
D2
D1
D0
SDIN(D1)
Solomon Systech
Apr 2008 P 52/59
Rev 1.1 SSD1306
Table 13-5 : 3-wire Serial Interface Timing Characteristics
(VDD - VSS = 1.65V to 3.3V, TA = 25°C)
Symbol
tcycle
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
Parameter
Min
100
20
10
15
15
20
20
-
Typ
Max Unit
Clock Cycle Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
40
40
tF
Fall Time
-
Figure 13-4 : 3-wire Serial interface characteristics
tCSS
tCSH
CS#
tCYCLE
tCLKH
tCLKL
SCLK
tF
tR
tDSW
Valid Data
tDSH
SDIN
CS#
SCLK
SDIN
D/C#
D7
D6
D5
D4
D3
D2
D1
D0
SSD1306
Rev 1.1
P 53/59
Apr 2008
Solomon Systech
Conditions:
VDD - VSS = VDD - VSS = 1.65V to 3.3V
TA = 25°C
Table 13-6 :I2C Interface Timing Characteristics
Symbol Parameter
Min
2.5
Typ
Max
Unit
us
tcycle
Clock Cycle Time
-
-
-
-
-
-
-
-
-
-
-
-
tHSTART
tHD
Start condition Hold Time
Data Hold Time (for “SDAOUT” pin)
Data Hold Time (for “SDAIN” pin)
Data Setup Time
0.6
0
us
ns
300
100
0.6
ns
tSD
ns
Start condition Setup Time (Only relevant for a repeated
Start condition)
tSSTART
us
tSSTOP
tR
Stop condition Setup Time
0.6
-
-
-
-
-
-
us
ns
ns
us
Rise Time for data and clock pin
Fall Time for data and clock pin
Idle Time before a new transmission can start
300
300
-
tF
-
tIDLE
1.3
Figure 13-5 : I2C interface Timing characteristics
//
//
SDA
SCL
tIDLE
tHD
tR
tF
tHSTART
tSSTART
tSSTOP
tSD
tCYCLE
Solomon Systech
Apr 2008 P 54/59
Rev 1.1 SSD1306
14 Application Example
Figure 14-1 : Application Example of SSD1306Z
The configuration for 8080-parallel interface mode is shown in the following diagram:
(VDD=2.8V, VCC =12V, IREF=12.5uA)
DISPLAY PANEL
128 x 64
SSD1306Z
BGGND
VCC VCOMH IREF D[7:0] E (RD#) R/W#(W/R#) D/C# RES# CS# BS1 BS2 VDD VBAT VBREF FR
VSS
C1N C1P C2N C2P
C3
C2
R1
C1
D[7:0] E (RD#) R/W# (W/R#) D/C# RES# CS#
VDD
VSS
VCC
VSS
[GND]
Pin connected to MCU interface: D[7:0], E, R/W#, D/C#, CS#, RES#
Pin internally connected to VSS: BS0, CL
Pin internally connected to VDD: CLS
C2P, C2N, C1P, C1N, VBREF, FB should be left open.
C1: 1.0uF (1)
C2: 2.2uF (1)
C3: 2.2uF (1)
Voltage at IREF = VCC – 2.5V. For VCC = 12V, IREF = 12.5uA:
R1 = (Voltage at IREF - VSS) / IREF
= (12-2.5) / 12.5u
=760KΩ
Note
(1) The capacitor value is recommended value. Select appropriate value against module application.
SSD1306
Rev 1.1
P 55/59
Apr 2008
Solomon Systech
15 PACKAGE INFORMATION
15.1 SSD1306TR1 Detail Dimension
Figure 15-1 SSD1306TR1 Detail Dimension
Solomon Systech
Apr 2008 P 56/59
Rev 1.1 SSD1306
SSD1306
Rev 1.1
P 57/59
Apr 2008
Solomon Systech
15.2 SSD1306Z Die Tray Information
Figure 15-2 : SSD1306Z die tray information
Solomon Systech
Apr 2008 P 58/59
Rev 1.1 SSD1306
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without
limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,
including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not con-
vey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the
part.
All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU) “Restriction of
Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with
control Marking Symbol
. Hazardous Substances test report is available upon requested.
http://www.solomon-systech.com
SSD1306
Rev 1.1
P 59/59
Apr 2008
Solomon Systech
SOLOMON SYSTECH
SEMICONDUCTOR APPLICATION NOTE
SSD1306
Application Note
128 x 64 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
http://www.solomon-systech.com
SSD1306 App Note
Rev 0.4
P 1/6
Jan 2009
Copyright 2008 Solomon Systech Limited
TABLE OF CONTENTS
1
2
INTRODUCTION
3
CHARGE PUMP REGULATOR
3
3
2.1
Command Table for Charge Bump Setting
3
SOFTWARE CONFIGURATION
5
TABLE OF FIGURES
Figure 1 : Application Example of SSD1306Z with charge bump...........................................................4
Figure 2 : Software Initialization Flow Chart ...........................................................................................5
Solomon Systech
Jan 2009
P 2/6
Rev 0.4 SSD1306 App note
1
Introduction
This application note of SSD1306 is written to explain the charge pump regulator function of
SSD1306. SSD1306 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer
light emitting diode dot-matrix graphic display system. It consists of 128 segments and 64 commons.
This IC is designed for Common Cathode type OLED panel.
For the detailed characteristics of the driver IC, please refer to SSD1306 datasheet.
2
Charge Pump Regulator
The internal regulator circuit in SSD1306 accompanying only 2 external capacitors can generate a
7.5V voltage supply, VCC, from a low voltage supply input, VBAT. The VCC is the voltage supply to the
OLED driver block. This is a switching capacitor regulator circuit, designed for handheld applications.
This regulator can be turned on/off by software command setting.
•
Power supply
o
o
V
DD = 1.65V to 3.3V,<VBAT
BAT = 3.3V to 4.2V
for IC logic
V
for charge pump regulator circuit
•
Pins description for related pins of the charge pump regulator
o
VBAT – Power supply for charge pump regulator circuit.
Status
Enable
VBAT
VDD
VCC
Connect to external Connect to external A capacitor should be connected
charge pump VBAT source
VDD source
between this pin and VSS
Disable
Connect with VDD
Connect to external Connect to external VCC source
VDD source
charge pump pin
o
o
C1P/C1N – Pin for charge pump capacitor; Connect to each other with a capacitor
C2P/C2N – Pin for charge pump capacitor; Connect to each other with a capacitor
2.1 Command Table for Charge Bump Setting
1. Charge Pump Command Table
D/C#Hex D7 D6 D5 D4 D3 D2 D1 D0 Command Description
0
0
8D
1
*
0
*
0
0
0
1
1
0
1
0
0
1
0
Charge
Pump
A[2] = 0b, Disable charge
pump(RESET)
A[7:0]
A2
Setting
A[2] = 1b, Enable charge pump
during display on
Note
(1)
The Charge Pump must be
enabled by the following command:
8Dh ; Charge Pump Setting
14h ; Enable Charge Pump
AFh; Display ON
SSD1306 App Note Rev 0.4
P 3/6
Jan 2009
Solomon Systech
Figure 1 : Application Example of SSD1306Z with charge bump
The configuration for 8080-parallel interface mode is shown in the following diagram:
(VDD= 1.65V ~ 3.3V, < VBAT , VBAT=3.3V~4.2V, IREF=12.5uA)
DISPLAY PANEL
104 x 16
SSD1306Z
BGGND
VCC VCOMH IREF D[7:0] E (RD#) R/W#(W/R#) D/C# RES# CS# BS1 BS2
VDD VBAT VBREF FR
VSS
C1N C1P C2N C2P
C1
C4
C3
C2
R1
C6
C7
D[7:0] E (RD#) R/W# (W/R#) D/C# RES# CS#
VDD VBAT
VSS
VSS
[GND]
Pin connected to MCU interface: D[7:0], E, R/W#, D/C#, CS#, RES#
Pin internally connected to VSS: BS0, CL
Pin internally connected to VDD: CLS
VBREF, FR should be left open.
C1, C4, C6, C7: 1.0uF (1)
C2, C3: 2.2uF (1)
Voltage at IREF = VCC – 2.5V. For VCC = 7.5V, IREF = 12.5uA:
R1 = (Voltage at IREF - VSS) / IREF
= (7.5-2.5) / 12.5u
=400KΩ
Note
(1) The capacitor value is recommended value. Select appropriate value against module application.
Solomon Systech
Jan 2009
P 4/6
Rev 0.4 SSD1306 App note
3
Software Configuration
SSD1306 has internal command registers that are used to configure the operations of the driver IC.
After reset, the registers should be set with appropriate values in order to function well. The registers
can be accessed by MPU interface in either 6800, 8080, SPI type with D/C# pin pull low or using I2C
interface. Below is an example of initialization flow of SSD1306. The values of registers depend on
different condition and application.
Figure 2 : Software Initialization Flow Chart
Set Contrast
Control
81h, 7Fh
Disable Entire
Display On
A4h
Set MUX
Ratio
A8h, 3Fh
Set Display
Offset
Set Normal
Display
A6h
D3h, 00h
Set Display
Start Line
40h
Set Osc
Frequency
D5h, 80h
Enable charge
pump regulator
8Dh, 14h
Set Segment
re-map
A0h/A1h
Set COM Output
Scan Direction
C0h/C8h
Display On
AFh
Set COM Pins
hardware
configuration
DAh, 02
SSD1306 App Note Rev 0.4
P 5/6
Jan 2009
Solomon Systech
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including
without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating
parameters, including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon
Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Solomon Systech was negligent regarding the design or manufacture of the part.
All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU)
“Restriction of Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求
(SJ/T11364-2006)” with control Marking Symbol
. Hazardous Substances test report is available upon requested.
http://www.solomon-systech.com
Solomon Systech
Jan 2009
P 6/6
Rev 0.4 SSD1306 App note
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