SSD1702T3R1 [ETC]
240-outputs LCD driver; 240输出LCD驱动器
| 型号： | SSD1702T3R1 |
| 厂家： | 
ETC |
| 描述： | 240-outputs LCD driver |
| 文件： | 总47页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1702
Advance Information
240 Outputs
Common / Segment Driver
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
http://www.solomon-systech.com
SSD1702
Rev 1.1
P 1/46
Dec 2003
Copyright 2003 Solomon Systech Limited
TABLE OF CONTENTS
1.
GENERAL DESCRIPTION................................................................................................................5
FEATURES........................................................................................................................................5
ORDERING INFORMATION .............................................................................................................5
BLOCK DIAGRAM ............................................................................................................................7
DIE PAD COORDINATES.................................................................................................................8
TAB PACKAGE PIN ASSIGNMENT...............................................................................................13
PIN DESCRIPTION..........................................................................................................................19
FUNCTIONAL BLOCK DESCRIPTIONS........................................................................................22
FUNCTIONAL OPERATIONS.........................................................................................................24
DISPLAY DATA AND DRIVER OUTPUT PINS MAPPING............................................................26
PRECAUTION..................................................................................................................................27
MAXIMUM RATINGS.......................................................................................................................28
DC CHARACTERISTICS.................................................................................................................29
AC CHARACTERISTICS.................................................................................................................31
APPLICATION EXAMPLES OF COMMON DRIVERS...................................................................35
APPLICATION EXAMPLES OF SEGMENT DRIVERS..................................................................37
TIMING CHART OF CASCADE CONNECTION OF SEGMENT DRIVERS...................................38
APPLICATION EXAMPLES............................................................................................................39
TAB PACKAGE DETAIL DIMENSIONS.........................................................................................40
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
Solomon Systech
Dec 2003
P 2/46
Rev 1.1
SSD1702
TABLE OF TABLES
Table 1 - Ordering Information ..................................................................................................................5
Table 2 - SSD1702Z die pad coordinates................................................................................................10
Table 3 - SSD1702T1 pin assignment .....................................................................................................14
Table 4 - SSD1702T2 pin assignment .....................................................................................................16
Table 5 - SSD1702T3 pin assignment .....................................................................................................18
Table 6 - Output level truth table for segment mode.............................................................................24
Table 7 - Output level truth table for common mode ............................................................................25
Table 8 - 4-bit parallel, Segment Mode....................................................................................................26
Table 9 - 8-bit parallel, Segment Mode....................................................................................................26
Table 10 - Common Mode.........................................................................................................................26
Table 11 - Maximum Ratings (Voltage Referenced to VSS)..................................................................28
Table 12 - DC Characteristics (Unless otherwise specified, voltage referenced to VSS, VDD = 2.4 to
3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C)...........................................................................29
Table 13 - DC Characteristics (Unless otherwise specified, voltage referenced to VSS, VDD = 2.4 to
3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C)...........................................................................30
Table 14 - Interface Timing Characteristics (Unless otherwise specified, voltage referenced to VSS,
VDD = +3.0 to +3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C) ................................................31
Table 15 - Interface Timing Characteristics (VDD – VSS = +2.4 to +3.0V, V0=+15.0 to +30.0V, TA = -
35 to 85°C)................................................................................................................................32
Table 16 - Interface Timing Characteristics (VDD - VSS = +2.4 to +3.6V, V0=+15.0 to +30.0V, TA = -35
to 85°C).....................................................................................................................................34
SSD1702
Rev 1.1
P 3/46
Dec 2003
Solomon Systech
TABLE OF FIGURES
Figure 1 - Block Diagram of SSD1702.......................................................................................................7
Figure 2 - SSD1702Z die pad assignment.................................................................................................8
Figure 3 - Alignment mark detail dimensions ..........................................................................................9
Figure 4 - SSD1702T1 pin assignment (Copper view)...........................................................................13
Figure 5 - SSD1702T2 pin assignment (Copper view)...........................................................................15
Figure 6 - SSD1702T3 pin assignment (Copper view)...........................................................................17
Figure 7 - Illustration of output voltages in segment mode .................................................................24
Figure 8 - Illustration of output voltages in common mode .................................................................25
Figure 9 - Recommended power up and down sequence ....................................................................27
Figure 10 - Timing characteristics of SSD1702 in Segment mode ......................................................33
Figure 11 - Timing characteristics of SSD1702 in Common mode......................................................34
Figure 12 - Application example of Single mode (L/R = L) ...................................................................35
Figure 13 - Application example of Single mode (L/R = H)...................................................................35
Figure 14 - Application example of Dual mode (L/R = L) ......................................................................36
Figure 15 - Application example of Dual mode (L/R = H)......................................................................36
Figure 16 - Application example of Segment mode (L/R = L)...............................................................37
Figure 17 - Application example of Segment mode (L/R = H) ..............................................................37
Figure 18 - Timing chart of cascade connection of segment drivers..................................................38
Figure 19 - Typical configuration for 320x240 application ...................................................................39
Figure 20 - SSD1702T1 TAB detail dimensions .....................................................................................40
Figure 21 - SSD1702T2 TAB detail dimensions .....................................................................................42
Figure 22 - SSD1702T3 TAB detail dimensions .....................................................................................44
Solomon Systech
Dec 2003
P 4/46
Rev 1.1
SSD1702
1. General Description
SSD1702 is a 240-outputs LCD driver capable of both COMMON or SEGMENT driving, selected by
hardware pin setting. It is designed for high resolution dot matrix type LCD panel for the use on PDA or
terminal.
SSD1702 can be used in cascade mode to support display system with more than 240 rows or columns.
In segment mode, 4-bit or 8-bit parallel input modes are available through pin selection.
2. FEATURES
BOTH SEGMENT AND COMMON MODE
Supply voltage for LC driver: +15.0 to +30.0 V
Supply voltage for logic system: +2.4 to +3.6 V
240 outputs for either common or segment driving
Pin selectable between common and segment mode
Low output impedance
Low power consumption
SEGMENT MODE
Maximum XCK clock frequency: 20 MHz (VDD = +3.0 to +3.6V)
15 MHz (VDD = +2.4 to +3.0V)
Pin selectable 4-bit or 8-bit input modes
Automatic transfer function of enable signal
Automatically stop the internal clock after counting 240 bits of input data in chip select mode
Line latch circuit reset function when DISPOFF# active
COMMON MODE
Maximum LP clock frequency: 1 MHz (VDD = +2.4 to 3.6V)
Built-in 240 bits bi-directional shift register
Single (240 bits shift register) or Dual mode (two 120 bits shift register) operations
Shift register circuit reset function when DISPOFF# active
3. ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number
Outerlead pitch (mm)
Package Form
Reference
Remark
Figure 2 on
page 7
SSD1702Z
N/A
0.21
0.20
0.055
Gold Bump Die
-
-
-
-
Figure 20 on
page 39
SSD1702T1R1
SSD1702T2R1
SSD1702T3R1
TAB
TAB
TAB
Figure 21 on
page 41
Figure 22 on
page 43
SSD1702
Rev 1.1
P 5/46
Dec 2003
Solomon Systech
Solomon Systech
Dec 2003
P 6/46
Rev 1.1
SSD1702
4. BLOCK DIAGRAM
Figure 1 - Block Diagram of SSD1702
Y240 Y239.......................................................Y2 Y1
V5
V5
V43
V12
V0
V43
V12
240 BITS 4-LEVEL DRIVER
V0
FR
LEVEL
DISPOFF#
SHIFTER
240
240 BITS LEVEL SHIFTER
EIO1
ACTIVE
CONTROL
240
EIO2
240 BITS LINE LATCH / SHIFT REGISTER
8
8
8
8
8
..............8 * 30...............
LP
DATA LATCH
...................................
4BITS*2
DATA
CONTROL
LOGIC
LATCH
XCK
S/C
MD
L/R
DATA LATCH CONTROL
8
POWER ON RESET
DATA CONTROL
D0
D1
D2
D4 D5
D6
D7
D3
VDD
VSS
SSD1702
Rev 1.1
P 7/46
Dec 2003
Solomon Systech
5. DIE PAD COORDINATES
Figure 2 - SSD1702Z die pad assignment
NC
NC
NC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
.
NC
NC
V43 (X5)
V5 (X5)
VSS (X7)
MD
MD
Y
L/R
L/R
X
FR
FR
FR
SSD1702Z
EIO1 (X3)
LP
.
LP
.
LP
Pad 1,2,3,… ->102
X
.
DISPOFF#
DISPOFF#
DISPOFF#
XCK
Gold Bumps face up
.
.
Die Size:
Die Height:
12.65mm x 1.25 mm
533um
.
Y
.
XCK
.
XCK
Bump Size:
Pad 1, 102, 113, 358
Pad 2-101
Pad 103-112, 359-368
Pad 114, 115, 356, 357
Pad 116-355
.
D7 (X3)
D6 (X3)
D5 (X3)
65um x 50um
49um x 105um
65um x 49um
50um x 95um
33um x 95um
.
.
.
Y231
Y232
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
NC
NC
NC
D4 (X3)
D3 (X3)
D2 (X3)
D1 (X3)
D0 (X3)
EIO2 (X3)
S/C
Alignment Mark:
Type
T shape
+ shape
Circle
Size
Coordinate
-5989.0, 147.3
5989.0, 147.3
-5989.0,-215.0
5989.0,-215.0
75um x 75um
75um x 75um
R-37.5um
R-37.5um
Circle
S/C
VDD (X12)
VSS (X9)
V5 (X5)
V43 (X5)
NC
NC
Solomon Systech
Dec 2003
P 8/46
Rev 1.1
SSD1702
Figure 3 - Alignment mark detail dimensions
T shape
+ shape
Circle
Unit in µm
SSD1702
Rev 1.1
P 9/46
Dec 2003
Solomon Systech
Table 2 - SSD1702Z die pad coordinates
Pad no.
1
Pad name
NC
X
Y
Pad no.
61
Pad name
D7
X
Y
Pad no.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pad name
Y6
X
Y
-6181.5
-6102.7
-6026.5
-5950.3
-5874.1
-5797.9
-5721.7
-5645.5
-5569.3
-5493.1
-5416.9
-5340.7
-5177.3
-5101.1
-5024.9
-4948.7
-4872.5
-4796.3
-4720.1
-4643.9
-4567.7
-4259.9
-4183.7
-4107.5
-4031.3
-3955.1
-3878.9
-3802.7
-3726.5
-3650.3
-3574.1
-3497.9
-3421.7
-3345.5
-2950.9
-2874.7
-2650.7
-2574.5
-2498.3
-2106.7
-2030.5
-1954.3
-1730.3
-1654.1
-1577.9
-1186.3
-1110.1
-1033.9
-809.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
1030.9
1107.1
1183.3
1574.9
1651.1
1727.3
1951.3
2027.5
2103.7
2495.3
2571.5
2647.7
2871.7
2947.9
3024.1
3331.9
3408.1
3484.3
3875.9
3952.1
4176.1
4252.3
4643.9
4720.1
4796.3
4872.5
4948.7
5024.9
5101.1
5177.3
5340.7
5416.9
5493.1
5569.3
5645.5
5721.7
5797.9
5874.1
5950.3
6026.5
6102.7
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6181.5
6081.0
5980.5
5880.0
5832.0
5784.0
5736.0
5688.0
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-473.9
-337.9
-261.7
-185.5
-109.3
-33.1
5640.0
5592.0
5544.0
5496.0
5448.0
5400.0
5352.0
5304.0
5256.0
5208.0
5160.0
5112.0
5064.0
5016.0
4968.0
4920.0
4872.0
4824.0
4776.0
4728.0
4680.0
4632.0
4584.0
4536.0
4488.0
4440.0
4392.0
4344.0
4296.0
4248.0
4200.0
4152.0
4104.0
4056.0
4008.0
3960.0
3912.0
3864.0
3816.0
3768.0
3720.0
3672.0
3624.0
3576.0
3528.0
3480.0
3432.0
3384.0
3336.0
3288.0
3240.0
3192.0
3144.0
3096.0
3048.0
3000.0
2952.0
2904.0
2856.0
2808.0
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
2
NC
62
D7
Y7
3
V43
V43
V43
V43
V43
V5
63
D7
Y8
4
64
XCK
XCK
XCK
DISPOFF#
DISPOFF#
DISPOFF#
LP
Y9
5
65
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
6
66
7
67
8
68
9
V5
69
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
V5
70
V5
71
LP
V5
72
LP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
S/C
S/C
EIO2
EIO2
EIO2
D0
73
EIO1
EIO1
EIO1
FR
74
75
76
77
FR
78
FR
79
L/R
80
L/R
81
MD
82
MD
83
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V5
84
85
86
87
88
89
90
91
92
V5
93
V5
94
V5
95
V5
96
V43
V43
V43
V43
V43
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
D0
D0
NC
D1
V12
V12
V12
V12
V12
V0
D1
D1
D2
D2
D2
43.1
D3
V0
119.3
195.5
271.7
347.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
D3
-733.7
V0
D3
-657.5
V0
D4
-265.9
V0
D4
-189.7
NC
D4
-113.5
NC
D5
110.5
NC
D5
186.7
Y1
D5
262.9
Y2
D6
654.5
Y3
D6
730.7
Y4
D6
806.9
Y5
Solomon Systech
Dec 2003
P 10/46 Rev 1.1
SSD1702
Pad no. Pad name
X
Y
Pad no. Pad name
X
Y
Pad no. Pad name
X
Y
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Y66
Y67
2760.0
2712.0
2664.0
2616.0
2568.0
2520.0
2472.0
2424.0
2376.0
2328.0
2280.0
2232.0
2184.0
2136.0
2088.0
1896.0
1848.0
1800.0
1752.0
1704.0
1656.0
1608.0
1560.0
1512.0
1464.0
1416.0
1368.0
1320.0
1272.0
1224.0
1176.0
1128.0
1080.0
1032.0
984.0
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
Y135
Y136
Y137
Y138
Y139
Y140
Y141
Y142
Y143
Y144
Y145
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y172
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
-264.0
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Y193
Y194
Y195
Y196
Y197
Y198
Y199
Y200
Y201
Y202
Y203
Y204
Y205
Y206
Y207
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
NC
-3288.0
-3336.0
-3384.0
-3432.0
-3480.0
-3528.0
-3576.0
-3624.0
-3672.0
-3720.0
-3768.0
-3816.0
-3864.0
-3912.0
-3960.0
-4008.0
-4056.0
-4104.0
-4152.0
-4200.0
-4248.0
-4296.0
-4344.0
-4392.0
-4440.0
-4488.0
-4536.0
-4584.0
-4632.0
-4680.0
-4728.0
-4776.0
-4824.0
-4872.0
-4920.0
-4968.0
-5016.0
-5064.0
-5112.0
-5160.0
-5208.0
-5256.0
-5304.0
-5352.0
-5400.0
-5448.0
-5496.0
-5544.0
-5592.0
-5640.0
-5688.0
-5736.0
-5784.0
-5832.0
-5880.0
-5980.5
-6081.0
-6181.5
-6181.5
-6181.5
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
495.9
347.9
271.7
-312.0
Y68
-360.0
Y69
-408.0
Y70
-456.0
Y71
-504.0
Y72
-552.0
Y73
-600.0
Y74
-648.0
Y75
-696.0
Y76
-744.0
Y77
-792.0
Y78
-840.0
Y79
-888.0
Y80
-936.0
Y81
-984.0
Y82
-1032.0
-1080.0
-1128.0
-1176.0
-1224.0
-1272.0
-1320.0
-1368.0
-1416.0
-1464.0
-1512.0
-1560.0
-1608.0
-1656.0
-1704.0
-1752.0
-1800.0
-1848.0
-1896.0
-2088.0
-2136.0
-2184.0
-2232.0
-2280.0
-2328.0
-2376.0
-2424.0
-2472.0
-2520.0
-2568.0
-2616.0
-2664.0
-2712.0
-2760.0
-2808.0
-2856.0
-2904.0
-2952.0
-3000.0
-3048.0
-3096.0
-3144.0
-3192.0
-3240.0
Y83
Y84
Y85
Y86
Y87
Y88
Y89
Y90
Y91
Y92
Y93
Y94
Y95
Y96
Y97
Y98
Y99
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
936.0
888.0
840.0
792.0
744.0
696.0
648.0
600.0
552.0
504.0
456.0
408.0
360.0
312.0
264.0
216.0
168.0
120.0
72.0
24.0
-24.0
-72.0
NC
-120.0
-168.0
-216.0
NC
V0
V0
SSD1702
Rev 1.1
P 11/46 Dec 2003
Solomon Systech
Pad no.
361
Pad name
V0
X
Y
-6181.5
-6181.5
-6181.5
-6181.5
-6181.5
-6181.5
-6181.5
-6181.5
195.5
119.3
43.1
362
V0
363
V0
364
V12
V12
V12
V12
V12
-33.1
-109.3
-185.5
-261.7
-337.9
365
366
367
368
Solomon Systech
Dec 2003
P 12/46 Rev 1.1
SSD1702
6. TAB package pin assignment
SSD1702T1 TAB
Figure 4 - SSD1702T1 pin assignment (Copper view)
SSD1702
Rev 1.1
P 13/46 Dec 2003
Solomon Systech
Table 3 - SSD1702T1 pin assignment
Pin no.
1
Pin Name
NC
Pin no.
61
Pin Name
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Pin no.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Pin Name
Y86
Pin no.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
Pin Name
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y172
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Y193
Y194
Pin no.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
Pin Name
Y206
Y207
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
NC
2
V0
62
Y87
3
V0
63
Y88
4
V12
V43
V5
64
Y89
5
65
Y90
6
66
Y91
7
NC
67
Y92
8
VDD
S/C
EIO2
D0
68
Y93
9
69
Y94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
70
Y95
71
Y96
D1
72
Y97
D2
73
Y98
D3
74
Y99
D4
75
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
D5
76
D6
77
D7
78
XCK
DISPOFF#
LP
79
80
81
EIO1
FR
L/R
MD
NC
VSS
NC
V5
82
83
84
85
86
87
88
89
V43
V12
V0
90
91
92
V0
93
NC
94
NC
95
Y1
96
Y2
97
Y3
98
Y4
99
Y5
100
101
102
103
104
105
106
107
108
109
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Solomon Systech
Dec 2003
P 14/46 Rev 1.1
SSD1702
SSD1702T2 TAB
Figure 5 - SSD1702T2 pin assignment (Copper view)
SSD1702
Rev 1.1
P 15/46 Dec 2003
Solomon Systech
Table 4 - SSD1702T2 pin assignment
Pin no.
1
Pin Name
NC
Pin no.
61
Pin Name
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
NC
Pin no.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Pin Name
Y84
Pin no.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
Pin Name
Y144
Y145
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y172
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Pin no.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
Pin Name
NC
2
V0
62
Y85
Y201
Y202
Y203
Y204
Y205
Y206
Y207
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
NC
3
V12
V43
V5
63
Y86
4
64
Y87
5
65
Y88
6
NC
66
Y89
7
VDD
S/C
EIO2
D0
67
Y90
8
68
Y91
9
69
Y92
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
70
Y93
D1
71
Y94
D2
72
Y95
D3
73
Y96
D4
74
Y97
D5
75
NC
Y98
D6
76
NC
NC
Y99
D7
77
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
XCK
DISPOFF#
LP
78
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
79
80
EIO1
FR
L/R
MD
VSS
V5
81
82
83
84
85
86
V43
V12
V0
87
88
89
NC
90
NC
91
NC
92
NC
93
Y1
94
Y2
95
Y3
96
Y4
97
Y5
98
Y6
99
Y7
100
101
102
103
104
105
106
107
108
109
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
NC
NC
Solomon Systech
Dec 2003
P 16/46 Rev 1.1
SSD1702
SSD1702T3 TAB
Figure 6 - SSD1702T3 pin assignment (Copper view)
SSD1702
Rev 1.1
P 17/46 Dec 2003
Solomon Systech
Table 5 - SSD1702T3 pin assignment
Pin no.
1
Pin Name
NC
Pin no.
61
Pin Name
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Pin no.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Pin Name
Y88
Pin no.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
Pin Name
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y172
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Y193
Y194
Y195
Y196
Pin no.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
Pin Name
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
NC
2
V0
62
Y89
3
V12
V43
V5
63
Y90
4
64
Y91
5
65
Y92
6
NC
66
Y93
7
VDD
S/C
EIO2
D0
67
Y94
8
68
Y95
9
69
Y96
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
70
Y97
D1
71
Y98
D2
72
Y99
D3
73
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
Y135
Y136
D4
74
D5
75
D6
76
D7
77
XCK
DISPOFF#
LP
78
79
80
EIO1
FR
L/R
MD
VSS
V5
81
82
83
84
85
86
V43
V12
V0
87
88
89
NC
90
NC
91
NC
92
NC
93
Y1
94
Y2
95
NC
Y3
96
NC
Y4
97
Y5
98
Y6
99
Y7
100
101
102
103
104
105
106
107
108
109
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Solomon Systech
Dec 2003
P 18/46 Rev 1.1
SSD1702
6. PIN DESCRIPTION
Pin Name
VDD
SEGMENT MODE
This is the logic system power supply pin.
Ground pin
COMMON MODE
VSS
These are the power supply pins for LC driving voltage. Normally, the bias voltages
used are set by a resistor divider.
V0, V12,
V43, V5
Voltage level must be set such that VSS ≤ V5 ≤ V43 ≤ V12 ≤ V0.
Refer to Section 8 for more details.
This pin switches the driver between Segment and Common mode.
It should be set to H when segment mode is used.
It should be set to L when common mode is used.
S/C
MD
This is for the selection of input interface.
This is for the selection between Single
mode and Dual mode operation.
When MD is set to H, 4-bit parallel input
mode is selected.
When MD is set to L, Single mode
operation is selected.
When MD is set to L, 8-bit parallel input
mode is selected.
When MD is set to H, Dual mode operation
is selected.
The relationship between display data and
driver output is shown in Table 8 and In Single mode, the internal shift register
Table 9.
will work as a 240-bit one. The scan pulse
will run between Y1 to Y240.
In Dual mode, the internal shift register will
be divided into two independent half, each
with 120 bits. Two independent scan
pulses
are
allowed
running
simultaneously.
One scan pulse run
between Y1 to Y120 and the other run
between Y121 to Y240. This makes the
chip effectively work like two 120 channels
common driver, which and thus allowing
split screen application.
Application examples can be found in
Figure 12 to Figure 15.
SSD1702
Rev 1.1
P 19/46 Dec 2003
Solomon Systech
Pin Name
L/R
SEGMENT MODE
COMMON MODE
L/R selects the scan direction of display L/R selects shift direction of shift register.
data output.
When L/R is set to L, data is shifted from
When L/R is set to L, data is read Y240 to Y1.
sequentially at the direction of Y240 to Y1.
When L/R is set to H, data is shifted from
When L/R is set to H, data is read Y1 to Y240.
sequentially at the direction of Y1 to Y240.
Refer to Table 10 for more illustration.
Refer to Table 8 and Table 9 for more
illustration.
This is the display off control pin.
This is the display off control pin.
DISPOFF#
When DISPOFF# is set to H, the input When DISPOFF# is set to H, the input
signal is level-shifted from logic voltage signal is level-shifted from logic voltage
level to LCD driving voltage level and level to LCD driving voltage level and
controls LCD drive circuit.
controls the LCD driving circuit.
When it is set to L, the contents stored in When it is set to L, the contents stored in
the line latch will be reset and Y1-Y240 will the shift register will be reset and Y1-Y240
output V5 level. However, data can still be will output V5.
read into data latch regardless of the
condition of DISPOFF#.
After the DISPOFF# function is cancelled,
the driver will output deselected level (V12
After the DISPOFF# function is cancelled, or V43, depends on the level of FR) until it
the driver will output deselected level (V12 encounters a falling edge of LP.
or V43, depends on the level of FR) until it
encounters a falling edge of LP.
DISPOFF# removal time must meet the
AC characteristics shown in Table 16.
DISPOFF# removal time must meet the Otherwise, the driver may not be able to
AC characteristics shown in Table 14 and output the correct data.
Table 15. Otherwise, the driver may not
be able to output the correct data.
These are display data input pins.
D0 - D6 are not used in common mode.
They should be tied to VSS.
D0 – D7
For 4 bits operation, only D0 - D3 are used
and D4 - D7 should be connected to either D7 is used as input pin in dual mode. Data
VDD or VSS.
is input starting from the 121st bit
according to the data shift register.
This is the shift clock input pin. Data is It is not used in common mode. It should
read at the falling edge of the clock pulse. be connected to VSS or left open.
XCK
LP
This is the latch pulse input pin. Data is This is the bi-directional shift register clock
latched at the falling edge of the clock pulse input pin. Data is shifted at the falling
pulse.
edge of this clock pulse.
Solomon Systech
Dec 2003
P 20/46 Rev 1.1
SSD1702
Pin Name
FR
SEGMENT MODE
COMMON MODE
FR is the AC signal input for LC driving waveform. Normally it is the frame inversion
signal.
The input signal is level-shifted from logic voltage level to LC driving voltage level to
control the LC driving circuit. The output voltage of the LC driver output pins are set by
the line latch / shift register output signal and the FR signal. Their relationship is shown
in Table 6 and Table 7.
These are the I/O pins for chip selection.
These are the bi-directional shift register
shift data I/O pin.
EIO1, EIO2
When L/R is set to L, EIO1 will be the
output and EIO2 will be the input.
When L/R is set to L, EIO1 will be the
output and EIO2 will be the input.
When L/R is set to H, EIO1 will be the
input and EIO2 will be the output.
When L/R is set to H, EIO1 will be the
input and EIO2 will be the output.
After an LP signal is input and the
EIO(input) is set to L, the chip will be A YD signal (Vertical scanning start pulse)
selected.
automatically after reading 240 bits of EIO(input) during LP falling edge indicates
data. the start of a vertical frame.
It will be deselected is expected at the EIO(input). A H level at
EIO(output) is normally H. It will only be Refer to Figure 11 for details timing.
pull L for one XCK cycle (from falling edge
to falling edge of XCK) when 240 bits of
data have been read.
Refer to Figure 10 for details timing.
These are LC driver output pins. The output level can be referred Table 6 and Table 7.
Y1-Y240
Note: Logic H means VDD level
Logic L means VSS level
SSD1702
Rev 1.1
P 21/46 Dec 2003
Solomon Systech
7. FUNCTIONAL BLOCK DESCRIPTIONS
Active control
In segment mode, this block controls the selection of the chip.
Following an LP signal input, and after the chip select signal is input, a select signal is generated
internally until 240 bits of data have been read in.
Once the data input is completed, a selection signal for cascade connection will be output and the
chip will be deselected.
In common mode, this block controls the input/output data of bi-directional pins.
Data Control
When the chip is in segment mode with 4-bit parallel mode enable, this block collects one 4-bit
data and transfers the data to Data Latch block in 4-bit format.
When the chip is in segment mode with 8-bit parallel mode enable, this block collects one 8-bit
data every XCK cycle and transfers the data to Data Latch block in 8-bit format.
This block has no function in common mode.
Data Latch
This block is only active in segment mode. It latches the data on the data bus which used to
determine the output level of each output pins. The latched state of each LC driver output pin is
controlled by the Data latch control.
Data Latch Control
This block is only active in segment mode.
There are 30 data latch unit in the chip. Each can store two 4-bit data. Data latch control
determines which of the data latch unit should receive the data from Data Control block.
The shift direction is controlled by the Control Logic block. After reading every 4 or 8 bits of data
(depending on 4-bit or 8-bit parallel mode), the selection signal will shift one bit to next data latch based
on the state of the control circuit logic.
Line Latch/Shift Register
In segment mode, it simultaneously latches all 240 bits of data into data latch at the falling edge
of the LP signal and output to the level shift block.
In common mode, it shifts data from the data input pin by one bit at the falling edge of the LP
signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD driving voltage level and outputs to the driver
block.
4-level Driver
This block is used to output appropriate LCD driving voltage level (V0, V12, V43, V5) based on the
combinations of S/C, FR and DISPOFF# signals and the data from the line latch or shift register.
Solomon Systech
Dec 2003
P 22/46 Rev 1.1
SSD1702
Control Logic
This block controls the operation of other blocks. In segment mode, when a LP pulse has been
input, it controls the Line latch to latches 240 bits data simultaneously and then resets the Data latch
control block.
In common mode, this block controls the direction of data shift.
Power on reset
Reset all blocks during power on. All outputs (Y1 – Y240) will be set to deselect level.
SSD1702
Rev 1.1
P 23/46 Dec 2003
Solomon Systech
8. FUNCTIONAL OPERATIONS
Output voltage level mapping
Table 6 - Output level truth table for segment mode
FR
Latch Data
DISPOFF#
Driver output voltage level
L
L
H
L
H
H
H
H
L
V43
V5
L
H
H
X
V12
V0
H
X
V5
Figure 7 - Illustration of output voltages in segment mode
Connect to V0 of segment driver
V0
R
Not use in segment driver
V1
R
Connect to V12 of segment driver
V2
(n-4)R
Connect to V43 of segment driver
V3
R
Not use in segment driver
V4
R
Connect to V5 of segment driver
V5
Latch Data
FR
H
L
L
L
H
L
H
H
H
L
H
H
H
H
H
X
X
L
DISPOFF#
H
H
H
Remark:
•
In segment mode, the voltage levels V1 and V4 are not used. V12 pin should be connected to voltage
level V2 and V43 pin should be connected to voltage level V3.
1/n bias is assumed
•
•
•
VSS ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0
H: VDD; L: VSS; X: Don’t care. These pins should be tied to either H or L and avoided from floating.
Solomon Systech
Dec 2003
P 24/46 Rev 1.1
SSD1702
Table 7 - Output level truth table for common mode
FR
L
Latch Data
DISPOFF#
Driver output voltage level
L
H
L
H
H
H
H
L
V43
V0
L
H
H
X
V12
V5
H
X
V5
Figure 8 - Illustration of output voltages in common mode
Connect to V0 of common driver
V0
R
Connect to V12 of common driver
V1
R
Not use in common driver
V2
(n-4)R
Not use in common driver
V3
R
Connect to V43 of common driver
V4
R
Connect to V5 of common driver
V5
Latch Data
FR
L
L
H
L
L
L
L
H
H
H
H
H
L
H
H
X
X
L
DISPOFF#
H
H
H
Remark:
•
In segment mode, the voltage levels V2 and V3 are not used. V12 pin should be connected to voltage
level V1 and V43 pin should be connected to voltage level V4.
1/n bias is assumed
•
•
•
VSS ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0
H: VDD; L: VSS; X: Don’t care. These pins should be tied to either H or L and avoided from floating.
SSD1702
Rev 1.1
P 25/46 Dec 2003
Solomon Systech
9. DISPLAY DATA AND DRIVER OUTPUT PINS MAPPING
Table 8 – 4-bit parallel, Segment Mode
MD
L/R
EIO1
EIO2
Data
Number of clock
1st
Y237
Y238
Y239
Y240
Y4
2nd
Y233
Y234
Y235
Y236
Y8
3rd
…
…
…
…
…
…
…
…
…
58th
59th
Y5
60th
Y1
Input
H
L
Output
Input
D0
D1
D2
D3
D0
D1
D2
D3
Y229
Y230
Y231
Y232
Y12
Y9
Y10
Y6
Y2
Y11
Y7
Y3
Y12
Y8
Y4
H
H
Input
Output
Y232
Y231
Y230
Y229
Y236
Y235
Y234
Y233
Y240
Y239
Y238
Y237
Y3
Y7
Y11
Y2
Y6
Y10
Y1
Y5
Y9
Table 9 – 8-bit parallel, Segment Mode
MD
L/R
EIO1
EIO2
Data
Number of clock
1st
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
Y8
2nd
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y16
3rd
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
28th
29th
Y9
30th
Y1
Input
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y24
Y17
Y18
Y10
Y2
Y19
Y11
Y3
Y20
Y12
Y4
L
L
Output
Input
Y21
Y13
Y5
Y22
Y14
Y6
Y23
Y15
Y7
Y24
Y16
Y8
Y224
Y223
Y222
Y221
Y220
Y219
Y218
Y217
Y232
Y231
Y230
Y229
Y228
Y227
Y226
Y225
Y240
Y239
Y238
Y237
Y236
Y235
Y234
Y233
Y7
Y15
Y23
Y6
Y14
Y22
Y5
Y13
Y21
L
H
Input
Output
Y4
Y12
Y20
Y3
Y11
Y19
Y2
Y10
Y18
Y1
Y9
Y17
Table 10 – Common Mode
MD
L/R
L
Data transfer direction
EIO1
EIO2
Input
D7
Y240 → Y1
Y1 → Y240
Y240 → Y121
Y120 → Y1
Y1 → Y120
Y121 → Y240
Output
Input
X
X
L
H
Output
L
Output
Input
Input
H
H
Input
Output
Input
Where H: VDD
L: VSS
X: Don’t care. The pin should be tied to either H or L and avoided from floating.
Solomon Systech
Dec 2003
P 26/46 Rev 1.1
SSD1702
10.PRECAUTION
This IC is a high voltage LC driver. If voltage is supplied to the LC driver power supply while the power
supply of the logic system is floating, there may have high current flow inside the IC and permanently
damaged the system.
Besides, the logic condition inside IC is undefined when the logic power is just applied, therefore a
DISPOFF# signal is suggested for resetting the IC.
The recommend power up and down sequence is as follow:
Power up:
•
•
•
•
Provide power to the logic system (VDD, VSS)
Pull DISPOFF# to L
Provide the LCD driving power (V0, V12, V43, V5)
DISPOFF# can then be pulled H for normal operation
Power down:
•
•
•
Pull DISPOFF# to L
Disconnect LCD driving power supply
Disconnect Logic system power supply
Figure 9 – Recommended power up and down sequence
VDD
VDD
VSS
V0
V0
VSS
VDD
DISPOFF#
VSS
SSD1702
Rev 1.1
P 27/46 Dec 2003
Solomon Systech
11.MAXIMUM RATINGS
Table 11 - Maximum Ratings (Voltage Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
V0
Logic supply voltage
-0.3 to +4.0
-0.3 to +32.0
-0.3 to + V0+0.3
-0.3 to + V0+0.3
-0.3 to + V0+0.3
-0.3 to VDD+0.3
-30 to +85
V
V
V12
V43
V5
V
LC driving voltage supply
V
V
VI
Input voltage
Operating Temperature
Storage Temperature
V
TA
°C
°C
TSTG
-65 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description
section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric
fields. However, it is advised that normal precautions to be taken to avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit. For proper operation, it is
recommended that VIN and VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of
operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either
VSS or VDD). Unused outputs must be left open. All dummy and NC pins should be left open and
unconnected. Do not group dummy or NC pins together. This device may be light sensitive. Caution
should be taken to avoid exposed of this device to any light source during normal operation. This device
is not radiation protected.
Solomon Systech
Dec 2003
P 28/46 Rev 1.1
SSD1702
12.DC CHARACTERISTICS
SEGMENT MODE
Table 12 - DC Characteristics (Unless otherwise specified, voltage referenced to VSS, VDD = 2.4 to
3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C)
Symbol Parameter
Test Condition
Min
Typ
Max
Unit
VDD
VDD operation voltage
-
2.4
-
3.6
V
V0
V0 operation voltage
-
15.0
-
-
-
30.0
5
V
Stand-by current at VDD
VDD = +3.6V, V0 = +30V,
V1 = VSS, all input static
VDD = +3.6V, V0 = +30V,
fXCK = 20MHz, fLP = 333kHz,
fFR=1389Hz, No-load,
EIO(input)=VDD, 4-bit mode,
D0-D4 switch at every XCK
cycle
ISTB
µA
pin
Consumed current at VDD
(Chip is in deselected
IDD1
-
-
-
450
750
-
900
1500
2.5
µA
µA
stage, i.e. non data-taking)
VDD = +3.6V, V0 = +30V,
fXCK = 20MHz, fLP = 333kHz,
fFR=1389Hz, No-load,
EIO(input)=VSS, 4-bit mode,
D0-D4 switch at every XCK
cycle
Consumed current at VDD
(Chip is in selected stage,
i.e. data-taking)
IDD2
VDD = +3.6V, V0 = +30V,
fXCK = 20MHz, fLP = 333kHz,
fFR=1389Hz, No-load,
EIO(input)=VSS, 4-bit mode,
D0-D4 switch at every XCK
cycle
IO
Consumed current at V0
mA
Input voltage at
VIH
VIL
0.8xVDD
-
-
-
-
V
V
D0-D7, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
DISPOFF#
0.2xVDD
VOH
VOL
Output voltage at
EIO1, EIO2
IOH = -0.4mA
IOL = +0.4mA
0.9xVDD
-
-
-
-
V
V
0.1xVDD
Input leakage current at
D0-D7, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
DISPOFF#
ILIH
VI = VDD
-
-
5
µA
ILIL
VI = VSS
-
-
5
µA
-
-
1.1
1.1
1.5
2.0
∆VON = 0.5V, V0 = +30V
∆VON = 0.5V, V0 = +20V
kΩ
kΩ
RON
Output resistance
SSD1702
Rev 1.1
P 29/46 Dec 2003
Solomon Systech
COMMON MODE
Table 13 - DC Characteristics (Unless otherwise specified, voltage referenced to VSS, VDD = 2.4 to
3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C)
Symbol Parameter
Test Condition
Min
Typ
Max
Unit
VDD
VDD operation voltage
-
2.4
-
3.6
V
V0
V0 operation voltage
Stand-by current at VDD
pin
-
15.0
-
-
-
30.0
5.0
V
VDD = +3.6V, V0 = +30V,
VI = VSS, all input static
VDD = +3.6V, V0 = +30V,
fLP = 333kHz, fFR=1389Hz,
1/240 duty operation,
No-load
ISTB
µA
Consumed current at VDD
pin
IDD1
-
-
15
-
100
500
µA
µA
VDD = +3.6V, V0 = +30V,
fLP = 333kHz, fFR=1389Hz,
1/240 duty operation,
No-load
Consumed current at V0
pin
IO
Input voltage at
VIH
VIL
0.8xVDD
-
-
-
-
V
V
D0-D7, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
DISPOFF#
0.2xVDD
VOH
VOL
ILIH
Output voltage at
EIO1, EIO2
IOH = -0.4mA
IOL = +0.4mA
VI = VDD
0.9xVDD
-
-
-
-
0.1xVDD
5
V
V
µA
-
-
Input leakage current at
D0-D7, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
DISPOFF#
ILIL
VI = VSS
-
-
5
µA
-
-
1.1
1.1
1.5
2.0
Output resistance at Y1-
Y240
∆VON = 0.5V, V0 = +30V
∆VON = 0.5V, V0 = +20V
kΩ
kΩ
RON
Solomon Systech
Dec 2003
P 30/46 Rev 1.1
SSD1702
13.AC CHARACTERISTICS
SEGMENT MODE
Table 14 - Interface Timing Characteristics (Unless otherwise specified, voltage referenced to VSS,
VDD = +3.0 to +3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C)
Symbol Parameter
Test Condition
Min
50
15
15
10
12
15
0
Typ
Max Unit
TWCK
TWCKH
TWCKL
TDS
Shift clock period (1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
TR, TF ≤ 10ns
Shift clock H pulse width
Shift clock L pulse width
Data setup time
-
-
-
-
-
-
TDH
Data hold time
TWLPH
TLD
Latch pulse H pulse width
Shift clock rise to Latch pulse rise
time
TSL
TLS
Shift clock fall to Latch pulse fall time
Latch pulse rise to Shift clock rise
time
-
-
25
25
-
-
-
-
ns
ns
TLH
Latch pulse fall to Shift pulse fall
time
-
25
-
-
ns
TR
TF
TS
Input signal rise time (2)
Input signal fall time (2)
Enable setup time
-
-
-
-
-
-
-
-
50
50
-
ns
ns
ns
10
TSD
TWDL
TD
DISPOFF# removal time
DISPOFF# L pulse width
Output delay time1
-
100
-
-
-
-
-
ns
µs
ns
ns
-
1.2
CL = 15pF
CL = 15pF
-
-
30
400
TPD1
,
Output delay time 2
TPD2
TPD3
Output delay time 3
CL = 15pF
-
-
400
ns
Note:
(1)
(2)
Take the cascade connection into consideration
(TCK-TWCKH-TWCKL)/2 is maximum in the case of high speed operation.
SSD1702
Rev 1.1
P 31/46 Dec 2003
Solomon Systech
SEGMENT MODE
Table 15 - Interface Timing Characteristics (VDD – VSS = +2.4 to +3.0V, V0=+15.0 to +30.0V, TA = -35
to 85°C)
Symbol Parameter
Test Condition
Min
66
23
23
15
23
30
0
Typ
Max Unit
TWCK
TWCKH
TWCKL
TDS
Shift clock period (1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
TR, TF ≤ 10ns
Shift clock H pulse width
Shift clock L pulse width
Data setup time
-
-
-
-
-
-
TDH
Data hold time
TWLPH
TLD
Latch pulse H pulse width
Shift clock rise to Latch pulse rise
time
TSL
TLS
Shift clock fall to Latch pulse fall time
Latch pulse rise to Shift clock rise
time
-
-
50
30
-
-
-
-
ns
ns
TLH
Latch pulse fall to Shift pulse fall
time
-
30
-
-
ns
TR
TF
Input signal rise time (2)
Input signal fall time (2)
Enable setup time
-
-
-
-
-
-
-
-
-
-
50
50
-
ns
ns
ns
ns
µs
ns
µs
-
TS
-
15
100
1.2
-
TSD
TWDL
TD
DISPOFF# removal time
DISPOFF# L pulse width
Output delay time1
-
-
-
-
CL = 15pF
CL = 15pF
41
400
TPD1
,
Output delay time 2
-
TPD2
TPD3
Output delay time 3
CL = 15pF
-
-
400
µs
Note:
(1)
(2)
Take the cascade connection into consideration
(TCK-TWCKH-TWCKL)/2 is maximum in the case of high speed operation.
Solomon Systech
Dec 2003
P 32/46 Rev 1.1
SSD1702
Figure 10 – Timing characteristics of SSD1702 in Segment mode
TWLPH
LP
TSL
TLH
TWCKH
TLD
TLS
TWCKL
XCK
TF
TR
TWCK
TDS
TDH
Last data of i-1th row
TWDL
First data of ith row
D0~D7
TSD
DISPOFF#
LP
n
2
1
Ts
XCK
EIO (input)
TD
EIO (output)
FR
TPD1
LP
TPD2
DISPOFF#
TPD3
Y1~Y240
In 4-bit mode, n = 240/4 = 60
In 8-bit mode, n = 240/8 = 30
SSD1702
Rev 1.1
P 33/46 Dec 2003
Solomon Systech
COMMON MODE
Table 16 - Interface Timing Characteristics (VDD - VSS = +2.4 to +3.6V, V0=+15.0 to +30.0V, TA = -35
to 85°C)
Symbol
TWLP
Parameter
Test Condition
Min
250
15
30
30
50
-
Typ
Max Unit
Shift clock period
Shift clock H pulse width
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
TR, TF ≤ 20ns
TWLPH
VDD = +3.0 to 3.6V
VDD = +2.4 to 3.0V
-
TSU
TH
Data setup time
-
-
Data hold time
-
-
TR
Input signal rise time
Input signal fall time
DISPOFF# removal time
DISPOFF# L pulse width
Output delay time (1)
-
50
50
-
TF
-
-
TSD
TWDL
TDL
-
100
1.2
-
-
-
CL=15 pF
CL=15 pF
CL=15 pF
200
1.2
1.2
TPD1,TPD2 Output delay time (2)
-
-
TPD3
Output delay time (3)
Figure 11 – Timing characteristics of SSD1702 in Common mode
TWLP
LP
TWLPH
TSU
TR
TF
TH
EIO(input)
/ D7
TDL
DISPOFF#
TSD
TWDL
FR
LP
TPD1
TPD2
DISPOFF#
Y1~Y240
TPD3
Solomon Systech
Dec 2003
P 34/46 Rev 1.1
SSD1702
14.APPLICATION EXAMPLES OF COMMON DRIVERS
Figure 12 – Application example of Single mode (L/R = L)
First
Last
Y240
EIO2
Y1
Y240
EIO2
Y1
Y240
EIO2
Y1
YD
EIO1
EIO1
EIO1
DISPOFF#
LP
VSS
FR
VSS (VDD)
VSS
Figure 13 – Application example of Single mode (L/R = H)
DISPOFF#
LP
VSS
FR
VSS (VDD)
VDD
YD
EIO1
Y1
EIO2
Y240
EIO1
Y1
EIO2
Y240
EIO1
Y1
EIO2
Y240
First
Last
SSD1702
Rev 1.1
P 35/46 Dec 2003
Solomon Systech
Figure 14 – Application example of Dual mode (L/R = L)
First
Last
First
Last
(Group A)
(Group A) (Group B)
(Group B)
Y240
EIO2
Y1
Y240 Y121 Y120 Y1
Y240
EIO2
Y1
YDA
EIO1
EIO2
EIO1
EIO1
DISPOFF#
LP
VSS
VDD
FR
VSS(VDD)
VSS
YDB
Figure 15 – Application example of Dual mode (L/R = H)
YDB
VDD
VSS (VDD)
FR
VDD
VSS
LP
DISPOFF#
EIO1
Y1
EIO2
Y240
EIO1
EIO2
EIO1
Y1
EIO2
Y240
YDA
Y1 Y120 Y121 Y240
First
(Group A)
Last
First
Last
(Group A)
(Group B)
(Group B)
Solomon Systech
Dec 2003
P 36/46 Rev 1.1
SSD1702
15.APPLICATION EXAMPLES OF SEGMENT DRIVERS
Figure 16 – Application example of Segment mode (L/R = L)
First Data
Last Data
Y240
EIO2
Y1
Y240
EIO2
Y1
Y240
EIO2
Y1
EIO1
EIO1
EIO1
VSS
XCK
LP
VSS
FR
8
D0-D7
VSS
Figure 17 – Application example of Segment mode (L/R = H)
XCK
LP
VSS
FR
D0-D7
VDD
8
EIO1
Y1
EIO2
Y240
EIO1
Y1
EIO2
Y240
EIO1
Y1
EIO2
Y240
VSS
First Data
Last Data
SSD1702
Rev 1.1
P 37/46 Dec 2003
Solomon Systech
16.TIMING CHART OF CASCADE CONNECTION OF SEGMENT DRIVERS
Figure 18 – Timing chart of cascade connection of segment drivers
FR
LP
XCK
First data
Last data
2
n
1
2
2
2
2
1
n
1
n
1
n
1
n
D0~D7
Device A
Device B
Device C
Device D
H
L
EIO (Device A input)
EIO (Device A output,
cascade to device B input)
EIO (Device B output,
cascade to device C input)
EIO (Device C output,
cascade to device D)
In 4-bit mode, n = 240/4 = 60
In 8-bit mode, n = 240/8 = 30
Solomon Systech
Dec 2003
P 38/46 Rev 1.1
SSD1702
17.APPLICATION EXAMPLES
Figure 19 – Typical configuration for 320x240 application
VEE
V
0
R
R
V
1
VDD, VSS,
V0, V1, V4, V5
COM1
V
2
COM2
.
.
.
(n-
4)R
V
3
Common driver
R
R
EIO1
320x240 Dot Matrix
LCD Panel
V
4
Y1-Y240
M
D
FR
LP
S/C
L/R
V
5
DISPOFF#
D0-D7
EIO2
.
XCK
.
.
COM239
COM240
VSS
VDD
YD
FR
Segment driver
SSD1703
LCD
LP
Controller
DISPOFF#
VDD, VSS,
V0, V2, V3, V5
XCK
D0- D7
Remark:
•
The circuit is in 1/n bias
•
•
•
VSS ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VEE
VEE is the maximum driving voltage allowed, which is equal to or above V0.
For common driver
o
o
o
o
V0 should be connected to pin V0
V1 should be connected to pin V12
V4 should be connected to pin V43
V5 should be connected to pin V5
•
For segment driver
o
o
o
o
V0 should be connected to pin V0
V2 should be connected to pin V12
V3 should be connected to pin V43
V5 should be connected to pin V5
SSD1702
Rev 1.1
P 39/46 Dec 2003
Solomon Systech
18.TAB PACKAGE DETAIL DIMENSIONS
SSD1702T1 TAB
Figure 20 – SSD1702T1 TAB detail dimensions
Solomon Systech
Dec 2003
P 40/46 Rev 1.1
SSD1702
SSD1702
Rev 1.1
P 41/46 Dec 2003
Solomon Systech
SSD1702T2 TAB
Figure 21 – SSD1702T2 TAB detail dimensions
Solomon Systech
Dec 2003
P 42/46 Rev 1.1
SSD1702
SSD1702
Rev 1.1
P 43/46 Dec 2003
Solomon Systech
SSD1702T3 TAB
Figure 22 – SSD1702T3 TAB detail dimensions
Solomon Systech
Dec 2003
P 44/46 Rev 1.1
SSD1702
SSD1702
Rev 1.1
P 45/46 Dec 2003
Solomon Systech
Solomon Systech
Dec 2003
P 46/46 Rev 1.1
SSD1702
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of
others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or
manufacture of the part.
http://www.solomon-systech.com
SSD1702
Rev 1.1
P 47/46 Dec 2003
Solomon Systech
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