SSM1105 [ETC]
NOT FOR NEW DESIGN: SCALAR SYSTEM MEMORY (SSM) FOR IMAGE PROCESSOR ICS ; 不适用于新设计：标量系统存储器（ SSM ）用于图像处理器IC\n
| 型号： | SSM1105 |
| 厂家： | 
ETC |
| 描述： | NOT FOR NEW DESIGN: SCALAR SYSTEM MEMORY (SSM) FOR IMAGE PROCESSOR ICS
|
| 文件： | 总4页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM1105V
Scalar System Memory (SSM)
for Image Processor ICs
NOT FOR NEW DESIGN
FEATURES SUMMARY
■ System solution for use with image processing
scalar ICs
decoders, chip-selects, inverters; and to
prioritize interrupts from DDC, I C, PWM
2
– For LCD monitors, projectors, and TVs
Figure 1. Packages
– Compatible with Pixelworks PW11x/PWx64
families (and similar image processors or mi-
cro-controllers)
■ Single integrated package, including:
– Dual bank Flash memories
2
– DDC, I C, and PWM channels
– General purpose I/O
– Programmable logic
– In-System Programming via JTAG
■ Dual bank Flash memories
– Provide concurrent operation
– 5 Mbit main Flash memory
– 384 Kbit secondary Flash memory (divided
into 10 small sectors)
TQFP100 (U)
– Programmable Decode PLD for flexible ad-
dress mapping of both memories
■ Dual Display Data Channels (DDC)
– Supports DDC for both analog RGB and digi-
tal DVI video input channels
– DDC1/DDC2B VESA standard compliant
– 256 byte SRAM buffer for each DDC channel
■ In-System Programming (ISP) with JTAG
– Program entire chip in 30-40 seconds with no
involvement of the processor
2
■ Dual independent I C channels
– Each capable of master or slave operation
– Program with low-cost FlashLINK
– Control A/D converters, video decoders, and
future devices (tuner, audio, etc.)
■ Content Security: Programmable Security Bit
blocks access of device programmers / readers
■ Four Pulse Width Modulator (PWM) channels
– 16-bit resolution for period and for duty cycle
– 16-bit clock prescalers
■ Zero-Power Technology: memory and PLD
blocks automatically switch to stand-by current
between input changes
■ Package and Specifications
– 100-pin TQFP, 14 x 14mm
– 90 ns memory access time
■ Seven I/O ports with 52 I/O pins for Multifunction
2
I/O: GPIO, DDC, I C, PWM, PLD I/O, and JTAG
■ 3000 gate PLD with 16 macrocells, for creating
glue logic, state machines, clock dividers,
– V Operating Voltage: 2.7V to 3.6V
CC
November 2002
1/4
This is information on a product still in production but not recommended for new designs.
SSM1105V
SUMMARY DESCRIPTION
SSM1105V devices bring in-system programma-
ble (ISP) and in-application programmable (IAP)
flash memory to LCD monitor, projector and televi-
sion applications utilizing a scalar IC from either
Pixelworks or other similar image processors or
micro-controllers (MCU). Figure 3 shows a typical
SSM based system with Pixelworks processor.
The dual-bank Flash memory architecture sup-
ports full concurrent operation permitting IAP in
the field, which means that firmware can be re-
motely updated with little interruption of system
operation. During run-time, the secondary Flash
memory array is ideal for EEPROM emulation,
thus eliminating the need for a separate external
EEPROM.
An on-chip, decode PLD provides for flexible ad-
dress mapping for both memories. Dual 256 byte
SRAMs provide buffer storage for the DDC chan-
nels, thus removing the burden from the proces-
sor.
The SSM1105V devices feature a dual -bank flash
architecture, Dual Display Data Channels (DDC),
2
I C, PWM channels, general purpose I/O, pro-
grammable logic, and in-system programming via
2
either JTAG or I C.
Figure 2. SSM Block Diagram
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU
CPU ADDR
I/O PORT
AD0
AD1
AD2
AD3
AD4
MAIN FLASH
SECURITY
LOCK
PD0
PD1
PD2
PD3
10 BLOCKS, 64 KB
640 KBytes total
TO PLD
IN BUS
PAGE REG
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
SECONDARY FLASH
FS0-9
DECODE
PLD
6 BLOCKS, 8 KB
48 KBytes total
I/O PORT
CSBOOT0-5
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
DDC SRAMs
DDC-SRAM
256 byte
256 byte
RUNTIME CONTROL
REG FILES
DDC
CSIP
CPU DATA
I2C
PWM
GPIO
POWER MNGMT
CSIOP
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
I/O PORT
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GENERAL PLD
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
AND
ARRAY
16 OUTPUT MICROCELLS
I/O PORT
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
C
C
C
C
C
C
C
C
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
24 INPUT
MICROCELLS
CPU CNTL
CNTL0
CNTL1
CNTL2
RST\
PIN FEEDBACK
NODE FEEDBACK
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU
DUAL I2C
I2C0 I2C1
DUAL DDC
DDC0 DDC1
QUAD PWM
PW1 PW2 PW3
JTAG ISP
CONTROLLER
PW0
I/O PORT
P P P P P P P
I/O PORT
P P P P P P P
P
I/O PORT
P P P P P P P
P
P
I
0
E E E E E E E E
1 2 5 6 7
H H H H H H H H
1 2 5 6 7
I
I
I
I
I
I I
3
4
3 4
0
0
1
2
3
4
5
6 7
AI04976
Note: Additional address lines can be brought in to the device via Port A, B, C or D.
2/4
SSM1105V
Table 1. Pin Assignments – TQFP100
Pin
Pin
Pin
Pin No. Assign
ments
Pin
Pin No. Assign
ments
Pin No. Assign
ments
Pin No. Assign
ments
1
PD2
PD3
GND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PA5
PA6
2
3
PA7
V
4
CNTL0
CNTL1
PB0
DD
5
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
GND
6
7
PB1
8
PB2
9
PB3
V
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PB4
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
PB5
PB6
PB7
V
DD
GND
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PD0
PD1
V
DD
GND
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
V
DD
ADIO12
ADIO13
ADIO14
ADIO15
RESET
CNTL2
PG0
V
DD
PA0
PA1
PA2
PA3
PA4
3/4
SSM1105V
Figure 3. SSM1105V-Based System Applications
DDC
ADC
ADDR
5 Mb FLASH
DDC
DATA
CPU
INTFC
ROMOE
ROMWE
BHE
I2C
I2C
TMDS R,G,B,CLK
DDC / I2C Logic
analog or digital Inputs
384Kb FLASH
OPTIONAL
NTSC/PAL
DECODER
YUV
CONTROL
KEYBD
PLD - 16
MACRO
CELLS
8
8
GPIO
GPIO
Pixelworks
PW11x
PWx64
I2C
PWM
PWM
PWM
PWM
BACKLIGHT
VOLUME
TREBEL
BASS
4 Channels
PWM
I2C MASTER/
SLAVE
I2C
Future
FEATURES
I2C MASTER/
I2C
SLAVE
MANU
FACTUR
ING
JTAG
JTAG In-Sytem Programming (ISP)
SSM1105V
DISPLAY DATA
AI04977
Table 2. Ordering Information Scheme
Example:
SSM1105
V
– 90 T
1
T
Device Type
SSM1105 = SSM for image processor ICs
Operating Voltage
V = V = 2.7 to 3.6V
CC
Speed
90 = 90 ns
Package
T = TQFP100
Temperature Range
1 = 0 to 70 °C (commercial)
Option
T = Tape & Reel Packing
4/4
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