SSTV16857MTDX [ETC]
Memory Driver ; 存储驱动器
| 型号： | SSTV16857MTDX |
| 厂家： | 
ETC |
| 描述： | Memory Driver
|
| 文件： | 总6页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2000
Revised February 2001
SSTV16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
Features
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin DDR-I memory modules. The device has
a differential input clock, SSTL-2 compatible data inputs
and a LVCMOS compatible RESET input. The device has
been designed for compliance with the JEDEC DDR mod-
ule and register specifications.
■ Compliant with DDR-I registered module specifications
■ Operates at 2.5V ± 0.2V VDD
■ SSTL-2 compatible input and output structure
■ Differential SSTL-2 compatible clock inputs
■ Low power mode when device is reset
■ Industry standard 48 pin TSSOP package
The device is fabricated on an advanced submicron CMOS
process and is designed to operate at power supplies of
less than 3.6V’s.
Ordering Code:
Order Number Package Number
Package Description
SSTV16857MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name Description
Q1-Q14
D1-D14
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
RESET
CK
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
Negative Master Clock Input
VREF
VDDQ
VDD
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
Dn
Qn
RESET
CK
CK
L
X or
X or
X or
L
Floating
Floating
Floating
H
H
H
H
L
H
X
X
↑
↑
↓
↓
L
H
L
H
H
L
Qn
Qn
L = Logic LOW
H = Logic HIGH
X = Don’t Care, but not floating unless noted
↑ = LOW-to-HIGH Clock Transition
↓ = HIGH-to-LOW Clock Transition
© 2001 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
Functional Description
The SSTV16857 is a 14-bit register with SSTL-2 compati-
ble inputs and outputs. Input data is captured by the regis-
ter on the positive edge crossing of the differential clock
pair.
RESET is removed, the system designer must insure the
clock and data inputs to the device are stable during the
rising transition of the RESET signal.
The SSTL-2 data inputs transition based on the value of
When the LV-CMOS RESET signal is asserted LOW, all
outputs and internal registers are asynchronously placed
into the LOW logic state. In addition, the clock and data dif-
ferential comparators are disabled for power savings. Out-
put glitches are prevented by disabling the internal
registers more quickly than the input comparators. When
VREF. VREF is a stable system reference used for setting
the trip point of the input buffers of the SSTV16857 and
other SSTL-2 compatible devices.
The RESET signal is a standard CMOS compatible input
and is not referenced to the VREF signal.
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VDDQ
Supply Voltage (VDD
)
−0.5V to +3.6V
−0.5V to +3.6V
)
Power Supply (VDDQ
Power Supply (VDD
)
2.3V to 2.7V
Reference Voltage (VREF
Input Voltage (VI)
)
−0.5V to +3.6V
)
−0.5V to VDD + 0.5V
Operating Range
Reference Supply
(VREF = VDDQ/2)
V
DDQ to 2.7V
Output Voltage (VO)
Outputs Active (Note 2)
DC Input Diode Current (IIK
VI < 0V
−0.5V to VDDQ + 0.5V
1.15 to 1.35
REF ± 40 mV
0V to VDD
)
Termination Voltage (VTT
)
V
−50 mA
+50 mA
Input Voltage
VI > VDD
Output Voltage (VO)
DC Output Diode Current (IOK
)
Output in Active States
Output Current IOH/IOL
0V to VDDQ
V
V
O < 0V
−50 mA
+50 mA
O > VDD
V
DD = 2.3V to 2.7V
±20 mA
DC Output Source/Sink Current
(IOH/IOL
Free Air Operating Temperature (TA)
0°C to +70°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
)
±50 mA
DC VDD or Ground Current
per Supply Pin (IDD or Ground)
Storage Temperature Range (Tstg
±100 mA
)
−65°C to +150°C
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: The RESET input of the device must be held at VDD or GND to
ensure proper device operation. The differential inputs must not be floating,
unless RESET is asserted LOW.
DC Electrical Characteristics (2.3V ≤ VDD ≤ 2.7V)
VDD
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.3
2.3
VIKL
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
II = −18 mA
−1.2
V
V
V
V
V
V
VIKH
II = +18 mA
Data Inputs
Data Inputs
Data Inputs
Data Inputs
3.5
VIH-AC
VIL-AC
VIH-DC
VIL-DC
V
REF+310mV
REF+150mV
V
V
REF−310mV
REF−150mV
V
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
RESET
RESET
1.7
V
V
VIL
0.7
VICR
Common Mode Input Voltage Range CLK, CLK
0.97
360
1.53
V
VI(PP)
VOH
Peak to Peak Input Voltage
HIGH Level Output Voltage
CLK, CLK
OH = −100 µA
OH = −16 mA
OL = 100 µA
OL = 16 mA
mV
I
2.3 to 2.7
2.3
V
DD − 0.2
V
V
I
1.95
VOL
LOW Level Output Voltage
I
2.3 to 2.7
2.3
0.2
I
0.35
±5.0
II
Input Leakage Current
Static Standby
VI = VDD or GND
2.7
µA
µA
IDD
RESET = GND, IO = 0
10
25
2.7
2.7
Static Operating
RESET = VDD, IO = 0
VI = VIH(AC) or VIL(AC)
mA
IDDD
Dynamic Operating Current
Clock Only
RESET = VDD, IO = 0
VI = VIH(AC) or VIL(AC)
CK, CK Duty Cycle 50%
90
15
µA/MHz
Dynamic Operating Current
per Data Input
RESET = VDD, IO = 0
VI = VIH(AC) or VIL(AC)
CK, CK Duty Cycle 50%
Data Input = ½ Clock
Rate 50% Duty Cycle
µA/MHz
3
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DC Electrical Characteristics (Continued)
VDD
Symbol
ROH
Parameter
Conditions
OH = −20 mA
Min
Max
Units
(V)
Output HIGH On Resistance
Output LOW On Resistance
I
I
I
2.3 to 2.7
2.3 to 2.7
2.5
7
7
20
20
4
Ω
Ω
Ω
ROL
RO∆
OL = 20 mA
| ROH - ROL
|
O = 20 mA, TA = 25°C
AC Electrical Characteristics (Note 4)
TA = 0°C to +70°C, CL = 30 pF, RL = 50Ω
Symbol
Parameter
VDD = 2.5V ± 0.2V; VDDQ = 2.5V ± 0.2V
Units
Min
Max
fMAX
Maximum Clock Frequency
200
MHz
ns
tW
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
2.5
22
tACT
ns
(Note 5)
tINACT
(Note 5)
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
data and clock inputs must be held at valid levels
(not floating) after RESET LOW
22
ns
tS
Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5)
Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5)
Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Reset Removal Time (Figure 7)
0.75
0.9
0.75
0.9
10
ns
ns
tH
tREM
ns
ns
tPHL, tPLH
Propagation Delay CLK, CLK to Qn (Figure 4)
1.1
2.8
tPHL
Propagation Delay RESET to Qn (Figure 6)
Output to Output Skew
5.0
ns
ps
tSK(Pn-Pn)
200
Note 4: Refer to Figure 1 through Figure 7.
Note 5: This parameter is not production tested.
Note 6: For data signal input slew rate ≥ 1 V/ns.
Note 7: For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
Note 8: For CK, CK signals input slew rates are ≥ 1 V/ns.
Capacitance (Note 9)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
DD = 2.5V, VI = VREF ± 350 mV
CIN
Data Pin Input Capacitance
2.0
3.0
pF
V
V
V
CK, CK - Input Capacitance
RESET
2.5
2.5
3.5
3.5
pF
pF
DD = 2.5V, VICR = 1.25V, VI(PP) = 360 mV
DD = 2.5V, VI = VDD to GND
Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
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4
AC Loading and Waveforms (See Notes A through F below)
Note: CL includes probe and jog capacitance
FIGURE 2. Voltage Waveforms - Pulse Duration
FIGURE 1. AC Test Circuit
Note: IDD tested with clock and data inputs held at VDD or GND,
and IO = 0 mA.
FIGURE 3. Voltage and Current Waveforms Inputs
Active and Inactive Times
FIGURE 4. Voltage Waveforms -
Propagation Delay Times
FIGURE 6. Voltage Waveforms -
RESET Propagation Delay Times
FIGURE 5. Voltage Waveforms - Setup and Hold Times
Note A: All input pulses are supplied by generators having
the following characteristics:
PRR ≤ 10 MHz, Z0 = 50Ω, input slew rate = 1V/ns ± 20%
(unless otherwise specified).
Note B: The outputs are measured one at a time with one
transition per measurement.
Note C: VTT = VREF = VDD/2.
Note D: VIH = VREF +310 mV (AC voltage levels) for differ-
ential inputs. VIH = VDD for LVCMOS input.
Note E: VIL = VREF −310 mV (AC voltage levels) for differ-
ential inputs. VIL = GND for LVCMOS input.
Note F: Removal time (tREM) is tested with one data input
held active HIGH. The propagation time from CK to the cor-
responding output must meet valid timing specifications for
the measurement to be accurate.
FIGURE 7. Voltage Waveforms -
RESET Removal Delay Times
5
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48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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