ST62T28CM3 [ETC]
8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS ; 8位微控制器（ MCU）和OTP 。只读存储器。 FASTR A / D转换器。 8位自动重加载定时器。 UART 。 OSG 。国家外汇管理局复位和28引脚\n
| 型号： | ST62T28CM3 |
| 厂家： | 
ETC |
| 描述： | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS
|
| 文件： | 总84页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST62T28C/E28C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
PDIP28
■ User Programmable Options
■ 20 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
PS028
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■ Digital Watchdog
■ 8-bit A/D Converter with 12 analog inputs
■ 8-bit Asynchronous Peripheral Interface
(UART)
SS0P28
■ 8-bit Synchronous Peripheral Interface (SPI)
■ On-chip Clock oscill ator can be driven by
Quartz Crystal, Ceramic resonator or RC
network
■ Oscillator Safe Guard
■ Low Voltage Detector for safe Reset
■
One external Non-Maskable Interrupt
■ ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
CDIP28W
DEVICE SUMMARY
(See end of Datasheet for Ordering Information)
OTP
(Bytes)
EPROM
(Bytes)
DEVICE
I/O Pins
ST62T28C
ST62E28C
7948
-
20
20
7948
Rev. 2.9
July 2001
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Table of Contents
Document
Page
ST62T28C/E28C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.6 Data RAM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 15
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 IINTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 27
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.4 SPI alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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4.1.5 UART alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.6 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.7 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.8 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 52
4.5.1 Ports Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.5.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.4 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.5 Interrupt Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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ST62P28C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ST6228C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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ST62T28C/E28C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T28C and ST62E28C devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de-
vices are based on a building block approach: a
common core is surrounded by a number of on-
chip peripherals.
fined in the programmable option byte of the OTP/
EPROM versions.OTP devices offer all the advan-
tages of user programmability at low cost, which
make them the ideal choice in a wide range of ap-
plications where frequent code changes, multiple
code versions or last minute programmability are
required.
The ST62E28C is the erasable EPROM version of
the ST62T28C device, which may be used to em-
ulate the ST62T28C device, as well as the respec-
tive ST6228C ROM devices.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer, with
1 input capture channel, capability, a serial asyn-
chronous port interface (UART), a synchronous
serial port interface, an 8-bit A/D Converter with 12
analog inputs and a Digital Watchdog timer, mak-
ing them well suited for a wide range of automo-
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
Figure 1. Block Diagram
PA0..PA1 / 20 mA Sink
PA2/ARTIMout / 20 mA Sink
PORT A
8-BIT
A/D CONVERTER
PA3/ARTIMin/ 20 mA Sink
PA4..PA5/20 mA Sink
TEST/V
NMI
PP
TEST
PORT B
PORT C
PB4..PB6/Ain
INTERRUPT
DATA ROM
USER
PC4..PC5/Ain
PC6..PC7/20 mA Sink
SELECTABLE
PROGRAM
Memory
PD1/Ain/Scl
PD2/Ain/Sin
PD3/Ain/Sout
PD4/Ain/RXD1
PD5/Ain/TXD1
PD6,PD7/Ain
DATA RAM
192 Bytes
7948 bytes
PORT D
UART
AUTORELOAD
TIMER
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
TIMER
TIMER
SPI
8 BIT CORE
DIGITAL
WATCHDOG
POWER
SUPPLY
RESET
RESET
OSCILLATOR
V
V
OSCin OSCout
DD SS
VR01823F
(V on EPROM/OTP versions only)
PP
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ST62T28C/E28C
1.2 PIN DESCRIPTIONS
V
and V . Power is supplied to the MCU via
the A/D converter, while PC6 and PC7 can sink
20mA for direct LED or TRIAC drive.
DD
SS
these two pins. V
is the power connection and
DD
V
is the ground connection.
SS
PD1...PD7. These 7 lines are organised as one I/O
port (portD). Each line may be configured under
software control as input with or without internal
pull-up resistor, input with interrupt generation and
pull-up resistor, analog input open-drain or push-
pull output. In addition, the pins PD5/TXD1 and
PD4/RXD1 can be used as UART output (PD5/
TXD1) or UART input (PD4/RXD1). The pins PD3/
Sout, PD2/Sin and PD3/Scl can also be used re-
spectively as data out, data in and clock pins for
the on-chip SPI.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET. The active-low RESET pin is used to re-
start the microcontroller.
TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM/
OTP programming Mode is entered.
TIMER. This is the TIMER 1 I/O pin. In input mode,
it is connected to the prescaler and acts as ex-
ternal timer clock or as control gate for the internal
timer clock. In output mode, the TIMER pin outputs
the data bit when a time-out occurs.The user can
select as option the availability of an on-chip pull-
up at this pin.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. Schmitt trigger
characteristics. The user can select as option the
availability of an on-chip pull-up at this pin.
Figure 2. ST62T28C/E28C Pin Configuration
PA0-PA5. These 6 lines are organised as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull outputs.
PA2/ARTIMout and PA3/ARTIMin can be used re-
spectively as output and input pins for the embed-
ded 8-bit Auto-Reload Timer.
V
V
DD
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SS
TIMER
OSCin
OSCout
NMI
2
PA0*
3
PA1*
4
PA2*/ARTIMout
PA3*/ARTIMin
PA4*
In addition, PA0-PA5 can sink 20mA for direct LED
or TRIAC drive.
5
PC7*
PC6*
6
PA5*
7
PB4...PB6. These 3 lines are organised as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull outputs,
analog inputs for the A/D converter.
Ain/PC5
PD1/Ain/Scl
PD2/Ain/Sin
PD3/Ain/Sout
PD4/Ain/RXD1
PD5/Ain/TXD1
PD6/Ain
8
Ain/PC4
9
(1)
10
11
12
13
14
TEST/V
PP
RESET
Ain/PB6
Ain/PB5
Ain/PB4
PC4-PC7. These 4 lines are organised as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, input with interrupt generation and
pull-up resistor, open-drain or push-pull output.
PC4 and PC5 can also be used as analog input for
PD7/Ain
(1) V on EPROM/OTP only
PP
(*) 20 mA Sink
VR01804B
6/84
6
ST62T28C/E28C
1.3 MEMORY MAP
1.3.1 Introduction
(STATIC) 2K page is available all the time for inter-
rupt vectors and common subroutines, independ-
ently of the PRPR register content. This “STATIC”
page is directly addressed in the 0800h-0FFFh by
the MSB of the Program Counter register PC 11.
Note this page can also be addressed in the 000-
7FFh range. It is two different ways of addressing
the same physical memory.
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in Program memory and user vectors; Data
space contains user data in RAM and in Program
memory, and Stack space accommodates six lev-
els of stack for subroutine and interrupt service
routine nesting.
Jump from a dynamic page to another dynamic
page is achieved by jumping back to the static
page, changing contents of PRPR and then jump-
ing to the new dynamic page.
1.3.2 Program Space
Figure 3. 8Kbytes Program Space Addressing
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
ROM SPACE
PC
1FFFh
SPACE
000h
0000h
Page 1
Static
Page
Page 3
Page 0
Page 2
7FFh
800h
Program Space is organised in 4K pages. 4 of
them are addressed in the 000h-7FFh locations of
the Program Space by the Program Counter and
by writing the appropriate code in the Program
ROM Page Register (PRPR register). A common
Page 1
Static
Page
FFFh
Figure 4. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
0000h
000h
RAM / EEPROM
BANKING AREA
0-63
03Fh
040h
DATA READ-ONLY
WINDOW
MEMORY
PROGRAM
MEMORY
07Fh
080h
081h
082h
083h
084h
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
DATA READ-ONLY
MEMORY
WINDOW SELECT
0C0h
0FF0h
DATA RAM
INTERRUPT &
RESET VECTORS
0FFFh
BANK SELECT
ACCUMULATOR
0FFh
VR01568
7/84
7
ST62T28C/E28C
MEMORY MAP (Cont’d)
Table 1. ST62E28C/T28C Program Memory Map
Program ROM Page Register (PRPR)
Address: CAh
7
—
Write Only
ROM Page Device Address
Description
0000h-007Fh
Page 0
Reserved
User ROM
0
0080h-07FFh
-
-
-
-
-
-
PRPR1 PRPR0
0800h-0F9Fh
0FA0h-0FEFh
User ROM
Reserved
Page 1
“STATIC”
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Bits 2-7= Not used.
Bit 5-0 = PRPR1-PRPR0: Program ROM Select.
These two bits select the corresponding page to
be addressed in the lower part of the 4K program
address space as specified in Table 2.
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Page 2
Page 3
0000h-000Fh
0010h-07FFh
Reserved
User ROM
This register is undefined on Reset. Neither read
nor single bit instructions may be used to address
this register.
Note: OTP/EPROM devices can be programmed
with the development tools available from STMicro-
electronics (ST62E3X-EPB or ST623X-KIT).
Table 2. 6Kbytes Program ROM Page Register
Coding
PRPR1
PRPR0 PC bit 11
Memory Page
Static Page (Page 1)
Page 0
X
0
0
1
1
X
0
1
0
1
1
0
0
0
0
1.3.2.1 Program ROM Page Register (PRPR)
The PRPR register can be addressed like a RAM
location in the Data Space at the address CAh;
nevertheless it is a write only register that cannot
be accessed with single-bit operations. This regis-
ter is used to select the 2-Kbyte ROM bank of the
Program Space that will be addressed. The
number of the page has to be loaded in the PRPR
register. Refer to the Program Space description
for additional information concerning the use of
this register. The PRPR register is not modified
when an interrupt or a subroutine occurs.
Page 1 (Static Page)
Page 2
Page 3
1.3.2.2 Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Care is required when handling the PRPR register
as it is write only. For this reason, it is not allowed
to change the PRPR contents while executing in-
terrupt service routine, as the service routine
cannot save and then restore its previous content.
This operation may be necessary if common rou-
tines and interrupt service routines take more than
2K bytes; in this case it could be necessary to di-
vide the interrupt service routine into a (minor) part
in the static page (start and end) and to a second
(major) part in one of the dynamic pages. If it is im-
possible to avoid the writing of this register in inter-
rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRPR it must write also
to the image register. The image register must be
written before PRPR, so if an interrupt occurs be-
tween the two instructions the PRPR is not af-
fected.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the Program memory contents.
Returned parts with a protection set can therefore
not be accepted.
8/84
8
ST62T28C/E28C
MEMORY MAP (Cont’d)
Table 4. ST62T28C/E28C Data Memory Space
000h
03Fh
1.3.3 Data Space
DATA RAM BANKS
040h
07Fh
080h
081h
082h
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in Program
memory.
DATA ROM WINDOW AREA
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
083h
084h
DATA RAM
1.3.3.1 Data ROM
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h*
0C9h*
0CAh*
0CBh*
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
0DAh
0DCh*
0DDh
0DEh
0E4h
0E5h
0E6h
0E7h
0E8h
0E9h
0EAh
0EBh
0ECh
OFFh
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
PORT D DATA REGISTER
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
PORT C DIRECTION REGISTER
PORT D DIRECTION REGISTER
INTERRUPT OPTION REGISTER
DATA ROM WINDOW REGISTER
ROM BANK SELECT REGISTER
RAM BANK SELECT REGISTER
PORT A OPTION REGISTER
PORT B OPTION REGISTER
PORT C OPTION REGISTER
PORT D OPTION REGISTER
A/D DATA REGISTER
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in Program memory.
1.3.3.2 Data RAM
In ST6228C and ST62E28C devices, the data
space includes 60 bytes of RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe-
ripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).
A/D CONTROL REGISTER
TIMER 1 PRESCALER REGISTER
TIMER 1 COUNTER REGISTER
TIMER 1 STATUS/CONTROL REGISTER
RESERVED
UART DATA SHIFT REGISTER
UART STATUS CONTROL REGISTER
WATCHDOG REGISTER
Additional RAM pages can also be addressed us-
ing banks of 64 bytes located between addresses
00h and 3Fh.
RESERVED
I/O INTERRUPT POLARITY REGISTER
SPI INTERRUPT DISABLE REGISTER
SPI DATA SHIFT REGISTER
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
RESERVED
ARTIMER MODE/CONTROL REGISTER
ARTIMER STATUS/CONTROL REGISTER ARSC0
ARTIMER STATUS/CONTROL REGISTER ARSC1
RESERVED
Table 3. Additional RAM Banks
ARTIMER RELOAD/CAPTURE REGISTER
ARTIMER COMPARE REGISTER
. ARTIMER LOAD REGISTER
RESERVED
Device
RAM
ST62T28C/E28C
2 x 64 bytes
ACCUMULATOR
* WRITE ONLY REGISTER
9/84
9
ST62T28C/E28C
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
Address: 0C9h
—
Write Only
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 1FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
7
0
-
DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 7 = Not used.
Bit 6-0 = DWR6-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 00h
loaded in the DWR register, the physical location
addressed in program memory is 00h. The DWR
register is not cleared on reset, therefore it must
be written to prior to the first access to the Data
read-only memory window area.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
13 12 11 10
9
3
8
2
7
1
6
0
5
4
3
2
1
1
0
0
PROGRAM SPACE ADDRESS
READ
DATA ROM
WINDOW REGISTER
CONTENTS
7
6
5
4
5
4
3
2
DATA SPACE ADDRESS
40h-7Fh
(DWR)
0
1
IN INSTRUCTION
Example:
DWR=28h
0
0
1
0
0
1
0
0
0
0
0
1
DATA SPACE ADDRESS
59h
1
1
1
1
0
0
0
0
0
0
ROM
ADDRESS:A19h
0
0
1
1
1
1
VR01573A
10/84
10
ST62T28C/E28C
MEMORY MAP (Cont’d)
1.3.6 Data RAM Bank Register (DRBR)
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Address: CBh
—
Write only
7
0
-
Notes:
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
-
-
-
DRBR4 DRBR3
-
-
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM
Page 1.
Bit 2.0 These bits are not used.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address CBh of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 5. Data RAM Bank Register Set-up
The DRBR register can be addressed like a RAM
Data Space location at the address CBh; never-
theless it is a write only register that cannot be ac-
cessed with single-bit operations. This register is
used to select the desired 64-byte RAM bank of
the Data Space. The number of banks has to be
loaded in the DRBR register and the instruction
has to point to the selected location as if it was in
bank 0 (from 00h address to 3Fh address).
DRBR
00h
ST62T28C/E28C
None
01h
Reserved
02h
Reserved
08h
RAM Page 1
RAM Page 2
Reserved
10h
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
other
11/84
11
ST62T28C/E28C
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
EXTCNTL is low, STOP mode is not available with
the watchdog active.
The two Option Bytes allow configuration capabili-
ty to the MCUs. Option byte’s content is automati-
cally read, and the selected options enabled, when
the chip reset is activated.
LVD. LVD RESET enable.When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
PROTECT. Readout Protection. This bit allows the
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.
The option bytes are located in a non-user map.
No address has to be specified.
OSCIL. Oscillator selection. When this bit is low,
the oscillator must be controlled by a quartz crys-
tal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
EPROM Code Option Byte (LSB)
7
0
PRO-
TECT
PORT
PULL
NMI
PULL PULL
TIM
OS-
GEN
OSCIL
-
WDACT
PORT PULL. Port Pull-Up. This bit must be set
high to disable pull-up at reset on the I/O port.
When this bit is low,I/O ports are in input with pull-
up.
EPROM Code Option Byte (MSB)
D4. Reserved. Must be cleared to zero.
15
8
NMI PULL. NMI Pull-Up. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
UART
FRAME
EXTC-
NTL
ADC
SYNCHRO
-
-
-
-
LVD
TIM PULL.TIM Pull-Up. This bit must be set high
to configure the TIMER pin with a pull-up resistor.
When it is low, no pull-up is provided.
D15-D13. Reserved. Must be cleared.
ADC SYNCHRO. When set, an A/D conversion is
started upon WAIT instruction execution, in order
to reduce supply noise. When this bit is low, an A/
D conversion is started as soon as the STA bit of
the A/D Converter Control Register is set.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
UART FRAME. When set, UART transmission
and reception are based on a 11-bit frame. When
cleared, a 10-bit frame is used.
OSGEN. Oscillator Safe Guard. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
D10. Reserved.
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode).
EXTCNTL. External STOP MODE control.. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one. When
12/84
12
ST62T28C/E28C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
2.2 CPU REGISTERS
The ST6FamilyCPUcorefeaturessixregistersand
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin
OSCout
INTERRUPTS
CONTROLLER
DATA SPACE
DATA
CONTROL
SIGNALS
FLAG
VALUES
OPCODE
ADDRESS/READ LINE
ADDRESS
2
RAM/EEPROM
PROGRAM
DATA
ROM/EPROM
256
ROM/EPROM
DECODER
B-DATA
A-DATA
DEDICATIONS
ACCUMULATOR
Program Counter
and
12
FLAGS
6 LAYER STACK
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
13/84
13
ST62T28C/E28C
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt
- Reset
PC=Interrupt vector
PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
Figure 7. ST6 CPU Programming Mode
l
b7 X REG. POINTER b0
INDEX
REGISTER
SHORT
DIRECT
ADDRESSING
MODE
b7 Y REG. POINTER b0
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
V REGISTER
W REGISTER
b7
b7
b0
b0
b0
b0
b7 ACCUMULATOR
PROGRAM COUNTER
b11
SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction.
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
C
C
C
Z
Z
Z
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
VA000423
14/84
14
ST62T28C/E28C
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita-
ble ceramic resonator, or with an external resistor
Figure 8. Oscillator Configurations
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
(R
). In addition, a Low Frequency Auxiliary Os-
NET
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the
benefits of a back-up clock system.
ST6xxx
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati-
OSC
OSC
out
in
cally limits the internal clock frequency (f ) as a
INT
function of V , in order to guarantee correct oper-
ation. These functions are illustrated in Figure 9,
C
DD
C
L1n
L2
Figure 10, Figure 11 and Figure 12.
Figure 8 illustrates various possible oscillator con-
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
(R
), or the lowest cost solution using only the
NET
ST6xxx
LFAO. C an C should have a capacitance in the
L1
L2
range 12 tST6_CLK1o 22 pF for an oscillator fre-
quency in the 4-8 MHz range.
OSC
OSC
out
in
The internal MCU clock frequency (f ) is divided
INT
NC
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
RC NETWORK
RC NETWORK option
With an 8MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
ST6xxx
OSC
OSC
NC
out
R
in
3.1.1 Main Oscillator
The oscillator configuration may be specified by se-
lectingtheappropriate option.WhentheCRYSTAL/
RESONATORoptionisselected,itmustbeusedwith
a quartz crystal, a ceramic resonator or an external
signalprovidedontheOSCinpin.WhentheRCNET-
WORK option is selected, the system clock is gen-
erated by an external resistor.
NET
INTEGRATED CLOCK
CRYSTAL/RESONATOR option
OSG ENABLED option
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatical-
ly started.
ST6xxx
OSC
NC
OSC
out
in
15/84
15
ST62T28C/E28C
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by re-
setting the OSCOFF bit of the A/D Converter Con-
trol Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Os-
cillator (LFAO), used to ensure minimum process-
ing in case of main oscillator failure, to offer re-
duced power consumption or to provide a fixed fre-
quency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera-
tion even if the power supply should drop.
the software instruction at f
clock frequency.
LFAO
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
9). In all cases, when the OSG is active, the maxi-
This oscillator is available when the OSG ENA-
BLED option is selected. In this case, it automati-
cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provid-
ed, main oscillator switched off...).
mum internal clock frequency, f , is limited to
INT
f
, which is supply voltage dependent. This re-
OSG
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
lationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscilla-
tor starts operating after the first missing edge of
the main oscillator (see Figure 10).
duced f
frequency. The A/D converter accura-
LFAO
cy is decreased, since the internal frequency is be-
low 1MHz.
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there-
fore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor starts.
particular device can stand (depending on V ),
DD
and below f
cy with OSG enabled.
: the maximum authorised frequen-
OSG
ADCR
Note. The OSG should be used wherever possible
as it provides maximum safety. Care must be tak-
en, however, as it can increase power consump-
tion and reduce the maximum operating frequency
Address: 0D1h
—
Read/Write
7
0
to f
.
OSG
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR
OFF
7
6
5
4
3
1
0
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accu-
rate.
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register. These bits are not used.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
For precise timing measurements, it is not recom-
mended to use the OSG and it should not be ena-
bled in applications that use the SPI or the UART.
3.1.3 Oscillator Safe Guard
It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).
The Oscillator Safe Guard (OSG) affords drastical-
ly increased operational integrity in ST62xx devic-
es. The OSG circuit provides three basic func-
16/84
16
ST62T28C/E28C
CLOCK SYSTEM (Cont’d)
Figure 9. OSG Filtering Principle
(1)
(2)
(3)
(4)
(1) Maximum Frequency for the device to work correctly
(2)
Actual Quartz Crystal Frequency at OSCin pin
(3)
(4)
Noise from OSCin
VR001932
Resulting Internal Frequency
Figure 10. OSG Emergency Oscillator Principle
Main
Oscillator
Emergency
Oscillator
Internal
Frequency
VR001933
17/84
17
ST62T28C/E28C
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
POR
Core
: 13
OSG
TIMER 1
M
U
X
f
MAIN
OSCILLATOR
INT
Watchdog
: 12
LFAO
: 1
Main Oscillator off
Figure 12. Maximum Operating Frequency (f
) versus Supply Voltage (V
)
DD
MAX
Maximum FREQUENCY (MHz)
8
4
7
6
5
4
3
2
1
3
f
OSG
f
Min (at 85°C)
OSG
2
1
f
Min (at 125°C)
OSG
2.5
3
3.6
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V
)
DD
VR01807J
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a f
OSG.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
4. When the OSG is disabled, operation in this
area is not guaranteed
anteed at a frequency of at least f
When the OSG is enabled, access to this area is
OSG Min.
prevented. The internal frequency is kept at f
OSG.
3. When the OSG is disabled, operation in this
18/84
18
ST62T28C/E28C
3.2 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
is executed immediately following the internal de-
lay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
cient level for the chosen frequency (see recom-
mended operation) before the reset signal is re-
leased. In addition, supply rising must start from
0V.
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
As a consequence, the POR does not allow to su-
pervise static, slowly rising, or falling, or noisy
(presenting oscillation) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interrupt Processing
the RESET pin are acceptable, provided V has
DD
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
RESET
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
SELECT
NMI MODE FLAGS
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
PUT FFEH
ON ADDRESS BUS
YES
IS RESET STILL
3.2.2 Power-on Reset
PRESENT?
The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the oscillator to fully stabilize before execut-
ing the first instruction. The initialization sequence
NO
LOAD PC
FROM RESET LOCATIONS
FFE/FFF
FETCH INSTRUCTION
VA000427
19/84
19
ST62T28C/E28C
RESETS (Cont’d)
3.2.3 Watchdog Reset
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
As long as the supply voltage is below the refer-
ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
ply voltage rises over the reference value. There-
fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represents a power-
up, power-down sequence.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage De-
tector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
V
DD
V
Up
V
dn
RESET
RESET
time
VR02106A
3.2.5 Application Notes
No external resistor is required between V
the Reset pin, thanks to the built-in pull-up device.
and
Direct external connection of the pin RESET to
V must be avoided in order to ensure safe be-
DD
DD
haviour of the internal reset sources (AND.Wired
structure).
20/84
20
ST62T28C/E28C
RESETS (Cont’d)
3.2.6 MCU Initialization Sequence
Figure 15. Reset and Interrupt Processing
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
RESET
JP:2 BYTES/4 CYCLES
JP
RESET
VECTOR
INITIALIZATION
ROUTINE
RETI: 1 BYTE/2 CYCLES
RETI
VA00181
Figure 16. Reset Block Diagram
V
DD
ST6
INTERNAL
RESET
f
CK
OSC
COUNTER
R
PU
AND. Wired
1)
ESD
R
RESET
RESET
RESET
ON RESET
POWER
WATCHDOG RESET
LVD RESET
VR02107A
1) Resistive ESD protection. Value not guaranteed.
21/84
21
ST62T28C/E28C
RESETS (Cont’d)
Table 6. Register Reset Status
Register
Address(es)
0C0h to 0C3h
Status
Comment
Port Data Registers
I/O are Input with or without pull-up
depending on PORT PULL option
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control
0C4h to 0C7h
0CCh to 0CFh
0C8h
Interrupt disabled
TIMER disabled
0D4h
00h
AR TIMER disabled
AR TIMER Mode/Control Register
0E5h
AR TIMER Status/Control Register 0 0E6h
AR TIMER Status/Control Register 1 0E7h
X, Y, V, W, Register
080H TO 083H
Accumulator
0FFh
Data RAM
084h to 0BFh
0CBh
Data RAM Page Register
Data ROM Window Register
A/D Result Register
0C9h
Undefined
0D0h
ARTIMER Reload/Capture Register
ARTIMER Compare Registers
ARTIMER Load Registers
0E9h
0EAh
0EBh
TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register
0D3h
0D2h
0D8h
0D1h
FFh
7Fh
FEh
40h
Max count loaded
A/D in Stand-by
UART disabled
UART Status Control
0D7h
22/84
22
ST62T28C/E28C
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU en-
ters STOP mode.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 7).
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR register has been set.
Table 7. Recommended Option Choices
Functions Required
Stop Mode & Watchdog
Stop Mode
Recommended Options
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
“SOFTWARE WATCHDOG”
Watchdog
“HARDWARE WATCHDOG”
23/84
23
ST62T28C/E28C
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the
user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen-
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set.
Figure 17. Watchdog Counter Control
D0
C
D1
SR
RESET
D2
D3
D4
D5
D6
D7
T5
T4
T3
T2
T1
T0
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in Figure 17.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384µs to 24.576ms).
8
÷2
OSC ÷12
VR02068A
24/84
24
ST62T28C/E28C
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
3.3.2 Application Notes
Address: 0D8h
—
Read/Write
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
Reset status: 1111 1110b
7
0
T0
T1
T2
T3
T4
T5
SR
C
When STOP mode is not required, hardware acti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
Bit 0 = C: Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
is idle.
When C is kept low the counter can be used as a
7-bit timer.
The NMI pin can be connected to an I/O line (see
Figure 18) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.
This bit is cleared to “0” on Reset.
Bit 1 = SR: Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
Bits 2-7 = T5-T0: Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
These bits are set to “1” on Reset.
jrr 0, WD, #+3
ldi WD, 0FDH
25/84
25
ST62T28C/E28C
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
Figure 18. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
SWITCH
NMI
I/O
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
VR02002
Figure 19. Digital Watchdog Block Diagram
RESET
Q
RSFF
7
8
-2
-2
-12
R
DB1.7 LOAD SET
SET
S
OSCILLATOR
CLOCK
8
DB0
WRITE
RESET
DATA BUS
VA00010
26/84
26
ST62T28C/E28C
3.4 IINTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vectors are located in Pro-
gram space (see Table 8).
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Table 8. Interrupt Vector Map
Interrupt Source
Interrupt source #0
Interrupt source #1
Interrupt source #2
Interrupt source #3
Interrupt source #4
Priority
Vector Address
(FFCh-FFDh)
(FF6h-FF7h)
(FF4h-FF5h)
(FF2h-FF3h)
(FF0h-FF1h)
1
2
3
4
5
Table 9. Interrupt Option Register Description
SET
Enable all interrupts
Disable all interrupts
GEN
CLEARED
Rising edge mode on inter-
rupt source #2
SET
ESB
3.4.1 Interrupt request
Falling edge mode on inter-
rupt source #2
CLEARED
SET
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Level-sensitive mode on in-
terrupt source #1
LES
Falling edge mode on inter-
rupt source #1
CLEARED
NOT USED
OTHERS
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
27/84
27
ST62T28C/E28C
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
MCU
– Automatically the MCU switches back to the nor-
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the interrupt routine in a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 20. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce-
dure:
INSTRUCTION
MCU
FETCH
– The interrupt is detected.
INSTRUCTION
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flags).
EXECUTE
– The PC contents are stored in the first level of
the stack.
INSTRUCTION
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
LOAD PC FROM
INTERRUPT VECTOR
NO
WAS
(FFC/FFD)
THE INSTRUCTION
?
A RETI
– TheassociatedinterruptvectorisloadedinthePC.
YES
IS THE CORE
ALREADY IN
NORMAL MODE?
SET
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and especially during the execu-
tion of an "ldi IOR, 00h" instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
YES
INTERRUPT MASK
?
NO
CLEAR
INTERRUPT MASK
PUSH THE
PC INTO THE STACK
SELECT
PROGRAM FLAGS
SELECT
INTERNAL MODE FLAG
User
"POP"
– User selected registers are saved within the in-
terrupt service routine (normally on a software
stack).
THE STACKED PC
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
NO
– The source of the interrupt is found by polling the
interrupt flags (if more than one source is associ-
ated with the same vector).
?
YES
VA000014
– The interrupt is serviced.
– Return from interrupt (RETI)
28/84
28
ST62T28C/E28C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
Address: 0C8h
—
Write Only
Reset status: 00h
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
7
-
0
-
This register is cleared on reset.
LES ESB GEN
-
-
-
3.4.4 Interrupt sources
Interrupt sources available on the ST62E28C/
T28C are summarized in the Table 10 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 10. Interrupt Requests and Mask Bits
Address
Interrupt
source
Peripheral
GENERAL
TIMER
A/D CONVERTER ADCR
Register
IOR
TSCR1
Mask bit
Masked Interrupt Source
Register
C8h
GEN
ETI
All Interrupts, excluding NMI All
D4h
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY: Byte received
TXMT: Byte sent
OVF: ARTIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
End of Transmission
PAn pin
source 4
D1h
EAI
source 4
RXIEN
TXIEN
OVIE
CPIE
EIE
UART
UARTCR
D7h
source 4
ARTIMER
ARMC
E5h
source 3
SPI
SIDR
DCh
ALL
source 1
source 1
source 2
source 0
source 2
Port PAn
Port PBn
Port PCn
Port PDn
ORPA-DRPA
ORPB-DRPB
C0h-C4h ORPAn-DRPAn
C1h-C5h ORPBn-DRPBn
PBn pin
ORPC-DRPC C2h-C6h ORPCn-DRPCn
ORPD-DRPD C3h-C7h ORPDn-DRPDn
PCn pin
PDn pin
29/84
29
ST62T28C/E28C
INTERRUPTS (Cont’d)
Interrupt Polarity Register (IPR)
generates interrupt on rising edge. At reset, IPR is
cleared and all port interrupts are not inverted (e.g.
Port C generates interrupts on falling edges).
Address: DAh
—
Read/Write
7
0
Bit 7 - Bit 4 = Unused.
Bit 3 = Port D Interrupt Polarity.
Bit 2 = Port C Interrupt Polarity.
Bit 1= Port A Interrupt Polarity.
Bit 0 = Port B Interrupt Polarity.
-
-
-
-
PortD PortC PortA PortB
In conjunction with I/O register ESB bit, the polarity
of I/O pins triggered interrupts can be selected by
setting accordingly the Interrupt Polarity Register
(IPR). If a bit in IPR is set to one the corresponding
port interrupt is inverted (e.g. IPR bit 2 = A; port C
Tables 11. I/O Interrupts selections according to IPR, IOR programming
Interrupt
source
GEN
IPR3
IPR0
IOR5
Port B occurrence
Port D occurrence
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
2
Interrupt
source
GEN
IPR1
IOR6
Port A occurrence
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
falling edge
low level
rising edge
high level
Disabled
1
IPR2
Port C occurrence
falling edge
Interrupt source
0
1
0
rising edge
30/84
30
ST62T28C/E28C
INTERRUPTS (Cont’d)
Figure 21. Interrupt Block Diagram
FROM REGISTER PORT A,B,C,D
SINGLE BIT ENABLE
PBE
IPR Bit 2
V
DD
FF
CLK
CLR
INT #0 NMI (FFC,D))
Q
PORT C
Bits
NMI
I
Start
0
IPR Bit 1
FF
CLK
CLR
0
Q
PORT A
Bits
PBE
INT #1 (FF6,7)
MUX
I
Start
1
1
IOR bit 6 (LES)
SPI
RESTART
FROM
STOP/WAIT
IPR Bit 0
FF
CLK
CLR
INT #2 (FF4,5)
PBE
Q
PORT B
Bits
I
Start
2
IOR bit 5 (ESB)
IPR Bit 3
PORT D
Bits
PBE
OVF
OVIE
CPF
CPIE
INT #3 (FF2,3)
ARTIMER
EF
EIE
TMZ
ETI
TIMER 1
EAI
EOC
INT #4 (FF0,1)
RXRDY
RXIEN
UART
IOR bit 4(GEN)
TXMT
TXIEN
31/84
31
ST62T28C/E28C
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraphs.
of the processor core prior to the WAIT instruction,
but also on the kind of interrupt request which is
generated. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention voltage, and the ST62xx core waits for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa-
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock
signal to the peripherals. Timer counting may be
enabled as well as the Timer interrupt, before en-
tering the WAIT mode: this allows the WAIT mode
to be exited when a Timer interrupt occurs. The
same applies to other peripherals which use the
clock signal.
If the STOP state is exited due to a Reset (by acti-
vating the external pin) the MCU will enter a nor-
mal reset procedure. Behaviour in response to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener-
ated.
If the WAIT mode is exited due to a Reset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the state
This case will be described in the following para-
graphs. The processor core generates a delay af-
ter occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
32/84
32
ST62T28C/E28C
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this rou-
tine pending interrupts will be serviced in accord-
ance with their priority.
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
interrupt mode.
Interrupts do not affect the oscillator selection.
3.5.3.1 Normal Mode
If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc-
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
3.5.3.2 Non Maskable Interrupt Mode
If the STOP or WAIT instruction has been execut-
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in-
terrupt mode, even if another interrupt has been
generated.
– placing all peripherals in their power down
modes before entering STOP mode;
When the hardware activated Watchdog is select-
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in-
terrupt, it will stop it generating a wake-up signal.
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
The WAIT and STOP instructions are not execut-
ed if an enabled interrupt request is pending.
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
33/84
33
ST62T28C/E28C
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurations:
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 22. I/O Port Block Diagram
RESET
V
DD
S
CONTROLS
IN
DATA
DIRECTION
REGISTER
V
DD
INPUT/OUTPUT
DATA
REGISTER
SHIFT
REGISTER
OPTION
REGISTER
S
OUT
TO INTERRUPT
TO ADC
VA00413
34/84
34
ST62T28C/E28C
I/O PORTS (Cont’d)
4.1.1 Operating Modes
4.1.1.2 Interrupt Options
Each pin may be individually programmed as input
or output with various configurations.
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR). Table 12 illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.3 Analog Input Options
4.1.1.1 Input Options
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Converter. ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
Table 12. I/O Port Option Selection
DDR
OR
0
DR
0
Mode
Input
Option
0
0
0
0
1
1
With pull-up, no interrupt
0
1
Input
No pull-up, no interrupt
1
0
Input
With pull-up and with interrupt
1
1
Input
Analog input (when available)
0
X
X
Output
Output
Open-drain output (20mA sink when available)
Push-pull output (20mA sink when available)
1
Note: X = Don’t care
35/84
35
ST62T28C/E28C
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure
23. All other transitions are potentially risky and
should be avoided when changing the I/O operat-
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the
analog multiplexer.
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
the conversion.
Figure 23. Diagram showing Safe I/O State Transitions
Interrupt
Input
010*
011
001
pull-up
Analog
Input
pull-up (Reset
000
Input
state)
Output
Output
100
101
111
Open Drain
Open Drain
Output
Push-pull
Output
Push-pull
110
Note *. xxx = DDR, OR, DR Bits respectively
36/84
36
ST62T28C/E28C
I/O PORTS (Cont’d)
Table 13. I/O Port configuration for the ST62T28C/E28C
MODE
AVAILABLE ON(1)
SCHEMATIC
PA0-PA5
Input
PB4-PB6
PC4-PC7
PD1-PD7
(Reset state if PORT
PULL option disabled)
Data in
Interrupt
PA0-PA5
PB4-PB6
PC4-PC7
PD1-PD7
Input
with pull up
Data in
(Reset state if PORT
PULL option enabled)
Interrupt
PA0-PA5
PB4-PB6
PC4-PC7
PD1-PD7
Input
with pull up
with interrupt
Data in
Interrupt
PA4-PA5
PB4-PB6
PC4-PC7
PD1-PD7
Analog Input
ADC
Open drain output
5mA
PB4-PB6
PC4-PC7
PD1-PD7
Data out
Open drain output
20mA
PA0-PA5
Push-pull output
5mA
PB4-PB6
PC4-PC7
PD1-PD7
Data out
VR01992A
Push-pull output
20mA
PA0-PA5
Note 1. Provided the correct configuration has been selected.
37/84
37
ST62T28C/E28C
I/O PORTS (Cont’d)
4.1.3 ARTimer alternate functions
PD3/Sout must be configured in open drain output
mode to be used as data out for the SPI. In output
mode, the value present on the pin is the port data
register content only if PD3 is defined as push pull
output, while serial transmission is possible only in
open drain mode.
When the PWMOE bit of ARMC register is low, the
PA2/ARTIMout pin is configured as any standard
pin of port B through the port registers.
PA2/ARTIMout pin must be configured as output
push-pull through the DDR and OR registers to be
used as PWM output. When the PWMOE bit is set,
PA2/ARTIMout becomes the PWM output.
4.1.5 UART alternate functions
PD4/RXD1 pin must be configured as input
through the DDR and OR registers to be used as
reception line for the UART. All input modes are
available and PD4 can be read independently of
the UART at any time.
ARTIMin/PA3 is connected through the port regis-
ters as any standard pin ofport B. To use PA3/PAR-
TIMin as AR Timer input, it must be configured as
input through DDRB.
PD5/TXD1 pin must be configured as output
through the DDR and OR registers to be used as
transmission line for the UART. Value present on
the pin in output mode is the Data register content
as long as no transmission is active.
4.1.4 SPI alternate functions
PD2/Sin and PD1/Scl pins must be configured as
input through the DDR and OR registers to be
used as data in and data clock (Slave mode) for
the SPI. All input modes are available and I/O's
can be read independently of the SPI at any time.
38/84
38
ST62T28C/E28C
I/O PORTS (Cont’d)
Figure 24. Peripheral Interface Configuration of SPI, UART and AR Timer
V
DD
PID
RXD
PD4/RXD1
PD5/TXD1
PD3/Sout
PD2/Sin
DR
UART
IARTOE
TXD
PID
PID
DR
0
1
MUX
PP/OD
OPR
DR
1
0
MUX
OUT
IN
PID
PID
PID
DR
SYNCHRONOUS
SERIAL I/O
CLOCK
DR
DR
PD1/Scl
ARTIMin
PA3/ARTIMin
ARTIMER
PID
PWMOE
PA2/ARTIMout
ARTIMout
1
0
MUX
DR
VR01661D
39/84
39
ST62T28C/E28C
I/O PORTS (Cont’d)
4.1.6 I/O Port Option Registers
4.1.8 I/O Port Data Registers
ORA/B/C/D (CCh PA, CDh PB, CEh PC, CFh PD)
Read/Write
DRA/B/C/D (C0h PA, C1h PB, C2h PC, C3h PD)
Read/Write
7
0
7
0
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
Bit 7-0 = Px7 - Px0: Port A, B, C, and D Option
Register bits.
Bit 7-0 = Px7 - Px0: Port A, B, C, and D Data Reg-
isters bits.
4.1.7 I/O Port Data Direction Registers
DDRA/B/C/D (C4h PA, C5h PB, C6h PC, C7h PD)
Read/Write
7
0
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
Bit 7-0 = Px7 - Px0: Port A, B, C, and D Data Di-
rection Registers bits.
40/84
40
ST62T28C/E28C
4.2 TIMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program-
mable prescaler, giving a maximum count of 2 .
The peripheral may be configured in three different
operating modes.
The prescaler input can be the internal frequency
f
divided by 12 or an external clock applied to
INT
15
the TIMER pin. The prescaler decrements on the
rising edge. Depending on the division factor pro-
grammed by PS2, PS1 and PS0 bits in the TSCR.
The clock input of the timer/counter register is mul-
tiplexed to different sources. For division factor 1,
the clock input of the prescaler is also that of timer/
counter; for factor 2, bit 0 of the prescaler register
is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres-
caler input clock. For factor 4, bit 1 of the PSC is
connected to the clock input of TCR, and so forth.
The prescaler initialize bit, PSI, in the TSCR regis-
ter must be set to “1” to allow the prescaler (and
hence the counter) to start. If it is cleared to “0”, all
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg-
ister.
Figure 25 shows the Timer Block Diagram. The
external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, while the state of
the 7-bit prescaler can be read in the PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraphs.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
Figure 26 illustrates the Timer’s working principle.
Figure 25. Timer Block Diagram
DATABUS 8
8
8
8
6
5
4
3
2
b5
b1
b0
b7
b6
b4
b3
b2
8-BIT
COUNTER
STATUS/CONTROL
REGISTER
SELECT
1 OF 7
PSC
ETI TOUT
TMZ
PSI
PS1
PS0
DOUT
PS2
1
0
3
TIMER
INTERRUPT
LINE
LATCH
SYNCHRONIZATION
LOGIC
:12
fOSC
VA00009
41/84
41
ST62T28C/E28C
TIMER (Cont’d)
4.2.1 Timer Operating Modes
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bit of the TSCR and trans-
fer it to the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f
the output mode.
÷ 12 or TIMER pin signal), and to
INT
4.2.1.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
Table 14. Timer Operating Modes
In this mode the prescaler is decremented by the
TOUT
DOUT
Timer Pin
Input
Timer Function
Event Counter
Gated Input
Output “0”
Timer clock input (f
÷ 12), but ONLY when the
INT
signal on the TIMER pin is held high (allowing
pulse width measurement). This mode is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
0
0
1
1
0
1
0
1
Input
Output
Output
Output “1”
4.2.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
4.2.2 Timer Interrupt
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request is generated as described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR register is set to
one.
4.2.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler clock input (f
÷ 12).
INT
Figure 26. Timer Working Principle
7-BIT PRESCALER
BIT0
BIT1
BIT2
BIT6
BIT3
BIT4
BIT5
CLOCK
PS0
PS1
PS2
0
1
2
4
7
3
6
5
8-1 MULTIPLEXER
BIT7
BIT2
BIT0
BIT1
BIT3
BIT4
BIT5
BIT6
8-BIT COUNTER
VA00186
42/84
42
ST62T28C/E28C
TIMER (Cont’d)
4.2.3 Application Notes
Bit 4 = DOUT: Data Output
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
Bit 3 = PSI: Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
If the Timer is programmed in output mode, the
DOUT bit is transferred to the TIMER pin when
TMZ is set to one (by software or due to counter
decrement). When TMZ is high, the latch is trans-
parent and DOUT is copied to the timer pin. When
TMZ goes low, DOUT is latched.
Table 15. Prescaler Division Factors
PS2
0
PS1
0
PS0
0
Divided by
1
2
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
0
0
1
0
1
0
4
0
1
1
8
1
0
0
16
32
64
128
1
0
1
1
1
0
1
1
1
4.2.4 Timer Registers
Timer Status Control Register (TSCR)
Address: 0D4h
—
Read/Write
Timer Counter Register TCR
7
0
Address: 0D3h
—
Read/Write
TMZ
ETI
TOUT DOUT PSI
PS2
PS1
PS0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit must
be cleared by user software before starting a new
count.
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Bit 6 = ETI: Enable Timer Interrupt
Address: 0D2h
—
Read/Write
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = TOUT: Timers Output Control
When low, this bit selects the input mode for the
TIMER pin. When high the output mode is select-
ed.
Bit 7 = D7: Always read as “0”.
Bit 6-0 = D6-D0: Prescaler Bits.
43/84
43
ST62T28C/E28C
4.3 AUTO-RELOAD TIMER
The Auto-Reload Timer (AR Timer) on-chip pe-
ripheral consists of an 8-bit timer/counter with
compare and capture/reload capabilities and of a
7-bit prescaler with a clock multiplexer, enabling
the prescaler and counter contents are frozen.
When TEN is set, the AR counter runs at the rate
of the selected clock source. The counter is
cleared on system reset.
the clock input to be selected as f , f
or an
INT INT/3
The AR counter may also be initialized by writing
to the ARLR load register, which also causes an
immediate copy of the value to be placed in the AR
counter, regardless of whether the counter is run-
ning or not. Initialization of the counter, by either
method, will also clear the ARPSC register, where-
upon counting will start from a known value.
external clock source. A Mode Control Register,
ARMC, two Status Control Registers, ARSC0 and
ARSC1, an output pin, ARTIMout, and an input
pin, ARTIMin, allow the Auto-Reload Timer to be
used in 4 modes:
– Auto-reload (PWM generation),
– Output compare and reload on external event
(PLL),
4.3.2 Timer Operating Modes
Four different operating modes are available for
the AR Timer:
– Input capture and output compare for time meas-
urement.
Auto-reload Mode with PWM Generation. This
mode allows a Pulse Width Modulated signal to be
generated on the ARTIMout pin with minimum
Core processing overhead.
– Input capture and output compare for period
measurement.
The AR Timer can be used to wake the MCU from
WAIT mode either with an internal or with an exter-
nal clock. It also can be used to wake the MCU
from STOP mode, if used with an external clock
signal connected to the ARTIMin pin. A Load reg-
ister allows the program to read and write the
counter on the fly.
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
edge of the clock signal.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the Re-
load/Capture Register, ARCC, and ARTIMout is
set. When the counter reaches the value con-
tained in the compare register (ARCP), ARTIMout
is reset.
4.3.1 AR Timer Description
The AR COUNTER is an 8-bit up-counter incre-
mented on the input clock’s rising edge. The coun-
ter is loaded from the ReLoad/Capture Register,
ARRC, for auto-reload or capture operations, as
well as for initialization. Direct access to the AR
counter is not possible; however, by reading or
writing the ARLR load register, it is possible to
read or write the counter’s contents on the fly.
On overflow, the OVF flag of the ARSC0 register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OVIE, in the
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare value, the
CPF flag of the ARSC0 register is set and a com-
pare interrupt request is generated, if the Compare
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set. The interrupt service rou-
tine may then adjust the PWM period by loading a
new value into ARCP. The CPF flag must be reset
by user software.
The AR Timer’s input clock can be either the inter-
nal clock (from the Oscillator Divider), the internal
clock divided by 3, or the clock signal connected to
the ARTIMin pin. Selection between these clock
sources is effected by suitably programming bits
CC0-CC1 of the ARSC1 register. The output of the
AR Multiplexer feeds the 7-bit programmable AR
Prescaler, ARPSC, which selects one of the 8
available taps of the prescaler, as defined by
PSC0-PSC2 in the AR Mode Control Register.
Thus the division factor of the prescaler can be set
to 2n (where n = 0, 1,..7).
The PWM signal is generated on the ARTIMout
pin (refer to the Block Diagram). The frequency of
this signal is controlled by the prescaler setting
and by the auto-reload value present in the Re-
load/Capture register, ARRC. The duty cycle of
the PWM signal is controlled by the Compare Reg-
ister, ARCP.
The clock input to the AR counter is enabled by the
TEN (Timer Enable) bit in the ARMC register.
When TEN is reset, the AR counter is stopped and
44/84
44
ST62T28C/E28C
AUTO-RELOAD TIMER (Cont’d)
Figure 27. AR Timer Block Diagram
DATA BUS
8
AR COMPARE
REGISTER
8
PWMOE
1
R
S
CPF
COMPARE
M
U
X
PA2/
ARTIMout
DR
0
8
OVF
OVF
f
INT
M
OVIE
8-Bit
7-Bit
f
/3
U
X
INT
AR PRESCALER
LOAD
AR COUNTER
TCLD
PS0-PS2
CC0-CC1
EIE
EF
AR TIMER
INTERRUPT
8
CPF
CPIE
8
8
PA3/
ARTIMin
SL0-SL1
AR
AR
EF
RELOAD/CAPTURE
REGISTER
LOAD
SYNCHRO
REGISTER
8
8
DATA BUS
VR01660B
45/84
45
ST62T28C/E28C
AUTO-RELOAD TIMER (Cont’d)
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of PWM output signal. To obtain a signal on ARTI-
Mout, the contents of the ARCP register must be
greater than the contents of the ARRC register.
The ARTC counter is initialized by writing to the
ARRC register and by then setting the TCLD (Tim-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and selection of the clock source is con-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status Control Register, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
The maximum available resolution for the ARTI-
Mout duty cycle is:
Resolution = 1/[255-(ARRC)]
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com-
pare Register, ARCP, must be in the range from
(ARRC) to 255.
In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 28. Auto-reload Timer PWM Function
COUNTER
255
COMPARE
VALUE
RELOAD
REGISTER
000
t
PWM OUTPUT
t
VR001852
46/84
46
ST62T28C/E28C
AUTO-RELOAD TIMER (Cont’d)
Capture Mode with PWM Generation. In this
mode, the AR counter operates as a free running
8-bit counter fed by the prescaler output. The
counter is incremented on every clock rising edge.
the count is incremented on every clock rising
edge.
Each counter overflow sets the ARTIMout pin. A
match between the counter and ARCP (Compare
Register) resets the ARTIMout pin and sets the
compare flag, CPF. A compare interrupt request is
generated if the related compare interrupt enable
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
software.
An 8-bit capture operation from the counter to the
ARRC register is performed on every active edge
on the ARTIMin pin, when enabled by Edge Con-
trol bits SL0, SL1 in the ARSC1 register. At the
same time, the External Flag, EF, in the ARSC0
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
in the ARMC register, is set. The EF flag must be
reset by user software.
Initialization of the counter is as described in the
previous paragraph. In addition, if the external AR-
TIMin input is enabled, an active edge on the input
pin will copy the contents of the ARRC register into
the counter, whether the counter is running or not.
Each ARTC overflow sets ARTIMout, while a
match between the counter and ARCP (Compare
Register) resets ARTIMout and sets the compare
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A PWM signal is generated on ARTI-
Mout. The CPF flag must be reset by user soft-
ware.
Notes:
The allowed AR Timer clock sources are the fol-
lowing:
AR Timer Mode
Auto-reload mode
Capture mode
Clock Sources
, f , ARTIMin
f
f
f
f
INT INT/3
The frequency of the generated signal is deter-
mined by the prescaler setting. The duty cycle is
determined by the ARCP register.
, f
INT INT/3
Capture/Reset mode
External Load mode
, f
INT INT/3
, f
INT INT/3
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip-
tion).
The clock frequency should not be modified while
the counter is counting, since the counter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Enabling and selection of clock sources is control-
led by the CC0 and CC1 bits in the AR Status Con-
trol Register, ARSC1.
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets
the prescaler at the same time.
The prescaler division ratio is selected by pro-
gramming the PS0, PS1 and PS2 bits in the
ARSC1 Register.
Care should be taken when both the Capture inter-
rupt and the Overflow interrupt are used. Capture
and overflow are asynchronous. If the capture oc-
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by software, in the interrupt routine), the Ex-
ternal Interrupt Flag, EF, may be cleared simul-
taneusly without the interrupt being taken into ac-
count.
In Capture mode, the allowed clock sources are
the internal clock and the internal clock divided by
3; the external ARTIMin input pin should not be
used as a clock source.
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi-
cal to the previous one, with the difference that a
capture condition also resets the counter and the
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
The solution consists in resetting the OVF flag by
writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).
Load on External Input. The counter operates as
a free running 8-bit counter fed by the prescaler.
47/84
47
ST62T28C/E28C
AUTO-RELOAD TIMER (Cont’d)
4.3.3 AR Timer Registers
ARSC0 register is also set, an interrupt request is
generated.
AR Mode Control Register (ARMC)
Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
lowing bit combinations will select the various op-
erating modes:
Address: E5h
—
Read/Write
Reset status: 00h
7
0
ARMC1
ARMC0
Operating Mode
Auto-reload Mode
Capture Mode
TCLD
TEN PWMOE
EIE
CPIE OVIE ARMC1 ARMC0
0
0
0
1
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be read and written to by the Core
and it is cleared on system reset (the AR Timer is
disabled).
Capture Mode with Reset
of ARTC and ARPSC
1
1
0
1
Load on External Edge
Mode
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edge and prescaler
multiplexer setting.
Bit 7 = TLCD: Timer Load Bit. This bit, when set,
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
is write-only and any attempt to read it will yield a
logical zero.
ARSC0 register bits 0,1 and 2 contain the interrupt
flags of the AR Timer. These bits are read normal-
ly. Each one may be reset by software. Writing a
one does not affect the bit value.
Bit 6 = TEN: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will
stop the timer and freeze ARPSC and ARTSC.
AR Status Control Register 0 (ARSC0)
Address: E6h
—
Read/Clear
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI-
Mout pin. When reset, the PWM output is disabled.
7
0
D7
D6
D5
D4
D3
EF
CPF
OVF
Bit 4 = EIE: External Interrupt Enable. This bit,
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bits 7-3 = D7-D3: Unused
Bit 2 = EF: External Interrupt Flag. This bit is set by
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. If CPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
ter are equal. The flag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the
48/84
48
ST62T28C/E28C
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
Address: E7h
—
Read/Write
7
0
AR Load Register (ARLR)
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
Address: EBh
—
Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
Table 16. Prescaler Division Ratio Selection
PS2
0
PS1
0
PS0
0
ARPSC Division Ratio
AR Reload/Capture Register. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
1
2
0
0
1
0
1
0
4
0
1
1
8
AR Reload/Capture (ARRC)
1
0
0
16
32
64
128
Address: E9h
—
Read/Write
1
0
1
7
0
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
Bit 4 = D4: Reserved. Must be kept reset.
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
inputpinforexternalsynchronization. IfbitSL0isre-
set, edge detection is disabled; if setedge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
SL1
X
SL0
0
Edge Detection
Disabled
Address: EAh
—
Read/Write
7
0
0
1
Rising Edge
Falling Edge
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clocksources is explained in the following Table
17:
Bit 7-0 = D7-D0: Compare Data Bits. These are
the Compare register data bits.
Table 17. Clock Source Selection.
CC1
CC0
Clock Source
0
0
1
1
0
1
0
1
Fint
Fint Divided by 3
ARTIMin Input Clock
Reserved
49/84
49
ST62T28C/E28C
4.4 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
one instruction before the beginning of the conver-
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of 12 or 6. After Reset, division by 12 is used
by default to insure compatibility with other mem-
bers of the ST62 MCU family. With an oscillator
clock frequency less than 1.2MHz, conversion ac-
curacy is decreased.
Figure 29. ADC Block Diagram
INTERRUPT
CLOCK
Ain
CONVERTER
RESET
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
AV
SS
AV
DD
CONTROL REGISTER
8
RESULT REGISTER
8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
CORE
CORE
CONTROL SIGNALS
VA00418
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
4.4.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
When selected as an analog channel, the input pin
is internally connected to a capacitor C of typi-
ad
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
6.5µs = 9 x C x ASI
ad
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for conversion. This bit must be set at least
cluding a 50% guardband. ASI can be higher if C
ad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
50/84
50
ST62T28C/E28C
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
achieved by setting ADC SYNC option. This way,
ADC conversion starts in effective WAIT for maxi-
mum accuracy.
Note: With this extra option, it is mandatory to ex-
ecute WAIT instruction just after ADC start instruc-
tion. Insertion of any extra instruction may cause
spurious interrupt request at ADC interrupt vector.
The accuracy of the conversion depends on the
quality of the power supplies (V
and V ). The
DD
SS
user must take special care to ensure a well regu-
lated reference voltage is present on the V and
A/D Converter Control Register (ADCR)
DD
Address: 0D1h
—
Read/Write
V
pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
SS
7
0
suitable decoupling capacitor is used at the V
pin.
DD
OSC
OFF
EAI
EOC
STA
PDS CLSEL
D1
D0
The converter resolution is given by:
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
VDD – VSS
---------------------------
256
Bit 6 = EOC: End of conversion. Read Only. This
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Conversion resolution can be improved if the pow-
er supply voltage (V ) to the microcontroller is
DD
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
Bit 5 = STA: Start of Conversion. Write Only. Writ-
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
instruction may cause a small variation of the V
DD
Bit 4 = PDS: Power Down Selection. This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
mode).
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
Bit 3= CLSEL: Clock Selection. When set, the
ADC is driven by the MCU internal clock divided by
6, and typical conversion time at 8MHz is 35µs.
When cleared (Reset state), MCU clock divided by
12 is used with a typical 70µs conversion time at
8MHz.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
Bit 1-0: Reserved. Must be kept cleared.
A/D Converter Data Register (ADR)
One extra feature is available in the ADC to get a
better accuracy. In fact, each ADC conversion has
to be followed by a WAIT instruction to minimize
the noise during the conversion. But the first con-
version step is performed before the execution of
the WAIT when most of clocks signals are still en-
abled . The key is to synchronize the ADC start
with the effective execution of the WAIT. This is
Address: 0D0h
—
Read only
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
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ST62T28C/E28C
4.5 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with an appropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 76,800 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
4.5.1 Ports Interfacing
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as output mode (Push-pull or open drain).
In the 11-bit character format option, the transmit-
ted data is inverted and can therefore use a single
transistor buffering stage. Defined as input, the
RXD line can be read at any time as an I/O line
during the UART operation. The TXD pin follows I/
O port registers value when UARTOE bit is
cleared, which means when no serial transmission
is in progress. As a consequence, a permanent
high level has to be written onto the I/O port in or-
der to achieve a proper stop condition on the TXD
line when no transmission is active.
Operating in Half-Duplex mode only, the UART
uses a 10-bit frame or a 11-bit frame according to
the choosen MCU option. Automatic parity bit gen-
eration is software selectable in the 10-bit charac-
ter format allowing either 7 data bit + 1 parity bit, or
8 data bit transmission. Transmitted data is sent di-
rectly, while received data is buffered allowing fur-
ther data characters to be received while the data
is being read out of the receive buffer register. Data
transmit has priority over data being received.
The UART is supplied with an MCU internal clock
thatisalsoavailableinWAITmodeoftheprocessor.
Figure 30. UART Block Diagram
START
DETECTOR
RXD1
UARTOE
TXD
1
DIN
DOUT
DATA SHIFT
REGISTER
MUX
TXD1
DR
0
D8 D7 D6 D5 D4 D3 D2 D1 D0
WRITE
READ
RECEIVE BUFFER
REGISTER
D8
CONTROL REGISTER
BAUD RATE
RX and TX
INTERRUPTS
PROGRAMMABLE
DIVIDER
f
OSC
BAUD RATE x 8
VR02009
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ST62T28C/E28C
U. A. R. T (Cont’d)
4.5.2 Clock Generation
LSB D0 at first.. The output is then set to 1 for a
period of one bit time to generate a Stop bit, and
then the UARTOE signal returns the TXD1 line to
its alternate I/O function. The end of transmission
is flagged by setting TXMT to 1 and an interrupt is
generated if enabled. The TXMT flag is reset by
writing a 0 to the bit position, it is also cleared au-
tomatically when a new character is written to the
Data Register. TXMT can be set to 1 by software
to generate a software interrupt so care must be
taken in manipulating the Control Register.
The UART contains a built-in divider of the MCU
internal clock for most common Baud Rates as
shown in Table 19. Other baud rate values can be
calculated from the chosen oscillator frequency di-
vided by the Divisor value shown.
The divided clock provides a frequency that is 8
times the desired baud rate. This allows the Data
reception mechanism to provide a 2 to 1 majority
voting system to determine the logic state of the
asynchronous incoming serial logic bit by taking 3
timed samples within the 8 time states.
4.5.3.1 Character Format
Once the MCU option is set as 10-bit or 11-bit
frame, the frame length is fixed. Within these 8 or 9
remaining bit, any format can be used as shown in
the Table 18. Only the even parity automatic com-
putation in the 10-bit frame is available. Any other
parity bit can however be software computed and
processed as a data bit
The bits not sampled provide a buffer to compen-
sate for frequency offsets between sender and re-
ceiver.
4.5.3 Data Transmission
Whatever the format selected as MCU option, 10-
bit or 11-bit frame, the start and stop bit are auto-
matically generated by the UART. Only the re-
maining 8 (Resp. 9) bit in the 10-bit (Resp. 11-bit)
frame are under control of the user.
Table 18. Character Options
10 bit frame
Transmission is started by writing the Data Regis-
ter, after having previously set the transmission
software options, the baudrate and the parity ena-
ble. In case of 11-bit frame, the 9th bit must then
be set before into the LSB of the UART Control
Register. Bit 9 remains in the state programmed
for consecutive transmissions until changed by the
user or until a character is received when the state
of this bit is changed to that of the incoming bit 9.
Start Bit
Start Bit
Start Bit
8 Data
7 Data
7 Data
No Parity
1 Stop
1 Stop
1 Stop
1 Even Parity (Auto)
1 Software Parity
11 bit frame
Start Bit
Start Bit
Start Bit
Start Bit
8 Data
9 Data
8 Data
7 Data
1 Software Parity
No Parity
1 Stop
1 Stop
2 Stop
2 Stop
No Parity
1 Software Parity
The UARTOE signal switches the output multi-
plexer to the UART output and a start bit is sent (a
0 for one bit time) followed by the data bit with the
Figure 31. 11-bit Character Format Example
Figure 32. UART Data Output
UARTOE
START
BIT
STOP
BIT
TXD
1
D0 D1
D7 D8
MUX
TXD1
PORT DATA
OUTPUT
BIT
POSITION
2
8
9
1
10
0
POSSIBLE
NEXT
VR02011
CHARACTER
START
START OF DATA
VR02012
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53
ST62T28C/E28C
U. A. R. T (Cont’d)
4.5.4 Data Reception
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. This implies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. First 8 bit are stored into the UART
Data Register, while the additionnal 9th bit is
stored into the LSB of the UART Control Register
in case of the 11-bit frame MCU option has been
selected. When the 10-bit frame option is selected,
the parity of the 8 received bit is automatically writ-
ten into the LSB of the UART Control Register
(PTYEN bit).
4.5.5 Interrupt Capabilities
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.5.6 Registers
After all bit have been received, the Receiver waits
for the duration of one bit (for the Stop bit) and
then transfers the received data into the buffer reg-
ister, allowing a following character to be received.
The interrupt flag RXRDY is set to 1 as the data is
transferred to the buffer register and, if enabled,
will generate an interrupt.
UART Data Register (UARTDR)
Address: D6h, Read/Write
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit7-Bit0. UART data bits. A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer. If the automatic even parity computation is
set (Bit PTYEN set), D7 must be cleared to 0 be-
fore transmission. Only the 7 LSB D0..D6 contain
the data to be sent.
Figure 33. Data Sampling Points
1 BIT
Warning. No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
0
1
2
3
4
5
6
7
8
SAMPLES
VR02010
Table 19. Baudrate Selection
Baud Rate
BR2
BR1
BR0
f
Division
INT
f
= 8MHz
1200
f
= 4MHz
600
INT
INT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.656
3.328
1.664
832
2400
1200
2400
4800
9600
4800
9600
416
19200
31200
38400
76800
256
15600
19200
38400
208
104
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54
ST62T28C/E28C
U. A. R. T (Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
7
Bit 4 = TXIEN. Transmit Interrupt Enable. When
this bit is set to 1, the transmit interrupt is enabled.
Writing to TXIEN does not affect the status of the
interrupt flag TXRDY.
0
Bit 3-1= BR2..BR0. Baudrate select. These bits
select the operating baud rate of the UART, de-
pending on the frequency of fOSC. Care should be
taken not to change these bits during communica-
tion as writing to these bits has an immediate ef-
fect.
RXRDY TXMT RXIEN TXIEN BR2 BR1 BR0 PTYEN
Bit 7 = RXRDY. Receiver Ready. This flag be-
comes active as soon as a complete byte has
been received and copied into the receive buffer. It
may be cleared by writing a zero to it. Writing a
one is possible. If the interrupt enable bit RXIEN is
set to one, a software interrupt will be generated.
Bit 0 = PTYEN. Parity/Data Bit 8. The function of
this bit depens on the MCU option set. In 11-bit
frame mode, it is the 9th bit of the trasmitted/re-
ceived character. In 10-bit frame mode, writing a 1
enables the automatic even parity computation,
while a read instruction after reception gives the
parity of the whole 8 bit word received. For the
even parity, a 0 value means no parity error.
Bit 6 = TXMT. Transmitter Empty. This flag be-
comes active as soon as a complete byte has
been sent. It may be cleared by writing a zero to it.
It is automatically cleared by the action of writing a
data value into the UART data register.
Bit 5 = RXIEN. Receive Interrupt Enable. When
this bit is set to 1, the receive interrupt is enabled.
Writing to RXIEN does not affect the status of the
interrupt flag RXRDY.
Note: As the PTYEN bit is modified in reception, it
must be to set to 1 before transmission if a recep-
tion occured in between.
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ST62T28C/E28C
4.6 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of indus-
try standard SPI specifications. The on-chip SPI is
controlled by small and simple user software to
perform serial data exchange. The serial shift
clock can be implemented either by software (us-
ing the bit-set and bit-reset instructions), with the
on-chip Timer 1 by externally connecting the SPI
clock pin to the timer pin or by directly applying an
external clock to the Scl line.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I²C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses. Figure 34 shows the SPI
block diagram.
The SCL line clocks, on the falling edge, the shift
register and the counter. To allow SPI operation in
slave mode, the SCL pin must be programmed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
The peripheral is composed by an 8-bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can be tied together
to implement two wires protocols (I²C-bus, etc).
When data is serialized, the MSB is the first bit. Sin
has to be programmed as input. For serial output
operation Sout has to be programmed as open-
drain output.
WARNING: In all cases, in both slave and master
mode, the SCL pin must always be configured as
input (Reset state).
In master mode, the SCL signal must be generat-
ed by software and output on another free I/O port
pin which must be connected externally to the SCL
input pin.
Figure 34. SPI Block Diagram
SPI Interrupt Disable Register
Write
SPI Data Register
Read
CLK
RESET
SCL
I/O Port
Data Reg
Direction
Set Res
DIN
Q4
Q4
RESET
4-Bit Counter
CP
(Q4=High after Clock8)
Sin
I/O Port
Data Reg
Direction
Interrupt
Reset
Load
8-Bit Data
Shift Register
CP
DIN
DOUT
Output
Enable
8-Bit Tristate Data I/O
OPR Reg.
Sout
I/O Port
0
1
DOUT
D0............................D7
to Processor Data Bus
Data Reg
Direction
VR01504
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ST62T28C/E28C
SERIAL PERIPHERAL INTERFACE (Cont’d)
After 8 clock pulses (D7..D0) the output Q4 of the
4-bit binary counter becomes low, disabling the
clock from the counter and the data/shift register.
Q4 enables the clock to generate an interrupt on
the 8th clock falling edge as long as no reset of the
counter (processor write into the 8-bit data/shift
register) takes place. After a processor reset the
interrupt is disabled. The interrupt is active when
writing data in the shift register and desactivated
when writing any data in the SPI Interrupt Disable
register.
As it is possible to directly read the Sin pin directly
through the port register, the software can detect a
difference between internal data and external data
(master mode). Similar condition can be applied to
the clock.
Three (Four) Wire Serial Bus
It is possible to use a single general purpose I/O
pin (with the corresponding interrupt enabled) as a
chip enable pin. SCL acts as active or passive
clock pin, Sin as data in and Sout as data out (four
wire bus). Sin and Sout can be connected together
externally to implement three wire bus.
The generation of an interrupt to the Core provides
information that new data is available (input mode)
or that transmission is completed (output mode),
allowing the Core to generate an acknowledge on
the 9th clock pulse (I²C-bus).
Note:
When the SPI is not used, the three I/O lines (Sin,
SCL, Sout) can be used as normal I/O, with the fol-
lowing limitation: bit Sout cannot be used in open
drain mode as this enables the shift register output
to the port.
The interrupt is initiated by a high to low transition,
and therefore interrupt options must be set accord-
ingly as defined in the interrupt section.
It is recommended, in order to avoid spurious in-
terrupts from the SPI, to disable the SPI interrupt
(the default state after reset) i.e. no write must be
made to the 8-bit shift register. An explicit interrupt
disable may be made in software by a dummy
write to the SPI interrupt disable register.
After power on reset, or after writing the data/shift
register, the counter is reset to zero and the clock
is enabled. In this condition the data shift register
is ready for reception. No start condition has to be
detected. Through the user software the Core may
pull down the Sin line (Acknowledge) and slow
down the SCL, as long as it is needed to carry out
data from the shift register.
SPI Data/Shift Register
Address: DDh - Read/Write (SDSR)
I²C-bus Master-Slave, Receiver-Transmitter
7
0
When pins Sin and Sout are externally connected
together it is possible to use the SPI as a receiver
as well as a transmitter. Through software routine
(by using bit-set and bit-reset on I/O line) a clock
can be generated allowing I²C-bus to work in mas-
ter mode.
D7
D6
D5
D4
D3
D2
D1
D0
A write into this register enables SPI Interrupt after
8 clock pulses.
When implementing an I²C-bus protocol, the start
condition can be detected by setting the processor
into a wait for start condition by enabling the inter-
rupt of the I/O port used for the Sin line. This frees
the processor from polling the Sin and SCL lines.
After the transmission/reception the processor has
to poll for the STOP condition.
SPI Interrupt Disable Register
Address: DCh - Read/Write (SIDR)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
In slave mode the user software can slow down
the SCL clock frequency by simply putting the SCL
I/O line in output open-drain mode and writing a
zero into the corresponding data register bit.
A dummy write to this register disables SPI Inter-
rupt.
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ST62T28C/E28C
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
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ST62T28C/E28C
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
Load & Store. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
All the instructions belonging to a given type are
presented in individual tables.
Table 20. Load & Store Instructions
Flags
Instruction
LD A, X
Addressing Mode
Short Direct
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
LD V, A
LD W, A
LD A, rr
LD rr, A
Direct
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected
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ST62T28C/E28C
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an immediate value in relation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 21. Arithmetic & Logic Instructions
Flags
Instruction
ADD A, (X)
Addressing Mode
Indirect
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
CLR r
COM A
Inherent
Indirect
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
DEC Y
*
DEC V
*
DEC W
*
DEC A
*
DEC rr
Direct
*
DEC (X)
DEC (Y)
INC X
Indirect
*
Indirect
*
Short Direct
Short Direct
Short Direct
Short Direct
Direct
*
INC Y
*
INC V
*
INC W
*
INC A
*
INC rr
Direct
*
INC (X)
Indirect
*
INC (Y)
Indirect
*
RLC A
Inherent
Inherent
Indirect
∆
∆
∆
∆
∆
∆
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Indirect
Direct
Immediate
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register
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ST62T28C/E28C
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 22. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
*
*
*
*
*
*
C
*
JRC e
C = 1
1
1
1
1
3
3
2
2
2
2
5
5
JRNC e
C = 0
Z = 1
*
JRZ e
*
JRNZ e
Z = 0
*
JRR b, rr, ee
JRS b, rr, ee
Bit = 0
Bit = 1
∆
∆
Notes:
b.
e.
3-bit address
rr. Data space register
∆ . Affected. The tested bit is shifted into carry.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
* . Not Affected
Table 23. Bit Manipulation Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
*
SET b,rr
Bit Direct
Bit Direct
2
2
4
4
*
*
RES b,rr
*
Notes:
b.
3-bit address;
* . Not<M> Affected
rr. Data space register;
Table 24. Control Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
NOP
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
RET
*
*
RETI
∆
*
∆
*
STOP (1)
WAIT
*
*
Notes:
1.
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*.
Not Affected
Table 25. Jump & Call Instructions
Instruction
Flags
Addressing Mode
Bytes
Cycles
Z
*
C
*
CALL abc
JP abc
Extended
Extended
2
2
4
4
*
*
Notes:
abc. 12-bit address;
* . Not Affected
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ST62T28C/E28C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW
LOW
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
HI
HI
2
JRNZ 4
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
JRNC
5
JRR 2
b0,rr,ee
bt 1
JRS 2
b0,rr,ee
bt 1
JRR 2
b4,rr,ee
JRZ
2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
#
x
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(x)
a,nn
0000
0000
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC 4
ind
LDI
5
INC 2
1
1
0001
0001
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
imm
CP
5
2
2
#
a,(x)
0010
0010
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
bt 1
JRS 2
pcr
JRZ 4
1
2
prc 1
JRC 4
ind
CPI
5
LD
sd
3
3
b4,rr,ee
e
bt 1
a,x
#
a,nn
0011
0011
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
1
2
prc 2
JRC 4
imm
ADD
a,(x)
5
JRR 2
b2,rr,ee
bt 1
JRS 2
b2,rr,ee
bt 1
JRR 2
b6,rr,ee
bt 1
JRS 2
b6,rr,ee
bt 1
JRR 2
b1,rr,ee
bt 1
JRS 2
b1,rr,ee
bt 1
JRR 2
b5,rr,ee
bt 1
JRS 2
b5,rr,ee
bt 1
JRR 2
b3,rr,ee
bt 1
JRS 2
b3,rr,ee
bt 1
JRR 2
b7,rr,ee
bt 1
JRS 2
b7,rr,ee
4
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
0100
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC 4
ind
ADDI
5
INC 2
5
5
y
a,nn
0101
0101
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
imm
INC
5
6
6
#
(x)
#
0110
0110
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
2
prc 1
JRC
ind
5
LD
sd
7
7
a,y
#
0111
0111
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
1
2
prc
JRC 4
5
LD
ind
8
8
(x),a
#
1000
1000
1
2
pcr 2
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC
RNZ
e
4
5
INC 2
9
9
v
1001
1001
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc
JRC 4
5
AND
a,(x)
A
1010
A
1010
e
e
e
e
e
e
#
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
2
prc 1
JRC 4
ind
ANDI
5
LD
sd
B
1011
B
1011
a,v
#
a,nn
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
1
2
prc 2
JRC 4
imm
SUB
5
C
1100
C
1100
a,(x)
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC 4
ind
SUBI
5
INC 2
D
1101
D
1101
w
a,nn
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
imm
DEC
5
E
1110
E
1110
#
(x)
#
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
2
prc 1
JRC
ind
5
LD
sd
F
1111
F
1111
a,w
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
1
prc
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
Cycle
Mnemonic
2
e
1
JRC
prc
Operand
imm Immediate
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Bytes
abc 12 bit address
ee 8 bit Displacement
Addressing Mode
pcr
ind
Program Counter Relative
Indirect
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ST62T28C/E28C
Opcode Map Summary (Continued)
LOW
LOW
8
9
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
1000
1001
HI
HI
2
JRNZ 4
JP 2
JRNC
4
RES 2
b0,rr
JRZ 4
LDI 2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
rr,nn
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(y)
0000
0000
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b0,rr
1
pcr 3
JRZ 4
imm 1
prc 1
JRC 4
ind
LD
4
DEC
2
1
1
x
a
a,rr
a,(y)
a,rr
0001
0001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b4,rr
1
pcr 1
JRZ 4
sd
1
prc 2
JRC 4
dir
CP
4
COM 2
1
2
2
0010
0010
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
1
pcr
JRZ 4
prc 1
JRC 4
ind
CP
4
SET 2
LD
2
3
3
b4,rr
e
1
x,a
0011
0011
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
pcr 1
JRZ 2
sd
1
prc 2
JRC 4
dir
ADD
a,(y)
4
RES 2
b2,rr
RETI 2
inh 1
4
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
0100
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b2,rr
1
pcr 1
JRZ 4
prc 1
JRC 4
ind
ADD
4
DEC
2
5
5
y
a,rr
(y)
rr
0101
0101
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b6,rr
1
pcr 1
JRZ 2
sd
1
prc 2
JRC 4
dir
INC
4
STOP 2
inh 1
6
6
0110
0110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b6,rr
1
pcr 1
JRZ 4
prc 1
JRC 4
ind
INC
4
LD
2
7
7
y,a
#
0111
0111
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b1,rr
1
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
dir
LD
4
8
8
(y),a
rr,a
1000
1000
1
2
pcr 2
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b1,rr
1
pcr
JRZ 4
1
2
prc 1
JRC 4
ind
LD
RNZ
e
4
4
DEC
sd
9
9
v
1001
1001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b5,rr
1
pcr 1
JRZ 4
1
prc 2
JRC 4
dir
AND
a,(y)
4
RCL 2
A
1010
A
1010
e
e
e
e
e
e
a
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b5,rr
1
pcr 1
JRZ 4
inh 1
prc 1
JRC 4
ind
AND
4
LD
sd
2
1
B
1011
B
1011
v,a
a,rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b3,rr
1
pcr 1
JRZ 2
prc 2
JRC 4
dir
SUB
4
RET 2
C
1100
C
1100
a,(y)
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b3,rr
1
pcr 1
JRZ 4
inh 1
prc 1
JRC 4
ind
SUB
4
DEC
sd
2
1
D
1101
D
1101
w
a,rr
(y)
rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b7,rr
1
pcr 1
JRZ 2
prc 2
JRC 4
dir
DEC
4
WAIT 2
E
1110
E
1110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b7,rr
1
pcr 1
JRZ 4
inh 1
prc 1
JRC 4
ind
DEC
4
LD
sd
2
1
F
1111
F
1111
w,a
1
pcr 2
ext 1
pcr 2
b.d
1
pcr 1
prc 2
dir
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
Cycle
Mnemonic
2
e
1
JRC
prc
Operand
imm Immediate
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Bytes
abc 12 bit address
ee 8 bit Displacement
Addressing Mode
pcr
ind
Program Counter Relative
Indirect
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ST62T28C/E28C
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:
Tj=TA + PD x RthJA
Where:TA = Ambient Temperature.
For proper operation it is recommended that V
I
.
RthJA =Package thermal resistance (junc-
tion-to ambient).
and V be higher than V
and lower than V
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
PD = Pint + Pport.
DD
or V ).
SS
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
Input Voltage
Output Voltage
-0.3 to 7.0
DD
(1)
(1)
V
V
V
- 0.3 to V + 0.3
V
I
SS
SS
DD
V
- 0.3 to V + 0.3
V
O
DD
IV
Total Current into V (source)
80
100
mA
mA
°C
°C
DD
DD
IV
Total Current out of V (sink)
SS
SS
Tj
Junction Temperature
150
T
Storage Temperature
-60 to 150
STG
Notes:
-
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
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ST62T28C/E28C
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Typ.
Symbol
Parameter
Test Conditions
6 Suffix Version
1 Suffix Version
3 Suffix Version
Unit
Min.
Max.
-40
0
-40
85
70
125
TA
Operating Temperature
°C
V
f
f
= 4MHz, 1 & 6 Suffix
= 4MHz, 3 Suffix
3.0
3.0
3.6
4.5
6.0
6.0
6.0
6.0
OSC
OSC
VDD
Operating Supply Voltage
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix
V
V
V
V
= 3.0V, 1 & 6 Suffix
= 3.0V , 3 Suffix
= 3.6V , 1 & 6 Suffix
= 3.6V , 3 Suffix
0
0
0
0
4.0
4.0
8.0
4.0
DD
DD
DD
DD
2)
f
Oscillator Frequency
MHz
OSC
IINJ+
IINJ-
Pin Injection Current (positive) VDD = 4.5 to 5.5V
Pin Injection Current (negative) VDD = 4.5 to 5.5V
+5
-5
mA
mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results
Figure 35. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
1 & 6 Suffix version
8
FUNCTIONALITY IS NOT
3 Suffix version
GUARANTEED IN
7
THIS AREA
6
5
4
3
2
1
3.6
2.5
3
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
65/84
65
ST62T28C/E28C
6.3 DC ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
V
Min.
Max.
x 0.3
V
Input Low Level Voltage
All Input pins
IL
V
DD
V
Input High Level Voltage
All Input pins
IH
V
x 0.7
V
DD
(1)
Hysteresis Voltage
All Input pins
V
V
= 5V
= 3V
0.2
0.2
DD
DD
V
V
Hys
V
LVD Threshold in power-on
LVD threshold in powerdown
4.1
3.8
4.3
up
V
3.5
dn
Low Level Output Voltage
All Output pins
V
V
= 5.0V; I = +10µA
0.1
0.8
DD
DD
OL
= 5.0V; I = + 3mA
OL
V
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
OL
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +7mA
OL
= 5.0V; I = +15mA
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
DD
DD
OH
V
V
OH
= 5.0V; I = -3.0mA
OH
All Input pins
RESET pin
40
100
350
350
900
R
Pull-up Resistance
ΚΩ
PU
150
Input Leakage Current
All Input pins but RESET
V
V
= V (No Pull-Up configured)
IN
IN
SS
0.1
-16
1.0
= V
I
I
DD
IL
µA
Input Leakage Current
RESET pin
V
V
= V
-8
-30
10
IH
IN
IN
SS
= V
DD
Supply Current in RESET
Mode
V
=V
RESET SS
7.0
7.0
1.5
20
mA
mA
mA
µA
f
=8MHz
=5.0V
OSC
Supply Current in
V
V
f
=8MHz
=8MHz
(2)
DD
INT
RUN Mode
Supply Current in WAIT
I
=5.0V
f
INT
(3)
DD
DD
Mode
Supply Current in STOP
Mode, with LVD disabled
I
=0mA
=5.0V
LOAD
(3)
V
DD
Supply Current in STOP
Mode, with LVD enabled
I
V
=0mA
=5.0V
LOAD
500
(3)
DD
Retention EPROM Data Retention
TA = 55°C
10
years
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by
66/84
66
ST62T28C/E28C
DC ELECTRICAL CHARACTERISTICS (Cont’d)
(T = -40 to +85°C unless otherwise specified))
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
V
V
LVD Threshold in power-on
LVD threshold in powerdown
V
+50 mV 4.1
4.3
V
V
up
dn
3.6
3.8
V
-50 mV
dn
up
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.2
DD
DD
DD
OL
Low Level Output Voltage
All Output pins
= 5.0V; I = + 5mA
OL
= 5.0V; I = + 10mAv
OL
V
V
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
2.0
OL
DD
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +10mA
OL
= 5.0V; I = +20mA
OL
= 5.0V; I = +30mA
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
DD
DD
OH
V
I
V
OH
= 5.0V; I = -5.0mA
OH
Supply Current in STOP
I
=0mA
=5.0V
LOAD
10
µA
(*)
DD
Mode, with LVD disabled
V
DD
Note:
(*) All Peripherals in stand-by.
6.4 AC ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
100
200
Max.
800
(1)
t
Supply Recovery Time
ms
REC
f
Internal frequency with LFAO active
400
kHz
LFAO
V
= 3V
1
1
2
2
DD
Internal Frequency with OSG
enabled
V
V
V
= 3.6V
= 4.5V
= 6V
DD
DD
DD
f
f
MHz
2)
OSG
OSC
VDD=5.0V
Internal frequency with RC oscillator R=47kΩ
4
2.7
800
5
3.2
850
5.8
3.5
900
MHz
MHz
kHz
f
2) 3)
RC
and OSG disabled
R=100kΩ
R=470kΩ
C
Input Capacitance
Output Capacitance
All Inputs Pins
10
10
pF
pF
IN
C
All Outputs Pins
OUT
Notes:
1. Period for which V has to be connected at 0V to allow internal Reset function at next power-up.
DD
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.
67/84
67
ST62T28C/E28C
6.5 A/D CONVERTER CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
8
Symbol
Parameter
Test Conditions
Unit
Bit
Min.
Max.
Res
Resolution
Total Accuracy
f
f
> 1.2MHz
> 32kHz
±2
±4
(1) (2)
OSC
OSC
A
LSB
TOT
f
f
= 8MHz (T < 85°C)
= 4 MHz
70
140
OSC
OSC
A
t
Conversion Time
Zero Input Reading
Full Scale Reading
µs
C
Conversion result when
= V
ZIR
00
Hex
Hex
V
IN
SS
Conversion result when
V
FSR
FF
= V
IN
DD
Analog Input Current During
Conversion
AD
V
= 4.5V
1.0
5
µA
I
DD
AC
Analog Input Capacitance
2
pF
IN
Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
6.6 TIMER CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
fINT
---------
4
f
Input Frequency on TIMER Pin
Pulse Width at TIMER Pin
MHz
IN
V
V
= 3.0V
>4.5V
1
125
µs
ns
DD
DD
t
W
6.7 SPI CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
500
F
Clock Frequency
Set-up Time
Hold Time
Applied on Scl
Applied on Sin
Applied onSin
kHz
ns
CL
t
250
50
SU
t
ns
h
6.8 ARTIMER ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ
Symbol
Parameter
Test Conditions
Unit
Min
Max
fINT
4
2
RUN and WAIT Modes
STOP mode
---------
f
Input Frequency on ARTIMin Pin
MHz
IN
68/84
68
ST62T28C/E28C
Figure 36.. RC frequency versus Vcc
10
R=47K
R=100K
R=470K
1
0.1
3
3.5
4
4.5
5
5.5
6
VDD (volts)
This curves represents typical variations and is given for guidance only
Figure 37. LVD thresholds versus temperature
4.2
4.1
4
Vup
Vdn
3.9
3.8
3.7
3.6
-40°C
25°C
95°C
125°C
Temp
This curves represents typical variations and is given for guidance only
69/84
69
ST62T28C/E28C
Figure 38. Idd WAIT versus Vcc at 8 Mhz for OTP devices
1.2
1
0.8
0.6
0.4
0.2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 39. Idd STOP versus Vcc for OTP devices
8
6
4
2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
-2
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 40. Idd STOP versus Vcc for ROM devices
2
1.5
1
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0.5
0
-0.5
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
70/84
70
ST62T28C/E28C
Figure 41. Idd WAIT versus Vcc at 8Mhz for ROM devices
0.8
0.6
0.4
0.2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 42. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices
8
6
4
2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 43. Vol versus Iol on all I/O port at Vdd=5V
8
6
4
2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
71/84
71
ST62T28C/E28C
Figure 44. Vol versus Iol on all I/O port at T=25°C
8
6
4
2
0
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
Figure 45. Vol versus Iol for High sink (20mA) I/Oports at T=25°C
5
4
3
2
1
0
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
0
10
20
30
40
Iol (mA)
Figure 46. Vol versus Iol for High sink (20mA) I/O ports at Vdd=5V
5
4
3
2
1
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
72/84
72
ST62T28C/E28C
Figure 47. Voh versus Ioh on all I/O port at 25°C
6
4
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
2
0
-2
0
10
20
30
40
Ioh (mA)
Figure 48. Voh versus Ioh on all I/O port at Vdd=5V
6
4
2
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0
-2
0
10
20
30
40
Ioh (mA)
This curves represents typical variations and is given for guidance only
73/84
73
ST62T28C/E28C
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 49. 28-Pin Plastic Dual In-Line Package, 600-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
E
A
6.35
0.250
A2 A
A1 0.38
A2 3.18
0.015
4.95 0.125
0.56 0.014
1.78 0.030
0.38 0.008
39.75 1.380
0.005
0.195
0.022
0.070
0.015
1.565
L
A1
E1
eB
C
B
0.36
D1
B1
B
e
B1 0.76
D
C
D
0.20
35.05
D1 0.13
e
2.54
0.100
eB
17.78
0.700
0.625
0.580
0.200
E
15.24
15.88 0.600
14.73 0.485
5.08 0.115
E1 12.32
L
2.92
Number of Pins
N
28
Figure 50. 28-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
D
h x 45×
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
18.10 0.697
7.60 0.291
0.104
0.012
0.020
0.013
0.713
0.299
L
A
A1 0.10
C
A1
B
C
D
E
e
0.33
0.23
a
e
B
17.70
7.40
1.27
0.050
H
h
α
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
L
0.40
1.27 0.016
0.050
Number of Pins
N
28
74/84
74
ST62T28C/E28C
PACKAGE MECHANICAL DATA (Cont’d)
Figure 51. 28-Pin Ceramic Side-Brazed Dual In-Line Package
mm
inches
Dim.
Min Typ Max Min Typ Max
4.17 0.164
A
A1 0.76
0.030
B
0.36 0.46 0.56 0.014 0.018 0.022
B1 0.76 1.27 1.78 0.030 0.050 0.070
C
D
0.20 0.25 0.38 0.008 0.010 0.015
34.95 35.56 36.17 1.376 1.400 1.424
D1
33.02
1.300
E1 14.61 15.11 15.62 0.575 0.595 0.615
e
2.54
0.100
G
12.70 12.95 13.21 0.500 0.510 0.520
G1 12.70 12.95 13.21 0.500 0.510 0.520
G2
L
1.14
0.045
2.92
5.08 0.115
0.200
CDIP28W
S
1.27
8.89
0.050
0.350
Ø
Number of Pins
N
28
Figure 52. 28-Pin Plastic Shrink Small Outline Package
mm
Min Typ Max Min Typ Max
2.00 0.079
inches
Dim.
D
L
A
A2
A
c
A1
A1 0.05
0.002
b
A2 1.65 1.75 1.85 0.065 0.069 0.073
h
e
b
c
0.22
0.09
0.38 0.009
0.25 0.004
0.015
0.010
D
E
9.90 10.20 10.50 0.390 0.402 0.413
7.40 7.80 8.20 0.291 0.307 0.323
E1 5.00 5.30 5.60 0.197 0.209 0.220
E1
E
e
θ
0.65
0.026
0°
4°
8°
0°
4°
8°
L
0.55 0.75 0.95 0.022 0.030 0.037
Number of Pins
N
28
75/84
75
ST62T28C/E28C
THERMAL CHARACTERISTIC
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
70
PDIP28
RthJA
Thermal Resistance
°C/W
PSO28
70
7.2 ORDERING INFORMATION
Table 26. OTP/EPROM VERSION ORDERING INFORMATION
Program
Sales Type
I/O
Temperature Range
Package
Memory (Bytes)
ST62E28CF1
7948 (EPROM)
0 to 70°C
CDIP28W
PDIP28
PSO28
ST62T28CB6
ST62T28CM6
ST62T28CN6
ST62T28CB3
ST62T28CM3
ST62T28CN3
7948 (OTP)
7948 (OTP)
-40 to 85°C
20
SSOP28
PDIP28
PSO28
-40 to +125°C
SSOP28
76/84
76
ST62P28C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
PRODUCT PREVIEW
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ 20 I/O pins, fully programmable as:
PDIP28
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
PS028
prescaler (AR Timer)
■ Digital Watchdog
■ 8-bit A/D Converter with 12 analog inputs
■ 8-bit Asynchronous Peripheral Interface
(UART)
■ 8-bit Synchronous Peripheral Interface (SPI)
■ On-chip Clock oscillator can be driven by Quartz
SS0P28
Crystal, Ceramic resonator or RC Network
■ Oscillator Safe Guard
(See end of Datasheet for Ordering Information)
■ Low Voltage Detector for safe Reset
■ One external Non-Maskable Interrupt
■ ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
ROM
DEVICE
I/O Pins
(Bytes)
ST62P28C
7948
20
Rev. 2.9
July 2001
77/84
77
ST62P28C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The selected options are communicated to STMi-
croelectronics using the correctly filled OPTION
LIST appended. See page 82.
The ST62P28C are the Factory Advanced Service
Technique ROM (FASTROM) versions of
ST62T18C OTP devices.
1.2.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the ROM con-
tents and options which will be used to produce
the specified MCU. The listing is then returned to
the customer who must thoroughly check, com-
plete, sign and return it to STMicroelectronics. The
signed listing forms a part of the contractual agree-
ment for the production of the specific customer
MCU.
They offer the same functionality as OTP devices,
selecting as FASTROM options the options de-
fined in the programmable option byte of the OTP
version. They also offer an identifier option. If this
option is enabled, each FASTROM device is pro-
grammed with a unique 5-byte number which is
mapped at addresses 0F9Bh-0F9Fh. The user
must therefore leave these bytes blanked.
The identification number is structured as follows:
0F9Bh
0F9Ch
0F9Dh
0F9Eh
0F9Fh
T0
T1
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
T2
T3
Table 1. ROM Memory Map for ST62P28C
Test ID
ROM Page Device Address
Description
with T0, T1, T2, T3 = time in seconds since 01/01/
1970 and Test ID = Tester Identifier.
0000h-007Fh
Page 0
Reserved
User ROM
0080h-07FFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
1.2 ORDERING INFORMATION
Page 1
“STATIC”
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
1.2.1 Transfer of Customer Code
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Page 2
Page 3
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Table 2. ROM version Ordering Information
Sales Type
ROM
I/O
Temperature Range
Package
ST62P28CB1/XXX
ST62P28CB6/XXX
ST62P28CB3/XXX(*)
0 to +70°C
-40 to 85°C
PDIP28
-40 to + 125°C
ST62P28CM1/XXX
ST62P28CM6/XXX
ST62P28CM3/XXX(*)
0 to +70°C
-40 to 85°C
7948
20
PSO28
-40 to + 125°C
ST62P28CN1/XXX
ST62P28CN6/XXX
ST62P28CN3/XXX(*)
0 to +70°C
-40 to 85°C
SSOP28
-40 to + 125°C
(*) Advanced information
78/84
78
ST6228C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
PRODUCT PREVIEW
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ 20 I/O pins, fully programmable as:
PDIP28
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
PS028
prescaler (AR Timer)
■ Digital Watchdog
■ 8-bit A/D Converter with 12 analog inputs
■ 8-bit Asynchronous Peripheral Interface
(UART)
■ 8-bit Synchronous Peripheral Interface (SPI)
■ On-chip Clock oscillator can be driven by Quartz
SS0P28
Crystal, Ceramic resonator or RC Network
■ Oscillator Safe Guard
(See end of Datasheet for Ordering Information)
■ Low Voltage Detector for safe Reset
■ One external Non-Maskable Interrupt
■ ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
ROM
DEVICE
I/O Pins
(Bytes)
ST6228C
7948
20
Rev. 2.9
July 2001
79/84
79
ST6228C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
1.2 ROM READOUT PROTECTION
The ST6228C is mask programmed ROM version
of ST62T28C OTP devices.
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin.
Figure 1. Programming wave form
Figure 2. Programming Circuit
0.5s min
TEST
5V
47mF
15
14V typ
10
100nF
5
V
SS
V
DD
TEST
150 µs typ
PROTECT
100mA
max
14V
TEST
100nF
ZPD15
15V
VR02003
4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection
80/84
80
ST6228C
1.3 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
part of the contractual agreement for the creation
of the specific customer mask.
1.3.1 Transfer of Customer Code
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
Table 1. ROM Memory Map for ST6228C
ROM Page Device Address
Description
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended. See page 82.
0000h-007Fh
Page 0
Reserved
User ROM
0080h-07FFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
1.3.2 Listing Generation and Verification
Page 1
“STATIC”
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Page 2
Page 3
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Table 2. ROM version Ordering Information
Sales Type
ROM
I/O
Temperature Range
Package
ST6228CB1/XXX
ST6228CB6/XXX
ST6228CB3/XXX
0 to +70°C
-40 to 85°C
PDIP28
-40 to + 125°C
ST6228CM1/XXX
ST6228CM6/XXX
ST6228CM3/XXX
0 to +70°C
-40 to 85°C
7948
20
PSO28
-40 to + 125°C
ST6228CN1/XXX
ST6228CN6/XXX
ST6228CN3/XXX
0 to +70°C
-40 to 85°C
SSOP28
-40 to + 125°C
81/84
81
ST6228C
ST6228C/P28C MICROCONTROLLER OPTION LIST
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone:
Reference:
STMicroelectronics references:
Device:
[ ] ST6228C (8 KB)
[ ] ST62P28C (8 KB)
Package:
[ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditioning
[ ] Shrink Small Outline Plastic with conditioning
Conditioning option:
Temperature Range:
[ ] Standard (Tube)
[ ] Tape & Reel
[ ] 0°C to + 70°C
[ ] - 40°C to + 125°C
[ ] - 40°C to + 85°C
Marking:
[ ] Standard marking
[ ] Special marking (ROM only):
PDIP28 (10 char. max): _ _ _ _ _ _ _ _ _ _
PSO28 (8 char. max): _ _ _ _ _ _ _ _
SSOP28 (11 char. max): _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Oscillator Safeguard:
Watchdog Selection:
[ ] Enabled
[ ] Software Activation
[ ] Hardware Activation
[ ] Disabled
Timer pull-up:
NMI pull-up:
Port pull-up:
[ ] Enabled
[ ] Enabled
[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
Oscillator Selection:
[ ] Quartz crystal / Ceramic resonator
[ ] RC network
Readout Protection:
FASTROM:
[ ] Enabled
[ ] Disabled
ROM:
[ ] Enabled:
[ ] Fuse is blown by STMicroelectronics
[ ] Fuse can be blown by the customer
[ ] Disabled
Low Voltage Detector:
External STOP Mode Control:
UART Frame:
[ ] Enabled
[ ] Enabled
[ ] 10-bit
[ ] Disabled
[ ] Disabled
[ ] 11-bit
ADC Synchro:
Identifier (FASTROM only):
[ ] Enabled
[ ] Enabled
[ ] Disabled
[ ] Disabled
Comments:
Oscillator Frequency in the application:
Supply Operating Range in the application:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
Date:
Signature:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82/84
82
ST6228C
2 SUMMARY OF CHANGES
Rev.
Main Changes
Date
Changed section 1.1 on page 78.
Changed section 4.1.3 on page 38.
Changed Figure 24 on page 39.
Changed Figure 27 on page 45.
2.9
July 2001
Changed Figure 49 and Figure 50 on page 74 and Figure 52 on page 75.
Changed option list (page 82).
83/84
83
ST6228C
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
84/84
84
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