ST72251G2M6/XXX [ETC]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | ST72251G2M6/XXX |
| 厂家： | 
ETC |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总100页 (文件大小：601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72251
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,
2
256 BYTES RAM, ADC, WDG, SPI, I C AND 2 TIMERS
DATASHEET
■ User Program Memory (ROM/OTP/EPROM):
4 to 8K bytes
■ Data RAM: 256 bytes, including 64 bytes of
stack
■ Master Reset and Power-On Reset
■ Run, Wait, Slow and Halt modes
■ 22 multifunctional bidirectional I/O lines:
PSDIP32
– 22 programmable interrupt inputs
– 8 high sink outputs
– 6 Analog alternate inputs
– 16 Alternate Functions
– EMI filtering
■ Programmable watchdog (WDG)
■ Two 16-bit Timers, each featuring:
– 2 Input Captures
– 2 Output Compares
CSDIP32W
– External Clock input (on Timer A only)
– PWM and Pulse Generator modes
■ Synchronous Serial Peripheral Interface (SPI)
2
■ Full I C multiple Master/Slave interface
■ 8-bit Analog-to-Digital converter (6 channels)
■ 8-bit Data Manipulation
■ 63 Basic Instructions
■ 17 main Addressing Modes
SO28
(See ordering information at the end of datasheet)
■ 8 x 8 Unsigned Multiply Instruction
■ True Bit Manipulation
Device Summary
■ Complete Development Support on PC/DOS-
TM
WINDOWS Real-Time Emulator
Features
ST72251G1
ST72251G2
■ Full Software Package on DOS/WINDOWSTM
Program Memory
- bytes
(C-Compiler, Cross-Assembler, Debugger)
4K
8K
RAM (stack) - bytes
Peripherals
256 (64)
2
Watchdog, Timers, SPI, I C, ADC
3 to 5.5 V
Operating Supply
8MHz max (16MHz oscillator)
CPU Frequency
4MHz max over 85°C
Temperature Range
Package
- 40°C to + 125°C
SO28 - SDIP32
Rev. 1.9
June 2001
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1
Table of Contents
ST72251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.4 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
95
5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.4.8 Application Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.4 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.6 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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7.8 I2C CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
95
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ST72251
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72251 HCMOS Microcontroller Unit is a
member of the ST7 family of Microcontrollers. The
device is based on an industry-standard 8-bit core
and features an enhanced instruction set. The de-
vice normally operates at a 16MHz oscillator fre-
quency. Under software control, the ST72251 may
be placed in either WAIT, SLOW or HALT modes,
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential. In addition to standard 8-
bit data management, the ST72251 features true
bit manipulation, 8x8 unsigned multiplication and
indirect addressing modes on the whole memory.
The device includes an on-chip oscillator, CPU,
program memory (ROM/OTP/EPROM versions),
RAM, 22 I/O lines and the following on-chip pe-
ripherals: Analog-to-Digital converter (ADC) with 6
multiplexed analog inputs, industry standard syn-
2
chronous SPI serial interface, I C multiple Master/
Slave interface, digital Watchdog, two independ-
ent 16-bit Timers, one featuring an External Clock
Input, and both featuring Pulse Generator capabil-
ities, 2 Input Captures and 2 Output Compares.
Figure 1. ST72251 Block Diagram
2
Internal
CLOCK
I C
OSCIN
OSC
OSCOUT
PA0 -> PA7
(8 bits)
PORT A
SPI
CONTROL
RESET
PORT B
TIMER A
PORT C
8-BIT ADC
TIMER B
PB0 -> PB7
(8 bits)
8-BIT CORE
ALU
PROGRAM
MEMORY
PC0 -> PC5
(6 bits)
(4 - 8K Bytes)
RAM
(256 Bytes)
V
WATCHDOG
DD
POWER
SUPPLY
V
SS
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ST72251
1.2 PIN DESCRIPTION
Figure 2. ST72251 Pinout (SDIP32)
V
V
1
2
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DD
SS
1)
TEST/V
PA0
PA1
PA2
PA3
NC
NC
PA4/SCL
PA5
PA6/SDA
PA7
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/CLKOUT/AIN2
3
PP
4
5
6
MISO/PB5
MOSI/PB4
7
8
NC
9
NC
10
11
12
13
14
15
16
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1) V
PP
on EPROM/OTP only
Figure 3. ST72251 Pinout (SO28)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
OSCIN
OSCOUT
V
V
DD
SS
2
1)
3
TEST/V
PA0
PP
4
SS/PB7
SCK/PB6
MISO/PB5
5
PA1
6
PA2
PA3
7
MOSI/PB4
8
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
PA4/SCL
PA5
9
10
11
12
PA6/SDA
PA7
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/CLKOUT/AIN2
13
14
1) V
on EPROM/OTP only
PP
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ST72251
Table 1. ST72251 Pin Configuration
Pin n° Pin n°
SDIP32 SO28
Pin Name
RESET
Type
Description
Remarks
1
2
1
2
3
4
5
6
7
I/O Bidirectional. Active low. Top priority non maskable interrupt.
I
OSCIN
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal,
or an external source to the on-chip oscillator.
3
OSCOUT
PB7/SS
O
4
I/O Port B7 or SPI Slave Select (active low)
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
5
PB6/SCK
PB5/MISO
PB4/MOSI
NC
I/O Port B6 or SPI Serial Clock
I/O Port B5 or SPI Master In/ Slave Out Data
I/O Port B4 or SPI Master Out / Slave In Data
Not Connected
6
7
8
9
NC
Not Connected
10
11
12
13
14
8
9
PB3/OCMP2_A
PB2/ICAP2_A
I/O Port B3 or TimerA Output Compare 2
I/O Port B2 or TimerA Input Capture 2
I/O Port B1 or TimerA Output Compare 1
I/O Port B0 or TimerA Input Capture 1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
10 PB1/OCMP1_A
11 PB0/ICAP1_A
12 PC5/EXTCLK_A/AIN5 I/O Port C5 or TimerA Input Clock or ADC Analog Input 5 External Interrupt: EI1
Port C4 or TimerB Output Compare 2 or ADC
15
16
13 PC4/OCMP2_B/AIN4
I/O
External Interrupt: EI1
Analog Input 4
Port C3 or TimerB Input Capture 2 or ADC Analog
Input 3
14 PC3/ICAP2_B/AIN3
I/O
External Interrupt: EI1
Port C2 or Internal Clock Frequency output or ADC
I/O Analog Input 2. Clockout is driven by the MCO bit External Interrupt: EI1
of the miscellaneous register.
17
15 PC2/CLKOUT/AIN2
Port C1 or TimerB Output Compare 1 or ADC
Analog Input 1
18
19
16 PC1/OCMP1_B/AIN1
17 PC0/ICAP1_B/AIN0
I/O
I/O
External Interrupt: EI1
External Interrupt: EI1
Port C0 or TimerB Input Capture 1 or ADC Analog
Input 0
20
21
22
23
24
25
26
27
28
29
18 PA7
19 PA6/SDA
20 PA5
21 PA4/SCL
NC
I/O Port A7, High Sink
External Interrupt: EI0
External Interrupt: EI0
External Interrupt: EI0
External Interrupt: EI0
2
I/O Port A6 or I C Data, High Sink
I/O Port A5, High Sink
2
I/O Port A4 or I C Clock, High Sink
Not Connected
Not Connected
NC
22 PA3
23 PA2
24 PA1
25 PA0
I/O Port A3, High Sink
I/O Port A2, High Sink
I/O Port A1, High Sink
I/O Port A0, High Sink
External Interrupt: EI0
External Interrupt: EI0
External Interrupt: EI0
External Interrupt: EI0
Test mode pin (should be tied low in user mode). In the EPROM program-
30
26 TEST/V
I/S
PP
ming mode, this pin acts as the programming voltage input V
PP.
31
32
27
28
V
V
S
S
Ground
SS
DD
Main power supply
7/100
6
ST72251
1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended ex-
ternal connections for the device.
The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.
The V pin is only used for programming OTP
PP
and EPROM devices and must be tied to ground in
user mode.
Unused I/Os should be tied high to avoid any un-
necessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC per-
formance/cost tradeoff.
Figure 4. Recommended External Connections
V
PP
V
V
DD
DD
SS
+
0.1µF
10nF
V
V
DD
4.7K
0.1µF
0.1µF
RESET
EXTERNAL RESET CIRCUIT
See
Clocks
OSCIN
Section
OSCOUT
Or configure unused I/O ports
by software as input with pull-up
10K
V
DD
Unused I/O
8/100
7
ST72251
1.4 MEMORY MAP
Figure 5. Memory Map
0000h
0080h
HW Registers
(see Table 3)
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
16-bit Addressing
RAM
256 Bytes RAM
Reserved
013Fh
0140h
017Fh
0180h
64 Bytes Stack/
16-bit Addressing RAM
017Fh
DFFFh
E000h
8K Bytes
Program Memory
F000h
4K Bytes
Program
Memory
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 2)
FFFFh
Table 2. Interrupt Vector Map
Vector Address
Description
Remarks
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h
FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
Not Used
Not Used
2
I C Interrupt Vector
Not Used
Internal Interrupt
Internal Interrupt
Not Used
Not Used
Not Used
TIMER B Interrupt Vector
Not Used
TIMER A Interrupt Vector
SPI Interrupt Vector
Not Used
Internal Interrupt
Internal Interrupt
External Interrupt Vector EI1
External Interrupt Vector EI0
External Interrupt
External Interrupt
CPU Interrupt
TRAP (software) Interrupt Vector
RESET Vector
9/100
8
ST72251
Table 3. Hardware Register Memory Map
Block
Address
Register Label
Register name
Reset Status
Remarks
Name
0000h
PCDR
PCDDR
PCOR
Data Register
00h
00h
00h
R/W
R/W
R/W
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
Port C
Data Direction Register
Option Register
Reserved Area (1 Byte)
PBDR
Data Register
00h
00h
00h
R/W
R/W
R/W
Port B
Port A
PBDDR
PBOR
Data Direction Register
Option Register
Reserved Area (1 Byte)
PADR
Data Register
00h
00h
00h
R/W
R/W
R/W
PADDR
PAOR
Data Direction Register
Option Register
000Bh to
001Fh
Reserved Area (21 Bytes)
0020h
0021h
0022h
0023h
0024h
MISCR
SPIDR
SPICR
SPISR
WDGCR
Miscellaneous Register
Data I/O Register
00h
xxh
0xh
00h
7Fh
R/W
R/W
SPI
Control Register
Status Register
Read Only
R/W
WDG
Watchdog Control register
0025h to
0027h
Reserved Area (3 Bytes)
R/W
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
I2CCR
Control Register
00h
00h
00h
00h
00h
40h
00h
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Status Register 1
Read Only
Read Only
R/W
Status Register 2
2
I C
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register
R/W
R/W
R/W
002Fh
0030h
Reserved Area (2 Bytes)
Control Register2
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
0031h
TACR2
Control Register1
R/W
0032h
TACR1
Status Register
Read Only
Read Only
Read Only
R/W
0033h
TASR
0034h-0035h
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer A TACHR
TACLR
Counter Low Register
TAACHR
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
R/W
0040h
Reserved Area (1 Byte)
10/100
9
ST72251
Block
Name
Address
0041h
Register Label
Register name
Control Register2
Reset Status
Remarks
TBCR2
TBCR1
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
0042h
Control Register1
0043h
0044h-0045h
TBSR
Status Register
Read Only
Read Only
Read Only
R/W
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
0046h-0047h
0048h-0049h
004Ah-004Bh
004Ch-004Dh
004Eh-004Fh
R/W
Timer B TBCHR
TBCLR
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Counter Low Register
TBACHR
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
R/W
0050h to
006Fh
Reserved Area (32 Bytes)
0070h
0071h
ADCDR
ADC
Data Register
00h
00h
Read Only
R/W
ADCCSR
Control/Status Register
0072h to
007Fh
Reserved Area (14 Bytes)
11/100
10
ST72251
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
2.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 6. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H I N Z
C
X
CONDITION CODE REGISTER
RESET VALUE =
8
1
X 1 X X
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
12/100
11
ST72251
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative.
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
th
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
13/100
12
ST72251
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Read/Write
Reset Value: 01 7Fh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
1
SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 64 bytes deep, the 10 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP5 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 7. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0140h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCH
PCL
SP
PCL
@ 017Fh
Stack Lower Address = 0140h
017Fh
Stack Higher Address =
14/100
13
ST72251
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
Figure 8. External Clock Source Connections
The MCU accepts either a Crystal or Ceramic res-
onator, or an external clock signal to drive the in-
ternal oscillator. The internal clock (f
) is de-
CPU
rived from the external oscillator frequency (f
)
OSC .
The external Oscillator clock is first divided by 2,
and a division factor of 32 can be applied if Slow
Mode is selected by setting the SMS bit in the Mis-
cellaneous Register. This reduces the frequency
OSCIN
OSCOUT
NC
of the f
on-chip peripherals.
; the clock signal is also routed to the
CPU
EXTERNAL
CLOCK
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resona-
tor in the frequency range specified for f . The
osc
circuit shown in Figure 9 is recommended when
using a crystal, and Table 4 lists the recommend-
ed capacitance and feedback resistance values.
The crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
Figure 9. Crystal/Ceramic Resonator
Use of an external CMOS oscillator is recom-
mended when crystals outside the specified fre-
quency ranges are to be used.
OSCIN
OSCOUT
Table 4. .Recommended Values for 16 MHz
Crystal Resonator (C < 7pF)
0
R
40 Ω
56pF
56pF
60 Ω
47pF
47pF
150 Ω
22pF
22pF
C
SMAX
C
OSCIN
OSCOUT
C
OSCIN
C
OSCOUT
C : parasitic shunt capacitance of the quartz crys-
0
tal.
SMAX
Figure 10. Clock Prescaler Block Diagram
R
: equivalent serial resistor of the crystal (up-
er limit, see crystal specification).
C
, C : maximum total capacitance on
OSCOUT
OSCIN
OSCIN and OSCOUT, including the external ca-
pacitance plus the parasitic capacitance of the
board and the device.
%2
% 16
f
CPU
to CPU and
Peripherals
OSCIN OSCOUT
C
C
OSCIN
OSCOUT
15/100
14
ST72251
3.2 RESET
3.2.1 Introduction
lowing a Reset event, or after exiting Halt mode, a
4096 CPU Clock cycle delay period is initiated in
order to allow the oscillator to stabilise and to en-
sure that recovery has taken place from the Reset
state.
There are three sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
In the high state, the RESET pin is connected in-
ternally to a pull-up resistor (R ). This resistor
ON
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
can be pulled low by external circuitry to reset the
device.
3.2.2 External Reset
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to use the exter-
nal connections shown in Figure 4.
The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low, for a duration of t
the whole application.
to reset
RESET,
3.2.4 Power-on Reset
This circuit detects the ramping up of V , and
DD
3.2.3 Reset Operation
generates a pulse that is used to reset the applica-
The duration of the Reset state is a minimum of
4096 internal CPU Clock cycles. During the Reset
state, all I/Os take their reset value.
tion (at approximately V = 2V).
DD
Power-On Reset is designed exclusively to cope
with power-up conditions, and should not be used
in order to attempt to detect a drop in the power
supply voltage.
A Reset signal originating from an external source
must have a duration of at least t
be recognised. This detection is asynchronous
and therefore the MCU can enter Reset state even
in Halt mode.
in order to
PULSE
Caution: to re-initialize the Power-On Reset, the
power supply must fall below approximately 0.8V
(Vtn), prior to rising above 2V. If this condition is
not respected, on subsequent power-up the Reset
pulse may not be generated. An external Reset
pulse may be required to correctly reactivate the
circuit.
At the end of the Reset cycle, the MCU may be
held in the Reset state by an External Reset sig-
nal. The RESET pin may thus be used to ensure
V
has risen to a point where the MCU can oper-
DD
ate correctly before the user program is run. Fol-
Figure 11. Reset Block Diagram
INTERNAL
RESET
OSCILLATOR
SIGNAL
TO ST7
RESET
RESET
V
DD
R
ON
POWER-ON RESET
WATCHDOG RESET
16/100
15
ST72251
4 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 12.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
It will be serviced according to the flowchart on
Figure 12.
4.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically ANDed and inverted before en-
tering the edge/level detection block.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– ThePC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
4.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
Interrupts and Low Power Mode
– Writing “0” to the corresponding bit in the status
register or
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
4.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
17/100
16
ST72251
INTERRUPTS (Cont’d)
Figure 12. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
18/100
17
ST72251
Table 5. Interrupt Mapping
Source
Exit
from
HALT
Register
Label
Vector
Address
Priority
Order
Description
Flag
Block
RESET
TRAP
EI0
Reset
Software
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
Highest
Priority
External Interrupt PA0:PA7
External Interrupt PB0:PB7, PC0:PC5
Not Used
yes
yes
EI1
Transfer Complete
Mode Fault
SPIF
MODF
SPI
SPISR
TASR
no
no
FFF4h-FFF5h
Input Capture 1
ICF1_A
OCF1_A
ICF2_A
OCF2_A
TOF_A
Output Compare 1
Input Capture 2
TIMER A
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
Output Compare 2
Timer Overflow
Not Used
Input Capture 1
ICF1_B
OCF1_B
ICF2_B
OCF2_B
TOF_B
Output Compare 1
Input Capture 2
TIMER B
TBSR
no
Output Compare 2
Timer Overflow
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
Not Used
I2CSR1
I2CSR2
I2C
I2C Peripheral Interrupts
Not Used
**
no
FFE4h-FFE5h
Lowest
Priority
FFE2h-FFE3h
FFE0h-FFE1h
** Many flags can cause an interrupt, see peripheral interrupt status register description.
19/100
18
ST72251
4.4 POWER SAVING MODES
4.4.1 Introduction
Figure 13. WAIT Flow Chart
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis-
cellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
WFI INSTRUCTION
4.4.2 Slow Mode
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
In Slow mode, the oscillator frequency can be di-
vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
ON
OFF
CLEARED
4.4.3 Wait Mode
N
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All otherregisters and memory remain unchanged.
The MCU will remain in Wait mode until an Inter-
rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In-
terrupt or Reset Service Routine.
RESET
N
Y
INTERRUPT
Y
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
ON
SET
Refer to Figure 13 below.
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
SET
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
20/100
19
ST72251
POWER SAVING MODES (Cont’d)
4.4.4 Halt Mode
Figure 14. HALT Flow Chart
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. Thestabilization time is 4096 CPU clock
cycles.
HALT INSTRUCTION
Y
WDG
WATCHDOG
RESET
ENABLED?
N
OSCILLATOR
OFF
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
OFF
CLEARED
N
After the start up delay, the CPU continues oper-
ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
RESET
N
EXTERNAL
INTERRUPT
Y
1)
Y
OSCILLATOR
ON
2)
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
ON
SET
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
SET
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1) or some specific interrupts
2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK = OFF
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
21/100
20
ST72251
4.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
0 - PC2 is a general purpose I/O port.
1 - MCO alternate function (f
pin).
is output on PC2
CPU
Register Address: 0020h
— Read/Write
Bit 4:3 = PEI[1:0] External Interrupt EI0 Polarity
Option.
Reset Value: 0000 0000 (00h)
These bits are set and cleared by software. They
determine which event on EI0 causes the exter-
nal interrupt according to Table 7.
7
0
PEI3 PEI2 MCO PEI1 PEI0
-
-
SMS
Refer to the Pin Description Table at the begin-
ning of this document for the list of pins connect-
ed to EI0.
Bit 7:6 = PEI[3:2] External Interrupt EI1 Polarity
Option.
These bits are set and cleared by software. They
determine which event on EI1 causes the exter-
nal interrupt according to Table 6.
Table 7. EI0 External Interrupt Polarity Options
MODE
PEI1
PEI0
Refer to the Pin Description Table at the begin-
ning of this document for the list of pins connect-
ed to EI1.
Falling edge and low level
(Reset state)
0
0
Falling edge only
Rising edge only
1
0
1
0
1
1
Rising and falling edge
Table 6. EI1 External Interrupt Polarity Options
MODE
PEI3
PEI2
Note:
Falling edge and low level
(Reset state)
Any modification of one of these two bits resets the
interrupt request related to this interrupt vector.
0
0
Falling edge only
Rising edge only
1
0
1
0
1
1
Bit 1:2 = Unused, always read at 0.
Rising and falling edge
Warning: Software must write 1 to these bits for
compatibility with future products.
Note: Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.
Bit 0 = SMS Slow Mode Select
This bit is set and cleared by software.
0- Normal mode - f
(Reset state)
= Oscillator frequency / 2
CPU
Bit 5 = MCO Main Clock Out
This bit is set and cleared by software. When set, it
enables the output of the Internal Clock on the
PC2 I/O port.
1- Slow mode - f
= Oscillator frequency /32
CPU
22/100
21
ST72251
5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
Interrupt function
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
terrupt request to the CPU. The interrupt polarity is
given independently according to the description
mentioned in the Miscellaneous register or in the
interrupt register (where available).
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-
ripherals.
Each pin can independently generate an Interrupt
request.
– external interrupt generation
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If several input pins are configured as inputs
to the same interrupt vector, their signals are logi-
cally ANDed before entering the edge/level detec-
tion block. For this reason if one of the interrupt
pins is tied low, it masks the other ones.
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital out-
put.
5.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
5.1.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit.
– Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor-
respondence is used for the DR register.
Note: In this mode, the interrupt function is disa-
bled.
The following description takes into account the
OR register, for specific ports which do not provide
this register refer to the I/O Port Implementation
Section 5.1.3. The generic I/O block diagram is
shown on Figure 16.
5.1.2.3 Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
5.1.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
Different input modes can be selected by software
through the OR register.
Notes:
Notes:
1. Input pull-up configuration can cause an unex-
pected value at the input of the alternate peripher-
al input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con-
figured as an output.
Warning: The alternate function must not be acti-
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious in-
terrupts.
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ST72251
I/O PORTS (Cont’d)
5.1.2.4 Analog Alternate Function
5.1.3 I/O Port Implementation
When the pin is used as an ADC input the I/O must
be configured as input, floating. The analog multi-
plexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put (see Figure 16) or true open drain. Switching
these I/O ports from one state to another should
be done in a sequence that prevents unwanted
side effects. Recommended safe transitions are il-
lustrated in Figure 15. Other transitions are poten-
tially risky and should be avoided, since they are
likely to present unwanted side-effects such as
spurious interrupt generation.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Warning: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
Figure 15. Recommended I/O State Transition Diagram
OUTPUT
push-pull
INPUT
no interrupt
OUTPUT
INPUT
with interrupt
open-drain
24/100
23
ST72251
I/O PORTS (Cont’d)
Figure 16. I/O Block Diagram
ALTERNATE ENABLE
1
V
ALTERNATE
OUTPUT
DD
M
U
X
P-BUFFER
(SEE TABLE BELOW)
0
DR
LATCH
ALTERNATE
ENABLE
PULL-UP
V
DD
PULL-UP
CONDITION
DIODE
(SEE TABLE BELOW)
DDR
LATCH
PAD
OR
ANALOG ENABLE
(ADC)
LATCH
(SEE TABLE BELOW)
GND
ANALOG
SWITCH
OR SEL
(SEE NOTE BELOW)
DDR SEL
N-BUFFER
ALTERNATE
ENABLE
1
0
DR SEL
M
U
X
GND
ALTERNATE INPUT
CMOS
SCHMITT TRIGGER
POLARITY
SEL
FROM
OTHER
BITS
EXTERNAL
INTERRUPT
SOURCE (EIx)
Table 8. Port Mode Configuration
Configuration Mode
Pull-up
P-buffer
V
Diode
DD
Floating
Pull-up
0
1
0
0
0
1
1
1
1
Push-pull
not present in OTP
and EPROM devices
True Open Drain
not present
not present
0
Open Drain (logic level)
0
1
Legend:
Notes:
– No OR Register on some ports (see register map).
– ADC Switch on ports with analog alternate functions.
0 -
1 -
present, not activated
present and activated
25/100
24
ST72251
Table 9. Port Configuration
Input (DDR = 0)
OR = 1
Output (DDR = 1)
OR = 0
Pin
Port
Name
OR = 0
OR = 1
True Open Drain,
High Sink Capability
Port A
PA0:PA7
Floating*
Floating with Interrupt
Reserved
Port B
Port C
PB0:PB7
PC0:PC5
Floating*
Floating*
Pull-up with Interrupt
Pull-up with Interrupt
Open Drain (Logic level)
Open Drain (Logic level)
Push-pull
Push-pull
* Reset State
26/100
25
ST72251
I/O PORTS (Cont’d)
5.1.4 Register Description
5.1.4.1 Data registers
5.1.4.3 Option registers
Port A Option Register (PAOR)
Port B Option Register (PBOR)
Port C Option Register (PCOR)
Read/Write
Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h) (no interrupt)
7
0
7
0
O7
O6
O5
O4
O3
O2
O1
O0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7:0 = O7-O0 Option Register 8 bits.
Bit 7:0 = D7-D0 Data Register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
The OR register allow to distinguish: in input mode
if the interrupt capability or the floating configura-
tion is selected, in output mode if the push-pull or
open drain configuration is selected.
Each bit is set and cleared by software.
Input mode:
5.1.4.2 Data direction registers
Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
Port C Data Direction Register (PCDDR)
0: floating input
1: input interrupt with or without pull-up
Output mode (only for PB0:PB7, PC0:PC5):
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
0: output open drain (with P-Buffer inactivated)
1: output push-pull
7
0
Output mode (only for PA0:PA7):
0: output open drain
1: reserved
DD
2
DD7 DD6 DD5 DD4 DD3
DD1 DD0
Bit 7:0 = DD7-DD0 Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
27/100
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ST72251
I/O PORTS (Cont’d)
Table 10. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PCDR
D7
0
D6
0
D5
0
D4
0
D37
0
D2
0
D1
0
D0
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
Reset Value
PCDDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PCOR
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
Reset Value
PBDR
D7
0
D6
0
D5
0
D4
0
D37
0
D2
0
D1
0
D0
0
Reset Value
PBDDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PBOR
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
Reset Value
PADR
D7
0
D6
0
D5
0
D4
0
D37
0
D2
0
D1
0
D0
0
Reset Value
PADDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PAOR
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
Reset Value
28/100
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ST72251
5.2 WATCHDOG TIMER (WDG)
5.2.1 Introduction
5.2.2 Main Features
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 17. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
T6
WDGA
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷12288
29/100
28
ST72251
WATCHDOG TIMER (Cont’d)
5.2.3 Functional Description
5.2.4 Low Power Modes
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
Mode
Description
WAIT
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
HALT
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11):
5.2.5 Interrupts
None.
5.2.6 Register Description
CONTROL REGISTER (CR)
Read/Write
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
Reset Value: 0111 1111 (7Fh)
– TheT5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Table 11. Watchdog Timing (f
= 8 MHz)
CPU
CR Register
initial value
WDG timeout period
(ms)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Max
Min
FFh
C0h
98.304
1.536
0: Watchdog disabled
1: Watchdog enabled
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0024h
Reset Value
30/100
29
ST72251
5.3 16-BIT TIMER
5.3.1 Introduction
5.3.3 Functional Description
5.3.3.1 Counter
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
It may be used for a variety of purposes, including
measuring the pulse lengths of up to two input sig-
nals (input capture) or generating up to two output
waveforms (output compare and PWM).
Counter Register (CR):
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register (SR).
(See note at the end of paragraph titled 16-bit read
sequence).
5.3.2 Main Features
■ Programmable prescaler:fCPU dividedby2, 4or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower thanthe CPUclock speed)with the choice
of active edge
■ Output compare functions with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 13. The
value in the counter register repeats every
131072, 262144 or 524288 CPU clock cycles de-
pending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Input capture functions with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
– 1 dedicated maskable interrupt
■ Pulse Width Modulation mode (PWM)
■ One Pulse mode
■ 5 alternate functionson I/O ports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 18.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
31/100
30
ST72251
16-BIT TIMER (Cont’d)
Figure 18. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
h
w
h
w
h
w
h
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1
1/2
1/4
1/8
COUNTER
REGISTER
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
OCMP2
pin
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2 EXEDG
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
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31
ST72251
16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
5.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
33/100
32
ST72251
16-BIT TIMER (Cont’d)
Figure 19. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 20. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 21. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
34/100
33
ST72251
16-BIT TIMER (Cont’d)
5.3.3.3 Input Capture
When an input capture occurs:
– The ICFi bit is set.
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 23).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
The ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, the transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function, select the fol-
lowing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 13).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
And select the following in the CR1 register:
4. In One Pulse mode and PWM mode only the
input capture 2 function can be used.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as a floating input).
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with an interrupt in
order to measure events that exceed the timer
range (FFFFh).
35/100
34
ST72251
16-BIT TIMER (Cont’d)
Figure 22. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC1 CC0
Figure 23. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
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35
ST72251
16-BIT TIMER (Cont’d)
5.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 13)
PRESC
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Where:
Timing resolution is one count of the free running
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
counter: (f
).
CC[1:0]
CPU/
f
EXT
Procedure:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
To use the output compare function, select the fol-
lowing in the CR2 register:
1. Reading the SR register while the OCFi bit is
set.
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 13).
And select the following in the CR1 register:
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
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ST72251
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
FOLVLi bits have no effect in either One-Pulse
mode or PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 25, on
page 39). This behaviour is the same in OPM
or PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 26, on page 39).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 24. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
FOLV2 FOLV1
OCIE
OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
38/100
37
ST72251
16-BIT TIMER (Cont’d)
Figure 25. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 26. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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38
ST72251
16-BIT TIMER (Cont’d)
5.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use One Pulse mode:
CPU - 5
OCiR Value =
PRESC
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 13)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
OCiR = t f
-5
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
* EXT
Where:
t
= Pulse period (in seconds)
3. Select the following in the CR2 register:
f
= External timer clock frequency (in hertz)
EXT
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin (see Figure 27).
– Select the timer clock CC[1:0] (see Table 13).
One Pulse mode cycle
When
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and the OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and
the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When One Pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate that a period of
time has elapsed but cannot generate an output
waveform because the OLVL2 level is dedi-
cated to One Pulse mode.
40/100
39
ST72251
16-BIT TIMER (Cont’d)
Figure 27. One Pulse Mode Timing Example
FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 28. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
41/100
40
ST72251
16-BIT TIMER (Cont’d)
5.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
The Pulse Width Modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used
when the PWM mode is activated.
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
Procedure
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 13)
To use Pulse Width Modulation mode:
PRESC
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
If the timer clock is an external clock the formula is:
OCiR = t f
-5
* EXT
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the oppo-
site column.
Where:
t
= Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 28)
Notes:
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Select the timer clock (CC[1:0]) (see Table
13).
If OLVL1=1 and OLVL2=0, the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
if ICIE is set.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
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41
ST72251
16-BIT TIMER (Cont’d)
5.3.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
5.3.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
5.3.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 5.3.3.5 One Pulse Mode
See note 5 in Section 5.3.3.5 One Pulse Mode
See note 4 in Section 5.3.3.6 Pulse Width Modulation Mode
43/100
42
ST72251
16-BIT TIMER (Cont’d)
5.3.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to becopied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
44/100
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ST72251
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bits 3:2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the internal Output Compare 1 function of the
timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 13. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse mode.
0: One Pulse mode is not active.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin (EXTCLK) will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
1: One Pulse mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
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ST72251
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
MSB
LSB
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter matches
the content of the OC1R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC1R (OC1LR) register.
7
0
MSB
LSB
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter has rolled over from
FFFFh to 0000h. To clear this bit, first read the
SR register, then read or write the low byte of
the CR (CLR) register.
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note: Reading or writing the ACLR register does
not clear TOF.
7
0
MSB
LSB
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
1: The content of the free running counter matches
the content of the OC2R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC2R (OC2LR) register.
7
0
MSB
LSB
Bit 2-0 = Reserved, forced by hardware to 0.
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ST72251
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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ST72251
16-BIT TIMER (Cont’d)
Table 14. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
TimerA: 32 CR1
ICIE
0
OCIE
TOIE
0
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
TimerB: 42 Reset Value
TimerA: 31 CR2
0
OC2E
0
0
PWM
0
0
CC1
0
0
0
0
OC1E
0
OPM
0
CC0
IEDG2
EXEDG
TimerB: 41 Reset Value
TimerA: 33 SR
0
-
0
-
0
-
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
TimerB: 43 Reset Value
TimerA: 34 IC1HR
TimerB: 44 Reset Value
TimerA: 35 IC1LR
0
0
0
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
MSB
-
LSB
-
TimerB: 45 Reset Value
TimerA: 36 OC1HR
TimerB: 46 Reset Value
TimerA: 37 OC1LR
TimerB: 47 Reset Value
TimerA: 3E OC2HR
TimerB: 4E Reset Value
TimerA: 3F OC2LR
TimerB: 4F Reset Value
TimerA: 38 CHR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
TimerB: 48 Reset Value
TimerA: 39 CLR
MSB
1
LSB
0
TimerB: 49 Reset Value
TimerA: 3A ACHR
MSB
1
LSB
1
TimerB: 4A Reset Value
TimerA: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
TimerB: 4B Reset Value
TimerA: 3C IC2HR
MSB
-
LSB
-
TimerB: 4C Reset Value
TimerA: 3D IC2LR
MSB
-
LSB
-
-
-
-
-
-
-
TimerB: 4D Reset Value
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ST72251
2
5.4 I C BUS INTERFACE (I2C)
5.4.1 Introduction
handshake. The interrupts are enabled or disabled
2
2
by software. The interface is connected to the I C
The I C Bus Interface serves as an interface be-
tween the microcontroller and the serial I C bus. It
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
2
It can be connected both with a standard I C bus
provides both multimaster and slave functions,
2
2
and a Fast I C bus. This selection is made by soft-
and controls all I C bus-specific sequencing, pro-
2
ware.
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
Mode Selection
5.4.2 Main Features
The interface can operate in the four following
modes:
2
■ Parallel-bus/I C protocol converter
– Slave transmitter/receiver
■ Multi-master capability
– Master transmitter/receiver
By default, it operates in slave mode.
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
2
I C Master Features:
■ Clock generation
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
5.4.3 General Description
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 29.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
2
Figure 29. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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ST72251
2
I C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast I C (100-
400KHz).
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 30. I C Interface Block Diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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ST72251
2
I C BUS INTERFACE (Cont’d)
5.4.4 Functional Description
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Refer to the CR, SR1 and SR2 registers in Section
5.4.7. for the bit definitions.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 31 Transfer se-
quencing EV2).
2
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
5.4.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 31 Transfer sequencing
EV3).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
When the acknowledge pulse is received:
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Address not matched: the interface ignores it
Closing slave communication
and waits for another Start condition.
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
– EVFand ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR2 reg-
ister (see Figure 31 Transfer sequencing EV4).
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 31
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
Note: In both cases, SCL line is not held low; how-
ever, SDA line can remain low due to possible «0»
bits transmitted last. It is then necessary to release
both lines by software.
– Acknowledge pulse if the ACK bit is set
51/100
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ST72251
2
I C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
5.4.4.2 Master Mode
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 31 Transfer sequencing EV6).
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Next the master must enter Receiver or Transmit-
ter mode.
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 31 Transfer sequencing EV5).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
Slave address transmission
– Acknowledge pulse if if the ACK bit is set
Then the slave address is sent to the SDA line via
the internal shift register.
– EVFand BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
In 7-bit addressing mode, one address byte is
sent.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 31 Transfer se-
quencing EV7).
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 31 Transfer se-
quencing EV9).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Then the second address byte is sent by the inter-
face.
52/100
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ST72251
2
I C BUS INTERFACE (Cont’d)
Master Transmitter
BERR bits are set by hardware with an interrupt
if ITE is set.
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 31 Transfer sequencing
EV8).
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
When the acknowledge bit is received, the
interface sets:
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then neces-
sary to release both lines by software.
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
53/100
52
ST72251
2
I C BUS INTERFACE (Cont’d)
Figure 31. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
Data2
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
Data2
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
A
DataN
....
.
A
P
r
EV1 EV3
EV6 EV8
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
DataN
A
P
.....
EV5
EV9
EV8
A
EV8
A
10-bit Master receiver:
S
Header
A
Data1
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend: S=Start, S = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
r
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
54/100
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ST72251
2
I C BUS INTERFACE (Cont’d)
5.4.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
HALT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
5.4.6 Interrupts
Figure 32. Event Flags and Interrupt Generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
55/100
54
ST72251
2
I C BUS INTERFACE (Cont’d)
5.4.7 Register Description
2
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
0
0
PE
ENGC START ACK STOP
ITE
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
2
– To enable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 32 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 31) is de-
tected.
0: General Call disabled
1: General Call enabled
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
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2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = BUSY Bus busy.
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still updat-
ed when the interface is disabled (PE=0).
0: No communication on the bus
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 31.
It is also cleared by hardware when the interface is
disabled (PE=0).
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
0: No event
1: One of the following events has occurred:
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 31). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
The SCL line is held low while BTF=1.
– Address byte successfully transmitted in Mas-
ter mode.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
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ST72251
2
I C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
1: Master mode
The SCL line is not held low while ARLO=1.
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following
0: No arbitration lost detected
1: Arbitration lost detected
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DRregister. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
2
I C STATUS REGISTER 2 (SR2)
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0
0
AF STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
0: No general call address detected on bus
1: general call address detected on bus
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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ST72251
2
I C BUS INTERFACE (Cont’d)
2
I C CLOCK CONTROL REGISTER (CCR)
2
Read / Write
I C DATA REGISTER (DR)
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
2
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (F
) de-
SCL
2
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
F
= F
/(2x([CC6..CC0]+2))
SCL
CPU
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= F
/(3x([CC6..CC0]+2))
SCL
CPU
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
59/100
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ST72251
2
I C BUS INTERFACE (Cont’d)
2
2
I C OWN ADDRESS REGISTER (OAR1)
I C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0100 0000 (40h)
7
0
7
0
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
FR1
FR0
0
0
0
ADD9 ADD8
7-bit Addressing Mode
Bit 7:6 = FR1-FR0 Frequency bits.
Bit 7:1 = ADD7-ADD1 Interface address.
These bits define the I C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
These bits are set by software only when the inter-
face is disabled (PE=0). To configure the interface
2
2
to I C specifed delays select the value corre-
sponding to the microcontroller frequency F
.
CPU
F
Range (MHz)
2.5 - 6
FR1
0
FR0
CPU
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
0
1
0
1
6 -10
0
10 - 14
1
14 - 24
1
Note: Address 01h is always ignored.
Bit 5:3 = Reserved
Bit 2:1 = ADD9-ADD8 Interface address.
These are the most significant bits of the I C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
10-bit Addressing Mode
Bit 7:0 = ADD7-ADD0 Interface address.
These are the least significant bits of the I C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
2
2
Bit 0 = Reserved.
2
Table 15. I C Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
28
29
2A
2B
2C
2D
2E
CR
SR1
PE
ENGC
BUSY
AF
START
BTF
ACK
ADSL
ARLO
STOP
M/SL
ITE
SB
EVF
FM/SM
FR1
TRA
SR2
STOPF
CC6 .. CC0
BERR
GCAL
CCR
OAR1
OAR2
DR
ADD7 .. ADD0
FR0
ADD9
ADD8
DR7 .. DR0
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ST72251
2
I C INTERFACE (Cont’d)
5.4.8 Application Considerations
5.4.8.1 Programming Considerations
The interface can be used in two modes:
– Interrupt
5.4.8.2 Application Example
The software routines given below describe a pos-
sible software driver to control the I C interface
connected to an external EEPROM without com-
munication error management.
2
– Polling
The interface configuration is Master mode.
Caution: Care should be taken when polling error
events as the asynchronous setting of error bits
can result in error events being missed.
This polling software does not use the EVF flag
and can be easily adapted to manage interrupts
keeping the same strategy.
/**************** (c) 1997 SGS-Thomson Microelectronics ********************/
/* */
/* THE SOFTWARE INCLUDED IN THIS DOCUMENT IS FOR GUIDANCE ONLY. SGS-THOMSON */
/*
SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
*/
*/
*/
/* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THIS SOFTWARE.
/*
/***************************************** *********************************/
/*---------------------------- Basic Routines -----------------------------*/
void I2Cm_Start (void)
{
/* Generates I2C-Bus Start Condition.*/
/* Generate start condition.*/
SetBit(I2C_CR,START);
while (!ValBit(I2C_SR1,SB)) ; /* Wait for the Start bit generation (“EV5”).*/
}
void I2Cm_Stop (void)
{
/* Generates I2C-Bus Stop Condition.*/
/* Generate stop condition.*/
SetBit(I2C_CR,STOP);
}
void I2Cm_Ack (void)
/* Activate acknowledge generation.*/
{
SetBit(I2C_CR,ACK);
}
/* Acknowledge after the next received data bytes.*/
void I2Cm_nAck (void)
/* Disactivate acknowledge generation.*/
{
ClrBit(I2C_CR,ACK); /* Non acknowledge after the next received data bytes.*/
}
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ST72251
2
I C INTERFACE (Cont’d)
/*------------------------- Initialization Routine ---------------- --------*/
void I2Cm_Init (void)
{
I2C_CR = 0x00;
I2C_CCR = 0X12;
asm TNZ I2C_DR;
asm TNZ I2C_SR1;
asm TNZ I2C_SR2;
I2C_CR = 0x24;
I2C_CR = 0x24;
I2Cm_Start();
/* Force reset status of the control register.*/
/* Set the I2C-bus speed to 0-100KHz.*/
/* Touch registers to remove pending interrupt.*/
/* PE=1, ACK=1: switch on the peripheral interface.*/
/* Write twice: switch on periph then set config.*/
/* Start condition generation.*/
I2Cm_Stop();
/* Stop condition generation.*/
}
/*------------------------- Communication Routines ------------------------*/
void I2Cm_SetAddr (char i2c_addr)
{
I2Cm_Start();
/* Generates a start condition.*/
I2C_DR = i2c_addr;
/* Write address to be transmitted.*/
}
void I2Cm_TxData (char i2c_data)
/* Transmits a data byte.*/
{
do {
if (I2C_SR2) while(1);
SetBit(I2C_CR,PE);
/* Communication error detected: infinite loop.*/
/* Touch the control register to pass ”EV6”.*/
} while (!ValBit(I2C_SR1,BTF));
I2C_DR = i2c_data;
/* Wait for BTF (”EV8”).*/
/* Write data byte to be transmitted.*/
}
char I2Cm_RxData (char last) /* Return received data byte (last one flagged).*/
{
do {
if (I2C_SR2) while(1);
SetBit(I2C_CR,PE);
/* Communication error detected: infinite loop.*/
/* Touch the control register to pass ”EV6”.*/
} while (!ValBit(I2C_SR1,BTF));
if (last) I2Cm_Stop(); /* End of communication: stop condition generation.*/
return(I2C_DR); /* Read/return data byte received.*/
/* Wait for BTF (”EV7”).*/
}
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ST72251
2
I C INTERFACE (Cont’d)
/*---------------------- EEPROM Communication Routines ---------------- ----*/
void I2Cm_Tx (char *buff_add, char sub_add, char nb, char dest_add)
{
/* Transmit data buffer to EEPROM with least significant bytes first.*/
I2Cm_SetAddr(dest_add);
I2Cm_TxData(sub_add);
/* Slave address selection on I2C bus.*/
/* Sub address selection.*/
for (;nb > 0; nb--)
I2Cm_TxData(*(bu ff_add+nb-1));
I2Cm_Stop(); /* End of communication: stop condition generation.*/
/* Loop to send all selected data from output buffer.*/
/* Next output buffer data byte sent.*/
}
void I2Cm_Rx (char *buff_add, char sub_add, char nb, char dest_add)
{ /* Receive data buffer from EEPROM with least significant bytes first.*/
I2Cm_SetAddr(dest_add);
I2Cm_TxData(sub_add);
/* Slave address selection on I2C bus.*/
/* Sub address selection.*/
I2Cm_SetAddr(dest_add|0x01);
/* Slave address selection in read mode.*/
do
{
/* Loop to send all selected data from output buffer.*/
nb--;
if (nb==0)
{
/* Last byte to receive.*/
I2Cm_nAck();
/* Non acknowledge after last reception.*/
*(buff_add+nb) = I2Cm_RxData(1);
/* Last data byte reception.*/
}
else
*(buff_add+nb) = I2Cm_RxData(0);
/* Next data byte reception.*/
/* Loop to receive the selected number of bytes.*/
/* Acknowledge after reception.*/
} while (nb > 0);
I2Cm_Ack();
}
/*** (c) 1997 SGS-Thomson Microelectronics *************** END OF EXAMPLE ***/
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ST72251
5.5 SERIAL PERIPHERAL INTERFACE (SPI)
5.5.1 Introduction
5.5.3 General description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 33.
5.5.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Write collision flag protection
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 36) but master and slave
must be programmed with the same timing mode.
Figure 33. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 34. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
SR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4 Functional Description
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Figure 33 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
– A Status Register (SR)
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
5.5.7for the bit definitions.
5.5.4.1 Master Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 36).
Clearing the SPIF bit is performed by the following
software sequence:
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
1. An access to the SR register while the SPIF bit
is set
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
36.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2.A read to the DR register.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 5.5.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
5.5.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 35).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 35).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 36, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 35. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 36. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MSBit
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 37).
Figure 37. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SR
Read SR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Read DR
Write DR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SR
1st Step
THEN
Note: Writing in DR register in-
2nd Step
Read DR
stead of reading in it do not reset
WCOL bit
WCOL=0
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.5 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
5.5.4.6 Overrun Condition
An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
This condition is not detected by the SPI peripher-
al.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 38).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 38. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
MCU
Slave
MCU
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.5 Low Power Modes
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
5.5.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
SPI End of Transfer Event
Master Mode Fault Event
SPIF
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Reset Value: 0000xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 5.5.4.5 Master Mode Fault).
0: I/O port connected to pins
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
These 2 bits have no effect in slave mode.
Table 16. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
Serial Clock
SPR2 SPR1 SPR0
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16.
0: Divider by 2 enabled
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
/16
/32
/64
CPU
1: Divider by 2 disabled
f
CPU
f
CPU
Bit 4 = MSTR Master.
f
/128
CPU
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 5.5.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
DATA I/O REGISTER (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: Undefined
7
0
-
7
0
SPIF
WCOL
-
MODF
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Data transfer between the device and an exter-
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 34 ).
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 37).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 5.5.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
DR
Reset Value
CR
Reset Value
SR
Reset Value
D7
x
D6
D5
x
D4
D3
x
D2
x
D1
x
D0
x
21
22
23
x
SPE
0
x
MSTR
0
SPIE
0
SPR2
0
-
CPOL
x
-
CPHA
SPR1
x
-
SPR0
x
-
x
-
0
SPIF
0
WCOL
0
MODF
0
0
0
0
0
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ST72251
5.6 8-BIT A/D CONVERTER (ADC)
5.6.1 Introduction
5.6.2 Main Features
■ 8-bit conversion
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 8 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 8 different sources.
■ Up to 8 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/Off bit (to reduce consumption)
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
The block diagram is shown in Figure 39.
Figure 39. ADC Block Diagram
-
ADON
0
-
CH2 CH1 CH0
COCO
(Control Status Register) CSR
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
SAMPLE
&
HOLD
ANALOG TO
DIGITAL
CONVERTER
ANALOG
MUX
f
CPU
AD6 AD5 AD4 AD3 AD2 AD1 AD0
(Data Register) DR
AD7
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ST72251
8-BIT A/D CONVERTER (ADC) (Cont’d)
5.6.3 Functional Description
The accuracy of the conversion is described in the
Electrical Characteristics Section.
The high level reference voltage V
must be
DDA
connected externally to the V pin. The low level
Procedure:
DD
reference voltage V
must be connected exter-
SSA
Refer to the CSR and DR register description sec-
tion for the bit definitions.
nally to the V pin. In some devices (refer to de-
vice pin out description) high and low level refer-
SS
Each analog input pin must be configured as input,
no pull-up, no interrupt. Refer to the “I/O Ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
ence voltages are internally connected to the V
DD
and V pins.
SS
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
In the CSR register:
Figure 40. Recommended Ext. Connections
– Select the CH2 to CH0 bits to assign the ana-
log channel to convert. Refer to Table 18.
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
µs). It then performs a continuous conversion
of the selected channel.
V
DD
V
V
DDA
SSA
0.1µF
ST7
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
R
AIN
V
Px.x/AINx
AIN
– The result is in the DR register.
A write to the CSR register aborts the current con-
version, resets the COCO bit and starts a new
conversion.
Characteristics:
The conversion is monotonic, meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
5.6.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
If input voltage is greater than or equal to V
(voltage reference high) then results = FFh (full
scale) without overflow indication.
DD
If input voltage ≤ V (voltage reference low) then
SS
the results = 00h.
Mode
Description
WAIT
No effect on A/D Converter
A/D Converter disabled.
The conversion time is 64 CPU clock cycles in-
cluding a sampling time of 31.5 CPU clock cycles.
R
is the maximum recommended impedance
AIN
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
HALT
The A/D converter is linear and the digital result of
the conversion is given by the formula:
5.6.5 Interrupts
255 x Input Voltage
Digital result =
None.
Reference Voltage
Where Reference Voltage is V - V
.
DD
SS
78/100
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ST72251
8-BIT A/D CONVERTER (ADC) (Cont’d)
5.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
These bits are set and cleared by software. They
select the analog input to convert.
Table 18. Channel Selection
Reset Value: 0000 0000 (00h)
Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
CH2
0
CH1
0
CH0
0
7
0
0
0
1
COCO
-
ADON
0
-
CH2
CH1
CH0
0
1
0
0
1
1
Bit 7 = COCO Conversion Complete
1
0
0
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete.
1: Conversion can be read from the DR register.
1
0
1
1
1
0
1
1
1
*IMPORTANT NOTE: The number of pins AND
the channel selection vary according to the device.
REFER TO THE DEVICE PINOUT).
Bit 6 = Reserved. Must always be cleared.
Bit 5 = ADON A/D converter On
DATA REGISTER (DR)
Read Only
This bit is set and cleared by software.
0: A/D converter is switched off.
1: A/D converter is switched on.
Reset Value: 0000 0000 (00h)
Note: A typical 30 µs delay time is necessary for
the ADC to stabilize when the ADON bit is set.
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Bit 4 = Reserved. Forced by hardware to 0.
Bit 3 = Reserved. Must always be cleared.
Bits 2:0: CH[2:0] Channel Selection
Bit 7:0 = AD[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Reading this register resets the COCO flag.
Table 19. ADC Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
70
AD7
0
AD6
0
AD5
0
AD4
0
AD3
0
AD2
0
AD1
0
AD0
0
DR
Reset Value
71
COCO
0
-
0
ADON
0
0
0
-
0
CH2
0
CH1
0
CH0
0
CSR
Reset Value
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ST72251
6 INSTRUCTION SET
6.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause itcan use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 20. ST7 Addressing Mode Overview
Pointer Pointer
Destination/
Source
Length
(Bytes)
Mode
Syntax
Address
(Hex.)
Size
(Hex.)
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
Direct
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative
Relative
btjt $10,#7,skip 00..FF
btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
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ST72251
ST7 ADDRESSING MODES (Cont’d)
6.1.1 Inherent
6.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
6.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
6.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
6.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST72251
ST7 ADDRESSING MODES (Cont’d)
6.1.6 Indirect Indexed (Short, Long)
SWAP
Swap Nibbles
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
CALL, JP
Call or Jump subroutine
6.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Instructions
JRxx
Conditional Jump
Call Relative
Indirect Indexed (Short)
CALLR
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long)
Relative (Direct)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 21. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
82/100
81
ST72251
6.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
83/100
82
ST72251
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
84/100
83
ST72251
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
MUL
NEG
NOP
OR
Multiply
X,A = X * A
X, Y, A
0
0
Negate (2’s compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
85/100
84
ST72251
7 ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
J
TA + PD x RthJA
Where:T = Ambient Temperature.
A
For proper operation it is recommended that V
I
RthJA = Package thermal resistance
(junction-to ambient).
and V be higher than V and lower than V .
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
P
P
=
P
+ P
.
PORT
DD
D
INT
or V ).
SS
= I x V (chip internal power).
INT
DD
DD
P
=Port power dissipation
determined by the user)
PORT
Symbol
Parameter
Value
Unit
V
Supply Voltage
Input Voltage
-0.3 to 6.0
V
V
DD
V
V
V
V
- 0.3 to V + 0.3
DD
I
SS
SS
SS
V
Analog Input Voltage (A/D Converter)
Output Voltage
- 0.3 to V + 0.3
V
AI
DD
V
- 0.3 to V + 0.3
V
O
DD
IV
IV
Total Current into V (source)
80
80
mA
mA
°C
°C
DD
DD
Total Current out of V (sink)
SS
SS
T
Junction Temperature
Storage Temperature
150
J
T
-60 to 150
STG
Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
86/100
85
ST72251
7.2 RECOMMENDED OPERATING CONDITIONS
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
1 Suffix Version
0
70
85
°C
°C
°C
T
Operating Temperature
6 Suffix Version
3 Suffix Version
-40
-40
A
125
f
f
= 16 MHz (1 & 6 Suffix)
= 8 MHz
3.5
3.0
5.5
5.5
OSC
OSC
V
Operating Supply Voltage
Oscillator Frequency
V
DD
1)
V
V
= 3.0V
= 3.5V (1 & 6 Suffix)
0
8
16
DD
DD
f
MHz
1)
OSC
0
Note 1: A/D operation and Oscillator start-up are not guaranteed below 1MHz.
Figure 41. Maximum Operating Frequency (Fmax) Versus Supply Voltage (VDD)
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
f
OSC
FUNCTIONALITY GUARANTEED IN THIS AREA
[MHz]
FOR TEMPERATURE HIGHER THAN 85°C
16
8
4
1
0
Supplly Voltage
[V]
2.5
3
3.5
4
4.5
5
5.5
6
FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR
87/100
86
ST72251
7.3 DC ELECTRICAL CHARACTERISTICS
(T = -40°C to +125°C and V = 5V unless otherwise specified)
A
DD
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
V x 0.3
DD
Input Low Level Voltage
All Input pins
V
3V < V < 5.5V
V
V
IL
DD
Input High Level Voltage
All Input pins
V
3V < V < 5.5V
V
x 0.7
DD
IH
DD
1)
Hysteresis Voltage
V
400
mV
HYS
All Input pins
Low Level Output Voltage
All Output pins
I
= +10µA
= + 2mA
0.1
0.4
OL
I
OL
I
= +10µA
= +10mA
= + 15mA
0.1
1.5
3.0
3.0
OL
V
V
OL
Low Level Output Voltage
High Sink I/O pins
I
OL
I
OL
I
= + 20mA, T < 85°C
OL
A
High Level Output Voltage
All Output pins
I
= - 10µA
= - 2mA
4.9
4.2
OH
V
V
OH
I
OH
I
Input Leakage Current
All Input pins but RESET
V
V
= V (No Pull-up configured)
SS
IL
IN
IN
0.1
1.0
1.0
4)
I
= V
= V
< V
IH
DD
DD
IL
µA
Input Leakage Current
RESET pin
I
V
V
0.1
IH
IN
IN
R
I/O Weak Pull-up RPU
100
kΩ
PU
f
= 4 MHz, f
= 8 MHz, f
= 16 MHz, f
= 2 MHz
= 4 MHz
3
5.5
10
6
11
20
OSC
CPU
CPU
Supply Current in
RUN Mode
f
mA
2)
OSC
f
= 8 MHz
OSC
CPU
f
= 4 MHz, f
= 8 MHz, f
= 16 MHz, f
= 125 kHz
= 250 kHz
1.5
2.5
4
3
5
8
OSC
CPU
CPU
2)
Supply Current in SLOW Mode
f
f
mA
mA
mA
OSC
= 500 kHz
OSC
CPU
f
= 4MHz, f
= 8MHz, f
= 16MHz, f
= 2MHz
= 4 MHz
2
3.5
6
4
7
12
OSC
CPU
CPU
3)
Supply Current in WAIT Mode
Supply Current in WAIT-MINI-
f
OSC
I
DD
f
= 8 MHz
OSC
CPU
f
= 4 MHz, f
= 8 MHz, f
= 16 MHz, f
= 125 kHz
= 250 kHz
0.8
1
1.6
1.5
2
3.5
OSC
CPU
CPU
f
5)
OSC
MUM Mode
f
= 500 kHz
OSC
CPU
Supply Current in HALT Mode
(ROM version)
Supply Current in HALT Mode
(OTP version)
I
= 0mA, T <85°C
1
5
1
10
20
10
50
LOAD
A
µA
µA
I
= 0mA, 85°C<T <125°C
LOAD
A
I
= 0mA, T <25°C
LOAD
A
I
= 0mA, 25°C<T <125°C
LOAD
A
Notes:
1. Hysteresis voltage between switching levels. Based on characterisation results, not tested.
2. CPU running with memory access, no DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.
3. No DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.
4. Except OSCIN and OSCOUT
5. WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested.
88/100
87
ST72251
7.4 RESET CHARACTERISTICS
o
(T =-40...+125 C and V =5V±10% unless otherwise specified.
A
DD
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
V
> V
20
60
40
120
80
240
IN
IN
IH
R
Reset Weak Pull-up RON
kΩ
ON
< V
IL
Pulse duration generated by watch-
dog and POR reset
t
t
1
µs
RESET
PULSE
Minimum pulse duration to be ap-
plied on external RESET pin
1)
10
ns
Note:
1) These values given only as design guidelines and are not tested.
7.5 OSCILLATOR CHARACTERISTICS
(T = -40°C to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
g
Oscillator transconductance
Crystal frequency
2
1
9
mA/V
MHz
ms
m
f
16
50
OSC
t
Osc. start up time
V
= 5V±10%
DD
START
89/100
88
ST72251
7.6 A/D CONVERTER CHARACTERISTICS
(T = -40°C to +125°C and V = 5V±10% unless otherwise specified )
A
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1/f
T
Sample Duration
31.5
SAMPLE
CPU
f
V
CPU=8MHz
Res
ADC Resolution
8
bit
=V
=5V
DDA
DD
DLE
ILE
Differential Linearity Error*
Integral Linearity Error*
Analog Input Voltage
±0.6
±1
±2
V
V
V
DDA
V
AIN
SSA
Supply current rise
during A/D conversion
I
t
t
1
mA
ADC
fCPU=8MHz
=V =5V
Stabilization time after ADC enable
Conversion Time
30
µs
STAB
CONV
V
DD
DDA
8
64
µs
1/f
CPU
Resistance of analog sources
R
C
R
15
22
2
ΚΩ
pF
AIN
(V
AIN)
fCPU=8MHz, T=25°C,
=V =5V
Hold Capacitance
HOLD
SS
V
DD
DDA
Resistance of sampling switch and
internal trace
ΚΩ
*Note: ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is
inj-
a loss of 1 LSB by 10KΩ increase of the external analog source impedance.
These measurement results and recommendations take worst case injection conditions into account:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
V
Sampling
Switch
DD
V
= 0.6V
R
T
AIN
V
AIN
R
SS
Px.x/AINx
SS
2ΚΩ
C
pin
C
hold
5pF
C
= input capacitance
= threshold voltage
pin
22 pF
V
T
leakage max.
±1µA
V
= 0.6V
T
SS
C
= sampling switch
V
= sample/hold
capacitance
SS
hold
leakage = leakage current
at the pin due
to various junctions
90/100
89
ST72251
Figure 42. ADC conversion characteristics
Offset Error OSE
Gain Error GE
255
254
253
252
251
250
( 2)
V
– V
refP
refM
code
out
1LSB
= ---------------------------------------
ideal
256
7
(1)
6
5
(5)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DLE)
(4) Integral non-linearity error (ILE)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
1 LSB (ideal)
2
1
0
1
2
3
4
5
6
7
250 251 252 253 254 255 256
(LSB
V
)
ideal
in(A)
Offset Error OSE
VR02133A
91/100
90
ST72251
7.7 SPI CHARACTERISTICS
Serial Peripheral Interface
Value
Ref.
Symbol
Parameter
Condition
Unit
Min.
Max.
Master
Slave
1/128
dc
1/4
1/2
f
t
SPI frequency
f
t
SPI
SPI
CPU
CPU
Master
Slave
4
2
1
SPI clock period
2
3
t
Enable lead time
Enable lag time
Slave
Slave
120
120
ns
ns
Lead
t
Lag
Master
Slave
100
90
4
5
t
Clock (SCK) high time
Clock (SCK) low time
Data set-up time
ns
ns
ns
ns
ns
ns
SPI_H
Master
Slave
100
90
t
SPI_L
Master
Slave
100
100
6
t
SU
Master
Slave
100
100
7
t
Data hold time (inputs)
H
Access time (time to data active
from high impedance state)
8
t
0
120
240
A
Slave
Disable time (hold time to high im-
pedance state)
9
t
Dis
Master (before capture edge)
Slave (after enable edge)
0.25
t
t
CPU
ns
10
11
12
13
t
Data valid
V
120
Master (before capture edge)
Slave (after enable edge)
0.25
0
CPU
ns
t
Data hold time (outputs)
Rise time
Hold
Outputs: SCK,MOSI,MISO
(20% V to 70% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Rise
DD
DD
L
Fall time
Outputs: SCK,MOSI,MISO
(70% V to 20% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Fall
DD
DD
L
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 43. SPI Master Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
1
13
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000109
92/100
91
ST72251
SPI CHARACTERISTICS (Cont’d)
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 44. SPI Master Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
1
13
12
12
13
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000110
Figure 45. SPI Master Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
1
13
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-OUT
D6-OUT
D0-OUT
6
7
MOSI
(OUTPUT)
D6-IN
D0-IN
D7-IN
11
10
VR000107
Figure 46. SPI Master Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
1
12
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000108
93/100
ST72251
SPI CHARACTERISTICS (Cont’d)
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 47. SPI Slave Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
2
1
12
3
13
11
SCK
(INPUT)
4
5
MISO HIGH-Z
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
8
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000113
Figure 48. SPI Slave Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
2
1
13
12
11
3
SCK
(INPUT)
5
4
MISO
HIGH-Z
8
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000114
Figure 49. SPI Slave Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
4
5
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
11
9
10
MOSI
(INPUT)
D7-IN
D0-IN
7
6
VR000111
Figure 50. SPI Slave Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
2
1
12
13
3
SCK
(INPUT)
5
4
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
11
10
9
MOSI
(INPUT)
D7-IN
D0-IN
6
7
VR000112
94/100
ST72251
7.8 I2C CHARACTERISTICS
I2C-Bus Electrical specifications
Standard mode I2C
Min Max
Fast mode I2C
Min Max
Symbol
Parameter
Unit
Low level input voltage:
fixed input levels
V
V
V
-0.5
-0.5
1.5
0.3 V
-0.5
-0.5
1.5
0.3 V
DD
V
IL
V
-related input levels
DD
DD
High level input voltage:
fixed input levels
3.0
0.7 V
V
V
+0.5 3.0
+0.5 0.7 V
V
V
+0.5
+0.5
V
IH
DD
DD
DD
DD
V
-related input levels
DD
DD
DD
Hysteresis of Schmitt trigger inputs
fixed input levels
na
na
na
na
0.2
0,05 V
V
HYS
V
-related input levels
DD
DD
Pulse width of spikes which must be suppressed by
the input filter
T
na
na
0 ns
50 ns
ns
SP
Low level output voltage (open drain and open col-
lector)
at 3 mA sink current
at 6 mA sink current
V
V
V
0
na
0.4
na
0
0
0.4
0.6
OL1
OL2
Output fall time from VIH min to VIL max with a bus
capacitor from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
T
ns
OF
250
na
20+0.1Cb 250
20+0.1Cb 250
na
Input current each I/O pin with an input voltage be-
I
- 10
10
10
-10
10
10
µA
tween 0.4V and 0.9 V max
DD
C
Capacitor for each I/O pin
pF
Note: Cb = total capacitance of one bus line in pF.
I2C-Bus Timings
Standard I2C
Fast I2C
Symbol
Parameter
Bus free time between a STOP and START condition
Unit
Min
Max
Min
Max
T
4.7
1.3
0.6
ms
BUF
Hold time START condition. After this period, the first clock
pulse is generated
T
4.0
µs
HD:STA
T
T
T
T
T
T
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
4.7
4.0
4.7
1.3
0.6
0.6
µs
µs
µs
ns
ns
ns
ns
ns
pF
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
(1)
(1)
(2)
0
0
0.9
Data set-up time
250
100
1000 20+0.1Cb
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
300
300
TF
300
20+0.1Cb
0.6
T
:
4.0
SU STO
Cb
400
400
Note 1: The device must internally provide a hold time of at least 300 ns for the SDA signal inorder to bridge the undefined
region of the falling edge of SCL
Note 2: The maximum hold time of the START condition has only to be met if the interface does not stretch the low period
of SCL signal
95/100
ST72251
8 GENERAL INFORMATION
8.1 EPROM ERASURE
EPROM version devices are erased by exposure
to high intensity UV light admitted through the
transparent window. This exposure discharges the
floating gate to its initial state through induced
photo current.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting con-
ditions. Covering the window also reduces I
in
DD
power-saving modes due to photo-diode leakage
currents.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional fail-
ure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An Ultraviolet source of wave length 2537 Å yield-
2
ing a total integrated dosage of 15 Watt-sec/cm is
required to erase the device. It will be erased in 15
2
to 20 minutes if such a UV lamp with a 12mW/cm
power rating is placed 1 inch from the device win-
dow without any interposed filters.
8.2 PACKAGE MECHANICAL DATA
Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
D
h x 45×
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
18.10 0.697
7.60 0.291
0.104
0.012
0.020
0.013
0.713
0.299
L
A
A1 0.10
C
A1
B
C
D
E
e
0.33
0.23
a
e
B
17.70
7.40
1.27
0.050
H
h
α
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
L
0.40
1.27 0.016
0.050
Number of Pins
N
28
96/100
ST72251
Figure 52. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
E
eC
A
3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51
A2 3.05 3.56 4.57 0.120 0.140 0.180
0.36 0.46 0.58 0.014 0.018 0.023
b1 0.76 1.02 1.40 0.030 0.040 0.055
0.020
A2
A
L
b
A1
E1
C
eA
eB
C
D
E
0.20 0.25 0.36 0.008 0.010 0.014
27.43 28.45 1.080 1.100 1.120
9.91 10.41 11.05 0.390 0.410 0.435
b
b2
e
D
E1 7.62 8.89 9.40 0.300 0.350 0.370
e
1.78
0.070
0.400
eA
eB
eC
L
10.16
12.70
1.40
0.500
0.055
2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N
32
Figure 53. 32-Pin Shrink Ceramic Dual In-Line Package
mm
Min Typ Max Min Typ Max
3.63 0.143
inches
Dim.
A
A1 0.38
0.015
B
0.36 0.46 0.58 0.014 0.018 0.023
B1 0.64 0.89 1.14 0.025 0.035 0.045
C
D
0.20 0.25 0.36 0.008 0.010 0.014
29.41 29.97 30.53 1.158 1.180 1.202
D1
E
26.67
10.16
1.050
0.400
E1 9.45 9.91 10.36 0.372 0.390 0.408
e
G
1.78
9.40
14.73
1.12
3.30
7.37
0.070
0.370
0.580
0.044
0.130
0.290
G1
G2
L
Ø
Number of Pins
32
CDIP32SW
N
97/100
ST72251
8.3 ORDERING INFORMATION
Each device is available for production in user pro-
grammable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. There is one common EPROM version
for debugging and prototyping which features the
maximum memory size and peripherals of the
family. Care must be taken to only use resources
available on the target device.
8.3.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All un-
used bytes must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 54. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
1 = standard 0 to +70°C
3 = automotive -40 to +125°C
6 = industrial -40 to +85°C
B = Plastic DIP
M = Plastic SOIC
ST72251G1
ST72251G2
Figure 55. OTP User Programmable Device Types
TEMP.
PACKAGE RANGE
DEVICE
XXX
Option (if any)
3 = automotive -40 to +125°C
6 = industrial -40 to +85°C
B = Plastic DIP
M = Plastic SOIC
ST72T251G1
ST72T251G2
Note: The ST72E251G2D0 (CERDIP 25 °C) is used as the EPROM version for the above devices.
98/100
ST72251
ST72251 MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72251
Package:
[ ] Dual in Line Plastic [ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:
Special Marking:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
[ ] No
[ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: SDIP32:
SO28:
10
8
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99/100
ST72251
9 SUMMARY OF CHANGES
Change Description (Rev. 1.5 to 1.6)
Page
Added new External Connections section
Removed RP external resistor .
8
15
Changed ORed to ANDed in External interrupts paragraph, to read “If several input pins, con-
nected to the same interrupt vector, are configured as interrupts, their signals are logically AN-
Ded before entering the edge/level detection block”.
17 and 23
Added note ”Any modification of one of these two bits resets the interrupt request related to
this interrupt vector.”
22
Added clamping diodes to I/O pin figure and table
Added sections on low power modes and interrupts to peripheral descriptions
Changed 16-bit timer Chapter
25
30,42,54,72,77
31 to 47
43
Added details to description of FOLV1 and FOLV2 bits
Added ADC recommended external connections
Added Reset characteristics section
77
88
Added figure to ADC electrical characteristics section
89
Change Description (Rev. 1.6 to 1.7)
SPR2 bit reinstated in SPI chapter
63 to 75
74
Change Description (Rev. 1.7 to 1.8) of 31 May 2001
SPI frequency changed from f
/2 to f
/4 in Table 16
CPU
CPU
Change Description (Rev. 1.8 to 1.9) of 7 June 2001
Changed section 7.3 on page 88 (IDD value for OTP versions).
88
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
100/100
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