ST72752J6B1_技术文档

ST7275-2

8-BIT, 42-PIN MCU FOR MONITORS WITH UP TO 32K ROM, 1K

2

RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I C

■ User ROM/OTP/EPROM: up to 32 Kbytes

■ Data RAM: up to 1 Kbytes (256 bytes stack)

■ 8 MHz Maximum Internal Clock Frequency in

fast mode, 4 MHz in normal mode

■ Run, Wait and Halt CPU modes

■ Sync Processor for Mode Recognition, power

management and composite video blanking,

clamping

and

free-running

frequency

generation.

– Corrector mode

– Analyzer mode

2

■ Fast I C Multi Master Interface

■ DDC Bus Interface fully compliant with DDC1,

PSDIP42

2B, 2B+, 2AB, 2Bi standards

■ 23 I/O lines

– 1 high current I/O (10 mA)

– Up to 5 high voltage outputs (9V)

■ 16-bit timer with 2 input captures and 2 output

compare functions (with 1 output pin)

■ 8-bit Analog to Digital Converter with 4 channels

Device Summary

on port B

Features

ST72752J6 ST72752J5 ST72752J4

ROM

(bytes)

■ 8 10-bit PWM/BRM Digital to Analog outputs

■ One 12-bit PWM/BRM Digital to Analog output

■ Master Reset and Power on/off reset

32K

1K

24K

768

16K

512

RAM

(bytes)

1

■ Programmable Watchdog for system reliability

■ 42-pin Shrink Dual In line Plastic package

■ Fully static operation

ADC

4 channels

Timer

1

2

I C Bus

one multimaster

o

■ 0 to + 70 C Operating Temperature Range

DDC/DMA

Sync

yes

9

■ 4.5V to 5.5V supply operating range

■ 24 MHz Quartz Oscillator

■ 63 basic instructions/17 main address modes

■ 8x8 unsigned multiply instruction

■ True bit manipulation

■ Versatile Development Tools (DOS and

Windows) including assembler, linker, C-

compiler, archiver, source level debugger,

programmer, and hardware emulator

PWM

I/O

23

EPROM

Device

ST72E752J6D1

ST72T752J6B1

OTP

Device

Note 1: Power On/Off reset not implemented in

this revision.

Rev. 1.7

September 2000

1/131

1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 EPROM/OTP PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.2 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Power On/Off and Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.2 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.2 Common Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4

4.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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2

4.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4 SYNC PROCESSOR (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.4.3 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4.4 Input Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4.5 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4.6 Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4.7 Output Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.4.8 Analyzer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.4.9 Corrector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.4.10 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.5 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.6 DDC / DMA INTERFACE (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.6.2 DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.6.3 DMA (Direct Memory Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.7 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3/131

6.1 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.2 AC/DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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ST7275-2

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST7275 is a HCMOS microcontroller unit

(MCU) from the ST7 family with dedicated periph-

erals for Monitor applications.

In addition to standard 8-bit data management the

ST7 features true bit manipulation, 8x8 unsigned

multiplication and indirect addressing modes.

It is based around an industry standard 8-bit core

and offers an enhanced instruction set. The proc-

essor runs with an external clock at 24 MHz with

a 5V supply. Due to the fully static design of this

device, operation down to DC is possible. Under

software control the ST7275 can be placed in

WAIT or HALT mode thus reducing power con-

sumption. The enhanced instruction set and ad-

dressing modes afford real programming potential.

The device includes an on-chip oscillator, CPU,

Sync Processor for video timing & Vfback analy-

sis, up to 32K ROM, up to 1K RAM, I/O, a timer

with 2 input captures and 2 output compares, a 4-

channel Analog to Digital Converter, DDC/DMA,

I C multi Master, Watchdog Reset, and one 12-bit

and eight 10-bit PWM/BRM outputs for analog DC

control of external functions.

2

Figure 1. ST7275-2 Block Diagram

PA1

Up to 32K Bytes

PA3-PA6

PORT A

PORT B

ADC

PA7/BLANKOUT

ROM/OTP/EPROM

PB0/VFBACK/AIN0

PB1-PB2/AIN1-AIN2

PB7/AIN3

Up to 1K Bytes

RAM

V

DDA

V

SSA

PORT C

PC0/OCMP/HFBACK

PC2/RX/SCLD

PC3/SDAD

PC4/SCLI

2

I C

CONTROL

RESET

PC5/SDAI

PC6

DDC

8-BIT CORE

ALU

TIMER

WATCHDOG

Mode

VSYNCI

HSYNCI

SYNC

PROCESSOR

OSCIN

PD0/CSYNCI

PD1/HSYNCO

PD2/VSYNCO

PD3/ITC

PD4/ITB

PD5/ITA

:3

OSC

Selection

OSCOUT

V

DD

POWER SUPPLY

V

SS

PORT D

PD6/CLAMPOUT

DA0, DA1, DA8

DAC (PWM)

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3

ST7275-2

1.2 PIN DESCRIPTION

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA0

1

2

TEST/V

RESET

PA1

PP

3

4

PA3

5

PA4

6

7

PA5

8

PA6

V

PA7/BLANKOUT

OSCIN

9

SSA

DDA

V

10

11

12

13

14

15

16

17

18

19

20

21

AIN3/PB7

AIN2/PB2

AIN1/PB1

OSCOUT

PC6

PC5/SDAI

VFBACK/AIN0/PB0

VSYNCI

PC4/SCLI

PC3/SDAD

CLAMPOUT/PD6

ITA/PD5

PC2/RX/SCLD

PC0/OCMP/HFBACK

ITB/PD4

ITC/PD3

V

DD

HSYNCI

VSYNCO/PD2

HSYNCO/PD1

V

SS

PD0/CSYNCI

RESET Bidirectional. This active low signal forces

the initialization of the MCU. This event is the top

priority non maskable interrupt. This pin is

switched low when the Watchdog has triggered or

V

: Power supply voltage (4.5V-5.5V)

DD

: Digital Ground.

SS

V_DDA: Power Supply for analog peripheral (ADC).

and V must be connected together on the

V

DDA

DD

V

is low. It can be used to reset external periph-

DD

PCB.

erals.

V

_SSA: Ground for analog peripheral (ADC). V

SSA

OSCIN/OSCOUT Input/Output Oscillator pin.

These pins connect a parallel-resonant crystal, or

an external source to the on-chip oscillator.

and V must be connected together on the PCB.

SS

Alternate Functions: several pins of the I/O ports

assume software programmable alternate func-

tions as shown in the pin description.

TEST/VPP: EPROM programming input. This pin

must be held low during normal operating modes.

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ST7275-2

PIN DESCRIPTION (Cont’d)

Table 1. Pin Description

Pin Name

DA1

Type

Description

10-bit PWM/BRM output

Remarks

1

O

2

3

4

5

6

7

8

DA2

DA3

DA4

DA5

DA6

DA7

DA8

10-bit PWM/BRM output

For analog controls, af-

ter external filtering

Must be connected ex-

9

V

S

Ground for analog peripheral (ADC)

SSA

DDA

ternally to V

ss

Must be connected ex-

ternally to V

10

Power Supply for analog peripheral (ADC)

DD

11

12

13

PB7/AIN3

PB2/AIN2

PB1/AIN1

I/O

Port B7 or ADC analog input 3

Port B2 or ADC analog input 2

Port B1 or ADC analog input 1

PB0/VFBACK/

AIN0

Port B0 or SYNC Vertical flyback input or ADC analog TTL levels with pull-up

14

15

I/O

I

input 0

(SYNC input)

TTL levels with pull-up-

Refer to Figure 16

VSYNCI

SYNC vertical synchronisation

16

17

18

19

20

21

PD6/CLAMPOUT

PD5/ITA

I/O

Port D6 or SYNC clamping/MOIRE output

Port D5 or Interrupt falling edge detector input

Port D4 or Interrupt falling edge detector input

Port D3 or Interrupt falling edge detector input

Port D2 or SYNC vertical synchronisation output

Port D1 or SYNC horizontal synchronisation output

PD4/ITB

PD3/ITC

PD2/VSYNCO

PD1/HSYNCO

TTL levels with pull-up

(SYNC input)

22

23

PD0/CSYNCI

I/O

S

Port D0 or SYNC composite synchronisation input

Ground 0V

V

SS

TTL levels with pull-up

Refer to Figure 16.

24

HSYNCI

I

SYNC horizontal synchronisation input

Supply (4V - 5.5V)

25

26

V

S

DD

PC0/HFBACK/

OCMP

Port C0 or SYNC horizontal flyback input or TIMER out- TTL levels with pull-up

I/O

put compare

(SYNC input)

Port C2 or Interrupt falling edge detector input or DDC

serial clock

27

PC2/RX/SCLD

I/O

28

29

30

31

PC3/SDAD

PC4/SCLI

PC5/SDAI

PC6

I/O

Port C3 or DDC serial data

Port C4 or I2C serial clock

Port C5 or I2C serial data

Port C6

High current

7/131

ST7275-2

PIN DESCRIPTION (Cont’d)

Pin Name

OSCOUT

Type

Description

Remarks

32

33

34

35

36

37

38

39

40

O

Oscillator output

Oscillator input

OSCIN

PA7/BLANKOUT

PA6

I

I/O

Port A7 or SYNC blanking output

Port A6

Port A5

Port A4

Port A3

Port A1

Reset pin

High voltage (9V)

Active low

PA5

PA4

PA3

PA1

RESET

Test mode pin or EPROM programming voltage (this

pin should be tied low in user mode)

41

42

TEST/VPP

DA0

S

For analog controls, af-

ter external filtering

O

12-bit PWM/BRM output

8/131

ST7275-2

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended ex-

ternal connections for the device.

The external reset network is intended to protect

the device against parasitic resets, especially in

noisy environments.

The V pin is only used for programming OTP

PP

and EPROM devices and must be tied to ground in

user mode.

Unused I/Os should be tied high to avoid any un-

necessary power consumption on floating lines.

An alternative solution is to program the unused

ports as inputs with pull-up.

The 10 nF and 0.1 µF decoupling capacitors on

the power supply lines are a suggested EMC per-

formance/cost tradeoff.

Figure 2. Recommended External Connections

V

PP

V

DD

SS

+

0.1µF

10nF

V

DD

4.7K

0.1µF

RESET

EXTERNAL RESET CIRCUIT

See

Clocks

OSCIN

Section

OSCOUT

Or configure unused I/O ports

by software as input with pull-up

10K

V

DD

Unused I/O

9/131

ST7275-2

1.4 MEMORY MAP

Figure 3. Program Memory Map

0000h

0060h

HW Registers

Short Addressing

RAM (zero page)

(see Table 3)

005Fh

0060h

0100h

01FFh

Stack

RAM

256 bytes

512 bytes

768 bytes

025Fh

035Fh

Reserved

1 Kbytes

7FFFh

8000h

03FFh

32K Bytes ROM

24K Bytes ROM

A000h

C000h

16K Bytes

ROM

FFDFh

FFE0h

Interrupt & Reset Vectors

(see Table 4)

FFFFh

Table 2. ROM and RAM Sizes

ROM

Start Address End Address Size (Bytes)

RAM

Device

Size (Bytes)

32K (32768)

24K (24576)

16K (16384)

Start Address End Address

ST72752J6

ST72752J5

ST72752J4

8000h

A000h

C000h

FFFFh

1K (928)

768

60h

3FFh

35Fh

25Fh

512

10/131

ST7275-2

MEMORY MAP (Cont’d)

Table 3. Hardware Register Memory Map

Reset

Status

Address

Block

Register Label

Register Name

Port A Data Register

Remarks

0000h

0001h

PADR

00h

R/W

Port A

PADDR

Port A Data Direction Register

00h

R/W

0002h

0003h

PCDR

Port C Data Register

00h

R/W

Port C

Port D

PCDDR

Port C Data Direction Register

0004h

0005h

PDDR

Port D Data Register

00h

R/W

PDDDR

Port D Data Direction Register

0006h

0007h

0008h

PBDR

Port B Data Register

00h

R/W

Port B

PBDDR

PBICFGR

Port B Data Direction Register

Port B Input Pull-Up Configuration Register 00h

0009h

MISCR

Miscellaneous Register

00h

R/W

000Ah

000Bh

ADCDR

ADC Data Register

00h

Read only

R/W

ADC

ADCCSR

ADC Control Status register

000Ch

WDG

WDGCR

ITRFRE

Watchdog Control Register

Reserved Area (3 bytes)

Interrupt Register

7Fh

R/W

000Dh

000Fh

00010h ITR

00h

0011h

0012h

0013h

0014h

0015h

0016h

TIMCR2

Timer Control Register 2

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

TIMCR1

Timer Control Register 1

R/W

TIMSR

Timer Status Register

Read only

R/W

TIMIC1HR

TIMIC1LR

TIMOC1HR

TIMOC1LR

TIMCHR

Timer Input Capture 1 High Register

Timer Input Capture 1 Low Register

Timer Output Compare 1 High Register

Timer Output Compare 1 Low Register

Timer Counter High Register

0017h

TIM

R/W

0018h

Read only

R/W

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

TIMCLR

Timer Counter Low Register

TIMACHR

TIMACLR

TIMIC2HR

TIMIC2LR

TIMOC2HR

TIMOC2LR

Timer Alternate Counter High Register

Timer Alternate Counter Low Register

Timer Input Capture 2 High Register

Timer Input Capture 2 Low Register

Timer Output Compare 2 High Register

Timer Output Compare 2 Low Register

Read only

R/W

Read only

R/W

0020h

0021h

Reserved Area (2 bytes)

11/131

ST7275-2

MEMORY MAP (Cont’d)

Reset

Status

Address

Block

Register Label

Register Name

Remarks

R/W

0022h

0023h

PWM0

BRM0

12-BIT PWM Register

12-BIT BRM Register

80h

C0h

R/W

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

PWM1

BRM21

PWM2

PWM3

BRM43

PWM4

PWM5

BRM65

PWM6

PWM7

BRM87

PWM8

80h

00h

80h

00h

80h

00h

80h

00h

80h

R/W

PWM

10 BIT PWM / BRM

0030h

003Fh

Reserved Area (16 bytes)

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

SYNCCFGR

SYNCMCR

SYNCCCR

SYNC Configuration Register

SYNC Multiplexer Register

SYNC Counter Register

00h

20h

00h

08h

00h

C3h

R/W

SYNCPOLR

SYNCLATR

SYNCHGENR

SYNCVGENR

SYNCENR

SYNC Polarity Register

SYNC

SYNC Latch Register

SYNC H Sync Generator Register

SYNC V Sync Generator Register

SYNC Processor Enable Register

12/131

ST7275-2

MEMORY MAP (Cont’d)

Reset

Status

Address

Block

Register Label

Register Name

Remarks

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

DDCIADHR

DDCIADLR

DDCCADHR

DDCCADLR

DDCICTR

DMA Initial High Address Register

DMA Initial Low Address Register

DMA current High Address Register

DMA current Low Address Register

DMA Initial Counter Register

DMA current Counter Register

DMA Control Register

xxh

R/W

xxh

00h

R/W

DDCCCTR

DDCCTLR

Reserved

DDC

0050h

0051h

0052h

0053h

0054h

0055h

0056h

DDCCR

DDC Control Register

DDC Status Register 1

DDC Status Register 2

DDC Clock Control Register

DDC (7 Bits) Slave address Register

Reserved

00h

R/W

DDCSR1

DDCSR2

DDCCCR

DDCOAR

Read only

R/W

DDCDR

DDC Data Register

00h

R/W

0057h

0058h

Reserved Area (2 bytes)

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

I2CDR

I2C Data Register

Reserved

00h

2

I2COAR

I2CCCR

I2CSR2

I2CSR1

I2CCR

I C (7 Bits) Slave Address Register

00h

R/W

2

I2C

I C Clock Control Register

R/W

2

I C Status Register 2

Read only

R/W

2

I C Status Register 1

2

I C Control Register

Table 4. Interrupt Vector Map

Vector Address

Description

Remarks

FFE0-FFE1h

FFE2-FFE3h

FFE4-FFE5h

FFE6-FFE7h

FFE8-FFE9h

FFEA-FFEBh

FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

FFFA-FFFBh

FFFC-FFFDh

FFFE-FFFFh

Not used

I2C interrupt vector

Internal Interrupts

External Interrupts

Timer Overflow interrupt vector

Timer Output Compare interrupt vector

Timer Input Capture interrupt vector

Not used

RX falling edge interrupt vector

ITA falling edge interrupt vector

ITB falling edge interrupt vector

ITC falling edge interrupt vector

Not used

DDC/DMA (OR wiring) interrupt vector

Not used

Internal Interrupt

CPU Interrupt

TRAP (software) interrupt vector

RESET vector

13/131

ST7275-2

1.5 EPROM/OTP PROGRAM MEMORY

The 32 Kbytes of EPROM/OTP of the ST72E75/

ST72T75 may be programmed using the EPROM

programming boards available from STMicroelec-

tronics.

mended to cover the window of the ST72E75

packages by an opaque label to prevent uninten-

tional erasure problems when testing the applica-

tion in such an environment.

EPROM Erasing

The recommended erasure procedure of the

EPROM is the exposure to short wave ultraviolet

light which have a wave-length 2537Å. The inte-

grated dose (i.e. U.V. intensity x exposure time) for

erasure should be a minimum of 15W-sec/cm2.

The erasure time with this dosage is approximate-

ly 30 minutes using an ultraviolet lamp with a

12000 mW/cm2 power rating. The ST72E75

should be placed within 2.5 cm (1 inch) of the lamp

tubes during erasure.

The EPROM of the windowed package of the

ST72E75 can be erased by exposure to Ultra-Vio-

let light.

The erasure characteristic of the ST72E75 is such

that erasure begins when the memory is exposed

to light with wave lengths shorter than approxi-

mately 4000Å. It should be noted that sunlight and

some types of fluorescent lamps have wave-

lengths in the range 3000-4000Å. It is recom-

14/131

ST7275-2

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

2.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 4 are not

present in the memory mapping and are accessed

by specific instructions.

Figure 4. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

H I N Z

C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

15/131

ST7275-2

CENTRAL PROCESSING UNIT (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

ter it and reset by the IRET instruction at the end of

the interrupt routine. If the I bit is cleared by soft-

ware in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

These bits can be individually tested and/or con-

trolled by specific instructions.

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask.

Bit 0 = C Carry/borrow.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

because the I bit is set by hardware when you en-

16/131

ST7275-2

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Read/Write

Reset Value: 01 FFh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 5.

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 5).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 256 bytes deep, the most signif-

icant byte is forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP7 to SP0 bits are set) which is the stack

higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 5. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 01FFh

Stack Higher Address = 01FFh

0100h

Stack Lower Address =

17/131

ST7275-2

3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

A division factor of 2 is added to generate the 12

MHz clock for theSync Processor (clamp function)

as shown in Figure 6. The CPU clock is used also

as clock for the ST7275 peripherals.

The MCU accepts either a crystal or an external

clock signal to drive the internal oscillator. The in-

ternal clock (CPU CLK running at f

from the external oscillator frequency (f

which is first divided by 3 and then optionally fur-

ther divided by 2, if the normal mode is selected in

) is derived

CPU

),

Note: In the Sync processor, an additional divider

by two is added in fast mode (same external timing

for this peripheral).

OSC

the miscellaneous register (fast mode bit =0).

.

Figure 6. Clock divider chain

%2

12 MHz

(Sync processor clampout signal)

%3

%2

f

: 4 or 8 MHz

OSC

CPU

normal or fast mode

(CPU and peripherals)

24MHz

FAST

18/131

ST7275-2

CLOCK SYSTEM (Cont’d)

3.1.2 Crystal Resonator

Table 5. Recommended Crystal Values

The internal oscillator is designed to operate with

an AT-cut parallel resonant quartz crystal resona-

24 Mhz

Unit

Ohms

pf

R

70

22

25

47

20

56

SMAX

tor in the frequency range specified for f . The

osc

C

circuit shown in Figure 7 is recommended when

using a crystal, and Table 5 lists the recommend-

ed capacitance and feedback resistance values.

The crystal and associated components should be

mounted as close as possible to the input pins in

order to minimize output distortion and start-up

stabilization time.

L1

C

pf

L2

Legend:

C , C = Maximum total capacitance on pins

L1

L2

OSCIN and OSCOUT (the value includes the ex-

ternal capacitance tied to the pin plus the parasitic

capacitance of the board and of the device).

Figure 7. Crystal/Ceramic Resonator

R

= Maximum series parasitic resistance of

SMAX

the quartz allowed.

CRYSTAL CLOCK

Note: The tables are relative to the quartz crystal

only (not ceramic resonator).

3.1.3 External Clock

An external clock should be applied to the OSCIN

input with the OSCOUT pin not connected as

shown in Figure 8. The Crystal clock specifications

do not apply when using an external clock input.

The equivalent specification of the external clock

source should be used.

OSCIN

OSCOUT

C

L1

L2

Figure 8. External Clock Source Connections

1M*

*Recommended for oscillator stability

OSCIN

OSCOUT

NC

EXTERNAL

CLOCK

19/131

ST7275-2

3.2 RESET

The Reset procedure is used to provide an orderly

software start-up or to quit low power modes.

3.2.1 Power On/Off and Watchdog Reset

Power on/off circuitry generates a reset when V

DD

Three reset modes are provided: a power on/off

reset, a watchdog reset and an external reset at

the RESET pin.

is below V

whenV isrising or V

when

TRH

DD

TRL VDD

is falling (refer to Figure 10). This circuitry is active

only when V is above V

DD

TRM.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

During Power on/off Reset, the RESET pin is held

low, thuspermitting theMCU to resetother devices.

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other devic-

es in the same way as when Power on/off (Figure

9) occurs.

An internal circuitry provides a 4096 CPU clock cy-

cle delay from the time that the oscillator becomes

active.

3.2.2 External Reset

The Reset pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, the best external network is a double

The external reset is an active low input signal ap-

plied to the RESET pin of the MCU.

As shown Figure 11, the RESET signal must stay

low for a minimum of one and a half CPU clock cy-

cles.

capacitive decoupling consisting of 0.1 µF to V

SS

and 0.1 µF to V

.

DD

An internal Schmitt trigger at the RESET pin is pro-

vided to improve noise immunity.

Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.6 for Wait and Halt Modes)

Section

RESET

WAIT

HALT

CPU clock running at 4 MHz

Timer Prescaler reset to zero

Timer Counter set to FFFCh

X

All Timer enable bits set to 0 (disabled)

Data Direction Registers set to 0 (as Inputs)

Set Stack Pointer to 01FFh

Force Internal Address Bus to restart vector FFFEh, FFFFh

Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)

Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)

Reset HALT latch

X

Reset WAIT latch

Disable Oscillator (for 4096 cycles)

Set Timer Clock to 0

X

Watchdog counter reset

Watchdog register reset

Port data registers reset

Other on-chip peripherals: registers reset

20/131

ST7275-2

RESET (Cont’d)

Figure 9. POWER ON/OFF Functional Diagram

Figure 10. POWER ON/OFF Signal Output

V

TRH

RESPOF

V

POWER ON/OFF

TRL

V

DD

V

TRM

V

RESET

TRM

V

DD

INTERNAL

RESET

FROM

WATCHDOG

RESET

Note: Typical hysteresis (V

expected

-V

) of 250 mV is

TRH TRL

Figure 11. Reset Timing Diagram

t

DDR

V

DD

OSCIN

t_OXOV

f

CPU

FFFF

FFFE

PC

RESET

4096 CPU

CLOCK

CYCLES

DELAY

WATCHDOG RESET

Note: Refer to Electrical Characteristics for values of t

, t_OXOV, V

, V

and V

DDR

TRH

TRL TRM

21/131

ST7275-2

3.3 INTERRUPTS

The ST7275 may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in Table 7 and a non-maskable software in-

terrupt (TRAP). The Interrupt processing flowchart

is shown in Figure 12.

The maskable interrupts must be enabled in order

to be serviced. However, disabled interrupts can

be latched and processed when they are enabled.

When an interrupt has to be serviced, the PC, X, A

and CC registers are saved onto the stack and the

interrupt mask (I bit of the Condition Code Regis-

ter) is set to prevent additional interrupts. The Y

register is not automatically saved.

RX interrupt. The RX (PC2) pin can generate an

interrupt when a falling edge occurs on this pin, if

this interrupt is enabled with the RXITE bit in the

miscellaneous register and the I bit of the CC reg-

ister is reset. When an enabled interrupt occurs,

normal processing is suspended at the end of the

current instruction execution. It is then serviced

according to the flowchart on Figure 12. Software

in the RX service routine must reset the cause of

this interrupt by clearing the RXLAT or RXITE bits

in the miscellaneous register.

ITA, ITB, ITC interrupts. The ITA (PD5), ITB

(PD4), ITC (PD3) pins can generate an interrupt

when a falling edge occurs on these pins, if these

interrupts are enabled with the ITAITE, ITBITE, IT-

CITE bits respectively in the ITRFRE register and

the I bit of the CC register is reset.

The PC is then loaded with the interrupt vector of

the interrupt to service and the interrupt service

routine runs (refer to Table 7 for vector address-

es). The interrupt service routine should finish with

the IRET instruction which causes the contents of

the registers to be recovered from the stack and

normal processing to resume. Note that the I bit is

then cleared if and only if the corresponding bit

stored in the stack is zero.

Though many interrupts can be simultaneously

pending, a priority order is defined (see Table 7).

The RESET pin has the highest priority.

If the I bit is set, only the TRAP interrupt is ena-

bled.

Peripheral Interrupts. Different peripheral inter-

rupt flags are able to cause an interrupt when they

are active if both the I bit of the CC register is reset

and if the corresponding enable bit is set. If either

of these conditions is false, the interrupt is latched

and thus remains pending.

The interrupt flags are located in the status regis-

ter. The Enable bits are in the control register.

When an enabled interrupt occurs, normal

processing is suspended at the end of the current

instruction execution. It is then serviced according

to the flowchart on Figure 12.

All interrupts allow the processor to leave the

WAIT low power mode. Only external interrupts

and allow the processor to leave the HALT low

power mode.

The general sequence for clearing an interrupt is

an access to the status register while the flag is set

followed by a read or write of an associated regis-

ter. Note that the clearing sequence resets the in-

ternal latch. A pending interrupt (i.e. waiting for be-

ing enabled) will therefore be lost if the clear se-

quence is executed.

Software Interrupt. The software interrupt is the

executable instruction TRAP. The interrupt is rec-

ognized when the TRAP instruction is executed,

regardless of the state of the I bit. When the inter-

rupt is recognized, it is serviced according to the

flowchart on Figure 12.

22/131

ST7275-2

INTERRUPTS (Cont’d)

INTERRUPT FALLING EDGE REGISTER

(ITRFRE)

Address: 0010h — Read/Write

Reset Value: 0000 0000 (00h)

7

0

-

ITALAT ITBLAT ITCLAT

0

ITAITE ITBITE ITCITE

Bit 7:5 = ITALAT, ITBLAT, ITCLAT Falling Edge

Detector Latches.

These bits are set by hardware when a falling

edge occurs on pins ITA/PD5 & ITB/PD4 or ITC/

PD3 in Port D. They are cleared by software.

When any of these bits are set, an interrupt is gen-

erated if the corresponding ITAITE, ITBITE or IT-

CITE bit =1 and the I bit in the CC register = 0.

0: No falling edge detected

1: Falling edge detected

Bit 4 = Reserved, forced by hardware to 0.

Bit 3:1 = ITAITE, ITBITE, ITCITE Interrupt Enable

Bits.

These bits are set and cleared by software.

0: Interrupt disabled

1: Interrupt enabled

Bit 0 = Reserved, must always be cleared.

23/131

ST7275-2

INTERRUPTS (Cont’d)

Figure 12. Interrupt Processing Flowchart

I

FROM RESET

Y

TRAP?

N

I BIT SET?

Y

N

INTERRUPT?

FETCH NEXT INSTRUCTION

Y

N

EXECUTE INSTRUCTION

IRET?

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM INTERRUPT VECTOR

Y

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

VR01172D

24/131

ST7275-2

INTERRUPTS (Cont’d)

Table 7. Interrupt Mapping

Source

Register

Label

Maskable

by I-bit

Exit from

HALT

Vector

Address

Priority

Order

Description

Block

Flag

RESET

TRAP

Reset

N/A

no

yes

no

FFFEh-FFFFh

Software

FFFCh-FFFDh

SR1

SR2

DDC

DDC Interrupt

**

yes

no

FFF8h-FFF9h

Port D bit 3

Port D bit 4

Port D bit 5

Port C bit 2

External Interrupt ITC

External Interrupt ITB

External Interrupt ITA

External Interrupt RX

Input Capture 1

ITRFRE ITCLAT

ITBLAT

yes

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

ITALAT

MISCR

TIMSR

RXLAT

ICF1

yes

no

FFEAh-FFEBh

Input Capture 2

ICF2

TIM

I2C

Output Compare 1

Output Compare 2

Timer Overflow

OCF1

OCF2

TOF

yes

no

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

Lowest

Priority

I2CSR1

I2CSR2

I C Peripheral Interrupts

**

** Many flags can cause an interrupt, see peripheral interrupt status register description.

25/131

ST7275-2

3.4 POWER SAVING MODES

3.4.1 WAIT Mode

Figure 13. WAIT Flow Chart

This mode is a low power consumption mode. The

WFI instruction places the MCU in WAIT mode:

The internal clock remains active but all CPU

processing is stopped; however, all other peripher-

als are still running.

WFI INSTRUCTION

Note: In WAIT mode DMA (DDC) accesses are

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

possible.

ON

During WAIT mode, the I bit in the condition code

register is cleared to enable all interrupts, which

causes the MCU to exit WAIT mode, causes the

corresponding interrupt vector to be fetched, the

interrupt routine to be executed and normal

processing to resume. A reset causes the program

counter to fetch the reset vector and processing

starts as for a normal reset.

OFF

CLEARED

N

Table 6 gives a list of the different sections affect-

ed by the low power modes. For detailed informa-

tion on a particular device, please refer to the cor-

responding part.

RESET

N

Y

INTERRUPT

Y

OSCILLATOR

ON

SET

PERIPH. CLOCK

CPU CLOCK

I-BIT

IF RESET

4096 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

26/131

ST7275-2

POWER SAVING MODES (Cont’d)

3.4.2 HALT Mode

Figure 14. HALT Flow Chart

The HALT mode is the MCU lowest power con-

sumption mode. The HALT mode is entered by ex-

ecuting the HALT instruction. The internal oscilla-

tor is then turned off, causing all internal process-

ing to be stopped, including the operation of the

on-chip peripherals. HALT mode cannot be used

when the watchdog is enabled, if the HALT in-

struction is executed while the watchdog system is

enabled, a watchdog reset is generated thus re-

setting the entire MCU.

HALT INSTRUCTION

WDG

Y

WATCHDOG

RESET

ENABLED?

When entering HALT mode, the I bit in the Condi-

tion Code Register is cleared. Thus, any of the ex-

ternal interrupts ITALAT, ITBLAT, ITCLAT or

RXLAT are allowed and if an interrupt occurs, the

CPU clock becomes active.

N

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

OFF

The MCU can exit HALT mode on reception of ei-

ther an external interrupt on RX, ITA, ITB or ITC or

a reset. The oscillator is then turned on and a sta-

bilization time is provided before releasing CPU

operation. Thestabilization time is 4096 CPU clock

cycles.

CLEARED

After the start up delay, the CPU continues opera-

tion by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

N

RESET

N

EXTERNAL

Y

INTERRUPT*

Y

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

SET

4096 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

27/131

ST7275-2

3.5 MISCELLANEOUS REGISTER

MISCELLANEOUS REGISTER (MISCR)

Address: 0009h — Read/Write

Reset Value: 0000 0000 (00h)

Bit 2:0 = POC[2:0] PWM/BRM Output Configura-

tion Bits.

These bits are set and cleared by software. They

select the PWM/BRM output configuration.

7

0

RXLAT RXITE FAST

-

POC2 POC1 POC0

PWM

Value

Group Channels

DA1.. DA4 P0C0

DA5,DA6 P0C1

DA7,DA8 P0C2

O

1

Bit 7 = RXLAT Falling Edge Detector Latch.

This bit is set by hardware when a falling edge oc-

curs on pin RX/PC2 in Port C. An interrupt is gen-

erated if RXITE=1 It is cleared by software.

0: No falling edge detected on RX

push-pull

open drain

1: Falling edge detected on RX

Note. DA0 is only Push-Pull Output.

Bit 6 = RXITE RX Interrupt Enable.

This bit is set and cleared by software.

0: RX interrupt disabled

1: RX interrupt enabled

Bit 5 = FAST Fast Mode.

This bit is set and cleared by software. It is used to

select the normal or fast mode CPU frequency.

0: f

1: f

= 4 MHz (normal mode)

= 8 MHz (fast mode)

CPU

Bit 4:3 = Reserved

28/131

ST7275-2

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

Each pin can be programmed independently as

digital input or digital output. Each pin can be an

analog input when an analog switch is connected

to the Analog to Digital Converter (ADC).

The I/O ports allow the transfer of data through

digital inputs and outputs, and, for specific pins,

the input of analog signals or the Input/Output of

alternate signals for on-chip peripherals (DDC,

TIMER...).

Figure 15. I/O Pin Typical Circuit

Alternate enable

1

V

Alternate

output

DD

0

P-BUFFER

(if required)

DR

latch

PULL-UP (if required)

Alternate enable

DDR

latch

PAD

Analog Enable

(ADC)

Analog

DDR SEL

Switch (if required)

N-BUFFER

1

DR SEL

Alternate Enable

VSS

0

Digital Enable

Alternate Input

Note: This is the typical I/O pin configuration. For cost optimisation, each port is customised with a specific

configuration.

29/131

ST7275-2

I/O PORTS (Cont’d)

Table 8. I/O Pin Functions

4.1.2.3 Analog input

Each I/O can be used as analog input by adding

an analog switch driven by the ADC.

The I/O must be configured in Input without pull-up

before using it as analog input.

DDR

MODE

Input

0

1

Output

The CMOS Schmitt trigger is OFF (write FFh twice

in the ICFGR register) and the analog value direct-

ly input through an analog switch to the Analog to

Digital Converter, when the analog channel is se-

lected by the ADC.

4.1.2 Common Functional Description

Each port pin of the I/O Ports can be individually

configured under software control as either input

or output.

4.1.2.4 Alternate mode

Each bit of a Data Direction Register (DDR) corre-

sponds to an I/O pin of the associated port. This

corresponding bit must be set to configure its as-

sociated pin as output and must be cleared to con-

figure its associated pin as input (Table 8). The

Data Direction Registers can be read and written.

A signal coming from a on-chip peripheral can be

output on the I/O.

In this case, the I/O is automatically configured in

output mode.

This must be controlled directly by the peripheral

with a signal coming from the peripheral which en-

ables the alternate signal to be output.

The typical I/O circuit is shown on Figure 15. Any

write to an I/O port updates the port data register

even if it is configured as input. Any read of an I/O

port returns either the data latched in the port data

register (pins configured as output) or the value of

the I/O pins (pins configured as input).

A signal coming from an I/O can be input in a on-

chip peripheral.

Before using an I/O as Alternate Input, it must be

configured in Input mode (DDR=0). So both Alter-

nate Input configuration and I/O Input configura-

tion are the same (with or without pull-up). The sig-

nal to be input in the peripheral is taken after the

CMOS Schmitt trigger or TTL Schmitt trigger for

SYNC.

Remark: when an I/O pin does not exist inside an

I/O port, the returned value is a logic one (pin con-

figured as input).

At reset, all DDR registers are cleared, which con-

figures all port’s I/Os as inputs with or without pull-

ups (see Table 9 to Table 13). The Data Registers

(DR) are also initialized at reset.

The I/O state is readable as in Input mode by ad-

dressing the corresponding I/O Data Register.

4.1.3 Port A

4.1.2.1 Input mode

Each Port A bit can be defined as an Input line (no

pull-up) or as an Output Open drain line. PA1,

PA3, PA4, PA5 and PA6 can also be used as high

voltage outputs (9V).

When DDR=0, the corresponding I/O is configured

in Input mode.

In this case, the output buffer is switched off, the

state of the I/O is readable through the Data Reg-

ister address, but the I/O state comes directly from

the CMOS Schmitt Trigger output and not from the

Data Register output.

Figure 16. Input Structure for SYNC signals

V

DD

4.1.2.2 Output mode

pull-up

When DDR=1, the corresponding I/O is configured

in Output mode.

In this case, the output buffer is activated accord-

ing to the Data Register’s content.

A read operation is directly performed from the

Data Register output.

TTL trigger

SYNC block

I/O logic (if existing)

30/131

ST7275-2

I/O PORTS (Cont’d)

Table 9. Port A Description

I / O

Alternate Function

Signal Condition

PORT A

Input*

Output

open drain (9V)

PA1

PA3

PA4

PA5

PA6

without pull-up

-

open drain (9V)

BLKEN = 1

(ENR[SYNC])

PA7

without pull-up

open drain

BLANKOUT

*Reset State

Figure 17. Port A

Alternate enable

1

Alternate

output

0

DR

latch

DDR

latch

PAD

DDR SEL

DR SEL

N-BUFFER

1

0

Alternate enable

VSS

CMOS Schmitt Trigger

31/131

ST7275-2

I/O PORTS (Cont’d)

4.1.4 Port B

All unused I/O lines should be tied to an appropri-

ate logic level (either V or V

)

SS

DD

Each bit of port B bit can be used as the Analog

source to the Analog to Digital Converter by se-

lecting each individual bit independently in the Port

B Configuration Register [ICFGR].

Since the ADC is on the same chip as the micro-

processor, the user should not switch heavily load-

ed signals during conversion, if high precision is

required. Such switching will affect the supply volt-

ages used as analog references. the accuracy of

the conversion depends on the quality of the pow-

Only one I/O line must be configured as an analog

input at any time. The user must avoid any situa-

tion in which more than one I/O pin is selected as

an analog input simultaneously to avoid device

malfunction.

er supplies (V

and V ). The user must take

DD

SS

special care to ensure that a well regulated refer-

ence voltage is present on the V and V pins

DD

SS

When the analog function is selected for an I/O

pin, the pull-up of the respective pin of Port B is

disconnected and the digital input is off.

(power supply variations must be less than 5V/

ms). This implies, in particular, that a suitable de-

coupling capacitor is used at the V pin.

DD

If the SYNC function is selected, Port B bit 0

MUST be set as input to enable the VFBACK tim-

ing input.

Table 10. Port B Description

PORT B

I/O

Alternate Function

Input*

Output

Signal

Condition

analog input (ADC) (without pull-up)

AD0=1 (ICFGR)

PB0

with pull-up

push-pull

VFBACK (input with TTL schmitt trigger)

AD0=0 (ICFGR)

PB1

with pull-up

push-pull

analog input (ADC) (without pull-up)

AD1=1 (ICFGR)

AD2=1 (ICFGR)

AD7=1 (ICFGR)

PB2

PB7

*Reset state

32/131

ST7275-2

I/O PORTS (Cont’d)

Figure 18. PB0

V

DD

P-BUFFER

DR

latch

PULL-UP

DDR

latch

ICFGR

latch

PAD

ICFGR SEL

analog enable

(ADC)

Analog

switch

DDR SEL

N-BUFFER

1

0

DR SEL

VSS

CMOS Schmitt Trigger

TTL Schmitt Trigger

Alternate input (VFBACK)

33/131

ST7275-2

I/O PORTS (Cont’d)

Figure 19. PB1, PB2, PB7

V

DD

P-BUFFER

DR

latch

PULL-UP

DDR

latch

ICFGR

latch

PAD

ICFGR SEL

Analog enable

(ADC)

Analog

switch

DDR SEL

N-BUFFER

1

0

DR SEL

VSS

CMOS Schmitt Trigger

34/131

ST7275-2

I/O PORTS (Cont’d)

4.1.5 Port C

DAD for PC2:3, the I/O pins of the on-chip I2C

SCLI & SCDAI for PC4:5, the Timer Output Com-

pare OCMP on PC0 and the input trigger falling

edge Detector RX for PC2.

The available port pins of port C may be used as

general purpose I/O.

The alternate functions are HFBACK input for

PC0, the I/O pins of the on-chip DDC SCLD & SC-

Table 11. Port C Description

I / O

Alternate Function

PORT C

Input*

Output

Signal

Condition

OC1E =1

(CR2[TIMER])

OCMP (push-pull)

PC0

PC2

with pull-up

push-pull

HFBACK (input with TTL schmitt trigger)

-

SCLD (input with CMOS schmitt trigger or open drain

output)

DDC enable

-

input without pull-up open-drain

RX (input)

SDAD (input with CMOS schmitt trigger or open drain

output)

PC3

PC4

PC5

PC6

input without pull-up open-drain

DDC enable

SCLI (input with CMOS schmitt trigger or open drain

output)

I2C enable

SDAI (input with CMOS schmitt trigger or open drain

output)

open-drain

input without pull-up

(10mA, 5V)

* Reset State

35/131

ST7275-2

I/O PORTS (Cont’d)

Figure 20. PC0

OC1E

1

V

DD

OCMP

0

P-BUFFER

DR

PULL-UP

latch

OC1E

DDR

latch

PAD

DDR SEL

N-BUFFER

1

DR SEL

OC1E

VSS

0

CMOS Schmitt Trigger

HFBACK input

TTL Schmitt Trigger

36/131

ST7275-2

I/O PORTS (Cont’d)

Figure 21. PC2 to PC6

Alternate enable

1

DR

latch

Alternate

output

0

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

Alternate enable

VSS

CMOS Schmitt Trigger

Alternate input

37/131

ST7275-2

I/O PORTS (Cont’d)

4.1.6 Port D

terrupt will be generated according to the status of

the INTX (ITAITE & ITBITE & ITCITE) bits in the

ITRFRE Register.

The Port D I/O pins PD0..3 are normally used for

the input and output of video synchronization sig-

nals of the Sync Processor, but are set to I/O Input

with pull-up upon reset. The I/O mode can be set

individually for each port bit to Input with pull-up

and output push-pull through the Port D DDR.

Port D, bit 6 is switched to the alternate (CLAM-

POUT) by resetting the CLMPEN bit of the ENR

Register inside SYNC block.

Note: As these inputs are switched from normal

I/O functionality, the video synchronization signals

may also be monitored directly through the Port D

Data Register for such tasks as checking for the

presence of video signals or checking the polarity

of Horizontal and Vertical synchronization signals

(when the Sync Inputs are switched directly to the

outputs using the multiplexers of the Sync Proces-

sor).

The configuration to support the Sync Processor

requires that the SYNOP (bit7) and CLMPEN

(bit6) of the ENR (Enable Register of SYNC) is re-

set. SYNOP enables port D bits 1, 2 and CLMPEN

enables Port D bit 6 to the sync outputs.

Port D, bit 5:3 are the alternate inputs ITA, ITB,

ITC (for the interrupt falling edge detector).

When a falling edge occurs on these inputs, an in-

Table 12. Port D Description

I / O

Alternate Function

PORT D

Input*

Output

Signal

Condition

CSYNCI

PD0

PD1

PD2

PD3

PD4

PD5

with pull-up

push-pull

-

(TTL Schmitt trigger & pull-up)

HSYNCO

SYNOP=0

with pull-up

push-pull

(push pull output)

(ENR [SYNC])

VSYNCO

SYNOP=0

(push pull output)

(ENR [SYNC])

ITC input with

-

(CMOS schmitt trigger & pull-up)

ITB input with

(CMOS schmitt trigger & pull-up)

ITA input with

(CMOS schmitt trigger & pull-up)

CLAMPOUT

CLMPEN=0

PD6

(push pull output)

(ENR [SYNC])

* Reset state

38/131

ST7275-2

I/O PORTS (Cont’d)

Figure 22. PD0

VDD

P-BUFFER

DR

PULL-UP

latch

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

VSS

CMOS Schmitt Trigger

CSYNCI input

TTL Schmitt Trigger

Figure 23. PD1 to PD6

Alternate enable

1

0

VDD

Alternate

output

P-BUFFER

DR

PULL-UP

latch

Alternate enable

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

Alternate enable

VSS

CMOS Schmitt Trigger

Alternate input

39/131

ST7275-2

4.1.7 Register Description

Data Registers (PxDR)

PORT B Configuration Register (ICFGR)

Read/Write

Reset Value: 0000 0000 (00h)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

AD7

-

AD2

AD1

AD0

MSB

LSB

Bit 7 = AD7 Digital/Analog Input Configuration Bit.

0: The pull-up is connected and pin configured as

digital input (reset condition)

1: The pull-up on pin 7i of Port B is disconnected

and the pin is configured as analog input .

Data Direction Registers (PxDDR)

Read/Write

Reset Value: 0000 0000 (00h) (as inputs)

7

0

Bit 6:3 = Reserved, forced by hardware to 0.

MSB

LSB

Bit 2:0 = AD[2:0] Digital/Analog Input Configura-

tion Bits.

0: The pull-up is connected and pin configured as

digital input (reset condition)

1: The pull-up on pin #i of Port B is disconnected

and the pin is configured as analog input .

Table 13. I/O Ports Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

00

01

02

03

04

05

06

07

08

PADR

PADDR

PCDR

MSB

AD7

LSB

AD0

PCDDR

PDDR

PDDDR

PBDR

PBDDR

ICFGR

Reserved

AD2

AD1

40/131

ST7275-2

4.2 WATCHDOG TIMER (WDG)

4.2.1 Introduction

4.2.2 Main Features

■ Programmable timer (64 increments of 49,152

CPU cycles)

■ Programmable reset

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

■ Reset (if watchdog activated) after a HALT

instruction or when the T6 bit reaches zero

Figure 24. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

T5 T0

T6

WDGA

T1

T4

T2

T3

7-BIT DOWNCOUNTER

CLOCK DIVIDER

f

CPU

÷ 49152

41/131

ST7275-2

WATCHDOG TIMER (Cont’d)

4.2.3 Functional Description

4.2.4 Low Power Modes

The counter value stored in the CR register (bits

T6:T0), is decremented every 49,152 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

Mode

Description

WAIT

No effect on Watchdog.

Immediate reset generation as soon as

the HALT instruction is executed if the

Watchdog is activated (WDGA bit is

set).

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 become cleared), it initiates a

reset cycle pulling low the reset pin for typically

500ns.

HALT

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 14):

4.2.5 Interrupts

None.

4.2.6 Register Description

CONTROL REGISTER (CR)

Read/Write

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

Reset Value: 0111 1111 (7Fh)

– The T5:T0bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

7

0

WDGA T6

T5

T4

T3

T2

T1

T0

Table 14. Watchdog Timing (f

= 8 MHz)

CPU

Bit 7= WDGA Activation bit.

CR Register

initial value

WDG timeout period

(ms)

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

Max

Min

FFh

C0h

393.216

6.144

0: Watchdog disabled

1: Watchdog enabled

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared) if WDGA=1.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction

will generate a Reset.

Table 15. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

0C

Reset Value

42/131

ST7275-2

4.3 16-BIT TIMER

4.3.1 Introduction

4.3.3 Functional Description

4.3.3.1 Counter

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

Counter Register (CR):

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modified.

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

4.3.2 Main Features

■ Programmable prescaler:f_CPUdividedby2, 4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slower thantheCPUclock speed)withthechoice

of active edge

■ Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 16. The

value in the counter register repeats every

131.072, 262.144 or 524.288 CPU clock cycles

depending on the CC[1:0] bits.

– 1 dedicated maskable interrupt

■ Input capture functions with

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ 5 alternatefunctionson I/O ports (ICAP1,ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 25.

*Note: Some timer pins may not available (not

bonded) in some ST7 devices. Refer to the device

pin out description.

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

43/131

ST7275-2

16-BIT TIMER (Cont’d)

Figure 25. Timer Block Diagram

ST7 INTERNAL BUS

f

CPU

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

EXEDG

h

w

h

w

h

w

h

low

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

ICF1 OCF1 TOF ICF2 OCF2

0

OCMP2

(Status Register) SR

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2 EXEDG

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

TIMER INTERRUPT

44/131

ST7275-2

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

is buffered

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

4.3.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in CR2 register.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronised with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

45/131

ST7275-2

16-BIT TIMER (Cont’d)

Figure 26. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 27. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 28. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

46/131

ST7275-2

16-BIT TIMER (Cont’d)

4.3.3.3 Input Capture

When an input capture occurs:

– ICFi bit is set.

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 30).

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition detected by the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

ICiHR

LS Byte

ICiLR

ICiR

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (f

/CC[1:0]).

CPU

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function select the follow-

ing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 16).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input).

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

And select the following in the CR1 register:

4. In One pulse Mode and PWM mode only the

input capture 2 can be used.

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture function.

– Select the edge of the active transition on the

ICAP1 pin with theIEDG1 bit (the ICAP1pin must

be configured as floating input).

Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user toggle

the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt in order

to measure event that go beyond the timer

range (FFFFh).

47/131

ST7275-2

16-BIT TIMER (Cont’d)

Figure 29. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

IEDG1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 30. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: Active edge is rising edge.

48/131

ST7275-2

16-BIT TIMER (Cont’d)

4.3.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicating when a period of time has

elapsed.

The OCiR register value required for aspecific tim-

ing application can be calculated using the follow-

ing formula:

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

∆t f

* CPU

PRESC

∆ OCiR =

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16)

PRESC

MS Byte

OCiHR

LS Byte

OCiLR

OCiR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆ OCiR = ∆t f

* EXT

Where:

Timing resolution is one count of the free running

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

counter: (f

).

CC[1:0]

CPU/

f

EXT

Procedure:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

To use the output compare function, select the fol-

lowing in the CR2 register:

1. Reading the SR register while the OCFi bit is

set.

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 16).

And select the following in the CR1 register:

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

– Select theOLVLi bit to applied to theOCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

49/131

ST7275-2

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

FOLVLi bits have no effect in both one pulse mode

and PWM mode.

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 32, on

page 51). This behaviour is the same in OPM

or PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 33, on page 51).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 31. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

FOLV2 FOLV1OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

50/131

ST7275-2

16-BIT TIMER (Cont’d)

Figure 32. Output Compare Timing Diagram, f

=f

/2

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 33. Output Compare Timing Diagram, f

=f

/4

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

51/131

ST7275-2

16-BIT TIMER (Cont’d)

4.3.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t _*f

To use one pulse mode:

CPU - 5

OCiR Value =

PRESC

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

Where:

t

= Output compare period (in seconds)

= ICPU clock frequency (in hertz)

2. Select the following in the CR1 register:

f

CPU

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16)

PRESC

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

∆ OCiR = ∆t f

-5

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

* EXT

Where:

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

3. Select the following in the CR2 register:

f

EXT

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 34).

– Select the timer clock CC[1:0] (see Table 16).

One pulse mode cycle

When

Notes:

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

OCMP1 = OLVL2

event occurs

on ICAP1

Counter is reset

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

to FFFCh

ICF1 bit is set

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

When

Counter

OCMP1 = OLVL1

= OC1R

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin, the ICF1 bit is set and the val-

ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

52/131

ST7275-2

16-BIT TIMER (Cont’d)

Figure 34. One Pulse Mode Timing Example

....

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 35. Pulse Width Modulation Mode Timing Example

34E2 FFFC FFFD FFFE

2ED0 2ED1 2ED2

34E2 FFFC

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

53/131

ST7275-2

16-BIT TIMER (Cont’d)

4.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

The OCiR register value required for aspecific tim-

ing application can be calculated using the follow-

ing formula:

t _*f

CPU

PRESC

- 5

OCiR Value =

The pulse width modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

register, and so these functionality can not be

used when the PWM mode is activated.

Where:

t

= Output compare period (in seconds)

= ICPU clock frequency (in hertz)

f

Procedure

CPU

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16)

To use pulse width modulation mode:

PRESC

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

If the timer clock is an external clock the formula is:

∆ OCiR = ∆t f

-5

* EXT

2. Load the OC1R register with the value corre-

sponding to the length of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

Where:

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

f

EXT

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 35)

Notes:

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

4. Select the following in the CR2 register:

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Select the timer clock (CC[1:0]) (see Table

16).

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Pulse Width Modulation cycle

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

When

Counter

= OC1R

OCMP1 = OLVL1

OCMP1 = OLVL2

When

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

54/131

ST7275-2

16-BIT TIMER (Cont’d)

4.3.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

WAIT

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

4.3.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the

CC register is reset (RIM instruction).

4.3.6 Summary of Timer modes

AVAILABLE RESOURCES

MODES

Input Capture 1

Input Capture 2

Yes

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1)

2)

3)

See note 4 in Section 4.3.3.5 One Pulse Mode

See note 5 in Section 4.3.3.5 One Pulse Mode

See note 4 in Section 4.3.3.6 Pulse Width Modulation Mode

55/131

ST7275-2

16-BIT TIMER (Cont’d)

4.3.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to becopied to theOCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

56/131

ST7275-2

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

57/131

ST7275-2

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Read Only

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

7

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

0

ICF1 OCF1 TOF ICF2 OCF2

0

7

0

MSB

LSB

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

7

0

MSB

LSB

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

Read/Write

Reset Value: 1000 0000 (80h)

1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Note: Reading or writing the ACLR register does

not clear TOF.

7

0

MSB

LSB

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read/Write

Reset Value: 0000 0000 (00h)

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

MSB

LSB

Bit 2-0 = Reserved, forced by hardware to 0.

58/131

ST7275-2

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to SR register does not clear the TOF bit in SR

register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the countervalue. A write to this register resets the

counter. An access to this register after accessing

the SR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

59/131

ST7275-2

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

CR2

OC1E

ICIE

OC2E

OCIE

OCF1

OPM

TOIE

TOF

PWM

FOLV2

ICF2

CC1

FOLV1

OCF2

CC0

OLVL2

0

IEDG2

IEDG1

0

EXEDG

OLVL1

0

CR1

SR

ICF1

MSB

IC1HR

IC1LR

OC1HR

OC1LR

CHR

LSB

CLR

ACHR

ACLR

IC2HR

IC2LR

OC2HR

OC2LR

60/131

ST7275-2

4.4 SYNC PROCESSOR (SYNC)

4.4.1 Introduction

– Generate free-running frequencies

– Generate a video blanking signal

The Sync processor handles all the management

tasks of the video synchronization signals, and is

used with the timer and software to provide infor-

mation and status on the video standard and tim-

ings. This block supports multiple video standards

such as: Separate Sync, Composite Sync and (via

an external extractor) Sync on Green. The internal

clock in the Sync processor is 4 MHz.

– Generate a clamping signal or a Moire signal

■ Analyzer Mode

– Measure the number of scan lines per frame to

simplify OSD vertical centering

– Detect HSYNCI reaching too high a frequency

– Detect pre/post equalization pulses

4.4.2 Main Features

■ Input Processing

– Measure the low level of HSYNCO or HFBACK

– Presence of incoming signals (edge detection)

– Read the HSYNCI / VSYNCI input signal levels

– Measure the signal periods

■ Corrector Mode

– Inhibit Pre/Post equalization pulses

– Program VSYNCO pulse width extension

– Extend VSYNCO pulse widths during:

– Detect the sync polarities

– Detect the composite sync and extract VSYNCO

post-equalization pulse detection only

pre and post-equalization pulse detection

■ Output Processing

Note: Some external pins are not available on all

devices. Refer to the device pinout description.

– Control the sync output polarities

Figure 36. Sync Processor Block Diagram

ICAP1 TIMER

Polarity

V Sync O

Polarity

HVGEN

0

Latch

Pulse Detect

Detector

1

SYNOP

VSYNCI1

VSYNCI2

VSYNCI

V Sync

Correction

VSYNCO

1

LCV1

Vsync*

1

0

BLKEN

Capture

Register

Control

Logic

VFBACK

LD

HVSEL

Blanking

Generator

BLANKOUT

LCV1

0

FBSEL

V

S

Y

N

C

O

Up / Down

EN

VSYNC Generator

40 - 200 Hz

Typical Pulse Width

20 - 256 µs

Sync

&

Edge

Detect

8-Bit Counter

CLK

0

HFBACK

Sync Generator

Sync Analyzer

Sync Corrector

Hardware Block

1

f_INT

Latch

00

Latch

1F

match

HSYNC Generator

15 -200 kHz

Duty cycle range

3 - 40 %

LCV0

FBSEL

match

(Positive polarity)

Prescaler

ICAP2 TIMER

H-Inhibit

Latch

Pulse Detect

HVSEL

1

PSCD

ON/OFF

HSYNCI1

HSYNCI2

CSYNCI

0

SYNOP

HSYNCI / CSYNCI

HSYNCO

H Sync O

Polarity

0

1

SCI0

1

Back Porch

Clamp

Generator

Latch

Clamp

Polarity

H Sync O

Correction

Pulse Detect

0

HVGEN

CLPINV

Other

HFBACK

00

CLAMPOUT

CLMPEN

BP1, BP0

VR02071C

VFBACK

Pull-Up Resistor (if existing)

61/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.3 Input Signals

4.4.5 Output Signals

The Sync Processor has the following inputs (TTL

level with pull-up):

The Sync Processor has the following outputs:

HSYNCO Horizontal Sync Output

Enable: SYNOP bit in ENR register

– VSYNCI1 Vertical Sync input1

– HSYNCI1 Horizontal Sync input1 or Composite

sync

Programmable polarity:

HS0/HS1 bits in MCR register

– VSYNCI2 Vertical Sync input2

In case of composite sync signal, the signal can be

blanked by software during the vertical period

(HINH bit in ENR register).

– HSYNCI2 Horizontal Sync input2 or Composite

sync

Note: The above input pairs can be used for

DSUB or BNC connectors. To select these inputs

use the HVSEL bit in the POLR register.

In case of separate sync, no blanking is

generated.

– CSYNCI Sync on Green (external extractor)

VSYNCO Vertical Sync Output

Note: If the CSYNCI pin is needed for another I/O

function, the composite sync signal can be con-

nected to HSYNCI using the SCI0 bit in the MCR

register.

Enable: SYNOP bit in ENR register

Programmable polarity:

VOP bit in the MCR register

In case of composite sync the delay of the

extracted Vsync signal is:

– HFBACK Horizontal Flyback input

– VFBACK Vertical Flyback input

minimum: 500ns + HSYNCO pulse width

maximum: 8750ns (max. threshold in ex-

traction mode)

4.4.4 Input Signal Waveforms

– Theinput signals must contain only synchroniza-

tion pulses. In case of serration pulses on CSYN-

CI/HSYNCI, the pulse width should be less than

8µs.

– The VSYNCI signal is internally connected to

Timer Input Capture 1 (ICAP1).

– The HSYNCI or CSYNCI signal, prescaled by

256, is internally connected to Timer Input Cap-

ture 2 (ICAP2).

– Typical timing range: See Figure 37 and 38

– If the timer clock is 2 MHz (external oscillator fre-

quency 24 MHz):

PV accuracy = +/- 1 Timer clock (500ns)

PH*256 accuracy = +/- 1 Timer clock (500ns)

(PV= Vertical pulse, PH = Horizontal pulse)

62/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

Figure 37. Typical Horizontal Sync Input Timing

or:

5µs < Typical Hor. Total time < 66.66µs

(200kHz)

(15kHz)

Maximum Sync. pulse width: 7µs

Note: Minimum HPeriod: 500ns + S/W interrupt servicing time

VR01961

(1 Timer Clock)

Figure 38. Vertical Sync Input Timing

or:

5ms < Typical Ver. Total time < 25ms

(200Hz)

(40Hz)

Typical Sync. pulse width: 0.0384ms - 0.600ms

Note: Minimum VPeriod: 500ns + S/W interrupt servicing time

VR01961A

(1 Timer Clock)

63/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

ClampOut and Moire Signal

Clamp Output signal

Moire Signal

The Moire output signal is available (instead of the

clamping signal) to reduce the screen Moire effect

and improve color transitions.

The clamping pulse generator can control the

pulse width and polarity signal and can be config-

ured as pseudo-front porch or back porch.

The CLAMPOUT pin is alternatively used to output

a Moire signal.

To use the ClampOut signal:

The output signal toggles at each HFBACK rising

edge. After each VFBACK falling edge, the value

of the Moire output is the opposite of the previous

one, independent of the number of HFBACK puls-

es during the VFBACK low level.

– Select the Clamping Pulse width:

BP0/BP1 bits in MCR register

– Program the Clamp polarity:

CLPINV bit in POLR register

– Select the ClampOut signal as back-porch (after

falling edge of HSYNCO) or pseudo-front porch

(after the rising edge of HSYNCO):

To use the Moire signal:

HS0/HS1 bits in MCR register.

– Select the Moire signal:

Reset the BP0/BP1 bits in MCR register

– Enable the CLAMPOUT signal:

CLMPEN bit in ENR register

– Enable the output signal:

CLMPEN bit in ENR register

Figure 39. Clamping Pulse (CLAMPOUT) Delay

HSYNCO

Maximum delay:

(Fixed delay of 10 to 30ns) + (f /2) = approx. 110ns.

OSC

-

CLAMPOUT

Programmable clamping width: 0, 167ns, 333ns, 666ns

Figure 40. Moire Output (instead of Clamping Output)

VFBACK

HFBACK

Moire

64/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.5.1 Blanking output signal

Note: HFBACK, VFBACK, VSYNCO signals must

have positive polarity.

The Video Blanking function uses VSYNCO,

HFBACK, VFBACK as input signals and

BLANKOUT output as Video Blanking Output.

This output pin is a 5V open-drain output and can

be AND-wired with any external video blanking

signal.

To use the video blanking signal:

– Program the polarity:

BLKINV bit in POLR register

– Enable the BLANKOUT output:

BLKEN bit in ENR register

Figure 41. Video Blanking Stage Simplified Schematic

To Edge detector (LATR)

HFBACK

To Edge detector (LATR)

BLANKOUT

BLKINV

VFBACK

VSYNCO

R

S

BLKEN

65/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6 Input Processing

4.4.6.2 Measuring Sync Period

4.4.6.1 Detecting Signal Presence

To measure the sync period, the Sync processor

block uses the Timer Input Capture interrupts:

The Sync Processor provides two ways of check-

ing input signal presence, by directly polling the

LATR Latch Register or using the Timer interrupts.

– ICAP1 connected to VSYNCI signal

– ICAP2 connected to HSYNCI/CSYNCI signal

with a 256 prescaler

Polling check

Use the Latch Register (LATR), to detect the pres-

ence of HSYNCI, VSYNCI, CSYNCI, HFBACK

and VFBACK signals. These latched bits are set

when the falling edge of the corresponding signal

is detected. They are cleared by software.

Calculating the difference between two subse-

quent Input Captures (16-bit value) gives the peri-

od for 256xPH (horizontal period) and PV (vertical

period).

The period accuracy is one timer clock (500ns at 2

MHz), so that the tolerance is 500ns for PH and

256 * PH (PH accuracy =1.95ns).

Interrupts check

Due to the fact that VSYNCI is connected to Timer

Input Capture 1 and HSYNCI or CSYNCI is con-

nected to Timer Input Capture 2, the Timer inter-

rupts can be used to detect the presence of input

signals. Refer to the 16-bit Timer chapter for the

description of the Timer registers.

Notes:

1) In case of composite sync, the HSYNCI period

measurement can be synchronized on the

VSYNCI pulseby setting and resetting the pres-

caler PSCD bit in the CCR register (for this

function, the ICAP2 detection must be selected

as falling edge).

To use the interrupt method:

– Select Input Capture1 edge detection:

IEDG1 bit in the Timer CR1 register

– Select Input Capture 2 edge detection (must be

falling edge):

This avoids errors in the period measurement

due to the Vsync pulse.

IEDG2 bit = 0 in the Timer CR2 register

2) The Timer Interrupt request should be masked

during a write access to any of the Sync proces-

sor control registers.

– Enable Timer Input Capture interrupts:

ICIE bit in the Timer CR1 register.

– Select the Hsync and Vsync input signals:

HVSEL bit in the POLR register

Important Note:

– Enable the prescaler for HSYNCI or CSYNCI

signal:

Since the recognition of the video mode relies

on the accuracy of the measurements, it is high-

ly recommended to implement a counter-style

algorithm which performs several consecutive

measurements before switching between

modes.

PSCD bit in the CCR register.

– Select the normal mode:

LCV1/LCV0 bits in the CCR register.

Perform any of the following:

The purpose of this algorithm is to filter out any

glitches occurring on the video signals.

– Check for VSYNCI presence by monitoring inter-

rupt requests from Timer ICAP1. When VSYNCI

is detected then either detect the VSYNCI polar-

ity or check for HSYNCI presence.

– Checkfor HSYNCI presence by monitoring inter-

rupt requests from Timer ICAP2. On detecting

HSYNCI, either detect its polarity or check if the-

composite sync on HSYNCI pin is detected or

check for CSYNCI presence.

– Checkfor CSYNCI presence by monitoring inter-

rupt requests from Timer ICAP2.

66/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6.3 Detecting Signal Polarity

4.4.6.4 Extracting VSYNCO from CSYNCI

The Sync Processor provides two ways for check-

ing input signal polarity by polling the latches or

using the 5-bit up/down counter.

In case of composite sync, the Vertical sync output

signal is extracted with the 5-bit up/down counter.

Initially, the width of an Horizontal Sync compo-

nent pulse is automatically determined by hard-

ware which defines a threshold for the 5-bit coun-

ter with a possible user-defined tolerance.

Polling check

– HSYNCI polarity detection:

UPLAT/DWNLAT bits in LATR register

The circuit then monitors for any incoming period

greater than this previously captured value. This is

then processed as the VSYNCO signal.

These bits are directly connected to the 5-bit

Up/Down counter.

UPLAT=1/ DOWNLAT=0 HSYNCI polarity<0

UPLAT=0/ DOWNLAT=1 HSYNCI polarity>0

To use the Vsync extractor, the following steps are

necessary:

– Detection of a composite sync signal:

– VSYNCI Polarity Detection

When the UPLAT and DOWNLAT bits in LATR

register are set, a composite sync signal or a

HSYNCI polarity change is detected.

If these bits are stable during two subsequent

ICAP2 interrupt, the composite sync signal is

stable.

– VPOL bit (VSYNCO polarity) in POLR and

– VOP bit (VSYNCO polarity control) in MCR

The delay between VSYNCI polarity changes

and the VPOL bit typically toggles within 4

msecs. The polarity detector includes an inte-

grator to filter possible incoming VSYNCI

glitches.

– Defining a threshold:

Select the normal mode (LCV1/LCV0=0 in the

CCR register).

Initialize the counter capture CV4-CV0 to 0.

5-bit Up/Down Counter Check

for HSYNCI Polarity

This method involves the internal 5-bit up/down

counter.

The counter value (CV4-CV0 bits) is updated with

the 5-bit counter value at every detected edge on

the signal monitored.

It is incremented when the signal is high, other-

wise it is decremented.

This automatically measures the HSYNCI pulse

width. It defines a threshold in the CV4-CV0 bits

used by the 5-bit up/down counter.

It also allows to check the HSYNCI polarity (re-

fer to the “5-bit Up/Down Counter Check” para-

graph.

If a user-defined tolerance is to be added, then

an updated value should be written in the CCR

register (CV4-CV0 bits).

In a composite sync signal, Hsync and Vsync

always have the same polarity.

– Start the detection phase:

Initialize the 5-bit counter: write ’00000’ in the

CCR register (CV4-CV0 bits).

– Starting the VSYNCO hardware extraction

mode:

Select normal mode on falling edge:

LCV1/LCV0 = 0 in the CCR register.

According to the Composite sync polarity, se-

lect the extraction mode (LCV1/LCV0 in CCR

register) and rewrite the counter if necessary.

– Software checks the counter value (CV4-CV0)

after an interrupt (with the signal internally con-

nected or ICAP2) or by polling (timeout 150µs).

Negative polarity: minimum threshold (00h)

Positive polarity: maximum threshold (1Fh)

Positive polarity: The counter value < 1Fh.

Negative polarity: The counter value =1Fh on

the falling edge.

Note:

In case of a composite incoming signal, the soft-

ware just has to check that the VSYNCO period

and polarity are stable.

The extracted VSYNCO signal always has nega-

tive polarity.

67/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6.5 Example of VSYNCO extraction for a

negative composite sync with serration pulses

When the vertical period is finished, the counter

starts counting up and when the maximum is

reached, VSYNCO is negated. The extracted sig-

nal may be validated by software since it is input to

Timer ICAP1.

Refer to Figure 42.

In extraction mode, the 5-bit comparator checks

the counter value with respect to the threshold.

Serration pulses during vertical blanking can be fil-

tered if the serration pulse widths are less than

8µs.

When the incoming signal is high, the counter is in-

creased, otherwise it is decreased.

When the counter reaches the threshold on its way

down, VSYNCO is asserted. During the vertical

blanking, the counter value is decreased down to a

programmable minimum, i.e. it does not under-

flow.

In the same way, positive composite sync signals

can be used by properly selecting the edge sensi-

tivity in HSYNCI width measurement mode (LCV0

bit).

Figure 42. VSYNCO Extraction from a Composite Signal (negative polarity)

Serration pulses

Composite signal

Input

Max Pulse width: 8µs

1F-Threshold

Counter value:

1F=Max

8µs

Threshold

0=Min

VSYNCO

generated

VSYNCO Pulse

Max Delay: 8µs

or threshold

HSYNCO

VR01990

Figure 43. Obtaining the 11-bit Vertical Period (V11BITS)

7

0

CFGR

VGENR

Q’2 Q’1 Q’0

Example:

VGENR=CCh, CFGR = 3h

V11bits=663h

10

0

V11BITS

68/131

ST7275-2

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.7 Output Processing

– Configure the following bits:

SYNOP = 0

HVGEN = 1

HACQ = 0

4.4.7.1 Generating Free-Running Frequencies

The free-running frequencies function is used to:

VACQ = 0

– Drive the monitor when no or bad sync signals

are received.

Horizontal Period

– Stabilize the OSD screen when the monitor is

unlocked.

PH = Horizontal period = ((HGENR+1)/4) µs

Pulse width: 2 µs => HGENR min=8

Polarity: Positive

– Perform fast alignment for maintenance purpos-

es.

HGENR range: [8..255]

Note: When free-running mode is active, the ana-

lyzer and corrector modes must be disabled.

Vertical Period

– VCORDIS = 1, VEXT = 0 in CFGR and POLR

registers for vertical output measurement

PV = Vertical period = (PH * V11bits) µs

V11bits is a concatenation of VGENR and the Q’2

Q’1 Q’0 bits of the CFGR register.

Refer to Figure 43.

– 2FHINH = 0 in CFGR register for horizontal

low level measurment

– VACQ, HACQ = 0, in CFGR register for ana-

lyzer mode

Pulse width: 4 * PH => min value= 8µs

Polarity: Positive

The Sync processor can generate any of the fol-

lowing output sync signals HSYNCO, VSYNCO,

CLAMPOUT, BLANKOUT.

VGENR/CFGR range: [5..7FF]

To select the generation mode:

– Programthe horizontal period using the HGENR

register.

– Program the vertical period using the VGENR (8

bits) and CFGR (3 bits) registers (2047 scan

lines per frame). Refer to Figure 43.

Table 18. Typical values for generated HSYNC signals

HGENR (hex value)

H Period

5 µs

HFREQ

200 kHz

125 kHz

62.5 kHz

31.25 kHz

15.6 kHz

Pulse Width

2 µs

Duty Cycle

40%

13

1F

3F

7F

FF

8 µs

2 µs

25%

16 µs

32 µs

64 µs

2 µs

12.5%

6.2%

2 µs

3.1%

Table 19. Typical values for generated VSYNC signals

HGENR

V11bits

H Period

H Freq

V Period

V Freq

Pulse width

(hex value)

7FF (2047)

400 (1024)

7FF (2047)

400 (1024)

7FF (2047)

400 (1024)

7FF (2047)

400 (1024)

13

1F

3F

7F

5 µs

200 kHz

125 kHz

62.5 kHz

31.25 kHz

10.2 ms

5.1 ms

97.7 Hz

195 Hz

61 Hz

20 µs

32 µs

64 µs

128 µs

8 µs

16.3 ms

8.2 ms

8 µs

122 Hz

30.6 Hz

60.9 Hz

15 Hz

16 µs

32 µs

32.6 ms

16.4 ms

65.5 ms

32.8 ms

30 Hz

69/131


型号：	ST72752J6B1
厂家：	ETC
描述：	Microcontroller 微控制器\n 微控制器
文件：	总69页 (文件大小：381K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST72752J6B1 [ETC]

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