STC62WV1024STCG55 [ETC]
VERY LOW POWER VOLTAGE CMOS SRAM; 功耗非常低电压CMOS SRAM
| 型号： | STC62WV1024STCG55 |
| 厂家： | 
ETC |
| 描述： | VERY LOW POWER VOLTAGE CMOS SRAM |
| 文件： | 总10页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
STC
STC62WV1024
• Easy expansion with CE2, CE1, and OE options
FEATURES
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 17mA (@55ns) operating current
I- grade : 18mA (@55ns) operating current
C-grade : 14mA (@70ns) operating current
I- grade : 15mA (@70ns) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 46mA (55ns) operating current
I- grade : 47mA (55ns) operating current
C-grade : 38mA (70ns) operating current
I- grade : 39mA (70ns) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
DESCRIPTION
The STC62WV1024 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
-55
-70
55ns
70ns
The STC62WV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The STC62WV1024 is available in DICE form , JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4
mm STSOP and 8mmx20mm TSOP.
• Automatic power down when chip is deselected
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
55ns : 3.0~5.5V
70ns : 2.7~5.5V
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Operating
STANDBY
(ICCSB1, Max)
PKG TYPE
(ICC, Max)
Vcc=3V
Vcc=5V
Vcc=5.0V Vcc=3.0V
70ns
70ns
STC62WV1024SC
STC62WV1024TC
STC62WV1024STC
STC62WV1024PC
STC62WV1024JC
STC62WV1024DC
STC62WV1024SI
STC62WV1024TI
STC62WV1024STI
STC62WV1024PI
STC62WV1024JI
STC62WV1024DI
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
+0 O C to +70 O
C
C
2.4V ~ 5.5V
2.4V ~ 5.5V
55/70
55/70
38mA
39mA
8.0uA
20uA
1.3uA
2.5uA
14mA
DICE
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
-40 O C to +85 O
15mA
DICE
BLOCK DIAGRAM
PIN CONFIGURATIONS
NC
A16
A14
A12
A7
1
VCC
32
2
A15
CE2
WE
A13
A8
31
A6
A7
A12
A14
A16
A15
A13
A8
3
30
4
29
Address
5
28
27
Memory Array
20
1024
Row
Decoder
A6
6
Input
A5
7
A9
62WV1024SC 26
1024 x 1024
A4
8
62WV1024SI
62WV1024PC
62WV1024PI
62WV1024JC
62WV1024JI
A11
OE
25
24
23
22
21
20
19
18
17
Buffer
A3
9
A2
A9
A11
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A1
A0
1024
DQ0
DQ1
DQ2
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
1
2
3
4
5
6
7
8
A11
A9
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
8
Data
Output
Buffer
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
128
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
Column Decoder
14
62WV1024TC
62WV1024TC
62WV1024TI
62WV1024STI
CE2
CE1
WE
9
Control
Address Input Buffer
10
11
12
13
14
15
16
OE
Vdd
Gnd
A5 A4 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
STC International Limited. reserves the right to modify document contents without notice.
Revision 2.1
Jan. 2004
STC62WV1024
1
STC62WV1024
STC
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
CE1
H
CE2
X
OE
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
(Power Down)
ICCSB, ICCSB1
X
X
L
X
Output Disabled
Read
H
L
H
H
L
High Z
ICC
ICC
ICC
OUT
H
L
H
D
IN
Write
L
L
H
X
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70O
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
RANGE
Vcc
V
TERM
V
Commercial
Industrial
C
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
O C
W
BIAS
T
-40 O C to +85O
C
STG
T
T
P
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
IN
PARAMETER
CONDITIONS
IN
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
C
V
=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 2.1
Jan. 2004
STC62WV1024
2
STC
STC62WV1024
DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
UNITS
NAME
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Guaranteed Input Low
Voltage(2)
VIL
-0.5
--
0.8
V
2.0
2.2
Guaranteed Input High
VIH
IIL
--
--
--
Vcc+0.3
V
Voltage(2)
IN
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
--
1
1
uA
uA
IH
IL,
Vcc = Max, CE1= V , CE2= V or
OE = V , V = 0V to Vcc
LO
I
--
IH
I/O
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 2.0mA
--
--
--
0.4
--
V
V
Vcc = Min, IOH = -1.0mA
2.4
--
--
--
--
--
--
--
--
15
39
IL
IH
Operating Power Supply CE1 = V , or CE2 = V ,
Current
(5)
70ns
ICC
mA
mA
uA
DQ
I
= 0mA, F = Fmax(3)
--
0.5
1.0
2.5
20
CE1 = VIH, or CE2 = VIL
DQ = 0mA
,
ICCSB
Standby Current-TTL
I
--
CE1≧Vcc-0.2V or CE2≦0.2V,
IN≧Vcc-0.2V or VIN≦0.2V
0.1
0.6
(4)
ICCSB1
Standby Current-CMOS
V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
4. IccSB1_Max. is 1.3uA/8.0uA at Vcc=3.0V/5.0V and TA=70oC.
5. Icc_Max. is 18mA(@3V)/ 47mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(3)
ICCDR
Data Retention Current
--
0
0.05
0.3
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.2uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE1
t
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
CE2
Revision 2.1
Jan. 2004
STC62WV1024
3
STC
STC62WV1024
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
READ CYCLE
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
UNIT
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVQV
tE1LQV
tE2HOV
tGLQV
tE1LQX
tE2HOX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
Read Cycle Time
tRC
tAA
55
--
--
--
--
--
--
--
--
--
--
--
--
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
55
55
55
30
--
70
70
70
40
--
tACS1
tACS2
tOE
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
Chip Select Access Time
(CE1)
(CE2)
--
--
Chip Select Access Time
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
(CE1)
(CE2)
10
10
10
--
10
10
10
--
--
--
--
--
(CE1)
(CE2)
35
35
30
40
40
35
--
--
--
--
tAXOX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
Revision 2.1
Jan. 2004
STC62WV1024
4
STC
STC62WV1024
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
ACS2
CE2
(5)
CHZ2
t
CHZ1,
t
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
t
ACS1
t
t
OHZ
(1,5)
(5)
t
t
CLZ1
CHZ1
CE2
t
ACS2
(2,5)
CHZ2
t
(5)
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
Revision 2.1
Jan. 2004
STC62WV1024
5
STC
STC62WV1024
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Write Cycle Time
UNIT
MIN. TYP. MAX.
tWC
tCW
tAS
tAVAX
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tE1LWH
Chip Select to End of Write
Address Set up Time
tAVWL
tAVWH
tWLWH
tWHAX
--
--
tAW
tWP
tWR1
tWR2
Address Valid to End of Write
Write Pulse Width
55
35
0
--
70
50
0
--
--
--
Write Recovery Time
(CE1 , WE)
(CE2)
--
--
tE2LAX
tWLOZ
tDVWH
tWHDX
tGHOZ
Write Recovery Time
0
--
0
--
t WHZ
t DW
t DH
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
--
25
--
--
30
--
25
0
30
0
--
--
t OHZ
t OW
--
25
--
--
30
--
tWHQX
5
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR1
t
(11)
t
CW
(5)
CE1
(5)
(11)
CE2
t
t
CW
WP
t
WR2
t
AW
(3)
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.1
Jan. 2004
STC62WV1024
6
STC
STC62WV1024
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CW
CE2
t
t
WR2
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
t
t
OW
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.1
STC62WV1024
7
Jan.
2004
STC
STC62WV1024
ORDERING INFORMATION
62WV1024 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
Note:
STC (STC International Limited.) assumes no responsibility for the application or use of any product or circuit described herein. STC does not authorize its products
for use as critical components in any application in which the failure of the STC product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 2.1
Jan. 2004
STC62WV1024
8
STC
STC62WV1024
PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision 2.1
STC62WV1024
9
Jan.
2004
STC
STC62WV1024
PACKAGE DIMENSIONS (continued)
PDIP - 32
SOJ - 32
Revision 2.1
STC62WV1024
10
Jan.
2004
相关型号：
©2020 ICPDF网 联系我们和版权申明