STEL-1177/CM_技术文档

STEL-1177

Data Sheet

STEL-1177

32-Bit Resolution

CMOS Phase and

Frequency Modulated

Numerically

Controlled Oscillator

R

F E A T U R E S

■ HIGH CLOCK FREQUENCY

■ HIGH SPECTRAL PURITY

- 60 MHz MAXIMUM OVER COMMERCIAL

- ALL SPURS < –75 dBc

TEMPERATURE

40 MHz MAXIMUM OVER FULL MILITARY

TEMPERATURE RANGE

■ HIGH FREQUENCY RESOLUTION

RANGE

■ MICROPROCESSOR

COMPATIBLE

-

I N P U T S

■ LOW POWER DISSIPATION

- COSINE CHANNEL CAN BE DISABLED

TO REDUCE POWER

- 32-BITS, 14 milli-Hz @ 60 MHz

■ WIDE OUTPUT BANDWIDTH

■ 84 PIN PLCC OR CLDCC PACKAGES

AND 84 PIN CERAMIC PGA PACKAGE

A V A I L A B L E

- 0 TO 25 MHz @ 60 MHz CLOCK

■ PRECISION

PHASE

MODULATION

- 12-BITS, 0.09° RESOLUTION, CAN BE

USED FOR LINEAR PM OR PULSE-

SHAPED PSK

TYPICAL

APPLICATIONS

■ PRECISION

FREQUENCY

MODULATION

■ FREQUENCY

SYNTHESIZERS

- 16 BITS RESOLUTION, CAN BE USED

FOR LINEAR FM OR PULSE-SHAPED FSK

■ FSK AND PSK MODULATORS

■ DIGITAL SIGNAL PROCESSORS

■ QUADRATURE

SIGNAL

GENERATION

- 12-BIT OUTPUTS WITH INDEPENDENT

PHASE MODULATION PER CHANNEL

■ HIGH SPEED HOPPED FREQUENCY

SOURCES

BLOCK

DIAGRAM

PHLD

ROUND

CLOCK

CIN

4

ADDR

CSEL

SYNC

FMSYNC

ADDRESS

SELECT

LOGIC

WRSTB

SINE

PHASE

MOD

PHSEL

DATA

8

12

CONTROL

COSINE

PHASE

MOD

32

13

SINE

PHASE

ALU

13

12

SINE

LUT

SINE

12

32

CONTROL

-PHASE

BUFFER

REGISTER

A

-PHASE

ALU

BUFFER

REGISTER

PHASE

ACCUM-

ULATOR

MUX

-PHASE

BUFFER

REGISTER

B

32

RESET

FRSEL

(TO ALL REGISTERS)

FRE-

QUENCY

MOD

COSINE

LUT

COSINE

PHASE

ALU

12

13

FMSUB

FMLD

COSINE

CONTROL

SIMLD

FMOD

16

2

RATE

2

FMADDR

FRLD

COSEN

STEL-1177

2

CONFIGURATION

1. Plastic (PLCC) (/CM) or Ceramic (CLDCC) (/CC and /MC) Leaded Chip Carrier

Package:

84 pin CLDCC

84 pin PLCC

Thermal coefficient, qja = 34°/W

Thermal coefficient, qja = 30°/W

0.145"

max.

1

8

8 8 8 8 7 7 7 7

7

5

1

0

8

4

8

3

8

2

8

1

8

0

7

9

7

8

7

6

7

5

1 0 9 8 7 6 5 4 3 2 1 4 3 2 1 0 9 8 7 6

9

8

7

6

5

4

3 2 1

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

0.017"

± 0.004" (2)

0.018"

± 0.004" (2)

1.190"

± 0.005"

Top View

0.05"

nominal (1)

0.05"

± 0.005" (1)

3

4

3

5

3

6

3

7

3

8

3

9

4

0

4

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

5

0

5

1

5

2

5

3

3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5

3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3

0.035"

nominal

0.200"

max.

1.154"

± 0.004"

1.150"

± 0.012"

Notes:

1. Dimensions shown are for plastic package.

Dimensions for ceramic package are similar.

2. Tolerances on pin spacing are not cumulative.

2. Ceramic Pin Grid Array (CPGA) (/CF and /MF)

1 2 3 4 5 6 7 8 9 1011

L

K

J

H

G

F

0.1"

± .005"

0.117"

max.

0.18"

± .005"

E

D

C

B

A

0.018"

± .001" dia.

1.10" ± .02 "sq..

Notes: 1. Tolerances on pin spacings are not

cumulative.

2. Corner pins have integral standoffs

which raise the package 0.07" (nominal)

above the mounting surface.

3. Orientation determined by extra pin at

location C3.

4. Thermal coefficient, θ_ja= 28°C/watt

3

STEL-1177

CONNECTIONS

1

2

3

4

5

6

7

8

9

(C6) V_SS

22 (F3) V_SS

43 (J6)

44 (J7)

V_SS

COS₄

64 (F9) V_SS

(A6) FMOD₇

(A5) FMOD₈

(B5) FMOD₉

(C5) FMOD₁₀

(A4) FMOD₁₁

(B4) FMOD₁₂

(A3) FMOD₁₃

(A2) FMOD₁₄

23 (G3) CLOCK

24 (G1) SIMLD

25 (G2) ADDR₃

26 (F1) ADDR₂

27 (H1) ADDR₁

28 (H2) ADDR₀

65 (F11) SINE₁₀

66 (E11) SINE₁₁

67 (E10) RATE₀

68 (E9) RATE₁

69 (D11) ROUND

70 (D10) COSEN

71 (C11) V_SS

72 (B11) FMLD

73 (C10) FMSYNC

74 (A11) V_DD

75 (B10) FMSUB

76 (B9) FMADDR₀

77 (A10) FMADDR₁

78 (A9) FMOD₀

79 (B8) FMOD₁

80 (A8) FMOD₂

81 (B6) FMOD₃

82 (B7) FMOD₄

83 (A7) FMOD₅

45 (L7) COS₅

46 (K7) COS₆

47 (L6) COS₇

48 (L8) COS₈

49 (K8) COS₉

50 (L9) COS₁₀

51 (L10) COS₁₁

52 (K9) V_SS

29 (J1)

30 (K1) FRSEL

31 (J2) V_SS

CSEL

10 (B3) FMOD₁₅

11 (A1) V_DD

32 (L1) V_DD

33 (K2) PHLD

34 (K3) PHSEL

35 (L2) CIN

36 (L3) FRLD

37 (K4) SYNC

38 (L4) I.C.

53 (L11) V_DD

12 (B2) DATA₇

13 (C2) DATA₆

14 (B1) DATA₅

15 (C1) DATA₄

16 (D2) DATA₃

17 (D1) DATA₂

18 (E3) DATA₁

19 (E2) DATA₀

20 (E1) WRSTB

21 (F2) RESET

54 (K10) SINE_0(LSB)

55 (J10) SINE₁

56 (K11) SINE₂

57 (J11) SINE₃

58 (H10) SINE₄

59 (H11) SINE₅

60 (F10) SINE₆

61 (G10) SINE₇

62 (G11) SINE₈

63 (G9) SINE₉

39 (J5)

COS_0(LSB)

40 (K5) COS₁

41 (L5) COS₂

42 (K6) COS₃

84 (C7

FMOD₆

Numeric pin connections are for PLCC and CLDCC packages, alphanumeric connections in parentheses are for

PGA package. Note: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias.

FUNCTIONAL

DESCRIPTION

number in the ∆-Phase register represents the phase

change for each cycle of the clock. This number is

directly related to the output frequency by the

following:

The STEL-1177 Modulated Numerically Controlled

Oscillator (MNCO) uses digital techniques to provide

a cost-effective solution for low noise signal sources.

The NCO features high frequency resolution with

exceptional spectral purity of outputs up to 25 MHz.

The STEL-1177 also features both phase and frequency

modulation at rates up to 25% of the clock frequency.

Separate 12-bit sine and cosine outputs are provided

which can be phase modulated independently. The

cosine channel can be disabled when not in use,

reducing the power consumption by approximately

30%. The device combines low power 1.5µ CMOS

technology with a unique architectural design

resulting in a power efficient, high-speed sinusoidal

waveform generator able to achieve fine tuning

resolution and exceptional spectral purity at clock

frequencies up to 60 MHz. The NCO is designed to

provide a simple interface to an 8-bit microprocessor

bus.

f_cx ∆-Phase

f_o=

2³²

where: f_ois the frequency of the output signal

and: f_cis the clock frequency.

The sine and cosine functions are generated from the

13 most significant bits of the phase accumulator. The

frequency of the NCO is determined by the number

stored in the ∆-Phase Register, which may be

programmed by an 8-bit microprocessor, and the

frequency modulation value loaded on the FMOD

bus. The carrier frequency and the frequency

modulation can be updated independently or

simultaneously, using an internal synchronization

circuit which ensures glitch-free updates.

The NCO maintains a record of phase which is

accurate to 32 bits. At each clock cycle, the number

stored in the 32-bit ∆-Phase register is added to the

previous value of the phase accumulator. The number

in the phase accumulator represents the current phase

of the synthesized sine and cosine functions. The

The NCO generates a sampled sine wave where the

sampling function is the clock. The practical upper

limit of the NCO output frequency is about 40% of the

clock frequency due to spurious components that are

created by sampling. Those components are at

STEL-1177

4

frequencies greater than half the clock frequency, and

become more difficult to remove by filtering as the

output frequency approaches half the clock frequency.

different phase modulation can be applied to the sine

and cosine channels.

∆-PHASE BUFFER REGISTERS A & B BLOCK

The two ∆-Phase Buffer Registers are used to

The phase noise of the NCO output signal may be

determined from the phase noise of the clock signal

input and the ratio of the output frequency to the clock

frequency. This ratio squared times the phase noise

power of the clock specified in a given bandwidth is

the phase noise power that may be expected in that

same bandwidth relative to the output frequency.

temporarily store the ∆-Phase data written into the

device. This allows the data to be written

asynchronously as four bytes per 32-bit ∆-Phase word.

The data is transferred from these registers into the ∆-

Phase ALU after a falling edge on the FRLD input.

MUX BLOCK

The NCO achieves its high operating frequency by

making extensive use of pipelining in its architecture.

The pipeline delays within the NCO represent 19 clock

cycles. The dual ∆-Phase registers used in the STEL-

1177 allow the frequency and frequency modulation to

be updated as rapidly as every fourth clock cycle, i.e. at

25% of the clock frequency. The pipeline delay

associated with the phase modulator is only 12 clock

cycles, since the phase modulating function is at the

output of the accumulator. The phase modulation may

also be changed as rapidly as every fourth clock cycle,

at 25% of the clock frequency, resulting in a maximum

modulation rate of 15 MHz with a clock frequency of

60 MHz. Note that when a phase or frequency change

occurs at the output the change is instantaneous, i.e., it

occurs in one clock cycle, with complete phase

coherence.

This block is used to select which ∆-Phase Buffer

Register is used as the source of frequency data for the

∆-Phase ALU, by means of the FRSEL input.

FREQUENCY

B L O C K

MODULATION

CONTROL

This block controls the writing of the frequency

modulation (FM) data on the FMOD_15-0bus into the

FM Buffer Register, and the loading of this data into

the ∆-Phase ALU. This data is multiplied by a factor of

2⁰, 2⁴, 2⁸, or 2¹², according to the state of the

FMADDR_1-0inputs, before being loaded into the ∆-

Phase ALU. This gives a wide range of values for the

maximum deviation and resolution. The writing of the

FM data can be either manual or automatic. It is

controlled by the RATE_1-0inputs, and the FMLD

input or the FMSYNC output, depending on the mode

selected. In addition, this block synchronizes the

simultaneous updating of the carrier frequency data

and FM data when the SIMLD input is high.

FUNCTION

BLOCK

DESCRIPTION

ADDRESS SELECT LOGIC BLOCK

∆-PHASE ALU BLOCK

This block controls the writing of data into the device

This block controls the updating of the ∆-Phase word

via the DATA_7-0inputs. The data is written into the

device on the rising edge of the WRSTB input, and the

register into which the data is written is selected by the

ADDR_3-0inputs. The CSEL input can be used to

selectively enable the writing of data from the bus.

used in the Accumulator. The frequency data from the

Mux Block is loaded into this block after a falling edge

on the FRLD input, and the FM data from the

Frequency Modulation Control block is loaded after a

falling edge on the FMLD input. However, if the

SIMLD input is high, the FMLD input will load both

sets of data simultaneously. The FM data is added to

or subtracted from the carrier frequency data, the

add/subtract operation being selected by the FMSUB

input. This block also generates the SYNC output,

which indicates the instant at which any phase or

frequency change made at the inputs affects the

SINE_11-0and COS_11-0output signals, and also the

FMSYNC output, which controls the loading of the

FM data on the FMOD_15-0bus in the automatic mode.

SIN/COS PHASE MODULATION BLOCK

This block includes the Phase Modulation Buffer

Registers, and controls the source of the phase

modulation (PM) data by means of the PHSEL input.

When this signal is low, data from the DATA_7-0and

ADDR_3-0inputs is written directly into the Phase ALUs

after a falling edge on the PHLD input. The same PM

data will be applied to both the Sine and Cosine Phase

ALUs in this mode. When PHSEL is high, data is

written into the Phase Modulation Buffer Registers

from the DATA_7-0bus on the rising edge of the WRSTB

input. The data will then be transferred into the Sine

and Cosine ALUs after the next falling edge of PHLD.

The sources of the PM data applied to the Sine and

Cosine Phase ALUs will be the independent Sine and

Cosine Phase Buffer Registers in this mode, so that

ALU BUFFER REGISTER BLOCK

This block stores the output from the ∆-Phase ALU for

use in the Phase Accumulator. It also controls the time

alignment of this data whenever it is changed, so that

glitch-free updating of the accumulator pipeline is

achieved.

5

STEL-1177

PHASE ACCUMULATOR BLOCK

This block forms the core of the NCO function. It is a

DATA₇through DATA₀

The 8-bit DATA_7-0bus is used to program the two 32-

high-speed, pipelined, 32-bit parallel accumulator,

generating a new sum in every clock cycle. A carry

input (the CIN input) allows the resolution of the

accumulator to be expanded by means of an auxiliary

NCO or phase accumulator. The overflow signal is

discarded, since the required output is the

modulo(2³²) sum only. This represents the modulo(2π)

phase angle.

bit ∆-Phase Registers and the two 12-bit Phase

Modulation Registers. DATA₀is the least significant

bit of the bus. The data programmed into the ∆-Phase

registers in this way determines the carrier frequency

of the NCO.

ADDR₃through ADDR₀

The four address lines ADDR_3-0control the use of the

DATA_7-0bus for writing frequency data to the ∆-

Phase Buffer Registers, and phase data to the Phase

Buffer Registers, as shown in the table:

PHASE ALU BLOCKS

The two Phase ALUs perform the addition of the sine

and cosine PM data to the Phase Accumulator output

in the sine and cosine channels, respectively. The PM

data words are both 12 bits wide, and these are added

to the 13 most significant bits from the Phase

Accumulator to form the modulated phase used to

address the lookup tables.

ADDR₃ADDR₁ADDR₀Register Field

0

1

0

1

0

1

0

1

0

1

0

1

0

1

∆-Phase Bits 0 (LSB)–7

∆-Phase Bits 8–15

∆-Phase Bits 16–23

∆-Phase Bits 24–31

Sine Bits 0(LSB)–3*

Sine Bits 4-11*

SINE AND COSINE LOOKUP TABLE BLOCKS

These blocks are the sine and cosine memories. The 13

bits from the Phase ALUs are used to address these

memories to generate the 12-bit SINE_11-0and COS_11-0

outputs. The Cosine LUT can be disabled when not in

use, to conserve power, by means of the COSEN

input.

Cosine Bits 0(LSB)–3*

Cosine Bits 4-11*

ADDR₃ADDR₂

Register Selected

INPUT

SIGNALS

0

1

0

1

∆-Phase Buffer Register 'A'

∆-Phase Buffer Register 'B'

Phase Buffer Registers

R E S E T

The RESET input is asynchronous and active low, and

clears all the registers in the device. When RESET goes

low, all registers are cleared within 20 nsecs, and

normal operation will resume after this signal returns

high. The data on the SINE_11-0and COS_11-0buses will

then be invalid for 7 clock cycles, and thereafter will

remain at the value corresponding to zero phase until

new frequency or modulation (either frequency or

phase) data is loaded with the FRLD, FMLD, or

PHLD inputs after the RESET returns high.

X

* Note: The Phase Buffer Registers are 12-bit registers.

When the least significant bytes of these registers are

selected (ADDR_3-0=1XX0), DATA_7-4is written into

Bits 3–0 of the registers. In all cases, it is not necessary

to reload unchanged bytes, and the byte loading

sequence may be random.

W R S T B

The Write Strobe input is used to latch the data on the

C L O C K

DATA_7-0bus into the device. On the rising edge of the

WRSTB input, the information on the 8-bit data bus is

transferred to the buffer register selected by the

ADDR_3-0bus.

All synchronous functions performed within the NCO

are referenced to the rising edge of the CLOCK input.

The CLOCK signal should be nominally a square

wave at a maximum frequency of 60 MHz. A non-

repetitive CLOCK waveform is permissible as long as

the minimum duration positive or negative pulse on

the waveform is always greater than 5 nanoseconds.

F R S E L

The Frequency Register Select line is used to control

the mux which selects the ∆-Phase Buffer Register in

use. When this signal is high ∆-Phase Buffer Register

'A' is selected as the source for the ∆-Phase ALU, and

the frequency corresponding to the data stored in this

register will be generated by the NCO after the next

falling edge on the FRLD input. When this line is low,

∆-Phase Buffer Register 'B' is selected as the source.

C S E L

The Chip Select input is used to control the writing of

data into the chip. It is active low. When this input is

high all data writing via the DATA_7-0bus is inhibited.

STEL-1177

6

F R L D

FMADDR₁through FMADDR₀

The two inputs FMADDR_1-0set the deviation of the

The Frequency Load input is used to control the

transfer of the data from the ∆-Phase Buffer Registers

to the ∆-Phase ALU. The data at the output of the Mux

Block must be valid during the clock cycle following

the falling edge of FRLD. The data is then transferred

during the subsequent cycle. The frequency of the

NCO output will change 19 clock cycles after the

FRLD command due to pipelining delays.

frequency modulation by controlling the significance

of the FM data in relation to the carrier frequency data.

The FM data word will be multiplied by 2⁰, 2⁴, 2⁸, or

2¹²according to the state of FMADDR_1-0, and the

consequent resolution and maximum values of the

deviation are shown in the table below. The values

shown are for a clock frequency of 60 MHz.

P H S E L

FM-

FM- Mult. factor Maximum Resol-

The Phase Source Select input selects the sources of

ADDR₁ADDR₀of FM data deviation

ution

data for the Phase ALUs. When it is high the sources

are the Sine and Cosine Phase Buffer Registers. They

are loaded from the DATA_7-0bus by setting address

line ADDR₃high, as shown in the tables. When

PHSEL is low, the sources for the phase modulation

data are the DATA_7-0and ADDR_3-0inputs, and the

data will be loaded independently of the states of

WRSTB and CSEL. The data on these 12 lines is

presented directly as a parallel 12-bit word to both

Phase ALUs, allowing high-speed phase modulation.

The 12-bit value is latched into the Phase ALUs by

means of the PHLD input. The data on the ADDR_3-0

lines is mapped onto Phase Bits 3 to 0 and the data on

the DATA_7-0lines are mapped onto Phase Bits 11 to 4

in this case. When using the parallel phase load mode

CSEL and/or WRSTB should remain high to ensure

that the phase data is not written into the phase and

frequency buffer registers of the STEL-1177.

0

1

0

1

0

1

2⁰

2⁴

2⁸

2¹²

± 915 Hz

14 mHz

± 14.6 KHz 0.22 Hz

± 234 KHz 3.6 Hz

± 3.75 MHz 57 Hz

F M L D

The FM Load input controls the writing of the

frequency modulation data on the FMOD_15-0bus and

the FMSUB input into the device. When RATE_1-0= 00

the data at the output of the Frequency Modulation

Control Block must be valid during the clock cycle

following the falling edge of FMLD. The data is then

transferred during the subsequent cycle. When

RATE_1-0= 01, 10 or 11 are selected the FM data will be

loaded automatically without the use of the FMLD

input. Note that FMLD must be held low during

automatic operation, otherwise the loading will be

inhibited.

P H L D

The Phase Load input is used to control the latching of

the Phase Modulation data into the Phase ALUs. The

12-bit data at the output of the Phase Modulation

Control Block must be valid during the clock cycle

following the falling edge of PHLD. The data is then

transferred during the subsequent cycle. The 12-bit

phase data is added to the 12 most significant bits of

the accumulator output, so that the MSB of the phase

data represents a 180° phase change. The source of this

data will be determined by the state of PHSEL. The

phase of the NCO output will change 12 clock cycles

after the PHLD command, due to pipelining delays.

S I M L D

The Simultaneous Load input allows the carrier

frequency data from the Mux Block and the FM data

to be updated simultaneously. When SIMLD is low,

only the FM data will be updated after a falling edge

on FMLD. When this input is high, both the FM data

and carrier frequency data will be updated

simultaneously. When SIMLD is low at least four

clock cycles are required between falling edges of

FMLD and FRLD to ensure glitch-free changes in the

outputs.

FMOD₁₅through FMOD₀

The Frequency Modulation bus is a 16-bit bus on

which the FM data is loaded into the STEL-1177. The

data should be a 16-bit unsigned number.

R A T E_{1 - 0}

The RATE_1-0signals control the rate at which the FM

data on the FMOD_15-0bus is added to or subtracted

from the carrier frequency, as shown in the table

below:

F M S U B

The FM Subtract input controls the Add/Subtract

operation of the ∆-Phase ALU. When it is high the FM

data on the FMOD_15-0bus will be subtracted from the

carrier frequency, and when it is low the FM data will

be added to the carrier frequency. In this way the FM

data can be treated as a 17-bit signed-magnitude

number, where the FMSUB signal is the sign bit.

RATE₁RATE₀

Modulation Update Rate

0

1

0

1

0

1

Manual, with FMLD signal

Every 4th clock cycle

Every 8th clock cycle

Every 16th clock cycle

FMSUB is latched at the same time as FMOD_15-0

.

7

STEL-1177

COS_11-0

C I N

The signal appearing on the COS_11-0outputs is

The Carry Input is an arithmetic carry to the least

derived from the 13 most significant bits of the Phase

Accumulator. The 12-bit cosine function is presented

in offset binary format. When the phase accumulator

is zero, e.g., after a reset, the decimal value of the

output is 4095 (FFF_H). When the phase modulation is

zero the value of the output for a given phase value

follows the relationship:

significant bit of the Accumulator. Normal operation

of the NCO requires that CIN be set at a logic 0. When

CIN is set at a logic 1 the effective value of the ∆-Phase

register is increased by one. This allows the resolution

of the accumulator to be expanded for higher

frequency resolution.

R O U N D

COS_11-0=2047 x cos (360 x (phase+0.5)/8192)°+2048

The ROUND input controls the precision of the

SINE_11-0and COS_11-0outputs. When the ROUND

input is set high, the sine and cosine signals appearing

on the SINE_11-0and COS_11-0buses are accurate to 12

bits. In some instances it may be desirable to use only

the 8 MSBs of these outputs. In such circumstances

the outputs appearing on the SINE_11-0and COS_11-0

buses can be rounded to present a more accurate 8-bit

representation of the signal by setting the ROUND

input low.

The result is accurate to within 1 LSB. However, when

ROUND is set low, the value appearing on the COS_11-

outputs will be rounded and will follow the

0

relationship:

COS_11-4=127 x cos (360 x (phase+0.5)/8192)°+128

The data appearing on the COS_3-0outputs will not be

meaningful under these circumstances.

S Y N C

C O S E N

The Sync output indicates the instant in time when

The Cosine Enable input controls the power supply to

the frequency, FM, or PM change made at the inputs

affects the SINE_11-0and COS_11-0output signals. The

normally high SYNC output goes low for one clock

cycle 19 clock cycles after an FRLD or FMLD

command, and 12 clock cycles after a PHLD

command, to indicate the end of the pipeline delay

and the start of the new steady state condition.

the Cosine Lookup Table. When it is low the cosine

lookup table in the STEL-1177 is disabled, and only

the SINE_11-0outputs will be valid. This reduces the

power consumption of the device by approximately

30%.

OUTPUT

SIGNALS

F M S Y N C

The FM Sync output indicates the instant in time when

SINE_11-0

the FM data on the FMOD bus is written into the

device. The FMSYNC output is normally high and

goes low for one clock cycle at a frequency depending

on the state of the RATE_1-0inputs. In the automatic

modulation modes (RATE_1-0≠ 00) the data on the

FMOD_15-0bus will be written into the FM Buffer

Register on the rising edge of the clock following the

falling edge of FMSYNC. This signal can be used to

synchronize the updating of the FM data externally.

The signal appearing on the SINE_11-0outputs is

derived from the 13 most significant bits of the Phase

Accumulator. The 12-bit sine function is presented in

offset binary format. When the phase accumulator is

zero, e.g., after a reset, the decimal value of the output

is 2049 (801_H). When the phase modulation is zero the

value of the output for a given phase value follows the

relationship:

SINE_11-0=2047 x sin (360 x (phase+0.5)/8192)°+2048

The result is accurate to within 1 LSB. However, when

ROUND is set low, the value appearing on the

SINE_11-0outputs will be rounded and will follow the

relationship:

SINE_11-4=127 x sin (360 x (phase+0.5)/8192)°+128

The data appearing on the SINE_3-0outputs will not be

meaningful under these circumstances.

STEL-1177

8

ELECTRICAL

CHARACTERISTICS

ABSOLUTE

MAXIMUM

RATINGS

Warning: Stresses greater than those shown below may cause permanent damage to the device.

Exposure of the device to these conditions for extended periods may also affect device reliability.

All voltages are referenced to V_SS.

Symbol

Parameter

Range

Units

T_stg

Storage Temperature

–40 to +125

–65 to +150

–0.3 to + 7

–0.3 to V_DD+ 0.3

± 10

°C (Plastic package)

°C (Ceramic package)

V_DDmax

V_I(max)

I_i

Supply voltage on V_DD

Input voltage

volts

mA

DC input current

RECOMMENDED

OPERATING

CONDITIONS

Symbol

Parameter

Range Units

V_DD

Supply Voltage

+5 ± 5%

Volts (Commercial)

Volts (Military)

+5 ± 10%

0 to +70

–55 to +125

T_a

Operating Temperature (Ambient)

°C

(Commercial)

(Military)

D.C. CHARACTERISTICS (Operating Conditions: V_DD= 5.0 V ±5%, VSS = 0 V, T_a= 0° to 70° C, Commercial

_DD= 5.0 V ±10%, VSS = 0 V, Ta = –55° to 125° C, Military)

V

Symbol

Parameter

Min. Typ.

Max. Units

Conditions

I_DD(Q)

I_DD

Supply Current, Quiescent

Supply Current, Operational

High Level Input Voltage

Standard Operating Conditions

Extended Operating Conditions

Low Level Input Voltage

High Level Input Current

Low Level Input Current

High Level Output Voltage

Low Level Output Voltage

Output Short Circuit Current

1.0 mA

Static, no clock

7.0

mA/MHz

V_IH(min)

2.0

volts

Logic '1'

2.25

Logic '1'

V_IL(max)

I_IH(min)

I_IL(max)

V_OH(min)

V_OL(max)

I_OS

0.8 volts

110 µA

10 µA

Logic '0'

10

35

CIN and CSEL, V_IN= V_DD

All other inputs, V_IN= V_DD

CIN and CSEL, V_IN= V_SS

All other inputs, V_IN= V_SS

I_O= –4.0 mA

–10 µA

–130 µA

volts

–15

2.4

–45

4.5

0.2

65

0.4 volts

130 mA

–130 mA

I_O= +4.0 mA

20

V_OUT= V_DD, V_DD= max

V_OUT= V_SS, V_DD= max

–10

–45

C_IN

C_OUT

Input Capacitance

Output Capacitance

2

4

pF

All inputs

All outputs

9

STEL-1177

NCO RESET SEQUENCE

t_RS

RESET

CLOCK

6 CLOCK

EDGES

1

2

3

4

5

6

SINE _11-0

COS _11-0

NOT VALID

801_H

NCO FREQUENCY CHANGE SEQUENCE

CSEL

ADDR _3-0

WRSTB

DATA _7-0

CLOCK

DON'T CARE

t_SU

t_HD

t_WR

DON'T CARE

19 CLOCK

EDGES

t_SU

t_CH

t_CL

FRLD

t_W

FSYNC

t_CD

OLD FREQUENCY NEW FREQUENCY

SINE _11-0

COS _11-0

STEL-1177

10

NCO PHASE CHANGE SEQUENCE

1. PHSEL=0. DIRECT LOADING.

12 CLOCK EDGES

CLOCK

t_SU

DATA _7-0

DON'T CARE

ADDR _3-0

t_HD

t_SU

PHLD

t_W

PSYNC

OLD PHASE

NEW PHASE

SINE _11-0

COS _11-0

ELECTRICAL

CHARACTERISTICS

A.C. CHARACTERISTICS (Operating Conditions: V_DD= 5.0 V ± 5%, V_SS=0 V, T_a= 0° to 70° C, Commercial

V_DD= 5.0 V ± 10%, V_SS=0 V, T_a=–55° to 125° C, Military)

Commercial

Military

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Units Conditions

t_RS

t_SR

t_SU

RESET pulse width

20

10

5

25

12

5

nsec.

RESET to CLOCK Setup

DATA, ADDR or CSEL

to WRSTB or PHLD Setup

and FRLD, PHLD, FMLD

or FMOD to CLOCK Setup

DATA, ADDR or CSEL

to WRSTB or PHLD Hold

and FRLD, PHLD, FMLD

or FMOD to CLOCK Hold

t_HD

5

nsec.

11

STEL-1177

NCO PHASE CHANGE SEQUENCE

2. PHSEL=1. BUS LOADING.

CSEL

ADDR _3-0

WRSTB

DATA _7-0

DON'T CARE

t_SU

t_HD

t_WR

DON'T CARE

12 CLOCK

EDGES

CLOCK

PHLD

t_SU

t_W

PSYNC

OLD PHASE

NEW PHASE

SINE _11-0

COS _11-0

ELECTRICAL

CHARACTERISTICS

A.C. CHARACTERISTICS (Operating Conditions: V_DD= 5.0 V ± 5%, V_SS=0 V, T_a= 0° to 70° C, Chimerical

V_DD= 5.0 V ± 10%, V_SS=0 V, T_a=–55° to 125° C, Military)

Commercial

Military

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Units Conditions

t_CH

CLOCK high

5

7

nsec.

f_CLK= 60 MHz

f_CLK= 40 MHz

f_CLK= 60 MHz

f_CLK= 40 MHz

8

t_CH

t_W

CLOCK low

8

WRSTB, FRLD, PHLD

or FMLD pulse width

CLOCK to output delay

(All outputs)

t_CD

12

3

20

nsec.

Load = 15 pF

STEL-1177

NCO FREQUENCY MODULATION SEQUENCE

1. RATE = 00. MANUAL LOADING.

19 CLOCK EDGES

CLOCK

t_HD

t_SU

FMOD _15-0

FMLD

DON'T CARE

VALID

DON'T CARE

t_SU

t_W

FMSYNC

SYNC

t_CD

NEW FREQUENCY

OLD FREQUENCY

SINE _11-0

COS _11-0

2. RATE ≠ 00. AUTOMATIC LOADING.

(RATE = 01 shown)

4 CLOCK CYCLES

CLOCK

FMOD _15-0

DON'T CARE

VALID

t_HD

DON'T CARE

VALID

DON'T CARE

t_SU

FMSYNC

SINE _11-0

COS _11-0

FMLD

13

STEL-1177

HIGH-SPEED

FREQUENCY

CHANGE

The frequency of the STEL-1177 NCO can be changed

as rapidly as 25% of the clock frequency. This is done

by synchronizing the writing to the two ∆-Phase

Buffer Registers, and updating both every eight clock

cycles. The timing for this procedure is shown below.

Each ∆-Phase Buffer Register is loaded while the

contents of the other are being transferred into the

ALU Buffer Register. The sequence for a load cycle

begins on the rising edge of the clock following a

falling edge of FRLD (or a falling edge of FMLD if

SIMLD is high). In the diagram below, ∆-Phase Buffer

Register A is being loaded in clock cycles 1 through 4,

while the contents of ∆-Phase Buffer Register B are

being transferred, because FRSEL was low during the

falling edge of FRLD. The reverse process happens

during clock cycles 5 through 8, and the process then

repeats starting in clock cycle 9. The FRLD signal can

be used to clock a bistable latch to generate the FRSEL

signal. The maximum update rate is 25%.

1

2

3

4

5

6

7

8

9

CLOCK

WRSTB

ADDR

0111

0000

0001

0010

0011

0100

0101

0110

0111

0000

FRLD

FRSEL

be slightly more than half the clock period at high

speeds some advantage can be gained by generating

the clock by inverting the WRSTB signal, rather than

the other way around. This makes the propagation

delay of the inverter used work for the timing

requirements instead of against them, since the hold

time requirement from the previous rising edge of the

clock (t_HD) is 2 nsec.

It is possible to update the frequency at up to 25% of

the clock frequency using only one buffer register. The

timing for this procedure is shown in the diagram

below, and must be adhered to rigorously in order to

assure adequate setup and hold times. The most

critical factor is the setup time (t_SU) for the WRSTB

relative to the clock (rising edge to rising edge). This

must be 8 nsec. for correct operation. Since this may

1

2

3

4

5

6

7

8

9

CLOCK

t_SU

t_HD

WRSTB

ADDR

0001 0010

0011

0000

0001

0010

0011

0000

0001

3-0

FRLD

FRSEL=1

STEL-1177

14

APPLICATIONS

INFORMATION

USING THE STEL-1177

IN A HIGH-SPEED

WRITE

WRSTB

FRLD

FREQ. LOAD

PHASE

MODULATOR

FROM

µC

By routing the data and address

lines from the microcontroller via

2:1 multiplexers (e.g. 74HC157)

the MNCO can be set up from the

microcontroller and then phase

modulated at high-speed from an

external source. The PHSEL line

should be set to a logic 0 to enable

this mode of operation. The

4

DATA

0-7

A

D0

.

ADDR

0-3

B

A/B

D3

4

A

D4

.

STEL-1177

MNCO

.

PHASE

0-11

B

A/B

D7

4

FROM

PHASE

MOD.

A

A0

.

system shown modulates all 12

bits. In a typical PSK system only

1 to 4 bits of modulation will be

used, simplifying the system

considerably.

B

A/B

FREQ./PH SEL

PHASE LOAD

A3

PHLD

APPLICATION EXAMPLE

-

A

HIGH-LINEARITY FM CARRIER GENERATOR

CONTROL

PROC-

ESSOR

STEL-

1177

NCO

SINE

12

BPF

12-25

MHz

95-108 MHz

BPF

95-108

MHz

D/A

FREQUENCY

MODULATOR

CLK

120 MHz

OSCILLATOR

÷2

The STEL-1177 can be used for high-linearity frequency modulation. The FM port has 16-bit resolution and

linearity, and this can be used to generate a very high-quality signal for FM broadcasting in the 88-108 MHz

frequency band. The audio signal can be digitized at a very high sampling rate, either directly or by

interpolation, to maximize the performance capability of the system.

SPECTRAL

PURITY

The sine and cosine signals generated by the STEL-

1177 have 12 bits of amplitude resolution and 13 bits

of phase resolution which results in spurious levels

which are theoretically at least 75 dB down. The

highest output frequency the NCO can generate is half

the clock frequency (f_c/2), and the spurious

components at frequencies greater than f_c/2 can be

removed by filtering. As the output frequency f_oof

In many applications the NCO is used with a digital

to analog converter (DAC) to generate an analog

waveform which approximates an ideal sinewave.

The spectral purity of this synthesized waveform is a

function of many variables including the phase and

amplitude quantization, the ratio of the clock

frequency to output frequency, and the dynamic

characteristics of the DAC.

15

STEL-1177

the NCO approaches f_c/2, the "image" spur at f_c– f_o

(created by the sampling process) also approaches

f_c/2 from above. If the programmed output frequency

is very close to f_c/2 it will be virtually impossible to

remove this image spur by filtering. For this reason,

the maximum practical output frequency of the NCO

should be limited to about 40% of the clock frequency.

the second harmonic frequency will be higher than the

Nyquist frequency, 50% of the clock frequency. When

this happens, the image of the harmonic at the

frequency f_c– 2f_o, which is not harmonically related to

the output signal, will become intrusive since its

frequency falls as the output frequency rises,

eventually crossing the fundamental output when its

frequency crosses through f_c/3. It would be necessary

to select a DAC with better dynamic linearity to

improve the harmonic spur levels. (The dynamic

linearity of a DAC is a function of both its static

linearity and its dynamic characteristics, such as

settling time and slew rates.) At higher output

frequencies the waveform produced by the DAC will

have large output changes from sample to sample. For

this reason, the settling time of the DAC should be

short in comparison to the clock period. As a general

rule, the DAC used should have the lowest possible

glitch energy as well as the shortest possible settling

time.

A spectral plot of the NCO output after conversion

with a DAC (Sony CX20202A-1) is shown below. In

this case, the clock frequency is 60 MHz and the output

frequency is programmed to 6.789 MHz. This 10-bit

DAC gives better performance than any of the

currently available 12-bit DACs at clock frequencies

higher than 10 or 20 MHz. The maximum non-

harmonic spur level observed over the entire useful

output frequency range in this case is –74 dBc. The

spur levels are limited by the dynamic linearity of the

DAC. It is important to remember that when the

output frequency exceeds 25% of the clock frequency,

TYPICAL

Center Frequency:

SPECTRUM

6.7 MHz

Frequency Span:

Reference Level:

10.0 MHz

–5 dBm

Resolution Bandwidth: 1 KHz

Video Bandwidth:

Scale:

3 kHz

Log, 10 dB/div

6.789 MHz

60 MHz

Output frequency:

Clock frequency:

STEL-1177

16

Information in this document is provided in connection with

Intel® products. No license, express or implied, by estoppel

or otherwise, to any intellectual property rights is granted by

this document. Except as provided in Intels Terms and Con-

ditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied

warranty, relating to sale and/or use of Intel® products in-

cluding liability or warranties relating to fitness for a particu-

lar purpose, merchantability, or infringement of any patent,

copyright or other intellectual property right. Intel products

are not intended for use in medical, life saving, or life sus-

taining applications.

Intel may make changes to specifications and product de-

scriptions at any time, without notice.

For Further Information Call or Write

INTEL CORPORATION

Cable Network Operation

350 E. Plumeria Drive, San Jose, CA 95134

Customer Service Telephone: (408) 545-9700

Technical Support Telephone: (408) 545-9799

FAX: (408) 545-9888


型号：	STEL-1177/CM
厂家：	ETC
描述：	Numeric-Controlled Oscillator 数字控制振荡器\n 振荡器外围集成电路时钟
文件：	总17页 (文件大小：268K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STEL-1177/CM [ETC]

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