STK11C88-S45I [ETC]
32K x 8 nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM; 32K ×8的nvSRAM量子陷阱CMOS非易失性静态RAM
| 型号： | STK11C88-S45I |
| 厂家： | 
ETC |
| 描述： | 32K x 8 nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| 文件： | 总9页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK11C88
32K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software
The Simtek STK11C88 is a fast static RAM with a
nonvolatile, electrically erasable PROM element
incorporated in each static memory cell. The SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation), or from EEPROM to
SRAM (the RECALL operation), take place using a
software sequence. Transfers from the EEPROM to
the SRAM (the RECALL operation) also take place
automatically on restoration of power.
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Commercial and Industrial Temperatures
• 28-Pin PDIP and SOIC Packages
The STK11C88 is pin-compatible with industry-
standard SRAMs.
BLOCK DIAGRAM
PIN CONFIGURATIONS
A
A
A
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
14
EEPROM ARRAY
2
12
512 x 512
3
A
A
A
A
7
6
5
4
3
2
13
8
A5
A6
A7
A8
A
4
A
A
A
A
A
A
DQ
DQ
DQ
5
9
STORE
STORE/
RECALL
CONTROL
6
11
7
G
STATIC RAM
ARRAY
8
A
E
10
RECALL
A9
9
1
0
A11
A12
A13
A14
512 x 512
10
11
12
13
14
DQ
DQ
7
6
5
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
0
DQ
1
DQ
DQ
2
4
3
SOFTWARE
DETECT
A0 - A13
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
PIN NAMES
COLUMN DEC
A
- A
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
0
14
W
A0 A1 A2 A3 A4A10
DQ - DQ
0
7
G
E
E
G
W
V
V
CC
SS
July 1999
5-1
STK11C88
a
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
b
DC CHARACTERISTICS
(V = 5.0V ± 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
c
I
110
97
80
N/A
100
85
mA
mA
mA
mA
t
t
t
t
= 20ns
CC
CC
AVAV
AVAV
AVAV
AVAV
1
= 25ns
= 35ns
= 45ns
70
70
d
I
Average V Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
2
c
I
Average V Current at t
CC
5V, 25°C, Typical
= 200ns
W ≥ (V – 0.2V)
All Others Cycling, CMOS Levels
CC
AVAV
CC
3
10
10
mA
e
e
I
Average V Current
(Standby, Cycling TTL Input Levels)
35
30
25
22
N/A
31
26
mA
mA
mA
mA
t
t
t
t
= 20ns, E ≥ V
= 25ns, E ≥ V
SB
CC
AVAV
AVAV
AVAV
AVAV
IH
IH
1
= 35ns, E ≥ V
= 45ns, E ≥ V
IH
IH
23
I
I
I
V
Standby Current
E ≥ (V
- 0.2V)
CC
SB
CC
2
750
±1
750
±1
µA
µA
µA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
±5
±5
= V to V , E or G ≥ V
IN
SS
CC
IH
V
V
V
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
V
– .5
0.8
V – .5
SS
0.8
IL
SS
2.4
2.4
V
I
I
=– 4mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
= 8mA
T
0
–40
°C
A
Note b: The STK11C88-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: ICC1 is the average current required for the duration of the STORE cycle (tSTORE ).
Note e: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
5.0V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
480 Ohms
OUTPUT
f
CAPACITANCE
(T = 25°C, f = 1.0MHz)
A
30 pF
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
C
Input Capacitance
Output Capacitance
5
7
pF
IN
pF
OUT
Note f: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
July 1999
5-2
STK11C88
b
SRAM READ CYCLES #1 & #2
(V = 5.0V + 10%)
CC
SYMBOLS
STK11C88-20 STK11C88-25 STK11C88-35 STK11C88-45
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
g
20
25
35
45
AVAV
RC
AA
h
3
Address Access Time
22
8
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
h
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
i
7
7
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
10
11
ELICCH
EHICCL
e, f
25
PS
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
g, h
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
g
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
July 1999
5-3
STK11C88
b
SRAM WRITE CYCLES #1 & #2
(V = 5.0V + 10%)
CC
SYMBOLS
STK11C88-20
STK11C88-25
STK11C88-35
STK11C88-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
20
15
15
8
MAX
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
0
DH
AW
t
t
t
15
0
20
0
25
0
30
0
AVWH
AVEH
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
0
WHAX
i, j
EHAX
WR
t
t
7
10
13
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
k
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
k
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
14
ELEH
18
AVEL
19
EHAX
t
t
t
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
July 1999
5-4
STK11C88
b
STORE INHIBIT/POWER-UP RECALL
(V = 5.0V + 10%)
CC
SYMBOLS
STK11C88
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
V
l
RESTORE
STORE
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
4.5
SWITCH
RESET
V
3.9
V
Note l: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE INHIBIT/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
RESET
V
STORE INHIBIT
OWER-UP RECALL
22
RESTORE
t
DQ (DATA OUT)
POWER-UP
BROWN OUT
BROWN OUT
BROWN OUT
RECALL
STORE INHIBIT
STORE INHIBIT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
July 1999
5-5
STK11C88
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
m, n
Nonvolatile STORE
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
m, n
Nonvolatile RECALL
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note n: While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
o, p
b
SOFTWARE STORE/RECALL CYCLE
(V = 5.0V ± 10%)
CC
STK11C88-20
STK11C88-25
STK11C88-35
STK11C88-45
NO.
SYMBOLS
PARAMETER
UNITS
MIN
20
0
MAX
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
26
27
28
29
30
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
µs
AVAV
o
o
AVEL
15
15
20
20
25
20
30
20
ELEH
o
Address Hold Time
ELAX
o
RECALL Duration
20
20
20
20
RECALL
Note o: The software sequence is clocked with E controlled reads.
Note p: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
p
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
AVAV
26
t
AVAV
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
t
ELEH
t
E
29
ELAX
t
23
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
July 1999
5-6
STK11C88
DEVICE OPERATION
The STK11C88 is a versatile memory chip that pro-
SOFTWARE NONVOLATILE STORE
vides several modes of operation. The STK11C88
can operate as a standard 32K x 8 SRAM. It has a
32K x 8 EEPROM shadow to which the SRAM infor-
mation can be copied or from which the SRAM can
be updated in nonvolatile mode.
The STK11C88 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
NOISE CONSIDERATIONS
Note that the STK11C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between V
cc
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
and V , using leads and traces that are as short as
ss
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
To initiate the software STORE cycle, the following
READ sequence must be performed:
The STK11C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-14 determines which of the 32,768 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
July 1999
5-7
STK11C88
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
an unlimited number of times.
HARDWARE PROTECT
The STK11C88 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When VCC < VSWITCH, all software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
POWER-UP RECALL
The STK11C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK11C88 depends on the fol-
lowing items: 1) CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of READs to WRITEs; 5)
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C88 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
the operating temperature; 6) the V level; and 7) I/
O loading.
100
80
cc
60
40
TTL
20
CMOS
150 200
0
50
100
Cycle Time (ns)
100
July 1999
5-8
STK11C88
ORDERING INFORMATION
- W 25 I
STK11C88
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
W = Plastic 28-pin 600 mil DIP
P = Plastic 28-pin 300 mil DIP
S = Plastic 28-pin 350 mil SOIC
N = Plastic 28-pin 300 mil SOIC
July 1999
5-9
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