STK12C68-5P45 [ETC]
8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM; 8K ×8 AutoStore⑩的nvSRAM QuantumTrap⑩ CMOS非易失性静态RAM
| 型号： | STK12C68-5P45 |
| 厂家： | 
ETC |
| 描述： | 8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM |
| 文件： | 总13页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK12C68
STK12C68-M SMD#5962-94599
8K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• 25ns, 35ns, 45ns and 55ns Access Times
The Simtek STK12C68 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in Nonvolatile Elements. Data
transfers from the SRAM to the Nonvolatile Elements
(the STORE operation) can take place automatically
on power down. A 68µF or larger capacitor tied from
VCAP to ground guarantees the STORE operation,
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the Nonvolatile
Elements to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initia-
tion of STORE and RECALL cycles can also be soft-
ware controlled by entering specific read
sequences. A hardware STORE may be initiated with
the HSB pin.
• “Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to Nonvolatile Elements Initiated by
Hardware, Software or AutoStore™ on Power
Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in Nonvolatile Ele-
ments (Commercial/Industrial)
• Commercial, Industrial and Military Tempera-
tures
• 28-Pin SOIC, DIP and LCC Packages
BLOCK DIAGRAM
PIN CONFIGURATIONS
V
V
CAP
CCX
1
2
3
4
5
6
7
8
V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CAP
CCX
A
W
12
A
HSB
7
6
POWER
A
A
8
QUANTUM TRAP
128 x 512
A
A
5
9
CONTROL
A
A
4
3
11
G
A
A5
A6
A7
A8
A9
A
A
E
2
10
9
A
A
1
0
STORE
10
11
12
13
14
DQ
7
STORE/
RECALL
DQ
DQ
6
0
1
2
SS
HSB
DQ
DQ
5
STATIC RAM
DQ
DQ
4
CONTROL
RECALL
V
DQ
3
ARRAY
128 x 512
28 - LCC
28 - DIP
A11
A12
28 - SOIC
SOFTWARE
DETECT
A
- A
12
0
PIN NAMES
DQ
DQ
DQ
0
1
2
COLUMN I/O
A
- A
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
0
12
COLUMN DEC
DQ -DQ
0
7
DQ
3
4
E
W
G
DQ
DQ
DQ
DQ
5
6
7
A
A A
A A
1 4
2 3
A
10
0
G
HSB
E
W
V
V
V
CCX
CAP
SS
Ground
October 2003
1
Document Control # ML0008 rev 0.4
STK12C68
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (V + 0.5V)
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (V + 0.5V)
CC
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
CC
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)e
INDUSTRIAL/
MILITARY
COMMERCIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
85
75
65
55
90
75
65
55
mA
mA
mA
mA
t
t
t
t
= 25ns
= 35ns
= 45ns
= 55ns
CC
CC
AVAV
AVAV
AVAV
AVAV
1
c
I
I
Average V Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3
10
10
mA
5V, 25°C, Typical
All Others Cycling, CMOS Levels
c
I
I
Average V
Current during
CAP
All Inputs Don’t Care
CC
4
2
2
mA
AutoStore™ Cycle
d
Average V Current
(Standby, Cycling TTL Input Levels)
27
23
20
19
28
24
21
19
mA
mA
mA
mA
t
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
= 55ns, E ≥ V
SB
CC
AVAV
AVAV
AVAV
AVAV
IH
IH
IH
IH
1
d
I
I
I
V
Standby Current
E ≥ (V – 0.2V)
CC
SB
CC
2
1.5
±1
±5
2.5
±1
±5
mA
µA
µA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
= V to V , E or G ≥ V
IH
IN
SS
CC
V
V
V
V
V
Input Logic “1” Voltage
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
Input Logic “0” Voltage
V
– .5
0.8
V – .5
SS
0.8
IL
SS
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
2.4
2.4
V
I
I
I
=–4mA except HSB
= 8mA except HSB
= 3mA
OH
OL
BL
OUT
OUT
OUT
0.4
0.4
70
0.4
0.4
V
V
T
0
–40/-55
85/125
°C
A
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC3 are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note e: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is con-
nected to ground.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
5.0V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
480 Ohms
OUTPUT
30 pF
CAPACITANCEf
(TA = 25°C, f = 1.0MHz)
255 Ohms
INCLUDING
SCOPE AND
FIXTURE
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
C
Input Capacitance
Output Capacitance
8
7
pF
IN
pF
OUT
Note f: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
October 2003
2
Document Control # ML0008 rev 0.4
STK12C68
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
SYMBOLS
STK12C68-25
STK12C68-35
STK12C68-45
STK12C68-55
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
25
35
45
55
AVAV
h
3
Address Access Time
25
10
35
15
45
20
55
35
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
h
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
i
7
10
10
25
10
10
35
12
12
45
12
12
55
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledg
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
E
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
October 2003
3
Document Control # ML0008 rev 0.4
STK12C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
SYMBOLS
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
45
45
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
AW
t
t
t
20
0
25
0
30
0
45
0
AVWH
AVEH
t
t
t
AVWL
AVEL
EHAX
AS
t
t
t
0
0
0
0
WHAX
WR
i, j
t
t
10
13
14
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
t
AVAV
ADDRESS
19
14
t
WHAX
t
ELWH
E
17
t
AVWH
18
t
AVWL
13
t
W
WLWH
15
16
t
t
DVWH
WHDX
DATA IN
DATA VALID
20
t
WLQZ
21
t
WHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
t
AVAV
ADDRESS
14
18
19
t
t
ELEH
t
AVEL
EHAX
E
17
t
AVEH
13
t
WLEH
W
15
16
t
DVEH
t
EHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
October 2003
4
Document Control # ML0008 rev 0.4
STK12C68
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
0
MODE
Not Selected
I/O
POWER
NOTES
12
H
X
X
X
X
Output High Z
Output Data
Input Data
Standby
Active
H
Read SRAM
o
L
H
Write SRAM
Active
X
X
L
Nonvolatile STORE
Output High Z
l
m
CC
2
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
Active
L
L
H
H
H
H
n, o
n, o
Read SRAM
Read SRAM
Nonvolatile STORE
l
CC
2
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
Active
Read SRAM
Read SRAM
Nonvolatile RECALL
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE STORE CYCLE
(VCC = 5.0V ± 10%)e
SYMBOLS
STK12C68
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
µs
ns
ns
ns
i, p
i, q
p, r
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
1
700
300
15
Hardware STORE Low to Store Busy
HLBL
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r: RECOVER is only applicable after tSTORE is complete.
t
HARDWARE STORE CYCLE
25
t
HLHX
HSB (IN)
24
t
RECOVER
22
t
STORE
26
t
HLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
t
DELAY
DQ (DATA OUT)
DATA VALID
October 2003
5
Document Control # ML0008 rev 0.4
STK12C68
AutoStore™/POWER-UP RECALL
(VCC = 5.0V ± 10%)e
SYMBOLS
STK12C68
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
550
10
27
28
29
30
31
32
t
t
t
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
ns
µs
V
s
RESTORE
STORE
VSBL
t
t
p, q, t
HLHZ
BLQZ
Low Voltage Trigger (V
) to HSB Low
300
l
SWITCH
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
1
p
DELAY
V
V
4.0
4.5
3.9
SWITCH
RESET
Low Voltage Reset Level
V
Note s: tRESTORE starts from the time VCC rises above VSWITCH
.
Note t: HSB is asserted low for 1µs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
will be released and no STORE will take place.
AutoStore™/POWER-UP RECALL
V
CC
31
V
SWITCH
32
V
RESET
TM
AutoStore
POWER-UP RECALL
29
28
27
t
VSBL
t
t
STORE
RESTORE
HSB
30
t
DELAY
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
AutoStore™
BROWN OUT
AutoStore™
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
October 2003
6
Document Control # ML0008 rev 0.4
STK12C68
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv
(VCC = 5.0V ± 10%)e
SYMBOLS
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
NO.
PARAMETER
UNITS NOTES
Standard Alternate
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
MIN
55
0
MAX
33
34
35
36
37
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
µs
p
u
u
u
AVAV
RC
AS
AVEL
20
20
25
20
30
20
30
20
ELEH
ELAX
RECALL
CW
Address Hold Time
RECALL Duration
20
20
20
20
Note u: The software sequence is clocked with E controlled READs.
Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledv
33
AVAV
33
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
34
AVEL
35
ELEH
t
t
E
36
ELAX
t
28
37
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA OUT)
October 2003
7
Document Control # ML0008 rev 0.4
STK12C68
DEVICE OPERATION
The STK12C68 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to Nonvolatile Elements (the STORE
operation) or from Nonvolatile Elements to SRAM
(the RECALL operation). In this mode SRAM func-
tions are disabled.
POWER-UP RECALL
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK12C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
NOISE CONSIDERATIONS
The STK12C68 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCAP and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SOFTWARE NONVOLATILE STORE
The STK12C68 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations. During the STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvol-
atile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are dis-
abled until the cycle is completed.
SRAM READ
The STK12C68 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A0-12 determines which of
the 8,192 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond
to address changes within the tAVQV access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
SRAM WRITE
Valid READ
Valid READ
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
October 2003
8
Document Control # ML0008 rev 0.4
STK12C68
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ opera-
tions must be performed:
In system power mode (Figure 3), both VCCX and
VCAP are connected to the + 5V power supply without
the 68µF capacitor. In this mode the AutoStore™
function of the STK12C68 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that VCCX does not drop below
3.6V during the 10ms STORE cycle.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
If an automatic STORE on power loss is not required,
then VCCX can be tied to ground and + 5V applied to
VCAP (Figure 4). This is the AutoStore™ Inhibit
mode, in which the AutoStore™ function is disabled.
If the STK12C68 is operated in this configuration,
references to VCCX should be changed to VCAP
throughout this data sheet. In this mode, STORE
operations may be triggered through software con-
trol or the HSB pin. It is not permissable to change
between these three options “on the fly”.
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. After
the tRECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the Nonvolatile
Elements. The nonvolatile data can be recalled an
unlimited number of times.
AutoStore™ OPERATION
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software-
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. An
optional pull-up resistor is shown connected to HSB.
This can be used to signal the system that the
AutoStore™ cycle is in progress.
The STK12C68 can be powered in one of three
modes.
During normal AutoStore™ operation, the
STK12C68 will draw current from VCCX to charge a
capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the VCAP pin drops below VSWITCH, the part will
automatically disconnect the VCAP pin from VCCX and
initiate a STORE operation.
1
28
27
26
1
28
27
26
1
28
27
26
+
15
15
14
14
15
14
Figure 2: AutoStore™ Mode
Figure 3: System Power Mode
Figure 4: AutoStore™
Inhibit Mode
*If HSB is not used, it should be left unconnected.
October 2003
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Document Control # ML0008 rev 0.4
STK12C68
HSB OPERATION
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB high with a driver capable of sourcing
30mA at a VOH of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB low for 20µs at the onset of a STORE. When
the STK12C68 is connected for AutoStore™ opera-
tion (system VCC connected to VCCX and a 68µF
capacitor on VCAP) and VCC crosses VSWITCH on the
way down, the STK12C68 will attempt to pull HSB
low; if HSB doesn’t actually get below VIL, the part
will stop trying to pull HSB low and abort the STORE
attempt.
The STK12C68 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin is used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK12C68 will
conditionally initiate a STORE operation after tDELAY
;
an actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin acts as an open drain
driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means)
is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK12C68 will
HARDWARE PROTECT
The STK12C68 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When VCAP < VSWITCH, all
externally initiated STORE operations and SRAM
WRITEs are inhibited.
continue SRAM operations for tDELAY. During tDELAY
,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
AutoStore™ can be completely disabled by tying
VCCX to ground and applying + 5V to VCAP . This is the
AutoStore™ Inhibit mode; in this mode, STOREs are
only initiated by explicit request using either the soft-
ware sequence or the HSB pin.
The HSB pin can be used to synchronize multiple
STK12C68s while using a single larger capacitor. To
operate in this mode the HSB pin should be con-
nected together to the HSB pins from the other
STK12C68s. An external pull-up resistor to + 5V is
required since HSB acts as an open drain pull down.
The VCAP pins from the other STK12C68 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK12C68s detects a power loss and asserts HSB,
the common HSB pin will cause all parts to request
a STORE cycle (a STORE will take place in those
STK12C68s that have been written since the last
nonvolatile cycle).
LOW AVERAGE ACTIVE POWER
The STK12C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK12C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
During any STORE operation, regardless of how it
was initiated, the STK12C68 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK12C68 will remain disabled until the HSB
pin returns high.
temperature; 6) the V level; and 7) I/O loading.
cc
If HSB is not used, it should be left unconnected.
October 2003
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Document Control # ML0008 rev 0.4
STK12C68
100
80
100
80
60
60
TTL
CMOS
40
20
40
20
TTL
CMOS
0
0
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 5: Icc (max) Reads
Figure 6: Icc (max) Writes
October 2003
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Document Control # ML0008 rev 0.4
STK12C68
ORDERING INFORMATION
- 5 P F 45 I
STK12C68
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
M = Military (–55 to 125°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
55 = 55ns
Lead Finish (Plastic only)
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP
W= Plastic 28-pin 600 mil DIP
S = Plastic 28-pin 350 mil SOIC
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
6
Blank = Comm/Ind (100 years/10 cycles)
5
5962-94599 01 MX X
5 = Military (10 years/10 cycles)
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
01 = 55ns
02 = 45ns
03 = 35ns
October 2003
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Document Control # ML0008 rev 0.4
STK12C68
Document Revision History
Revision
0.0
Date
December 2002
January 2003
July 2003
September 2003
October 2003
Summary
Combined commercial, industrial and military datasheets. Removed 20 nsec device.
Added 35 nsec SMD to order information
Added “28 - SOIC” label to page 1 pinout drawing
Added lead-free lead finish
0.1
0.2
0.3
0.4
Restored “W” 600 mil DIP package to ordering information
October 2003
13
Document Control # ML0008 rev 0.4
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