STN1110-I/SO [ETC]
Multiprotocol OBD to UART Interpreter;
| 型号： | STN1110-I/SO |
| 厂家： | 
ETC |
| 描述： | Multiprotocol OBD to UART Interpreter |
| 文件： | 总24页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STN1110
Multiprotocol OBD to UART Interpreter
Datasheet
STN1110
Table of Contents
1.0
2.0
3.0
4.0
4.1
4.2
5.0
Overview.........................................................................................................................................................3
Feature Highlights .........................................................................................................................................3
Typical Applications......................................................................................................................................3
Pinout..............................................................................................................................................................4
Pinout Summary..........................................................................................................................................5
Detailed Pin Descriptions ............................................................................................................................6
Guidelines for Getting Started with STN1110 .............................................................................................8
Basic Connection Requirements.................................................................................................................8
Decoupling Capacitors ................................................................................................................................8
5.1
5.2
5.2.1 Tank Capacitors ......................................................................................................................................8
5.3
AVDD and AVSS Pins...................................................................................................................................8
Internal Voltage Regulator Filter Capacitor .................................................................................................8
Device Reset Pin .........................................................................................................................................8
Oscillator Pins..............................................................................................................................................9
NVM Reset Input .........................................................................................................................................9
Open Drain Outputs.....................................................................................................................................9
Unused Inputs and Unused Open Drain Outputs........................................................................................9
Reference Schematics.................................................................................................................................10
Recommended Minimum Connection .......................................................................................................10
Typical Configuration.................................................................................................................................11
Electrical Characteristics............................................................................................................................15
Absolute Maximum Ratings.......................................................................................................................15
Electrical Characteristics ...........................................................................................................................15
Packaging Diagrams and Parameters .......................................................................................................18
SPDIP (SP) Package.................................................................................................................................18
SOIC 300mil (SO) Package.......................................................................................................................19
SOIC 300mil (SO) Land Pattern................................................................................................................20
QFN-S (MM) Package...............................................................................................................................21
QFN-S (MM) Land Pattern ........................................................................................................................22
Ordering Information...................................................................................................................................23
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
7.0
7.1
7.2
8.0
8.1
8.2
8.3
8.4
8.5
9.0
Appendix A: Revision History..............................................................................................................................24
Appendix B: Contact Information........................................................................................................................24
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your OBD Solutions
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please visit our web site at http://www.obdsol.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last
character of the literature number is the version number, (e.g., STN1110DSA is version A of document STN1110DS).
All rights Reserved. Copyright © 2012 OBD Solutions
Every effort is made to verify the accuracy of information provided in this document, but no representation or warranty can be given and no
liability assumed by OBD Solutions with respect to the accuracy and/or use of any products or information described in this document. OBD
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to the device(s) described in the document in order to improve reliability, function, or design.
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STN1110DSB
STN1110
1.0 Overview
This datasheet summarizes the features of the STN1110 device. It is not intended as a comprehensive reference source. To
complement the information in this datasheet refer to the “STN1100 Family Reference and Programming Manual”.
Please see the OBD Solutions website (www.obdsol.com) for the latest version of the STN1100 Family Reference Manual.
The STN1110 is an OBD to UART interpreter IC
designed to provide bi-directional half-duplex
communication with the vehicle’s On-Board Diagnostic
System (OBD-II). It supports all legislated OBD-II
protocols
A wealth of information can be obtained by tapping
into the OBD bus, including the status of the
malfunction indicator light (MIL), diagnostic trouble
codes (DTCs), inspection and maintenance (I/M)
information, freeze frames, VIN, hundreds of real-time
parameters, and more.
The STN1110 is fully compatible with the de facto
industry standard ELM327 command set. Based on a
16-bit processor core, the STN1110 offers more
features and better performance than any other
ELM327 compatible IC.
2.0 Feature Highlights
•
•
•
•
•
•
Stable, field-tested firmware
Fully compatible with the ELM327 AT command set
Extended ST command set
UART interface (baud rates from 38 bps to 10 Mbps1)
Secure bootloader for easy firmware updates
Support for all legislated OBD-II protocols:
o
o
o
o
o
ISO 15765-4 (CAN)
ISO 14230-4 (Keyword Protocol 2000)
ISO 9141-2 (Asian, European, Chrysler vehicles)
SAE J1850 VPW (GM vehicles)
SAE J1850 PWM (Ford vehicles)
•
Support for non-legislated OBD protocols:
o
o
ISO 15765
ISO 11898 (raw CAN)
•
•
•
•
•
•
Support for the heavy-duty SAE J1939 OBD protocol
Superior automatic protocol detection algorithm
Large memory buffer
Sophisticated PowerSave Sleep/Wakeup Triggers
Available in SPDIP, SOIC and QFN-S packages
RoHS compliant
Note 1: Maximum theoretical baud rate. Actual maximum baud rate is
application dependent and may be limited by driver hardware.
3.0 Typical Applications
•
•
•
•
•
•
Vehicle telematics
Fleet management and tracking applications
Usage-based insurance (UBI)
OBD data loggers
Automotive diagnostic scan tools and code readers
Digital dashboards
STN1110DSB
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STN1110
4.0 Pinout
28-Pin SPDIP, SOIC
5V tolerant pins
RESET
ANALOG_IN
PWM/VPW
VPW_RX
PWM_RX
J1850_BUS+_TX
J1850_BUS-_TX
VSS
1
28
AVDD
AVSS
3
26
25
24
23
22
21
20
19
18
17
16
15
ISO_L_TX
ISO_K_TX
UART_RX_LED
UART_TX_LED
4
5
6
7
OBD_RX_LED / INT
OBD_TX_LED / RST_NVM
VCAP
8
OSC1
9
OSC2
10
11
12
13
14
VSS
ISO_RX
PWR_CTRL
UART_TX
SLEEP
VDD
UART_RX
CAN_RX
CAN_TX
28-Pin QFN-S(1)
5V tolerant pins
VPW_RX
1
2
3
4
5
6
7
21 UART_RX_LED
20 UART_TX_LED
19 OBD_RX_LED / INT
18 OBD_TX_LED / RST_NVM
17 VCAP
PWM_RX
J1850_BUS+_TX
J1850_BUS-_TX
VSS
STN1110-I/MM
OSC1
16 VSS
OSC2
15 PWR_CTRL
Note 1. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
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STN1110
4.1 Pinout Summary
Table 1: Pinout Summary
Pin Number
Pin Name
Pin Type
Pin Description
SOIC
SPDIP
QFN-S
1
2
26
27
I, 5V
A
Active low device reset input
Analog voltage measurement input
R¯E¯¯S¯E¯T
ANALOG_IN
SAE J1850 PWM/VPW Bus+ voltage select
output
3
28
O, 4x
PWM/¯V¯P¯W¯
4
5
6
1
2
3
I
I
Active low J1850 VPW receive input
SAE J1850 PWM receive input
SAE J1850 Bus+ transmit output
¯V¯P¯W¯_¯R¯X¯
PWM_RX
J1850_BUS+_TX
O, 4x
7
4
5
O, 4x
Active low SAE J1850 Bus- transmit output
Ground reference for logic and I/O pins
16.000 MHz oscillator crystal input
16.000 MHz oscillator crystal output
Active low ISO 9141/ISO 14230 K-line input
External sleep control input
J¯1¯8¯5¯0¯_¯B¯U¯S¯-¯_¯T¯X
VSS
8
P
9
6
OSC1
I
10
11
12
13
14
15
16
17
18
19
20
7
OSC2
O
8
I
I
I¯S¯O¯_¯R¯X¯
S¯L¯E¯E¯¯P
9
10
11
12
13
14
15
16
17
VDD
P
Positive supply for logic and I/O pins
CAN receive input
CAN_RX
CAN_TX
UART_RX
UART_TX
PWR_CTRL
VSS
I, 5V
OD, 5V, 4x CAN transmit output
I, 5V UART receive input
OD, 5V, 4x UART transmit output
OD, 5V, 4x External power control output
P
P
Ground reference for logic and I/O pins
CPU logic filter capacitor connection
VCAP
Active low OBD transmit activity LED output and
21
22
18
19
OD/I, 5V, 2x active low input to reset non-volatile settings to
factory defaults
¯O¯B¯D¯_¯T¯X¯_¯L¯E¯D¯ / ¯R¯S¯T¯_¯N¯V¯M¯
Active low OBD receive activity LED or interrupt
OD, 5V, 2x
output
¯O¯B¯D¯_¯R¯X¯_¯L¯E¯D¯ / ¯IN¯T¯
23
24
25
26
27
28
—
20
21
O, 4x
O, 4x
O, 4x
O, 4x
P
Active low UART transmit activity LED output
Active low UART transmit activity LED output
Active low ISO 9141/ISO 14230 K-line output
Active low ISO 9141/ISO 14230 L-line output
Analog ground reference
¯U¯A¯R¯T¯_¯T¯X¯_¯L¯E¯D¯
¯U¯A¯R¯T¯_¯R¯X¯_¯L¯E¯D¯
¯IS¯O¯_¯K¯_¯T¯X¯
¯IS¯O¯_¯L¯_¯T¯X¯
AVSS
22
23
24
25
AVDD
P
Analog positive supply
PAD
—
Thermal pad
Legend:
I
A
P
– Schmitt trigger input with CMOS levels
– analog input
– power pin
O
– digital output
2x – 2x source/sink driver
4x – 4x source/sink driver
OD – open drain output
5V – 5 volt tolerant pin
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STN1110
4.2 Detailed Pin Descriptions
¯R¯E¯S¯E¯T¯
J¯1¯8¯5¯0¯_¯B¯U¯S¯-¯_¯T¯X
Device reset input. A logic low pulse (min 2 μs) on
this pin will reset the device. Apply a continuous logic
low to hold the device in reset. If your circuit does not
use this functionality, connect this pin to VDD.
Active low SAE J1850 Bus- transmit output. When
the pin is high, Bus- should be low (dominant). This
pin has a 4x current rating (see Table 6 “Output Pin
DC Specifications”). Leave unconnected if unused.
VSS
ANALOG_IN
Ground reference for logic and I/O pins.
Analog voltage measurement input (AVDD max).
By default, this input is calibrated for an external
62 kΩ/10 kΩ voltage divider connected to battery
positive. Connect to AVSS if unused.
OSC1, OSC2
16.000 MHz oscillator crystal connection.
PWM / ¯V¯P¯W¯
I¯S¯O¯_¯R¯X¯
The firmware uses this pin to control the voltage
level of the SAE J1850 PWM/VPW Bus+ supply.
When the PWM protocol is selected, it outputs a logic
high to switch the supply voltage to a nominal 5V.
When the VPW protocol is selected, it outputs a logic
low to switch the supply voltage to a nominal 8V. This
pin has a 4x current rating (see Table 6 “Output Pin
DC Specifications”). Leave unconnected if unused.
Active low ISO 9141/ISO 14230 K-line receive
input. When K-line is high (recessive), this pin should
be at a logic low level. Connect to VSS if unused.
S¯L¯E¯E¯¯P
External sleep control input. When enabled in
firmware, puts the device into low-power sleep mode.
Polarity of this pin can be configured in firmware;
default configuration is active low. Internal pull-up to
VDD is enabled by default, but can be disabled in
firmware. Leave unconnected if unused.
¯V¯P¯W¯_¯R¯X¯
Active low SAE J1850 VPW receive input. When
the SAE J1850 Bus+ is in the recessive (low) state,
this pin should be at a logic high level. When the
SAE J1850 Bus+ is in the dominant (high) state, this
pin should be at a logic low level. Pull up to VDD if
unused.
VDD
Positive 3.0 – 3.6V supply for logic and I/O pins.
PWM_RX
CAN_RX
SAE J1850 PWM receive input. When the
SAE J1850 bus is in the recessive state (Bus+ is low,
Bus- is high), this pin should be at a logic low level.
When the SAE J1850 bus is in the dominant (Bus+ is
high) state, this pin should be at a logic high level.
Connect to VSS if unused.
CAN receive input. Compatible with 3.3V and 5V
logic. Pull up to VDD if unused.
CAN_TX
CAN transmit output. Open drain – requires a pull-
up to VDD or 5V. This pin has a 4x current rating (see
Table 6 “Output Pin DC Specifications”). Pull-up value
depends on CAN baud rates used and the trace
length (higher resistor values can be used with lower
baud rates and shorter traces); recommended value is
1 kΩ. Pull up to VDD via 100 kΩ resistor if unused.
J1850_BUS+_TX
SAE J1850 Bus+ transmit output. When the pin is
high, Bus+ should be high (dominant). This pin has a
4x current rating (see Table 6 “Output Pin DC
Specifications”). Leave unconnected if unused.
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STN1110DSB
STN1110
UART_RX
UART receive input. Compatible with 3.3V and 5V
This pin has a 4x current rating (see Table 6 “Output
Pin DC Specifications”). Leave unconnected if un-
used.
logic.
U¯¯A¯R¯T¯_¯R¯X¯_¯L¯E¯D¯
UART_TX
Active low UART transmit activity LED output.
Voltage on the anode of the LED must not exceed
VDD + 0.3V. This pin has a 4x current rating (see
Table 6 “Output Pin DC Specifications”). Leave
unconnected if unused.
UART transmit output. Open drain – requires a
pull-up to VDD or 5V. This pin has a 4x current rating
(see Table 6 “Output Pin DC Specifications”). Pull-up
value depends on UART baud rate and the trace
length (higher resistor values can be used with lower
baud rates and shorter traces); typical value is 1 kΩ.
¯IS¯O¯_¯K¯_¯T¯X¯
PWR_CTRL
Active low ISO 9141/ISO 14230 K-line output.
When the pin is logic high, K-line should be low. This
pin has a 4x current rating (see Table 6 “Output Pin
DC Specifications”). Leave unconnected if unused.
External power control output. Used to switch
external circuitry into low-power (sleep) state. Polarity
can be configured in firmware; default configuration is
active high (logic low = sleep mode). Open drain –
requires a pull-up to VDD or 5V; be mindful of the fact
that the pull-up will draw current in low-power state.
This pin has a 4x current rating (see Table 6 “Output
Pin DC Specifications”). Pull down to VSS via 100 kΩ
resistor if unused.
¯IS¯O¯_¯L¯_¯T¯X¯
Active low ISO 9141/ISO 14230 L-line output.
When the pin is logic high, L-line should be low. This
pin has a 4x current rating (see Table 6 “Output Pin
DC Specifications”). Leave unconnected if unused.
VCAP
CPU logic filter capacitor connection. Connect to a
low-ESR (< 5 Ω) tantalum or ceramic capacitor.
Minimum value is 4.7 μF; typical value is 10 μF.
AVSS
Analog ground reference. Must be connected to
analog “clean” ground (between VSS - 0.3V and
VSS + 0.3V) or VSS.
¯O¯B¯D¯_¯T¯X¯_¯L¯E¯D¯ / ¯R¯S¯T¯_¯N¯V¯M¯
Active low OBD transmit activity LED output and
active low input to reset NVM to factory defaults.
Open drain – requires a pull-up to VDD or 5V. This pin
has a 2x current rating (see Table 6 “Output Pin DC
Specifications”). Pull up to VDD via 100 kΩ resistor if
unused.
AVDD
Analog positive supply. Must be connected to VDD
or an external voltage reference (between VDD - 0.3V
or 3.0V, whichever is greater and VDD + 0.3V or 3.6V,
whichever is less). AVDD may be decoupled from
digital supply by connecting it to VDD via a 10 Ω
resistor or a small (10 μH – 47 μH) inductor.
O¯¯B¯D¯_¯R¯X¯_¯L¯E¯D¯ / ¯IN¯T¯
Active low OBD receive activity LED or interrupt
output. Open drain – requires a pull-up to VDD or 5V
when configured as interrupt. This pin has a 2x
PAD
The metal plane at the bottom of the device (QFN
package only). It is not connected to any pins
internally. Connect to VSS externally.
current rating (see Table
6
“Output Pin DC
Specifications”). Pull up to VDD if unused.
¯U¯A¯R¯T¯_¯T¯X¯_¯L¯E¯D¯
Active low UART transmit activity LED output.
Voltage on the anode of the LED must not exceed
VDD + 0.3V.
STN1110DSB
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STN1110
5.0 Guidelines for Getting Started with STN1110
return traces to the decoupling capacitors first,
5.1 Basic Connection
Requirements
Getting started with the STN1110 IC requires
attention to a minimal set of device pin connections
before proceeding with development. The following is
a list of pin names, which must always be connected:
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
•
VDD and both VSS pins (see Section 5.2
“Decoupling Capacitors”)
5.2.1 Tank Capacitors
On boards with power traces running longer than
six inches in length, use a tank capacitor for
integrated circuits, including STN1110, to supply a
local power source. The value of the tank capacitor
should be determined based on the trace resistance
that connects the power supply source to the device,
and the maximum current drawn by the device in the
application. In other words, select the tank capacitor
so that it meets the acceptable voltage sag at the
device. Typical values range from 4.7 µF to 47 µF.
•
AVDD and AVSS pins (see Section 5.2
“Decoupling Capacitors” and Section 5.3 “AVDD
and AVSS Pins”)
•
VCAP (see Section 5.4 “Internal Voltage
Regulator Filter Capacitor”)
•
•
¯R¯E¯S¯E¯T¯ pin (see Section 5.5 “Device Reset Pin”)
OSC1 and OSC2 pins (see Section 5.6
“Oscillator Pins”)
•
•
¯R¯S¯T¯_¯N¯V¯M¯ pin (see Section 5.7 “NVM Reset
Input”)
5.3 AVDD and AVSS Pins
Open Drain Output Pull-ups (see Section 5.8
“Open Drain Outputs”)
As a minimum, AVDD must be connected directly
to VDD and AVSS must be connected directly to VSS.
It is recommended that AVDD be connected to to VDD
via a 10 Ω resistor or a small (10 μH – 47 μH)
inductor.
AVSS should be connected to the electrically
cleanest ground net (plane). For best results, analog
circuitry should have a separate ground plane with a
point connection to VSS ground plane as close as
possible to the AVSS pin.
5.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS and AVDD,
AVSS is required. Consider the following criteria when
using decoupling capacitors:
•
Value and type of capacitor: Recommendation
of 1 μF, 10-20V. This capacitor should be a low-
ESR and have resonance frequency in the range
of 20 MHz and higher. It is recommended that
ceramic capacitors be used.
5.4 Internal Voltage Regulator
Filter Capacitor
•
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within ¼”
(6 mm) in length.
A low-ESR (< 5 Ω) capacitor is required on the
VCAP pin, which is used to stabilize the internal
voltage regulator output voltage. The VCAP pin must
not be connected to VDD, and must have a capacitor
between 4.7 µF and 10 µF, 16V connected to ground.
The type can be ceramic or tantalum. Refer to
Section 7.2 “Electrical Characteristics” for additional
information. The placement of this capacitor should
be close to the VCAP pin. It is recommended that the
trace length not exceed ¼” (6 mm).
•
•
Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add
a second ceramic-type
capacitor in parallel to the above described
decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 µF to
0.001 µF. Place this second capacitor next to the
primary decoupling capacitor.
5.5 Device Reset Pin
R¯E¯¯S¯E¯T pin must be logic high for STN1110 to
run. If this pin is not controlled by the host controller,
it must be connected to VDD.
It is recommended to pull up R¯E¯¯S¯E¯T pin to VDD
via a 10 kΩ resistor.
Maximizing performance: On the board layout
from the power supply circuit, run the power and
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STN1110DSB
STN1110
circuit. Leaving any of its inputs or open drain outputs
floating may result in IC damage.
Unused open drain outputs can only be
terminated with a resistor connected to VDD or 5V.
Unused inputs can be terminated via a resistor or
direct connection to VSS or VDD.
Unused inputs and open drain outputs should be
connected as shown in Table 2. See section 4.2
“Detailed Pin Descriptions” and section 6.1
“Recommended Minimum Connection” for more
information.
5.6 Oscillator Pins
The oscillator circuit should be placed on the
same side of the board as the device. Also, place the
oscillator circuit close to the oscillator pins, not
exceeding one-half inch (12 mm) distance between
them. The load capacitors should be placed next to
the oscillator itself, on the same side of the board.
Use a grounded copper pour around the oscillator
circuit to isolate them from surrounding circuits. The
grounded copper pour should be routed directly to
the STN1110 ground. Do not run any signal traces or
power traces inside the ground pour. Also, if using a
two-sided board, avoid any traces on the other side
of the board where the crystal is placed. A suggested
layout is shown in Figure 1.
Table 2 – Recommended Unused Input and
Open Drain Output Connections
Pin Number
Pin Name
Level
SOIC
SPDIP
Figure 1 – Suggested Placement of the
Oscillator Circuit
QFN-S
1
26
27
1
H
R¯E¯¯S¯E¯T
L(1)
H(1)
L(1)
L(1)
2
ANALOG_IN
¯V¯P¯W¯_¯R¯X¯
PWM_RX
I¯S¯O¯_¯R¯X¯
4
Oscillator
5
2
Guard Ring
11
12
14
15
16
17
18
8
(2)
9
S¯L¯E¯E¯¯P
—
11
12
13
14
15
CAN_RX
CAN_TX
H
H(3)
UART_RX
UART_TX
PWR_CTRL
H
H(3)
L(4)
5.7 NVM Reset Input
¯R¯S¯T¯_¯N¯V¯M¯ pin must be pulled up to VDD via a
100 kΩ resistor for proper device operation.
¯O¯B¯D¯_¯T¯X¯_¯L¯E¯D¯
/ ¯R¯S¯T¯_¯N¯V¯M¯
H(3)
H(3)
21
22
18
19
5.8 Open Drain Outputs
¯O¯B¯D¯_¯R¯X¯_¯L¯E¯D¯ / ¯IN¯T¯
All open drain outputs (as specified in section 4.1)
that are in use must be pulled up to VDD or 5V.
Specifically, UART_TX pin must be pulled up in order
to be able to communicate with the device. See
section 4.2 “Detailed Pin Descriptions” for more
information.
Note 1. These inputs may be connected to either VDD or
VSS. However, the preferred level is shown.
2.
S¯L¯E¯E¯¯P input has internal pull-up to VDD enabled by
default. Therefore, it can be left unconnected.
3. These open drain outputs cannot be connected to
VDD directly. They can only be connected to VDD or
5V via a resistor.
5.9 Unused Inputs and Unused
Open Drain Outputs
None of the unused inputs or unused open drain
outputs (as specified in section 4.1) should be left
unconnected. The STN1110 is a CMOS integrated
4. This open drain output should not be connected to
VSS directly. For reduced current consumption
during sleep, when unused, this output should be
connected to VSS via a resistor.
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STN1110
6.0 Reference Schematics
6.1 Recommended Minimum Connection
Figure 2 shows the recommended minimum of components necessary to get the STN1110 to operate reliably,
while minimizing power consumption. It is not a practical circuit; it is intended as a reference to show what to do
with unused pins. Refer to the detailed pin descriptions (section 4.2) for more information.
Figure 2 – Recommended Minimum Connection
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STN1110DSB
STN1110
6.2 Typical Configuration
This section contains schematics showing the typical configuration for the various circuit blocks. Pay special
attention when choosing substitutes for components with specific part numbers, to make sure they have the same
or better characteristics. Components without specific part numbers are generic. Use good engineering practices
and common sense to make sure the specific parts you choose are appropriate for your application.
Figure 3 – STN1110 IC
Figure 4 – LEDs
STN1110DSB
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STN1110
Figure 5 – Voltage Sense
Figure 6 – Power Supplies
Figure 7 – Switched Power Control
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STN1110DSB
STN1110
Figure 8 – OBD Port Connector
Figure 9 – ISO Transceiver
Figure 10 – CAN Transceiver
STN1110DSB
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Important: Q4, Q5, and Q6 can only be substituted with transistors that have the same or better switching
characteristics. OK to substitute fast-switching silicon diodes (e.g., 1N4148) for D10, D12 and D13. Also, note that
the comparator IC4 is powered from DLC_SW.
Figure 11 – J1850 Transceiver
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7.0 Electrical Characteristics
This section provides an overview of STN1110 electrical characteristics. Additional information will be provided
in future revisions of this document as it becomes available.
The STN1110 is based on the PIC24HJ128GP502 device from Microchip Technology. For more detailed device
specifications or clarification, refer to Microchip documentation, available at http://www.microchip.com.
7.1 Absolute Maximum Ratings (1)
Ambient temperature under bias ................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +160°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +4.0V
(2)
Voltage on any pin that is not 5V tolerant with respect to VSS ......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(2) ......................................... -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(2) ........................................... -0.3V to 3.6V
Maximum current sourced/sunk by any 2x output(3) ....................................................................................... 8 mA
Maximum current sourced/sunk by any 4x output(3) ..................................................................................... 15 mA
Note 1. Stresses beyond those listed here can cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods can affect device reliability.
2. See section 4.0 “Pinout” for the list of 5V tolerant pins.
3. See section 4.1 “Pinout Summary” to determine current rating of individual pins.
7.2 Electrical Characteristics
Table 3: Thermal Operating Conditions
Sym
Characteristic
Min
Typ
Max
Units
Conditions
TJ Operating Junction Temperature
TA Operating Ambient Temperature
-40
-40
—
—
+125
+85
°C
°C
Table 4: Power Specifications
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
VDD Supply Voltage
3.0
—
—
—
3.6
V
V
VPOR VDD Start Voltage
VSS
to ensure internal power-on reset
(POR) signal
VDD Rise Rate(2)
to ensure internal power-on reset
(POR) signal
SvDD
0.03
—
—
—
—
V/ms 0–3.0V in 0.1s
AVDD Analog Supply Voltage
Greater of
VDD – 0.3
or 3.0
Lesser of
VDD + 0.3
or 3.6
V
V
AVSS Analog Ground Reference
VSS – 0.3
VSS + 0.3
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Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
Brown-out Reset Voltage(3)
VBOR
2.40
—
2.55
V
on VDD transition high-to-low
Operating Current(4)
Average Sleep Current(4,6)
68
98
300(5)
82(5)
210(5)
710(5)
—
IDD
IPD
—
—
mA
μA TA = +25°C
μA TA = +85°C
—
External Filter Capacitor(7)
CEFC
4.7
10
μF
ESR < 5 Ω
connected to VCAP pin
Note 1. Data in Typ column is at 3.3V, 25°C, unless otherwise stated.
2. This spec must be met in order to ensure that a correct internal power-on reset (POR) occurs. It is easily achieved using most
common types of supplies, but may be violated if a supply with slowly varying voltage is used, as may be obtained through direct
connection to solar cells or some charge pump circuits.
3. This parameter is for design guidance only and is not tested in manufacturing.
4. STN1110 device current only. Does not include any load currents.
5. Values are characterized, but not tested.
6. All wakeup triggers are on and wakeup trigger inputs are in their inactive states.
7. Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN.
Table 5: Input Pin DC Specifications
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL Input Low Voltage
MS_CAN_RX pin
VSS
VSS
—
—
0.3 VDD
0.2 VDD
V
V
all other inputs
VIH Input High Voltage
non-5V tolerant pins(2)
5V tolerant pins(2)
0.7 VDD
0.7 VDD
AVSS
—
—
—
—
—
VDD
5.5
V
V
V
Ω
VIN ANALOG_IN Input Voltage
AVDD
200
RIN Recommended ANALOG_IN
Voltage Source Impedance
IPU Internal Pull-up Current
50
0
250
—
400
-5(4,7)
μA
VDD = 3.3V, VPIN = VSS
IICL Input Low Injection Current
mA All pins, except VDD, VSS,
AVDD, AVSS, R¯E¯¯S¯E¯T,
VCAP, S¯L¯E¯E¯¯P, I¯S¯O¯_¯R¯X¯
and ¯IS¯O¯_¯K¯_¯T¯X¯
+5(5,6,7)
IICH Input High Injection Current
0
0
—
—
mA All pins, except VDD, VSS,
AVDD, AVSS, R¯E¯¯S¯E¯T,
VCAP, S¯L¯E¯E¯¯P, I¯S¯O¯_¯R¯X¯
, ¯IS¯O¯_¯K¯_¯T¯X¯, and 5V tolerant
designated pins
20(8)
ΣIICT Total Input Injection Current
mA Absolute instantaneous sum
of all ± input injection
sum of all I/O and control pins
currents from all I/O pins
(|IICL| + |IICH|) ≤ ΣIICT
Note 1. Data in Typ column is at 3.3V, 25°C, unless otherwise stated.
2. See section 4.0 “Pinout” for the list of 5V tolerant pins.
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3. Negative current is defined as current sourced by the pin.
4. VIL source < (VSS – 0.3). Characterized, but not tested.
5. Non-5V tolerant pins: VIH source > (VDD + 0.3), 5V tolerant pins: VIH source > 5.5V. Characterized, but not tested.
6. 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
7. Injection currents > 0 can affect the ADC results by approximately 4-6 counts.
8. Any number and/or combination of inputs listed under IICL or IICH conditions are permitted, provided the mathematical “absolute
instantaneous” sum of the input injection currents from all pins does not exceed the specified limit. Characterized, but not tested.
Table 6: Output Pin DC Specifications
Sym
Characteristic
Min
Typ
Max
Units
Conditions
Output Low Voltage(1)
2x Sink Driver Pins(2)
4x Sink Driver Pins(2)
Output High Voltage(1)
2x Source Driver Pins(2)
4x Source Driver Pins(2)
Output High Voltage(1)
2x Source Driver Pins(2)
VOL
—
—
—
—
0.4
0.4
V
V
IOL ≤ 3 mA, VDD = 3.3V
IOL ≤ 6 mA, VDD = 3.3V
VOH
2.4
2.4
—
—
—
—
V
V
IOH ≥ -3 mA, VDD = 3.3V
IOH ≥ -6 mA, VDD = 3.3V
VOH1
1.5
2.0
3.0
1.5
2.0
3.0
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
IOH ≥ -6 mA, VDD = 3.3V
IOH ≥ -5 mA, VDD = 3.3V
IOH ≥ -2 mA, VDD = 3.3V
IOH ≥ -12 mA, VDD = 3.3V
IOH ≥ -11 mA, VDD = 3.3V
IOH ≥ -3 mA, VDD = 3.3V
4x Source Driver Pins(2)
Note 1. Parameters are characterized, but not tested.
2. See section 4.1 “Pinout Summary” for the output driver current rating designations.
Table 7: I/O Pin Timing Requirements
Sym
Characteristic
Min
Typ
Max
Units
Conditions
TRST
2
—
—
μs
¯R¯E¯S¯E¯T¯ Pulse Width (low)
TUWM Minimum UART Rx Pulse Width
—
15
—
1
20
—
15
—
—
ns
μs
μs
user setting < 15
user setting ≥ 15
user setting = 0
required for wakeup (user settable)
65,534
—
TSTM
Minimum S¯L¯E¯E¯¯P Input Time
to stay high before wakeup (user
settable)
65,534
ms user setting > 0
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8.0 Packaging Diagrams and Parameters
8.1 SPDIP (SP) Package
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
N
NOTE 1
E1
1
2
3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
INCHES
NOM
28
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
—
Top to Seating Plane
A
—
.120
.015
.290
.240
1.345
.110
.008
.040
.014
—
.200
.150
—
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.135
—
.310
.285
1.365
.130
.010
.050
.018
—
.335
.295
1.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
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8.2 SOIC 300mil (SO) Package
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
D
N
E
E1
NOTE 1
1
2 3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
A
—
—
2.65
—
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
—
—
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
—
0.75
1.27
L
—
Footprint
L1
φ
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
0°
0.18
0.31
5°
—
—
—
—
—
8°
c
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
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8.3 SOIC 300mil (SO) Land Pattern
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Contact Pitch
E
C
1.27 BSC
9.40
Contact Pad Spacing
Contact Pad Width (x28)
Contact Pad Length (x28)
Distance Between Pads
Distance Between Pads
X
0.60
2.00
Y
Gx
G
0.67
7.40
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2052A
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8.4 QFN-S (MM) Package
28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S] with
0.40 mm Contact Length
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
D2
D
EXPOSED
PAD
e
E2
E
b
2
1
2
1
K
N
N
L
NOTE 1
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Number of Pins
N
e
28
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
6.00 BSC
3.70
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
3.65
4.70
6.00 BSC
3.70
D2
b
3.65
0.23
0.30
0.20
4.70
0.43
0.50
—
0.38
L
0.40
K
—
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-124B
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8.5 QFN-S (MM) Land Pattern
28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S] with
0.40 mm Contact Length
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Contact Pitch
E
W2
T2
C1
C2
X1
Y1
G
0.65 BSC
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (x28)
Contact Pad Length (x28)
Distance Between Pads
4.70
4.70
6.00
6.00
0.40
0.85
0.25
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2124
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9.0 Ordering Information
TA
Package
SPDIP (SP)
Part Number
STN1110-I/SP
STN1110-I/SO
STN1110-I/MM
SKU
Tube
Tube
Tube
365101
365111
365121
-40°C to +85°C
SOIC (SO)
QFN-S (MM)
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Appendix A: Revision History
Revision A (October 22, 2010)
Initial release of this document.
Revision B (July 13, 2012)
Revised the “Overview”, “Feature Highlights”, and “Typical Applications” sections. Added current capability
ratings to the “Pinout Summary” table and relevant pin descriptions. Changed recommended connections for
unused pins. Deleted last sentence of NVM Reset Input description (RST_NVM needs a pullup whether an LED is
connected or not). Added “Recommended ANALOG_IN Voltage Source Impedance” (RIN) specification to “Input
Pin Specifications” table. Updated schematics, and added short descriptions to the “Recommended Minimum
Connection” and “Typical Configuration” sections. Minor typographical and formatting changes.
Appendix B: Contact Information
OBD Solutions
1819 W Rose Garden Ln Ste 3
Phoenix, AZ 85027
United States
Phone: +1 623.434.5506
Fax:
+1 623.321.1628
Email: sales@obdsol.com
Web:
www.obdsol.com
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相关型号：
STN1810
STN1810 is the N-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology.
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