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STP2001QFP [ETC]

I/O Controller ; I / O控制器\n
STP2001QFP
型号： STP2001QFP
厂家： ETC    ETC
描述：

I/O Controller
I / O控制器\n

控制器 时钟
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STP2001.frm Page 1 Monday, August 25, 1997 2:46 PM  
STP2001QFP  
July 1997  
Slave I/O  
Integrated SBus Interface Slave I/O Controller  
DATA SHEET  
DESCRIPTION  
The STP2001Slave I/O Controller is a highly integrated, low-cost, low-power device designed for use in single-processor  
systems with an SBus interface. The STP2001 provides serial I/O for keyboard, mouse and general-purpose use. In addi-  
tion, a floppy disk interface, an external byte-wide expansion bus (EBus) for TOD and EPROM, I/O registers and reset  
control logic are integrated. Together, the STP2001 and the STP2000 Master I/O Controller, provide a complete I/O  
subsystem.  
The two serial ports for keyboard/mouse and general purpose use are compatible with the AMD AM85C30, rev C Serial  
Communications Controller. The TTY A/B serial ports are fully synchronous, while the keyboard/mouse ports are asyn-  
chronous only. All ports support data rates up to 38.4 Kb/s. The NCR82077 floppy disk interface is compatible with the  
Intel 8077A-1 single-chip floppy controller, supporting up to a 1 MBit/sec transfer rate.  
Features  
Benefits  
• Integrates two dual serial controllers, a high-speed  
floppy controller, uniprocessor interrupt, reset, and  
counter/timer circuitry, power-down control and an  
EBus in a single package  
• Saves cost, power, board space, and weight  
• Directly interfaces to CPU through the SBus  
• Improved performance  
• Auxiliary I/O registers (used for LED, floppy and  
system power-down)  
• High level of system integration; ease of design  
• Interrupt Controller for single-processor SBus  
system  
• High level of system integration; ease of design  
• System reset control  
• High level of system integration; ease of design  
• High level of system integration; ease of design  
• Generic 8-bit interface available  
• Improved chip and board level testability  
• Cost effective packaging  
• Counter/timers for single-processor SBus system  
• EBus interface  
• JTAG internal and boundary SCAN logic  
• 160-pin PQFP packaging  
• IC is also available from NCR Corp. (PN -  
NCR89105)  
• Second source  
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This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 2 Monday, August 25, 1997 2:46 PM  
Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
BLOCK, APPLICATION, AND LOGIC DIAGRAMS  
SBus  
SBus Slave Interface  
System Reset  
Misc. I/O Pins  
8-Bit Bus Interface  
Reset/  
Misc  
Keyboard/Mouse  
Controller  
(NCR85C30A)  
Serial Controller  
(NCR85C30)  
Floppy Controller  
(NCR82077)  
Interrupt  
Controller  
Counter/  
Timers  
Interrupt  
Priority Level  
Interrupt Sources  
EPROM  
NVRAM Generic  
RS232 Serial  
Transceivers  
Keyboard/Mouse  
Floppy Disk Drive  
Figure 1. STP2001 Block Diagram  
SCSI Connector  
160-Pin I/O Connector  
SCSI  
Ethernet Parallel  
Video  
Floppy Key/Mouse Audio  
Serial  
2
1
0
DRAM Banks  
RAMDAC  
VRAM  
Bank 0  
STP2000  
Master I/O  
MicroSPARC CPU  
Frame Buffer  
SBUS  
Slot 1  
Slot 0  
STP2001  
Slave I/O  
SBus Connectors  
Floppy Connector  
Internal EBus  
TOD/NVRA  
Boot PROM  
Figure 2. STP2001 Typical Application  
2
July 1997  
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STP2001.frm Page 3 Monday, August 25, 1997 2:46 PM  
Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
32  
8
SB_D[31:0]  
SB_SEL  
EBD[7:0]  
EB_WR  
EB_RD  
CHIP_SEL  
SB_PA[V]  
SB_PA[W]  
SB_PA[X]  
SB_PA[Y]  
SB_PA[Z]  
SB_PA[16]  
SB_PA[4:0]  
SB_SIZ[2:0]  
SB_RD  
EBUS_LATCH  
EBus Interface  
GENERIC_RDY  
GENERIC_CS  
TOD_CS  
SBus Signals  
EPROM_CS  
5
3
FPY_DENSEL  
FPY_INDEX  
FPY_MOTEN  
FPY_DRVSEL  
FPY_DIR  
SB_AS  
3
SB_ACK[2:0]  
SB_CLK  
FPY_STEP  
FPY_WRDAT  
7
4
SB_IRQ[7:1]  
M0_IRL[3:0]  
ENET_IRQ  
SCSI_IRQ  
PFD  
FPY_WRGATE  
(FDTRK0)  
Floppy Interface  
FPY_WRPROT  
FPY_RDDATA  
(FDHDSEL) FPY_HEADSEL  
(FDDENSEN)  
FPY_EJECT  
Interrupt Signals  
MSI_IRQ  
MODERR_IRQ  
FPY_DISKCHG  
FPY_CLK32  
POWER_OFF  
MON_MSE_MUX  
LINK_TEST_EN  
CLK10_MHZ  
SYS_LED  
FPY_CLK24  
Miscellaneous  
System Signals  
SER_TXD_A  
SER_RXD_A  
SER_TRXC_A  
SER_RTXC_A  
SER_SYNC_A  
SER_DTR_A  
SER_RTS_A  
SER_CTS_A  
SER_DCD_A  
SER_TXD_B  
SER_RXD_B  
SER_TRXC_B  
SER_RTXC_B  
SER_SYNC_B  
SER_DTR_B  
SER_RTS_B  
SER_CTS_B  
SER_DCD_B  
SER_CLK  
IU_ERROR  
POR_RST_IN  
Reset Signals  
JTAG Signals  
SYS_RST_OUT  
MMC_RST_OUT  
JTAG_TDIN  
JTAG_TMS (JTAG_MODEL)  
JTAG_CLK  
Serial Interface  
JTAG_RESET  
JTAG_TDOUT  
KBD_DIN  
Keyboard/Mouse  
Interface  
KBD_DOUT  
MSE_DIN (MOUSEDIN)  
MSE_OUT  
Figure 3. STP2001 Logical Connections  
July 1997  
3
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Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
SIGNAL DESCRIPTIONS  
SBus Interface: 54 Pins  
Signal  
SB_D[31:0]  
SB_ACK[2:0]  
SB_CLK  
Type  
Description  
I/O  
SBus Data Bus  
3-State SBus Acknowledge  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
SBus Clock Input  
SBus Read/Write  
SBus Select  
SB_RD  
SB_SEL  
SB_SIZ[2:0]  
SB_AS  
SBus Transfer Size  
SBus Address Strobe (address is valid)  
[1]  
CHIP_SEL  
High order physical address bits (for slave decodes)  
High order physical address bits (for slave decodes)  
PA[16] (for system/user selection in INT/TMR)  
Low order physical address bits  
[2]  
SB_PA[V:Z]  
SB_PA[16]  
SB_PA[4:0]  
1. The CHIP_SEL pin is an additional qualifier (active low) to the SB_SEL line. When sharing a single SBus select line with another  
device (such as the STP2000QFP), one of the high order SBus physical address lines, such as PA[27], can be tied to the CHIP_SEL  
pin to distinguish between the two devices.  
2. In some system configurations, the high order physical address bits can be connected as follows: SB_A[V, W, X, Y, Z]=PA[24:20].  
EBus Interface: 15 pins  
Signal  
EB_D[7:0]  
Type  
Description  
I/O  
EBus data  
EB_ADDRLATCH  
EB_RD  
Output EBus address latch  
Output EBus read  
EB_WR  
Output Ebus write  
TOD_CS  
Output TOD chip select  
Output EPROM chip select  
Output Generic port chip select  
EPROM_CS  
GENERIC_CS  
GENERIC_RDY  
Input  
Generic port ready (25 mA pull-up)  
4
July 1997  
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Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
Floppy Interface: 17 pins  
Signal  
FPY_CLK32  
Type  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Description  
32 MHz clock for floppy DDS  
FPY_CLK24  
24 MHz clock for floppy ASF  
Density sense input (auxio1 register bit)  
Disk change  
FPY_DENSENSE  
FPY_DISKCHG  
FPY_WRPROT  
FPY_TRACK0  
FPY_RDDATA  
FPY_INDEX  
Write protect  
Track 0 indicator  
Read data  
Track index  
FPY_EJECT  
FPY_HEADSEL  
FPY_STEP  
Output Floppy eject (ME[3] of 82077 ASF)  
Output Head select  
Output Drive step pulse  
FPY_DIR  
Output Head step direction  
FPY_WRDATA  
FPY_WRGATE  
FPY_DRVSEL  
FPY_MOTEN  
FPY_DENSEL  
Output Write data  
Output Write enable  
Output Floppy drive select (DS[0] of 82077 ASF)  
Output Floppy motor enable (ME[0] of 82077 ASF)  
Output Density select (ME[2] or DENSEL of 82077 ASF)  
Keyboard/Mouse Interface: 4 pins  
Signal  
KBD_DIN  
Type  
Description  
Input  
Keyboard data in  
KBD_DOUT  
MSE_DIN  
Output Keyboard data out  
Input Mouse data in  
Output Mouse data out  
MSE_OUT  
Reset Signals: 3 pins  
Signal  
Type  
Description  
POR_RST_IN  
SYS_RST_OUT  
MMC_RST_OUT  
Input  
Power-up reset input  
Output System (SBus) reset output  
Output MMC reset output  
July 1997  
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Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
Serial Interface: 19 pins  
Signal  
SER_CLK  
Type  
Input  
Input  
Input  
Input  
Input  
Description  
19.66 MHz serial clock  
Receive/transmit clock A  
Clear to send A  
SER_RTXC_A  
SER_CTS_A  
SER_RXD_A  
SER_DCD_A  
SER_DTR_A  
SER_TXD_A  
SER_RTS_A  
SER_SYNC_A  
SER_TRXC_A  
SER_RTXC_B  
SER_CTS_B  
SER_RXD_B  
SER_DCD_B  
SER_DTR_B  
SER_TXD_B  
SER_RTS_B  
SER_SYNC_B  
SER_TRXC_B  
Receive data A  
Data carrier detect A  
Output Data terminal ready A  
Output Transmit data A  
Output Request to send A  
I/O  
Sync IO, A  
I/O  
Transmit clock A  
Receive/transmit clock B  
Clear to send B  
Input  
Input  
Input  
Input  
Receive data B  
Data carrier detect B  
Output Data terminal ready B  
Output Transmit data B  
Output Request to send B  
I/O  
I/O  
Sync IO, B  
Transmit clock B  
Interrupt Signals: 16 pins  
Signal  
MO_IRL[3:0]  
SB_IRQ[7:1]  
ENET_IRQ  
SCSI_IRQ  
PFD  
Type  
Description  
Output Module 0 encoded interrupt level  
Input  
Input  
Input  
Input  
Input  
Input  
SBus interrupt requests  
Ethernet interrupt request  
SCSI interrupt request  
Power fail detect (level 15 interrupt)  
MSI interrupt  
MSI_IRQ  
MODERR_IRQ  
Processor level 15 interrupt (async error)  
6
July 1997  
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Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
Miscellaneous System Signals: 6 pins  
Signal  
CLK_10MHZ  
MON_MSE_MUX  
POWER_OFF  
LINK_TEST_EN  
SYS_LED  
Type  
Description  
Input  
10 MHz clock for counter/ timer block  
Output Monitor/mouse mux select  
Output Power off output (to power supply)  
Output T7213 link test enable  
Output System LED output  
IU_ERROR  
Input  
Processor watchdog reset/Video interrupt  
JTAG Signals: 5 pins  
Signal  
JTAG_TDO  
JTAG_TDI  
Type  
Output JTAG test data output  
Description  
Input  
Input  
Input  
Input  
JTAG test data input (100 mA pull-up)  
JTAG clock  
JTAG_CLK  
JTAG_TMS  
JTAG_RST  
JTAG test mode select (100 mA pull-up)  
JTAG reset (100 mA pull-up)  
July 1997  
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Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings [1]  
Symbol  
Parameter  
Rating  
Units  
V
V
V
Power supply voltage  
Input voltage  
7.0  
CC  
0 £ V £ V  
V
IN  
IN  
CC  
I
Current Drain V and GND  
CC  
100  
250  
mA  
°C  
I
T
T
T
Lead temperature (less than 10 second soldering)  
Operating temperature  
L
J
0 to +70  
°C  
Storage temperature  
-55 to +150  
560  
°C  
S
P
Power dissipation  
mW  
D
1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages  
are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under  
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect  
device reliability.  
Recommended Operating Conditions  
Symbol  
Parameter  
Min  
4.75  
0
Typ  
5.0  
25  
Max  
5.25  
70  
Units  
V
V
Supply voltage  
CC  
T
Operating Temperature  
Power dissipation  
°C  
A
P
–
280  
560  
mW  
D
Capacitance  
Symbol  
Parameter  
Typ  
6
Max  
Units  
pF  
C
C
C
Input capacitance  
–
–
–
IN  
Output capacitance  
6
pF  
OUT  
BI  
Bidirectional pin capacitance  
6
pF  
8
July 1997  
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STP2001.frm Page 9 Monday, August 25, 1997 2:46 PM  
Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
DC Characteristics  
Symbol  
Parameter  
Min  
2.0  
–
Typ  
–
Max  
–
Units  
V
V
V
V
V
Input high voltage  
Input Low voltage  
IH  
–
0.8  
–
V
IL  
High level output voltage  
Low level output voltage  
Input leakage current  
4.4  
–
4.5  
0
V
OH  
OL  
0.1  
10  
–
V
I
-10  
2
–
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IN  
OH  
I
High level source  
I
I
I
I
I
I
I
I
I
I
I
= 2.0 mA  
= 4.0 mA  
–
OH  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
OL  
current (V = 2.4 V)  
OH  
4
–
–
= 8.0 mA  
8
–
–
= 16.0 mA  
= 24.0 mA  
= -2.0 mA  
= -4.0 mA  
= -8.0 mA  
= -16.0 mA  
= -24.0 mA  
= -48.0 mA  
16  
24  
2
–
–
–
–
I
Low level sink  
–
–
OL  
current (V = 0.4 V)  
OL  
4
–
–
8
–
–
16  
24  
48  
48  
48  
-10  
–
–
–
–
–
–
SCSIPAD (V = 0.5 V)  
–
–
OL  
SCSIPADF (V = 0.5 V)  
–
–
OL  
I
Hi-Z output leakage current  
–
10  
OZ  
July 1997  
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Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
AC Characteristics: SBus Timing  
Signal #  
Parameter  
SBus clock frequency  
Conditions  
Min  
16.7  
40.0  
17.0  
17.0  
0.0  
15.0  
15.0  
–
Max  
25.0  
60.0  
–
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
f
SB  
1
Clock period  
2
3
4
5
6
7
8
9
Clock high  
Clock low  
–
Hold WRT CLK rising  
Setup to CLK rising  
Setup to CLK rising  
Hold WRT CLK rising  
–
–
–
[1]  
1.0  
22.5  
22.5  
22.5  
25.0  
22.5  
22.5  
CLK rising to output valid  
CLK rising to output invalid  
CLK rising to output valid  
CLK rising to output invalid  
CLK rising to output low  
CLK rising to output high  
100 pF load  
100 pF load  
100 pF load  
100 pF load  
100 pF load  
100 pF load  
–
–
10  
11  
12  
13  
–
2.5  
–
–
1. This is the only violation of SBus Specification B.0. No known implementation to date provides less than 1.0 ns hold time on these  
signals.  
AC Characteristics: EBus Timing  
Signal #  
Parameter  
Setup to CLK rising  
Conditions  
Min  
15.0  
–
Max  
–
Units  
ns  
14  
15  
16  
17  
18  
Hold WRT CLK rising  
2.0  
ns  
CLK rising to output valid  
CLK rising to output invalid  
CLK rising to output valid  
100 pF load  
100 pF load  
100 pF load  
–
22.5  
22.5  
22.5  
ns  
–
ns  
–
ns  
AC Characteristics: Miscellaneous Timing  
Signal #  
19  
Parameter  
Conditions  
Min  
–
Max  
22.5  
–
Units  
ns  
CLK rising to output valid  
100 pF load  
[1]  
20  
10 MHz clock period  
50  
ns  
1. This clock must be run at 10 MHz (100 ns period) for correct software operation.  
10  
July 1997  
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Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
AC Characteristics: Floppy Controller Timing  
Signal #  
21  
Parameter  
Conditions  
Min  
31.3  
16.7  
16.7  
41.7  
62.5  
1.0  
Max  
31.3  
25  
25  
41.7  
250  
–
Units  
ns  
[1]  
FPY_CLK32 clock period  
22  
FPY_CLK24 clock high time  
FPY_CLK24 clock low time  
ns  
23  
ns  
[1]  
24  
FPY_CLK24 clock period  
ns  
[2]  
25  
Internal clock period (t  
)
ns  
CI  
26  
FPY_DIR change to FPY_STEP setup time  
FPY_STEP pulse width  
ms  
27  
7
8
ms  
[3]  
28  
FPY_STEP rate  
1
15  
–
ms  
29  
FPY_INDEX pulse width  
FPY_RDDATA pulse width  
4
t
CI  
30  
50  
–
ns  
bit/s  
ns  
[4]  
31  
FPY_RDDATA data rate  
250 K  
250  
1 M  
–
32  
FPY_WRGATE to FPY_WRDATA setup  
time  
[5]  
33  
FPY_WRDATA pulse width  
125  
500  
ns  
1. The NCR82077 core uses a digital data separator to read the data off of the disk. Any variation from the nominal input clock frequencies  
will shift the capture range of the cell.  
2. NOTE 4: Internal clock period is a function of the selected data rate.  
Data Rate  
1 Mbs  
Frequency  
16 MHz  
8 MHz  
Period  
62.5 ns  
125 ns  
208 ns  
250 ns  
500 Kbs  
300 Kbs  
250 Kbs  
4.8 MHz  
4 MHz  
3. FPY_STEP Rate time is selected by a SPECIFY command. Failure to issue a specify command before issuing a Recalibrate or Seek  
command or implied seek will cause unpredictable results.  
4. FPY_RDDATA data rate is determined by the floppy tape drive or tape drive. The values are:  
• 1 Mbs – 1.0 ms minimum  
• 500 Kbs – 2.0 ms minimum  
• 300 Kbs – 3.3 ms minimum  
• 250 Kbs – 4.0 ms minimum  
5. FPY_WRDATA pulse width is based on the selected data rate. The values are 2 x tCI  
:
• 1 Mbs - 2 x 62.5 = 125 ns  
• 500 Kbs - 2 x 125 = 250 ns  
• 300 Kbs - 2 x 208 = 416 ns  
• 250 Kbs - 2 x 250 = 500 ns  
July 1997  
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Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
AC Characteristics: Serial/Keyboard/Mouse Controllers Timing  
Signal #  
34  
Parameter  
Conditions  
Min  
50  
50  
122  
150  
4
Max  
–
Units  
ns  
[1]  
SER_CLK low width  
35  
SER_CLK high width  
SER_CLK cycle time (t  
SER_RTXC width  
–
ns  
36  
)
–
ns  
PC  
37  
–
ns  
38  
SER_RTXC cycle time  
SER_TRXC width  
–
t
PC  
39  
150  
4
–
ns  
40  
SER_TRXC cycle time  
–
t
PC  
41  
SER_DCD or SER_CTS width  
SER_SYNC width  
200  
200  
0
–
ns  
42  
–
ns  
ns  
ns  
ns  
43  
SER_RXD to SER_RTXC setup time  
SER_RXD to SER_RTXC hold time  
SER_SYNC to SER_RTXC setup time  
SER_SYNC to SER_RTXC hold time  
SER_TRXC to SER_TXD delay  
SER_TXD to SER_TRXC delay  
–
44  
150  
-200  
5
–
45  
–
46  
–
t
PC  
47  
–
200  
200  
ns  
48  
–
ns  
1. The input SER_CLK is used to clock the serial controllers and the keyboard/mouse controller. The timing numbers in this section  
apply to both of these controllers.  
12  
July 1997  
This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 13 Monday, August 25, 1997 2:46 PM  
Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
TIMING DIAGRAMS  
1
2
3
SB_CLK  
5
6
4
5
SB_AS, SB_SEL  
SB_RD  
7
SB_PA[X, Y, 3, 2, 1]  
SB_SIZE[2:0]  
SB_ACK[2:0]  
SB_D[31:0]  
14  
15  
EB_D[7:0]  
GENERIC_RDY  
Figure 4. SBus/EBus Input Timing  
1
2
3
SB_CLK  
SB_ACK[2:0]  
SB_D[31:0]  
SYS_RST_OUT  
EB_D[7:0]  
8
9
10  
11  
13  
17  
12  
16  
1
IRL[3:0]  
EB_ADDRLATCH  
EPROM_CS  
1
GENERIC_CS  
TOD_CS, EB_RD  
EB_WR  
Figure 5. SBus/EBus Output Timing  
July 1997  
13  
This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 14 Monday, August 25, 1997 2:46 PM  
Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
20  
2
3
CLK_10MHZ  
Figure 6. Counter/Timer Input Clock  
21  
FPY_CLK32  
FPY_CLK24  
22  
23  
24  
Figure 7. Floppy Controller Clock Inputs  
FPY_DIR  
FPY_STEP  
FPY_INDEX  
26  
28  
27  
29  
Figure 8. Floppy Drive Interface Timing  
31  
30  
FPY_RDDATA  
Figure 9. Floppy Read Data  
FPY_WRGATE  
FPY_WRDATA  
32  
33  
Figure 10. Floppy Write Data  
14  
July 1997  
This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 15 Monday, August 25, 1997 2:46 PM  
Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
36  
35  
34  
SER_CLK  
Figure 11. Serial/Keyboard/Mouse Clock Input  
38  
37  
39  
41  
42  
37  
39  
41  
42  
SER_RTXC  
SER_TRXC  
SER_CTS,  
SER_RTXC  
40  
Figure 12. Serial Pulse Widths  
SER_RFXC,  
SER_RXD  
SER_SYNC  
SER_TRXC,  
SER_TXD  
FM Mode Only  
44  
43  
43  
44  
45  
46  
FM Mode Only  
47  
47  
48  
SER_TRXC  
Figure 13. Serial Data Timing  
July 1997  
15  
This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 16 Monday, August 25, 1997 2:46 PM  
Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
PACKAGE INFORMATION  
160-Pin PQFP Pin Assignment  
Pin  
1
Signal Name  
ENET_IRQ  
Pin  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
Signal Name  
SB_PA[y]  
Pin  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
Signal Name  
SB_D[19]  
Pin  
97  
Signal Name  
SER_DTR_B  
Pin  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
Signal Name  
TOD_CS  
2
SCSI_IRQ  
FPY_DENSENSE  
FPY_DISKCHG  
FPY_WRPROT  
FPY_TRACK0  
FPY_RDDATA  
FPY_INDEX  
FPY_CLK24  
GND  
SB_PA[x]  
SB_PA[w]  
SB_PA[v]  
GND  
SB_D[20]  
SB_D[21]  
VCC  
98  
SER_SYNC_B  
KBD_DOUT  
MSE_OUT  
EB_RD  
3
99  
EB_WR  
4
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
EB_D[0]  
5
SB_D[22]  
SB_D[23]  
SB_D[24]  
SB_D[25]  
SB_D[26]  
SB_D[27]  
GND  
POWER_OFF  
JTAG_TDO  
VCC  
GND  
6
CHIP_SEL  
SB_RD  
EB_D[1]  
7
EB_D[2]  
8
SB_AS  
SER_CLK  
EB_D[3]  
9
SB_SEL  
SB_D[0]  
SB_D[1]  
SB_D[2]  
SB_D[3]  
GND  
SER_RTXC_B  
SER_CTS_B  
GND  
EB_D[4]  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
EB_D[5]  
FPY_EJECT  
FPY_HEADSEL  
FPY_STEP  
FPY_DIR  
EB_D[6]  
SB_D[28]  
SB_D[29]  
SB_D[30]  
SB_D[31]  
SB_SIZ[2]  
SB_SIZ[1]  
SB_SIZ[0]  
GND  
SER_RXD_B  
SER_DCD_B  
SER_RTXC_A  
SER_CTS_A  
VCC  
VCC  
EB_D[7]  
EB_ADDRLATCH  
SYS_RST_OUT  
MMC_RST_OUT  
M0_IRL[0]  
M0_IRL[1]  
GND  
GND  
SB_D[4]  
SB_D[5]  
SB_D[6]  
SB_D[7]  
SB_D[8]  
SB_D[9]  
VCC  
FPY_WRDATA  
FPY_WRGATE  
FPY_DRVSEL  
VCC  
SER_RXD_A  
SER_DCD_A  
LINK_TEST_EN  
MSE_DIN  
FPY_MOTEN  
FPY_DENSEL  
VCC  
SB_ACK[2]  
SB_ACK[1]  
SB_ACK[0]  
SER_DTR_A  
SER_TXD_A  
GND  
M0_IRL[2]  
M0_IRL[3]  
CLK_10MHZ  
SB_IRQ[1]  
SB_IRQ[2]  
SB_IRQ[3]  
SB_IRQ[4]  
SB_IRQ[5]  
SB_IRQ[6]  
SB_IRQ[7]  
PFD  
KBD_DIN  
SB_D[10]  
SB_D[11]  
SB_D[12]  
SB_D[13]  
SB_D[14]  
SB_D[15]  
GND  
MON_MSE_MUX  
JTAG_TDI  
FPY_CLK32  
SB_PA[0]  
JTAG_CLK  
JTAG_TMS  
JTAG_RST  
GENERIC_RDY  
IU_ERROR  
POR_RST_IN  
GENERIC_CS  
SYS_LED  
SB_PA[1]  
SB_PA[2]  
SER_RTS_A  
SER_SYNC_A  
SER_TRXC_A  
SER_TXD_B  
SER_TRXC_B  
VCC  
GND  
SB_PA[3]  
SB_PA[4]  
SB_CLK  
SB_D[16]  
SB_D[17]  
SB_D[18]  
SB_PA[16]  
SB_PA[z]  
MODERR_IRQ  
MSI_IRQ  
VCC  
SER_RTS_B  
EPROM_CS  
16  
July 1997  
This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 17 Monday, August 25, 1997 2:46 PM  
Slave I/O  
Integrated SBus Interface Slave I/O Controller  
STP2001QFP  
160-Pin PQFP Package Dimensions  
July 1997  
17  
This Material Copyrighted by Its Respective Manufacturer  
STP2001.frm Page 18 Monday, August 25, 1997 2:46 PM  
Slave I/O  
STP2001QFP  
Integrated SBus Interface Slave I/O Controller  
ORDERING INFORMATION  
Part Number  
Description  
STP2001QFP  
160-Pin Plastic Leaded Chip Carrier (PQFP)  
Document Part Number: STP2001  
18  
July 1997  
This Material Copyrighted by Its Respective Manufacturer  

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