STV102 [ETC]
; - 12号的铝制车身绘（ RAL 7032 ）
ETC 
www.smartasic.com
STV102 - TV Video Processor Data Sheet
December 2000
OFFICES:
SmartASIC Inc.
SmartASIC Technology, Inc.
525 Race Street, Suite 250, San Jose,
3F, No. 68, Chou-Tze St., Nei Hu District,
CA 95126, USA
Taipei 114, Taiwan, R.O.C.
Tel: (408) 283-5098; Fax: (408) 283-5099
Email: info@smartasic.com
Tel: 886-2-8797-7889; Fax: 886-2-87976829
Email: info_tw@smartasic.com
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COPYRIGHT NOTICE
Copyright © 2000, SmartASIC, Inc.
ALL RIGHTS RESERVED. Printed in Taiwan.
No part or whole of this document may be reproduced, transmitted, stored in a retrieval system, translated into any language,
or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording without prior
written consent of SmartASIC, Inc.
SmartASIC, Inc. reserves the right to change or modify the information contained herein without notice. It is the customer’s
responsibility to ensure that he/she has the most recent version of this document. The information contained in this document
has been carefully checked and is believed to be accurate. However, SmartASIC, Inc. makes no warranty for the use of this
information and bears no responsibility for any errors or omissions, which may appear in this document.
SmartASIC, Inc. subjects its products to quality control sampling techniques which are intended to assure high quality products
suitable for general commercial applications. SmartASIC does not do testing appropriate to provide 100% product quality
assurance and does not assume any liability for consequential or incidental events arising from any misuse of its products. If
such products are to be used in applications in which personal injury might occur from failure, customer must do its own
quality assurance testing appropriate to such applications.
All product names or trademarks are properties of their respective owners.
REVISION HISTORY
Document
Revisions
Date
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TABLE OF CONTENTS
OVERVIEW............................................................................................................................................................... 1
FEATURES................................................................................................................................................................ 1
PROPRIETARY DE-INTERLACING ENGINE ..................................................................................................................................1
VIDEO INPUT .............................................................................................................................................................................1
PROPRIETARY SCALING ENGINE................................................................................................................................................1
COLOR PROCESSING..................................................................................................................................................................2
NOISE REDUCTION ....................................................................................................................................................................2
ADVANCED VIDEO ENHANCEMENT PROCESSOR .......................................................................................................................2
INTERNAL OSD.........................................................................................................................................................................2
OUTPUT CONTROL ....................................................................................................................................................................2
MISCELLANEOUS.......................................................................................................................................................................2
STV102 FUNCTIONAL BLOCK DIAGRAM........................................................................................................ 3
FUNCTIONAL DESCRIPTION.............................................................................................................................. 3
CHANNEL INPUTS ......................................................................................................................................................................4
PICTURE IN PICTURE / PICTURE SCAN .......................................................................................................................................4
SDRAM CONTROLLER .............................................................................................................................................................4
DE-INTERLACING ......................................................................................................................................................................4
NOISE REDUCTION ....................................................................................................................................................................5
DYNAMIC PEAKING FILTER / BLACK LEVEL EXPANDER ...........................................................................................................5
COLOR TRANSIENT IMPROVEMENT ...........................................................................................................................................5
POST PROCESSING .....................................................................................................................................................................5
OUTPUT FORMATTING...............................................................................................................................................................5
STV102A PIN DESCRIPTIONS.............................................................................................................................. 6
STV102DP PIN DESCRIPTIONS.......................................................................................................................... 12
PACKAGE DIMENSIONS..................................................................................................................................... 19
CPU INTERFACE................................................................................................................................................... 20
CONTROL AND STATUS REGISTERS ............................................................................................................. 22
EEPROM CONTROL REGISTER: (CPU READ ONLY) ...............................................................................................................22
INPUT FORMAT CONVERSION REGISTERS, MAIN PICTURE:.....................................................................................................22
INPUT FORMAT CONVERSION REGISTERS, PIP PICTURE: ........................................................................................................23
PICTURE-IN-PICTURE (PIP) CONTROL REGISTERS...................................................................................................................24
DE-INTERLACE CONTROL REGISTERS......................................................................................................................................25
ADAPTIVE FILTER CONTROL REGISTERS.................................................................................................................................26
LUMA AND COLOR TRANSIENT IMPROVEMENT (LCTI) REGISTERS ........................................................................................26
DYNAMIC PEAKING FILTER REGISTERS ...................................................................................................................................27
BLACK LEVEL EXPANSION REGISTERS....................................................................................................................................27
GAMMA CORRECTION REGISTERS...........................................................................................................................................27
GENERAL FILTER CONTROL REGISTERS..................................................................................................................................28
RGB GAMMA CONTROL REGISTERS .......................................................................................................................................28
POINT FILTER CONTROL REGISTERS........................................................................................................................................28
OUTPUT CONTROL REGISTERS ................................................................................................................................................29
TIMING GENERATION REGISTERS............................................................................................................................................30
RAM CONTROL REGISTERS ....................................................................................................................................................31
SCALING CONTROL REGISTERS ...............................................................................................................................................31
OUTPUT COLOR CONTROL REGISTERS ....................................................................................................................................31
DAC AND PLL CONTROL REGISTERS .....................................................................................................................................32
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PAD CONTROL REGISTERS .....................................................................................................................................................32
START REGISTER (CPU READ/WRITE).....................................................................................................................................33
DEFINITION OF THE SUB-ADDRESSED REGISTERS ................................................................................. 33
RGB GAMMA CONTROL REGISTERS .......................................................................................................................................33
OSD CONTROL REGISTERS .....................................................................................................................................................35
ELECTRICAL SPECIFICATIONS...................................................................................................................... 37
ABSOLUTE MAXIMUM RATINGS..............................................................................................................................................37
RECOMMENDED OPERATING CONDITIONS ..............................................................................................................................37
GENERAL DC CHARACTERISTICS............................................................................................................................................37
DC ELECTRICAL CHARACTERISTICS FOR 3.3 V OPERATION ...................................................................................................38
DC ELECTRICAL CHARACTERISTICS FOR 5V OPERATION .......................................................................................................38
ORDER INFORMATION ...................................................................................................................................... 38
LIST OF FIGURES
FIGURE 1. STV102 FUNCTIONAL BLOCK DIAGRAM ................................................................................. 3
FIGURE 2: STV102A PACKAGE DIAGRAM..................................................................................................... 6
FIGURE 3: STV102DP PACKAGE DIAGRAM................................................................................................. 12
FIGURE 4: STV102 PACKAGE DIMENSIONS ................................................................................................. 19
FIGURE 5: START, STOP AND DATA DEFINITIONS IN THE 2-WIRE SERIAL INTERFACE............. 20
FIGURE 6: DATA SEQUENCE FOR READ ACCESS (BOTH SINGLE AND MULTIPLE BYTES)......... 21
FIGURE 7: DATA SEQUENCE FOR WRITE ACCESS (BOTH SINGLE AND MULTIPLE BYTES) ...... 21
LIST OF TABLES
TABLE 1: STV102A PIN DESCRIPTIONS (SORTED BY FUNCTION) .......................................................... 7
TABLE 2: STV102A PIN LIST (ALPHABETICAL ORDER)........................................................................... 10
TABLE 3: STV102A PIN LIST (NUMERICAL ORDER).................................................................................. 11
TABLE 4: STV102DP PIN DESCRIPTIONS (SORTED BY FUNCTION)...................................................... 13
TABLE 5: STV102DP PIN LIST (ALPHABETICAL ORDER)......................................................................... 17
TABLE 6: STV102DP PIN LIST (NUMERICAL ORDER) ............................................................................... 18
TABLE 7: STV102 PACKAGE MEASUREMENTS........................................................................................... 19
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OVERVIEW
Consumers often have to decide whether to choose today’s traditional analog TVs or tomorrow’s High Definition TVs (HDTV).
Now new products that bridge these two choices are available — progressive scan TVs, LCD TVs and Projection TVs. These
new products display traditional analog broadcast signals with resolution that is twice or more beyond the resolution of today’s
standard televisions. SmartASIC’s video processor powers these new digital display products.
SmartASIC has developed STV102, its second generation video processing technology and third generation scaling technology.
This video processor handles various formats of traditional TV video, such as NTSC, PAL and SECAM, and it also accepts
digital video input such as RGB and YUV. STV102 video processor implements several proprietary video processing
technologies to improve video quality, which includes input mode detection, noise filtering, bandwidth expansion, de-
interlacing, anti-flickering, line-doubling, image scaling, frame rate conversion and many other image enhancement features.
There are two package options for STV102. STV102A is in a 160-pin package that provides analog video output, while
STV102DP is in a 208-pin package with digital video output. In this datasheet, STV102 shall refer to both package options
unless otherwise indicated.
FEATURES
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♦
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3D motion adaptive de-interlacing
Motion adaptive noise reduction
Programmable parametric non-linear scaling
Movie mode support
Non-linear programmable 16:9 expansion
Color transient improvement, provides sharper color transition
Dynamic peaking filter that greatly compensates the high frequency input
PIP support with arbitrary location and size
Proprietary De-interlacing Engine
Proprietary Scaling Engine
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Programmable 3D motion detection
Motion adaptive de-interlacing
User programmable thresholds
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Programmable non-linear scaling engine can be
optimized for any expansion ratio
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Independent expansion ratio in both horizontal and
vertical direction
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Picture in picture (PIP)
Supports video over video
Easy switching between main and sub picture
Programmable size and location of sub picture
Video Input
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Supports two active input videos
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One channel input can be programmed with 24 bits
RGB or 12/16/24 bit YUV, the other channel
supports 16 bit YUV input
Picture scan allows up to 16 pictures on the same
screen
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Seamless interface with industry standard video
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Both main and sub channel can be progressive or
interlaced input
Programmable PIP boarder support
decoder
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Progressive input support up to 480p
Built-in odd/even field indicator generation
STV102 TV Video Processor
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Data Sheet
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Color Processing
Internal OSD
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Built-in color space converter
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Bit-mapped OSD supports up to 128 internal fonts
for multi-language support
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Programmable gamma correction for different color
temperature and contrast
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Each character is 16x18 pixels
Blinking, inverse, transparency and highlight
support
Noise Reduction
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32 foreground color and 8 background color
Programmable window location
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Adaptive non-linear spatial noise reduction filter
Programmable filter algorithm
Automatic reduce uniform, Gaussian and
Output Control
Salt/Pepper noise while preserving edge
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Motion based noise reduction
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24/48 bit RGB; 24 bit 4:4:4 YUV; 16 bit 4:2:2 YUV
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Programmable output refresh rate up to 75hz
progressive
Advanced Video Enhancement Processor
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Programmable output resolution up to XGA
(1024 x 768)
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Inverse 3:2 pull down for movie input
Non-linear 16:9 conversion
Programmable output timing control for various
LCD panel support
Scan velocity modulation output with adjustable
delay
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Dual pixel (48 bit) output support for LCD TV
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Programmable sharpness enhancement/anti-aliasing
Color transient improvement
Black level expander to enhance contrast
Programmable peaking
Digital brightness, saturation and hue color controls
Background coloring
Built-in output DAC for digital progressive scan
TV
Miscellaneous
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Two wire serial CPU interface
Supports both internal and external OSD
Interface for external SDRAM/SGRAM
No external clock source required
Frame rate conversion to increase output refresh
rate
STV102 TV Video Processor
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Data Sheet
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STV102 FUNCTIONAL BLOCK DIAGRAM
Figure 1. STV102 Functional Block Diagram
Composite
S-Video
YUV/
RGB
Channel
Input 1
Dynamic
Peaking/
YUV
Black Level
Expander
RGB
Composite
S-Video
Color
YUV/
RGB
Channel
Input 2
Transient
RGB
Improvement
SDRAM
SDRAM
STV102
27MHz
108MHz
(for STV102)
(for SDRAM)
Clock Generator
MCU
16M bits
2M bytes
FUNCTIONAL DESCRIPTION
The STV102 has the following major function blocks:
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♦
♦
♦
♦
♦
♦
♦
♦
Channel inputs
Picture in picture/Picture scan
SDRAM controller
De-interlacing
Noise reduction
Dynamic peaking filter/Black-Level Expander
Color transient improvement
Post processing
Output formatting
The following sections will describe the functionality of these blocks.
STV102 TV Video Processor
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Data Sheet
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Channel Inputs
The color space converters of STV102 can accept many different input formats and convert them into internal processing
format. This allows STV102 to seamlessly interface with many industry standard video decoders. STV102 accepts the
following input formats with both positive dual codes and two’s complement codes:
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♦
♦
♦
♦
24 bit 4:4:4
16 bit 4:2:2
12 bit 4:1:1
8 bit 4:2:2 (CCIR 656)
24 bit RGB
Picture in Picture / Picture Scan
There are two video channels picture in picture mode supported by STV102 processor. Either channel can be used as the main
channel, with the other channel used as the sub channel. The switching between these two channels can easily be programmed
through the micro-controller. The size, location and the algorithm used in scaling down the sub picture are also programmable.
By programming the locations of the sub pictures, users can create multiple pictures on the screen, too. This is called the
picture scan capability. The STV102 can support three sub picture modes: 2x2, 3x3 and 4x4.
This TV video processor also supports panning between two inputs. This is done by cutting one section of an input and
attaching it to the other input.
SDRAM Controller
The STV102 has a very high speed SDRAM/SGRAM controller which can seamlessly interface with industry standard 16Mb
DRAMs. The controller can run up to 120Mhz and can provide 240MB data buffer bandwidth. Note that the DRAM can store
up to 4 input fields.
De-interlacing
The STV102 has a motion adaptive de-interlacing unit. Since conventional TV signals come interlaced (scanned every other
lines), it is important to convert these signals into progressive ones (scanned every line) to reduce line flickering. This process
is called de-interlacing, and is basically inserting new lines between the two input lines. The de-interlacing unit of this chip
detects motion based on user programmable thresholds. When there is no motion between two adjunct fields, a simple merged
method is used to insert a new line. However, when there is motion between two adjunct fields, a vector computed using the
top and bottom lines is used to insert a new line. This method greatly reduces the aliasing problem.
STV102 TV Video Processor
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Data Sheet
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Noise Reduction
One of the major problems with conventional TV signals is the noise. There are two basic types of noises:
♦
♦
Salt and pepper noise: typically caused by the insertion of high frequency noise
Gaussian noise: caused by any electrical transmission
Many noise reduction filters work well with one of the noises. However, some filters remove the noise at the expense of the
sharpness of the image. The STV102 adaptively removes both noises by examining surrounding areas of each pixel and
applying different noise reduction algorithms pixel by pixel. The proprietary adaptive method not only removes both type of
noises but also preserves the sharpness (edges) of the image. The thresholds of detections and the parameters of noise filter are
completely programmable through the micro-controller.
Dynamic Peaking Filter / Black Level Expander
The STV102 has two filters, the peaking filter and the sharpness filter. These two filters are used to enhance the sharpness of
the incoming video. Due to the limitation of video decoders, many high frequency luminance are lost during video decoding.
STV102’s programmable dynamic peaking filter can reproduce those lost high frequency information resulting to a sharper
image. The sharpness filter, on the other hand, works directly on each edge of the input image. By stretching the edge
according to user programmable gains, any arbitrary sharpness level can be achieved.
A black level expander is also implemented to make dark regions darker, thereby greatly enhancing contrast.
Color Transient Improvement
Most video has blurred color transition. In order to enhance images, the STV102 applies a proprietary method to detect such
color transition and replace it with a sharper transition. The sharpness of the transition can be programmed through the micro-
controller.
Post Processing
STV102 supports digital brightness and contrast adjustment for the luminance data. For the color data, it supports digital
saturation and hue adjustment.
Output Formatting
The output formatter of STV102 supports many different output formats, such as:
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♦
♦
♦
RGB (24 bit)
YUV 4:4:4 (24 bit)
YUV 4:2:2 (16 bit)
YUV 4:1:1 (12 bit)
STV102 TV Video Processor
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Data Sheet
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STV102A PIN DESCRIPTIONS
Figure 2: STV102A Package Diagram
120
81
80
121
RAM_DATA<1>
RAM_DATA<0>
RAM_ADDR<11>
RAM_ADDR<10>
GND
GND
OUT_HREF
OUT_VREF
OUT_HS
OUT_VS
RAM_ADDR<9>
RAM_ADDR<8>
VCC
GND
VCC
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
RAM_ADDR<7>
RAM_ADDR<6>
GND
RAM_ADDR<5>
RAM_ADDR<4>
RAM_ADDR<3>
RAM_ADDR<2>
VCC
CPU_SCL
CPU_SDA
GND
IN_CLK_2
IN_CLK22
RAM_ADDR<1>
RAM_ADDR<0>
GND
IN_VS2
IN_HS2
IN_VREF2
SmartASIC
RAM_CLK0
VCC
IN_HREF2
IN_FLD2
RAM_QDM
RAM_WEN
RAM_CASN
RAM_RASN
SCAN_EN
CLK_INT
STV102A
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
VCCA
TEST_EN
RST_N
VCC
CLK_RAM
GND
IN_VIDEO1<23>
IN_VIDEO1<22>
IN_VIDEO1<21>
IN_VIDEO1<20>
GNDA
VCCA
IN_VIDEO1<19>
IN_VIDEO1<18>
IN_VIDEO1<17>
GNDA
IN_VIDEO2<14>
IN_VIDEO2<15>
41
160
1
40
STV102 TV Video Processor
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Data Sheet
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Descriptions of each pin of STV102A video processor are provided in this section, sorted by function, pin number and pin
name. STV102A is a 160-pin QFP packaged chip.
Table 1: STV102A Pin Descriptions (Sorted by Function)
Symbol
GNDA
Pin No.
I/O
Description
45, 118, 158
Analog GND.
Analog VCC.
VCCA
44, 117, 157
CPU_SCL
CLK_INT
CLK_VO
CLK_RAM
GNDA
DAC_AB
DAC_AG
DAC_AR
VCCA
DAC_COMP
DAC_VREF
DAC_RSET
CPU_SDA
OUT_OE_N
GND
132
I
I
I
I
Clock for CPU serial interface.
Clock for internal use.
Clock for output video.
Clock for SDRAM.
142
114
51
104
DAC analog GND.
108
O
O
O
DAC analog output, B.
DAC analog output, G.
DAC analog output, R.
DAC analog VCC.
106
107
105
101
I
I
I
DAC compensation capacitor.
DAC reference voltage.
DAC resistor.
103
102
133
BIDIR Data for CPU serial interface.
115
I
Digital output enable. If 1, OUT_VIDEO is in high impedance state.
1, 2, 19, 21,
30, 50, 62, 70,
76, 81, 87, 92,
98, 109, 111,
121, 126, 134
136
Ground
IN_CLK22
IN_CLK21
I
I
I
Input clock 2, 13.5 MHz or at half the frequency of IN_CLK.
Input clock 2, 13.5 MHz or at half the frequency of IN_CLK_1.
Input clock, 27 MHz.
6
IN_CLK_1
5
135
11
141
10
140
138
8
IN_CLK_2
IN_FLD1
I
I
I
I
I
I
Input field indicator. Programmable.
Input H reference. Active pixel indicator.
Input H sync.
IN_FLD2
IN_HREF1
IN_HREF2
IN_HS2
IN_HS1
IN_VREF1
9
Input V reference. Active line indicator.
Input V sync.
IN_VREF2
139
137
7
IN_VS2
IN_VS1
IN_VIDEO1<0>
IN_VIDEO1<1>
IN_VIDEO1<2>
IN_VIDEO1<3>
IN_VIDEO1<4>
IN_VIDEO1<5>
IN_VIDEO1<6>
IN_VIDEO1<7>
IN_VIDEO1<8>
22
23
24
25
26
27
28
29
31
Input video.
STV102 TV Video Processor
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Data Sheet
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Symbol
Pin No.
32
I/O
Description
I
Input video.
IN_VIDEO1<9>
IN_VIDEO1<10>
IN_VIDEO1<11>
IN_VIDEO1<12>
IN_VIDEO1<13>
IN_VIDEO1<14>
IN_VIDEO1<15>
IN_VIDEO1<16>
IN_VIDEO1<17>
IN_VIDEO1<18>
IN_VIDEO1<19>
IN_VIDEO1<20>
IN_VIDEO1<21>
IN_VIDEO1<22>
IN_VIDEO1<23>
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
IN_VIDEO2<14>
IN_VIDEO2<15>
OUT_FLD
33
34
35
36
37
38
40
41
42
43
46
47
48
49
143
144
145
146
147
148
149
150
151
152
153
154
155
156
159
160
119
128
129
130
131
120
124
122
I
Input video.
O
I
Odd/even field indicator. Programmable.
OSD data bit 0, RGB or YUV depending on the output format.
OSD data bit 1, RGB or YUV depending on the output format.
OSD data bit 2, RGB or YUV depending on the output format.
OSD enable. When 1, OUT_VIDEO is OSD_DATA.
Output data enable. VREF AND with HREF.
Output H sync.
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
I
I
I
OUT_DE
O
O
O
OUT_HS
OUT_HREF
Output horizontal reference, covering active pixels. HREF is present
during the vertical-blanking interval.
OUT_CLK
OUT_VS
112
125
123
4
O
O
O
I
Output pixel clock.
Output V sync.
OUT_VREF
Output vertical reference, covering active lines.
PLL reference clock.
PLL_RCLK
RAM_ADDR<0>
RAM_ADDR<1>
RAM_ADDR<2>
RAM_ADDR<3>
63
O
RAM address.
64
66
67
STV102 TV Video Processor
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Data Sheet
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Symbol
Pin No.
I/O
Description
O
RAM address.
RAM_ADDR<4>
RAM_ADDR<5>
RAM_ADDR<6>
RAM_ADDR<7>
RAM_ADDR<8>
RAM_ADDR<9>
RAM_ADDR<10>
RAM_ADDR<11>
RAM_CASN
68
69
71
72
74
75
77
78
57
O
O
RAM CAS_N.
RAM clock.
RAM_CLKO
61
RAM_DATA<0>
RAM_DATA<1>
RAM_DATA<2>
RAM_DATA<3>
RAM_DATA<4>
RAM_DATA<5>
RAM_DATA<6>
RAM_DATA<7>
RAM_DATA<8>
RAM_DATA<9>
RAM_DATA<10>
RAM_DATA<11>
RAM_DATA<12>
RAM_DATA<13>
RAM_DATA<14>
RAM_DATA<15>
RAM_QDM
79
BIDIR RAM data.
80
82
83
84
85
88
89
90
91
93
94
96
97
99
100
59
O
O
O
I
RAM QDM.
RAM_RASN
56
RAM RAS_N.
RAM_WEN
58
RAM WE_N.
RST_N
53
Reset, active low.
Scan enable.
SCAN_EN
55
I
GNDA
16
SVM DAC analog GND.
SVM DAC analog output.
SVM DAC analog VCC.
SVM_AOUT
18
O
VCCA
17
13
SVM_COMP
I
I
I
I
SVM DAC compensation capacitor.
SVM DAC reference voltage.
SVM DAC resistor.
Test enable.
SVM_VREF
15
SVM_RSET
14
TEST_EN
54
VCC
3, 12, 20, 39,
52, 60, 65, 73,
86, 95, 110,
113, 116, 127
VCC.
STV102 TV Video Processor
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Data Sheet
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Table 2: STV102A Pin List (Alphabetical Order)
Symbol
CLK_INT
CLK_RAM
CLK_VO
CPU_SCL
CPU_SDA
DAC_AB
DAC_AG
DAC_AR
DAC_COMP
DAC_RSET
DAC_VREF
GND
Pin No.
142
51
Symbol
Pin No.
10
Symbol
Pin No.
149
150
151
152
9
Symbol
Pin No.
97
IN_HREF1
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VREF1
RAM_DATA<13>
IN_HREF2
140
8
RAM_DATA<14>
99
114
132
133
108
106
107
101
102
103
1
IN_HS1
RAM_DATA<15> 100
IN_HS2
138
22
RAM_DATA<2>
RAM_DATA<3>
RAM_DATA<4>
RAM_DATA<5>
RAM_DATA<6>
RAM_DATA<7>
RAM_DATA<8>
RAM_DATA<9>
RAM_QDM
RAM_RASN
RAM_WEN
RST_N
82
83
84
85
88
89
90
91
59
56
58
53
55
18
13
14
15
54
3
12
20
39
52
60
65
73
86
95
110
113
116
127
17
44
105
117
157
IN_VIDEO1<0>
IN_VIDEO1<1>
IN_VIDEO1<10>
IN_VIDEO1<11>
IN_VIDEO1<12>
IN_VIDEO1<13>
IN_VIDEO1<14>
IN_VIDEO1<15>
IN_VIDEO1<16>
IN_VIDEO1<17>
IN_VIDEO1<18>
IN_VIDEO1<19>
IN_VIDEO1<2>
IN_VIDEO1<20>
IN_VIDEO1<21>
IN_VIDEO1<22>
IN_VIDEO1<23>
IN_VIDEO1<3>
IN_VIDEO1<4>
IN_VIDEO1<5>
IN_VIDEO1<6>
IN_VIDEO1<7>
IN_VIDEO1<8>
IN_VIDEO1<9>
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
IN_VIDEO2<14>
IN_VIDEO2<15>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
23
IN_VREF2
139
7
33
IN_VS1
34
IN_VS2
137
128
129
130
131
112
120
119
122
124
115
123
125
4
35
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
36
37
38
GND
2
40
OUT_CLK
GND
19
41
OUT_DE
GND
21
42
OUT_FLD
GND
30
43
OUT_HREF
SCAN_EN
SVM_AOUT
SVM_COMP
SVM_RSET
SVM_VREF
TEST_EN
VCC
GND
50
24
OUT_HS
GND
62
46
OUT_OE_N
GND
70
47
OUT_VREF
GND
76
48
OUT_VS
GND
81
49
PLL_RCLK
GND
87
25
RAM_ADDR<0>
RAM_ADDR<1>
RAM_ADDR<10>
RAM_ADDR<11>
RAM_ADDR<2>
RAM_ADDR<3>
RAM_ADDR<4>
RAM_ADDR<5>
RAM_ADDR<6>
RAM_ADDR<7>
RAM_ADDR<8>
RAM_ADDR<9>
RAM_CASN
63
GND
92
26
64
VCC
GND
98
27
77
VCC
GND
109
111
121
126
134
16
28
78
VCC
GND
29
66
VCC
GND
31
67
VCC
GND
32
68
VCC
GND
143
144
153
154
155
156
159
160
145
146
147
148
69
VCC
GNDA
71
VCC
GNDA
45
72
VCC
GNDA
104
118
158
5
74
VCC
GNDA
75
VCC
GNDA
57
VCC
IN_CLK_1
IN_CLK_2
IN_CLK21
IN_CLK22
IN_FLD1
IN_FLD2
RAM_CLKO
61
VCC
135
6
RAM_DATA<0>
RAM_DATA<1>
RAM_DATA<10>
RAM_DATA<11>
RAM_DATA<12>
79
VCCA
80
VCCA
136
11
93
VCCA
94
VCCA
141
96
VCCA
STV102 TV Video Processor
- 10 -
Data Sheet
www.smartasic.com
Table 3: STV102A Pin List (Numerical Order)
Pin No.
1
Symbol
GND
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
IN_VIDEO1<17>
IN_VIDEO1<18>
IN_VIDEO1<19>
VCCA
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Symbol
GND
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Symbol
GND
2
GND
RAM_DATA<2>
RAM_DATA<3>
RAM_DATA<4>
RAM_DATA<5>
VCC
OUT_HREF
OUT_VREF
OUT_HS
3
VCC
4
PLL_RCLK
IN_CLK_1
IN_CLK21
IN_VS1
5
GNDA
OUT_VS
6
IN_VIDEO1<20>
IN_VIDEO1<21>
IN_VIDEO1<22>
IN_VIDEO1<23>
GND
GND
7
GND
VCC
8
IN_HS1
RAM_DATA<6>
RAM_DATA<7>
RAM_DATA<8>
RAM_DATA<9>
GND
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
9
IN_VREF1
IN_HREF1
IN_FLD1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CLK_RAM
VCC
VCC
CPU_SCL
SVM_COMP
SVM_RSET
SVM_VREF
GNDA
RST_N
RAM_DATA<10>
RAM_DATA<11>
VCC
CPU_SDA
TEST_EN
GND
SCAN_EN
IN_CLK_2
RAM_RASN
RAM_CASN
RAM_WEN
RAM_QDM
VCC
RAM_DATA<12>
RAM_DATA<13>
GND
IN_CLK22
VCCA
IN_VS2
SVM_AOUT
GND
IN_HS2
RAM_DATA<14>
IN_VREF2
VCC
GND
100 RAM_DATA<15>
IN_HREF2
RAM_CLKO
GND
RAM_ADDR<0>
RAM_ADDR<1>
VCC
RAM_ADDR<2>
RAM_ADDR<3>
RAM_ADDR<4>
RAM_ADDR<5>
GND
RAM_ADDR<6>
RAM_ADDR<7>
VCC
RAM_ADDR<8>
RAM_ADDR<9>
GND
RAM_ADDR<10>
RAM_ADDR<11>
RAM_DATA<0>
RAM_DATA<1>
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DAC_COMP
DAC_RSET
DAC_VREF
GNDA
IN_FLD2
IN_VIDEO1<0>
IN_VIDEO1<1>
IN_VIDEO1<2>
IN_VIDEO1<3>
IN_VIDEO1<4>
IN_VIDEO1<5>
IN_VIDEO1<6>
IN_VIDEO1<7>
GND
CLK_INT
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
VCCA
VCCA
DAC_AG
DAC_AR
DAC_AB
GND
VCC
GND
OUT_CLK
VCC
IN_VIDEO1<8>
IN_VIDEO1<9>
IN_VIDEO1<10>
IN_VIDEO1<11>
IN_VIDEO1<12>
IN_VIDEO1<13>
IN_VIDEO1<14>
IN_VIDEO1<15>
VCC
CLK_VO
OUT_OE_N
VCC
VCCA
GNDA
GNDA
IN_VIDEO2<14>
IN_VIDEO2<15>
OUT_FLD
OUT_DE
IN_VIDEO1<16>
STV102 TV Video Processor
- 11 -
Data Sheet
www.smartasic.com
STV102DP PIN DESCRIPTIONS
Figure 3: STV102DP Package Diagram
156
105
157
104
OUT_FLD
GND
OUT_VIDEO<5>
OUT_VIDEO<4>
VCC
OUT_DE
GND
OUT_HREF
OUT_VREF
OUT_HS
OUT_VIDEO<3>
OUT_VIDEO<2>
GND
OUT_VS
GND
OUT_VIDEO<1>
OUT_VIDEO<0>
RAM_ADDR<11>
RAM_ADDR<10>
GND
OUT_VIDEO<16>
OUT_VIDEO<17>
VCC
OUT_VIDEO<18>
OUT_VIDEO<19>
OUT_VIDEO<20>
OUT_VIDEO<21>
GND
RAM_ADDR<9>
RAM_ADDR<8>
VCC
RAM_ADDR<7>
RAM_ADDR<6>
GND
OUT_VIDEO<22>
OUT_VIDEO<23>
VCC
RAM_ADDR<5>
RAM_ADDR<4>
RAM_ADDR<3>
RAM_ADDR<2>
VCC
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
SmartASIC
STV102DP
CPU_SCL
RAM_ADDR<1>
RAM_ADDR<0>
GND
CPU_SDA
GND
IN_CLK_2
RAM_CLKO
VCC
IN_CLK22
IN_VS2
RAM_QDM
RAM_WEN
IN_HS2
IN_VREF2
RAM_CASN
RAM_RASN
SCAN_EN
IN_HREF2
IN_FLD2
CLK_INT
TEST_EN
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
VCCA
RST_N
VCC
CLK_RAM
GND
IN_VIDEO1<23>
IN_VIDEO1<22>
IN_VIDEO1<21>
IN_VIDEO1<20>
GNDA
VCCA
IN_VIDEO1<19>
IN_VIDEO1<18>
IN_VIDEO1<17>
IN_VIDEO1<16>
VCC
GNDA
IN_VIDEO1<15>
IN_VIDEO1<14>
IN_VIDEO1<13>
IN_VIDEO2<14>
IN_VIDEO2<15>
208
52
1
STV102 TV Video Processor
- 12 -
Data Sheet
www.smartasic.com
Descriptions of each pin of STV102DP video processor are provided in this section, sorted by function, pin number and pin
name. STV102DP is a 208-pin QFP packaged chip.
Table 4: STV102DP Pin Descriptions (Sorted by Function)
Symbol
GNDA
Pin No.
I/O
Description
62
Analog GND.
Analog GND.
Analog GND.
Analog VCC.
Analog VCC.
Analog VCC.
GNDA
156
GNDA
206
VCCA
61
VCCA
155
VCCA
205
CPU_SCL
CLK_INT
CLK_VO
CLK_RAM
CPU_SDA
OUT_OE_N
GND
180
I
I
I
I
Clock for CPU serial interface.
Clock for internal use.
Clock for output video.
Clock for SDRAM.
190
152
68
181
BIDIR Data for CPU serial interface.
153
I
Digital output enable. If 1, OUT_VIDEO is in high impedance state.
1, 4, 27, 31,
Ground.
47, 67, 79, 87,
93, 98, 104,
109, 115, 120,
126, 131, 139,
149, 159, 164,
172, 182
184
14
IN_CLK22
IN_CLK21
I
I
I
Input clock 2, 13.5 MHz or at half the frequency of IN_CLK.
Input clock 2, 13.5 MHz or at half the frequency of IN_CLK_1.
Input clock, 27 MHz.
IN_CLK_1
13
IN_CLK_2
183
19
IN_FLD1
I
I
I
I
I
I
Input field indicator. Programmable.
Input H reference. Active pixel indicator.
Input H sync
IN_FLD2
189
18
IN_HREF1
IN_HREF2
188
186
16
IN_HS2
IN_HS1
IN_VREF1
17
Input V reference. Active line indicator.
Input V sync
IN_VREF2
187
185
15
IN_VS2
IN_VS1
IN_VIDEO1<0>
IN_VIDEO1<1>
IN_VIDEO1<2>
IN_VIDEO1<3>
IN_VIDEO1<4>
IN_VIDEO1<5>
IN_VIDEO1<6>
IN_VIDEO1<7>
IN_VIDEO1<8>
IN_VIDEO1<9>
IN_VIDEO1<10>
39
Input video
40
41
42
43
44
45
46
48
49
50
STV102 TV Video Processor
- 13 -
Data Sheet
www.smartasic.com
Symbol
Pin No.
51
I/O
Description
I
Input video.
IN_VIDEO1<11>
IN_VIDEO1<12>
IN_VIDEO1<13>
IN_VIDEO1<14>
IN_VIDEO1<15>
IN_VIDEO1<16>
IN_VIDEO1<17>
IN_VIDEO1<18>
IN_VIDEO1<19>
IN_VIDEO1<20>
IN_VIDEO1<21>
IN_VIDEO1<22>
IN_VIDEO1<23>
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
IN_VIDEO2<14>
IN_VIDEO2<15>
OUT_FLD
52
53
54
55
57
58
59
60
63
64
65
66
191
192
193
194
195
196
197
198
199
200
201
202
203
204
207
208
157
176
177
178
179
158
162
160
I
Input video.
O
I
Odd/even field indicator. Programmable.
OSD data bit 0, RGB or YUV depending on the output format.
OSD data bit 1, RGB or YUV depending on the output format.
OSD data bit 2, RGB or YUV depending on the output format.
OSD enable. When 1, OUT_VIDEO is OSD_DATA.
Output data enable. VREF AND with HREF.
Output H sync.
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
I
I
I
OUT_DE
O
O
O
OUT_HS
OUT_HREF
Output horizontal reference, covering active pixels. HREF is present
during the vertical-blanking interval.
OUT_CLK
150
163
161
2
O
O
O
O
Output pixel clock.
Output V sync.
OUT_VS
OUT_VREF
Output vertical reference, covering active lines.
Output video.
OUT_VIDEO<32>
OUT_VIDEO<33>
OUT_VIDEO<34>
OUT_VIDEO<35>
OUT_VIDEO<36>
OUT_VIDEO<37>
OUT_VIDEO<38>
3
5
6
7
9
10
STV102 TV Video Processor
- 14 -
Data Sheet
www.smartasic.com
Symbol
Pin No.
11
I/O
Description
O
Output video.
OUT_VIDEO<39>
OUT_VIDEO<40>
OUT_VIDEO<41>
OUT_VIDEO<42>
OUT_VIDEO<43>
OUT_VIDEO<44>
OUT_VIDEO<45>
OUT_VIDEO<46>
OUT_VIDEO<47>
OUT_VIDEO<0>
OUT_VIDEO<1>
OUT_VIDEO<2>
OUT_VIDEO<3>
OUT_VIDEO<4>
OUT_VIDEO<5>
OUT_VIDEO<6>
OUT_VIDEO<7>
OUT_VIDEO<8>
OUT_VIDEO<9>
OUT_VIDEO<10>
OUT_VIDEO<11>
OUT_VIDEO<12>
OUT_VIDEO<13>
OUT_VIDEO<14>
OUT_VIDEO<15>
OUT_VIDEO<16>
OUT_VIDEO<17>
OUT_VIDEO<18>
OUT_VIDEO<19>
OUT_VIDEO<20>
OUT_VIDEO<21>
OUT_VIDEO<22>
OUT_VIDEO<23>
OUT_VIDEO<16>
OUT_VIDEO<17>
OUT_VIDEO<18>
OUT_VIDEO<19>
OUT_VIDEO<20>
OUT_VIDEO<21>
OUT_VIDEO<22>
OUT_VIDEO<23>
PLL_RCLK
29
30
32
33
35
36
37
38
96
97
99
100
102
103
105
106
129
130
132
133
135
136
137
138
140
141
142
143
145
146
147
148
165
166
168
169
170
171
173
174
12
I
O
PLL reference clock.
RAM address.
RAM_ADDR<0>
RAM_ADDR<1>
RAM_ADDR<2>
RAM_ADDR<3>
RAM_ADDR<4>
RAM_ADDR<5>
80
81
83
84
85
86
STV102 TV Video Processor
- 15 -
Data Sheet
www.smartasic.com
Symbol
Pin No.
I/O
Description
O
RAM address.
RAM_ADDR<6>
RAM_ADDR<7>
RAM_ADDR<8>
RAM_ADDR<9>
RAM_ADDR<10>
RAM_ADDR<11>
RAM_CASN
88
89
91
92
94
95
74
O
O
RAM CAS_N.
RAM clock.
RAM_CLKO
78
RAM_DATA<0>
RAM_DATA<1>
RAM_DATA<2>
RAM_DATA<3>
RAM_DATA<4>
RAM_DATA<5>
RAM_DATA<6>
RAM_DATA<7>
RAM_DATA<8>
RAM_DATA<9>
RAM_DATA<10>
RAM_DATA<11>
RAM_DATA<12>
RAM_DATA<13>
RAM_DATA<14>
RAM_DATA<15>
RAM_QDM
107
BIDIR RAM data.
108
110
111
112
113
116
117
118
119
121
122
124
125
127
128
76
O
O
O
I
RAM QDM.
RAM_RASN
73
RAM RAS_N.
RAM_WEN
75
RAM WE_N.
RST_N
70
Reset, active low.
Scan enable.
SCAN_EN
72
I
GNDA
24
SVM DAC analog GND.
SVM DAC analog output.
SVM DAC analog VCC.
SVM_AOUT
26
O
VCCA
25
21
SVM_COMP
I
I
I
I
SVM DAC compensation capacitor.
SVM DAC reference voltage.
SVM DAC resistor.
SVM_VREF
23
SVM_RSET
22
TEST_EN
71
Test enable.
VCC
8, 20, 28, 34,
56, 69, 77, 82,
90, 101, 114,
123, 134, 144,
151, 154, 167,
175
STV102 TV Video Processor
- 16 -
Data Sheet
www.smartasic.com
Table 5: STV102DP Pin List (Alphabetical Order)
Symbol
CLK_INT
CLK_RAM
CLK_VO
CPU_SCL
CPU_SDA
GND
Pin No.
190
68
Symbol
Pin No.
60
Symbol
Pin No.
165
141
166
142
168
143
169
99
Symbol
RAM_ADDR<8>
RAM_ADDR<9>
RAM_CASN
RAM_CLKO
RAM_DATA<0>
RAM_DATA<1>
RAM_DATA<10>
RAM_DATA<11>
RAM_DATA<12>
RAM_DATA<13>
RAM_DATA<14>
RAM_DATA<15>
RAM_DATA<2>
RAM_DATA<3>
RAM_DATA<4>
RAM_DATA<5>
RAM_DATA<6>
RAM_DATA<7>
RAM_DATA<8>
RAM_DATA<9>
RAM_QDM
RAM_RASN
RAM_WEN
RST_N
Pin No.
91
IN_VIDEO1<19>
IN_VIDEO1<2>
IN_VIDEO1<20>
IN_VIDEO1<21>
IN_VIDEO1<22>
IN_VIDEO1<23>
IN_VIDEO1<3>
IN_VIDEO1<4>
IN_VIDEO1<5>
IN_VIDEO1<6>
IN_VIDEO1<7>
IN_VIDEO1<8>
IN_VIDEO1<9>
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
IN_VIDEO2<14>
IN_VIDEO2<15>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VREF1
OUT_VIDEO<16>
OUT_VIDEO<17>
OUT_VIDEO<17>
OUT_VIDEO<18>
OUT_VIDEO<18>
OUT_VIDEO<19>
OUT_VIDEO<19>
OUT_VIDEO<2>
OUT_VIDEO<20>
OUT_VIDEO<20>
OUT_VIDEO<21>
OUT_VIDEO<21>
OUT_VIDEO<22>
OUT_VIDEO<22>
OUT_VIDEO<23>
OUT_VIDEO<23>
OUT_VIDEO<3>
OUT_VIDEO<32>
OUT_VIDEO<33>
OUT_VIDEO<34>
OUT_VIDEO<35>
OUT_VIDEO<36>
OUT_VIDEO<37>
OUT_VIDEO<38>
OUT_VIDEO<39>
OUT_VIDEO<4>
OUT_VIDEO<40>
OUT_VIDEO<41>
OUT_VIDEO<42>
OUT_VIDEO<43>
OUT_VIDEO<44>
OUT_VIDEO<45>
OUT_VIDEO<46>
OUT_VIDEO<47>
OUT_VIDEO<5>
OUT_VIDEO<6>
OUT_VIDEO<7>
OUT_VIDEO<8>
OUT_VIDEO<9>
OUT_VREF
41
92
152
180
181
1
63
74
78
64
65
107
108
121
122
124
125
127
128
110
111
112
113
116
117
118
119
76
66
GND
4
42
GND
27
43
GND
31
44
145
170
146
171
147
173
148
174
100
2
GND
47
45
GND
67
46
GND
79
48
GND
87
49
GND
93
191
192
201
202
203
204
207
208
193
194
195
196
197
198
199
200
17
GND
98
GND
104
109
115
120
126
131
139
149
159
164
172
182
24
GND
GND
GND
3
GND
5
GND
6
GND
7
73
GND
9
75
GND
10
70
GND
11
SCAN_EN
SVM_AOUT
SVM_COMP
SVM_RSET
SVM_VREF
TEST_EN
VCC
72
GND
102
29
26
GND
21
GNDA
30
22
GNDA
62
32
23
GNDA
156
206
13
33
71
GNDA
IN_VREF2
187
15
35
8
IN_CLK_1
IN_CLK_2
IN_CLK21
IN_CLK22
IN_FLD1
IN_FLD2
IN_HREF1
IN_HREF2
IN_HS1
IN_VS1
36
VCC
20
183
14
IN_VS2
185
176
177
178
179
150
158
157
160
162
153
96
37
VCC
28
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
38
VCC
34
184
19
103
105
106
129
130
161
163
12
VCC
56
VCC
69
189
18
VCC
77
OUT_CLK
VCC
82
188
16
OUT_DE
VCC
90
OUT_FLD
VCC
101
114
123
134
144
151
154
167
175
25
IN_HS2
186
39
OUT_HREF
OUT_VS
PLL_RCLK
VCC
IN_VIDEO1<0>
IN_VIDEO1<1>
IN_VIDEO1<10>
IN_VIDEO1<11>
IN_VIDEO1<12>
IN_VIDEO1<13>
IN_VIDEO1<14>
IN_VIDEO1<15>
IN_VIDEO1<16>
IN_VIDEO1<17>
IN_VIDEO1<18>
OUT_HS
VCC
40
OUT_OE_N
RAM_ADDR<0>
RAM_ADDR<1>
RAM_ADDR<10>
RAM_ADDR<11>
RAM_ADDR<2>
RAM_ADDR<3>
RAM_ADDR<4>
RAM_ADDR<5>
RAM_ADDR<6>
RAM_ADDR<7>
80
VCC
50
OUT_VIDEO<0>
OUT_VIDEO<1>
OUT_VIDEO<10>
OUT_VIDEO<11>
OUT_VIDEO<12>
OUT_VIDEO<13>
OUT_VIDEO<14>
OUT_VIDEO<15>
OUT_VIDEO<16>
81
VCC
51
97
94
VCC
52
132
133
135
136
137
138
140
95
VCC
53
83
VCC
54
84
VCC
55
85
VCCA
57
86
VCCA
61
155
205
58
88
VCCA
59
89
VCCA
STV102 TV Video Processor
- 17 -
Data Sheet
www.smartasic.com
Table 6: STV102DP Pin List (Numerical Order)
Pin No.
1
Symbol
GND
OUT_VIDEO<32>
OUT_VIDEO<33>
GND
OUT_VIDEO<34>
OUT_VIDEO<35>
OUT_VIDEO<36>
VCC
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Symbol
IN_VIDEO1<13>
IN_VIDEO1<14>
IN_VIDEO1<15>
VCC
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Symbol
OUT_VIDEO<6>
OUT_VIDEO<7>
RAM_DATA<0>
RAM_DATA<1>
GND
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Symbol
OUT_FLD
2
OUT_DE
3
GND
4
OUT_HREF
OUT_VREF
OUT_HS
5
IN_VIDEO1<16>
IN_VIDEO1<17>
IN_VIDEO1<18>
IN_VIDEO1<19>
VCCA
6
RAM_DATA<2>
RAM_DATA<3>
RAM_DATA<4>
RAM_DATA<5>
VCC
7
OUT_VS
GND
OUT_VIDEO<16>
OUT_VIDEO<17>
VCC
OUT_VIDEO<18>
OUT_VIDEO<19>
OUT_VIDEO<20>
OUT_VIDEO<21>
GND
OUT_VIDEO<22>
OUT_VIDEO<23>
VCC
8
9
OUT_VIDEO<37>
OUT_VIDEO<38>
OUT_VIDEO<39>
PLL_RCLK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GNDA
IN_VIDEO1<20>
IN_VIDEO1<21>
IN_VIDEO1<22>
IN_VIDEO1<23>
GND
GND
RAM_DATA<6>
RAM_DATA<7>
RAM_DATA<8>
RAM_DATA<9>
GND
IN_CLK_1
IN_CLK21
IN_VS1
IN_HS1
CLK_RAM
IN_VREF1
VCC
RAM_DATA<10>
RAM_DATA<11>
VCC
RAM_DATA<12>
RAM_DATA<13>
GND
RAM_DATA<14>
RAM_DATA<15>
OUT_VIDEO<8>
OUT_VIDEO<9>
GND
OUT_VIDEO<10>
OUT_VIDEO<11>
VCC
OUT_VIDEO<12>
OUT_VIDEO<13>
OUT_VIDEO<14>
OUT_VIDEO<15>
GND
OUT_VIDEO<16>
OUT_VIDEO<17>
OUT_VIDEO<18>
OUT_VIDEO<19>
VCC
IN_HREF1
RST_N
IN_FLD1
TEST_EN
VCC
SCAN_EN
OSD_DATA<0>
OSD_DATA<1>
OSD_DATA<2>
OSD_EN
SVM_COMP
SVM_RSET
SVM_VREF
GNDA
RAM_RASN
RAM_CASN
RAM_WEN
RAM_QDM
VCC
CPU_SCL
VCCA
CPU_SDA
SVM_AOUT
GND
RAM_CLKO
GND
RAM_ADDR<0>
RAM_ADDR<1>
VCC
RAM_ADDR<2>
RAM_ADDR<3>
RAM_ADDR<4>
RAM_ADDR<5>
GND
RAM_ADDR<6>
RAM_ADDR<7>
VCC
RAM_ADDR<8>
RAM_ADDR<9>
GND
RAM_ADDR<10>
RAM_ADDR<11>
OUT_VIDEO<0>
OUT_VIDEO<1>
GND
OUT_VIDEO<2>
OUT_VIDEO<3>
VCC
OUT_VIDEO<4>
OUT_VIDEO<5>
GND
GND
IN_CLK_2
VCC
IN_CLK22
OUT_VIDEO<40>
OUT_VIDEO<41>
GND
IN_VS2
IN_HS2
IN_VREF2
OUT_VIDEO<42>
OUT_VIDEO<43>
VCC
IN_HREF2
IN_FLD2
CLK_INT
OUT_VIDEO<44>
OUT_VIDEO<45>
OUT_VIDEO<46>
OUT_VIDEO<47>
IN_VIDEO1<0>
IN_VIDEO1<1>
IN_VIDEO1<2>
IN_VIDEO1<3>
IN_VIDEO1<4>
IN_VIDEO1<5>
IN_VIDEO1<6>
IN_VIDEO1<7>
GND
IN_VIDEO2<0>
IN_VIDEO2<1>
IN_VIDEO2<2>
IN_VIDEO2<3>
IN_VIDEO2<4>
IN_VIDEO2<5>
IN_VIDEO2<6>
IN_VIDEO2<7>
IN_VIDEO2<8>
IN_VIDEO2<9>
IN_VIDEO2<10>
IN_VIDEO2<11>
IN_VIDEO2<12>
IN_VIDEO2<13>
VCCA
OUT_VIDEO<20>
OUT_VIDEO<21>
OUT_VIDEO<22>
OUT_VIDEO<23>
GND
OUT_CLK
VCC
IN_VIDEO1<8>
IN_VIDEO1<9>
IN_VIDEO1<10>
IN_VIDEO1<11>
IN_VIDEO1<12>
CLK_VO
OUT_OE_N
VCC
GNDA
IN_VIDEO2<14>
IN_VIDEO2<15>
VCCA
GNDA
STV102 TV Video Processor
- 18 -
Data Sheet
www.smartasic.com
PACKAGE DIMENSIONS
Figure 4: STV102 Package Dimensions
Table 7: STV102 Package Measurements
STV102A
STV102DP
Inch (REF)
Symbol\Unit
Inch (REF)
MM (BASE)
4.07 (MAX)
3.225 0.075
MM (BASE)
3.683 (MAX)
3.226 0.127
A
A1
A2
0.16 (MAX)
0.127 0.003
0.145 (MAX)
0.127 0.005
+0.004
-0.002
+0.102
0.01 MIN.
0.25 MIN.
0.006
0.152
-0.051
b
D
E
e
0.012 (REF)
1.102 0.004
1.102 0.004
0.026 0.006
0.300 (REF)
28.00 0.10
28.000 0.10
0.650 0.152
0.008 (REF)
1.102 0.005
1.102 0.005
0.020 0.004
0.200 (REF)
28.000 0.127
28.000 0.127
0.500 0.102
+0.004
+0.102
+0.004
+0.102
t
0.006
0.152
0.006
0.152
-0.002
-0.051
-0.002
-0.051
y
0.003 (MAX)
0.076 (MAX)
0.003 (MAX)
0.076 (MAX)
0°~7°
0°~7°
0°~7°
0°~7°
Θ1
HD
HE
L
1.2285 0.0095
1.2285 0.0095
0.033 0.006
0.063 0.008
31.200 0.25
31.200 0.25
0.85 0.15
1.2285 0.012
1.2285 0.012
0.034 0.008
0.063 0.008
31.200 0.300
31.200 0.300
0.867 0.203
1.600 0.203
L1
1.600 0.203
STV102 TV Video Processor
- 19 -
Data Sheet
www.smartasic.com
CPU INTERFACE
The STV102 contains a 2-wire serial interface for connection to an external CPU allowing it to read status registers and access
and modify control registers inside this chip. These are SCL and SDA.
The external CPU is the host that drives the SCL all the time. It is mainly used as the sampling clock for clock signals and for
“start” and “stop” bits. The SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. It is mainly used
as a data signal. This interface supports random and sequential write operations for the CPU to modify one or multiple control
registers. Also, it supports random and sequential read operations for the CPU to read all or part of the control registers.
The figure below shows the basic bit definitions of this 2-wire serial interface:
Figure 5: START, STOP and DATA Definitions in the 2-wire Serial Interface
SCL
SDA
DATA
STABLE
START
STOP
DATA
DATA
CHANGE
CHANGE
STV102 TV Video Processor
- 20 -
Data Sheet
www.smartasic.com
The 2-wire serial interface supports random and sequential read/write operations. The following figures show the data
sequences for random read/write and sequential read/write operations:
Figure 6: Data Sequence for Read Access (Both Single and Multiple Bytes)
S
T
A
R
T
W
S
R
E
S
T
O
P
R
I
T
A
R
T
A
C
K
A
C
K
A
C
K
WORD
A
C
K
DEVICE
DEVICE
DATA READ
A
D
T
E
ADDRESS
ADDRESS
L
S
M
S
L
S
M
S
L
S
M
S
R
M
S
/
___
B
B
B
B
B
B
B
W
B
I
B
I
B
I
B
I
B
I
B
I
B
I
T
0
T
7
T
0
T
7
T
0
T
6
T
6
Figure 7: Data Sequence for Write Access (Both Single and Multiple Bytes)
S
T
A
R
T
W
S
T
O
P
R
I
A
C
K
A
A
C
K
WORD
A
C
K
DEVICE
ADDRESS
DATA n
C
K
DATA n+x
T
E
ADDRESS
L
S
M
S
L
S
M
S
L
M
S
R
M
S
S
/
___
B
B
B
B
B
B
B
W
B
I
B
I
B
I
B
I
B
I
B
I
B
I
T
0
T
7
T
0
T
7
T
0
T
6
T
7
STV102 TV Video Processor
- 21 -
Data Sheet
www.smartasic.com
The 2-wire serial interface allows the external CPU to read the control and status registers of the STV102 in order to know its
state as well as the result of the input mode detection and phase calibration. It can also modify these control registers to disable
several STV102 features and force the STV102 into a particular state.
Aside from the above, the external CPU is also able to adjust the size of the output image and move the output image up and
down by simply changing the porch size, pixel and line numbers of the input signal. These adjustments can be tied to the
external user control button on the monitor.
CONTROL AND STATUS REGISTERS
EEPROM Control Register: (CPU read only)
Address
00H
Signal
Bit Pos Default
Description
EEP_DONE
[7]
[6]
0
0
EEPROM initialization done;
Reserved;
EEP_CLKC
[5:0]
9H
EEPROM clock control;
EEP_CLKC = (Input video clock / (8 * desired EEPROM clock)) – 1
Input Format Conversion Registers, Main Picture:
Address
01H
02H
03H
04H
05H
06H
07H
08H
09H
Signal
Bit Pos
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[5]
Default
Description
Lower 8 bits of active pixels per line
Upper 2 bits of active pixels per line
Lower 8 bits of active lines per field
Upper 2 bits of active lines per field
Lower 8 bits of active pixels per line – 1
Upper 2 bits of active pixels per line – 1
Lower 8 bits of active lines per field – 1
Upper 2 bits of active lines per field – 1
Input select.
IFC_PIXEL1 [7:0]
IFC_PIXEL1 [9:8]
IFC_LINE1 [7:0]
IFC_LINE1 [9:8]
IFC_HSIZE1 [7:0]
IFC_HSIZE1 [9:8]
IFC_VSIZE1 [7:0]
IFC_VSIZE1 [9:8]
IFC_CH21
D0H
2
E4H
1
CFH
2
E3H
1
1
0: channel 1
1: channel 2
IFC_PROG_IN1
IFC_CLAMP1
IFC_FORMAT1
[4]
[3]
[2:0]
1
1
1
0: TV input with field
0: no clamping
1: progressive input w/o field
1: clamping
000: YCbCr/YUV444 ( 127)
001: YCbCr/YUV422 ( 127)
010: YCbCr/YUV411 ( 127)
011: YCbCr 444 (0 – 255)
100: YCbCr 422 (0 – 255)
101: YCbCr 411 (0 – 255)
110: RGB
111: ITU 656 8-bit YUV 4:2:2 ( 127)
0AH
IFC_STILL1
[7]
[6]
[5]
[4]
[3]
0
0
0
1
0
0: normal
1: still picture
IFC_INT_FLD1
IFC_DE_SEL1
IFC_FIELD_PL1
IFC_VSYNC_PL1
0: use external field
0: external DE for input
0: field low is even field
1: use internal field
1: internally generated DE for input
1: field high is even field
0: v start at v sync falling edge 1: v start at v sync rising edge
STV102 TV Video Processor
- 22 -
Data Sheet
www.smartasic.com
Address
Signal
Bit Pos
[2]
Default
Description
0AH
IFC_HSYNC_PL1
IFC_VREF_PL1
IFC_HREF_PL1
VSTART_E1[7:0]
VSTART_E1[9:8]
VSTART_O1[7:0]
VSTART_O1[9:8]
VEND_E1[7:0]
0
1
0: h start at h sync falling edge 1: h start at h sync rising edge
[1]
0: active low
0: active low
1: active high
1: active high
[0]
1
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
14H
0
Lower 8 bits of active line start for even field
Upper 2 bits of active line start for even field
Lower 8 bits of active line start for odd field
Upper 2 bits of active line start for odd field
Lower 8 bits of active line end for even field
Upper 2 bits of active line end for even field
Lower 8 bits of active line end for odd field
Upper 2 bits of active line end for odd field
Lower 8 bits of active pixel start
15H
0
14H
0
VEND_E1[9:8]
VEND_O1[7:0]
VEND_O1[9:8]
IFC_HSTART1[7:0]
IFC_HSTART1[9:8]
IFC_HEND1[7:0]
IFC_HEND1[9:8]
15H
0
14H
0
Upper 2 bits of active pixel start
14H
0
Lower 8 bits of active pixel end
Upper 2 bits of active pixel end
Input Format Conversion Registers, PIP Picture:
Address
17H
Signal
Bit Pos
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[5]
Default
Description
Lower 8 bits of active pixels per line
Upper 2 bits of active pixels per line
Lower 8 bits of active lines per field
Upper 2 bits of active lines per field
Lower 8 bits of active pixels per line – 1
Upper 2 bits of active pixels per line – 1
Lower 8 bits of active lines per field – 1
Upper 2 bits of active lines per field – 1
Input select.
IFC_PIXEL2 [7:0]
IFC_PIXEL2 [9:8]
IFC_LINE2 [7:0]
IFC_LINE2 [9:8]
IFC_HSIZE2 [7:0]
IFC_HSIZE2 [9:8]
IFC_VSIZE2 [7:0]
IFC_VSIZE2 [9:8]
IFC_CH22
D0H
2
18H
19H
E4H
1
1AH
1BH
1CH
1DH
1EH
1FH
CFH
2
E3H
1
1
0: channel 2
1: channel 1
IFC_PROG_IN2
IFC_CLAMP2
IFC_FORMAT2
[4]
[3]
[2:0]
1
1
1
0: TV input with field
0: no clamping
1: progressive input w/o field
1: clamping
000: YCbCr/YUV444 ( 127)
001: YCbCr/YUV422 ( 127)
010: YCbCr/YUV411 ( 127)
011: YCbCr 444 (0 – 255)
100: YCbCr 422 (0 – 255)
101: YCbCr 411 (0 – 255)
110: RGB
111: ITU 656 8-bit YUV 4:2:2 ( 127)
20H
IFC_STILL2
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
1
0
0
1
1
0: normal
1: still picture
IFC_INT_FLD2
IFC_DE_SEL2
IFC_FIELD_PL2
IFC_VSYNC_PL2
IFC_HSYNC_PL2
IFC_VREF_PL2
IFC_HREF_PL2
0: use external field
0: external DE for input
0: field low is even field
1: use internal field
1: internally generates DE for input
1: field high is even field
0: v start at v sync falling edge 1: v start at v sync rising edge
0: h start at h sync falling edge 1: h start at h sync rising edge
0: active low
0: active low
1: active high
1: active high
STV102 TV Video Processor
- 23 -
Data Sheet
www.smartasic.com
Address
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
Signal
Bit Pos
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
Default
14H
0
Description
VSTART_E2[7:0]
VSTART_E2[9:8]
VSTART_O2[7:0]
VSTART_O2[9:8]
VEND_E2[7:0]
Lower 8 bits of active line start for even field
Upper 2 bits of active line start for even field
Lower 8 bits of active line start for odd field
Upper 2 bits of active line start for odd field
Lower 8 bits of active line end for even field
Upper 2 bits of active line end for even field
Lower 8 bits of active line end for odd field
Upper 2 bits of active line end for odd field
Lower 8 bits of active pixel start
15H
0
14H
0
VEND_E2[9:8]
VEND_O2[7:0]
15H
0
VEND_O2[9:8]
IFC_HSTART2[7:0]
IFC_HSTART2[9:8]
IFC_HEND2[7:0]
IFC_HEND2[9:8]
14H
0
Upper 2 bits of active pixel start
14H
0
Lower 8 bits of active pixel end
Upper 2 bits of active pixel end
Picture-in-Picture (PIP) Control Registers
Address
Signal
PIP_PP_CTL
PIP_ON
Bit Pos
Default
Description
2DH
00H
PIP control;
[7]
[6]
[5]
[4]
0: PIP off
1: PIP on
Reserved
PIP_SPLIT
PIP_BGC
0: normal screen
Main picture area:
0: display video
0: moving main picture
1: split screen (side by side)
1: display background color
1: still main picture
PIP_STILLM
PIP_SCALEM
[3]
[2]
Only in split mode, only horizontally:
0: pan main picture
0: moving sub picture
1: scale main picture by 2
1: still sub picture
PIP_STILLS
PIP_SCALES
[1]
[0]
Only in split mode, only horizontally:
0: pan sub picture
1: scale sub picture by 2
2EH
2FH
PIP_PM_IPS [7:0]
PIP_PM_IPS [9:8]
[7:0]
[1:0]
0
0
Lower 8 bits of input pixel start for main picture (used in split
pan mode)
Upper 2 bits of input pixel start for main picture (used in split
pan mode)
30H
31H
32H
33H
PIP_PM_BGY [7:0]
PIP_PM_BGU [7:0]
PIP_PM_BGV [7:0]
PIP_PS_CTL
PIP_PS_AY
PIP_PS_AX
[7:0]
[7:0]
[7:0]
0
0
0
0
Background color, Y
Background color, U
Background color, V
PIP sub picture control;
[7:6]
[5:4]
Algorithm in Y scaling:
Algorithm in X scaling:
00: drop
01: 2 point
10: 3 point
11: adaptive
PIP_PS_SY
PIP_PS_SX
[3:2]
[1:0]
Scaling factor in Y;
Scaling factor in X:
00: no scale
01: by 2
11: by 4
10: by 3
34H
35H
36H
37H
PIP_PS_IPS [7:0]
PIP_PS_IPS [9:8]
PIP_PS_ILS [7:0]
PIP_PS_ILS [8]
[7:0]
[1:0]
[7:0]
[0]
0
0
0
0
Lower 8 bits of input pixel start for sub picture
Upper 2 bits of input pixel start for sub picture
Lower 8 bits of input line start for sub picture
Upper 1 bit of input line start for sub picture
STV102 TV Video Processor
- 24 -
Data Sheet
www.smartasic.com
Address
38H
Signal
Bit Pos
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[0]
Default
68H
1
Description
PIP_PS_OPS [7:0]
PIP_PS_OPS [9:8]
PIP_PS_OPW [7:0]
PIP_PS_OPW [9:8]
PIP_PS_OLS [7:0]
PIP_PS_OLS [8]
PIP_PS_OLH [7:0]
PIP_PS_OLH [8]
PIP_PS_OBS [7:0]
Lower 8 bits of output pixel start for sub picture
Upper 2 bits of output pixel start for sub picture
Lower 8 bits of output picture width for sub picture
Upper 2 bits of output picture width for sub picture
Lower 8 bits of output line start for sub picture
Upper 1 bit of output line start for sub picture
Lower 8 bits of output picture height for sub picture
Upper 1 bit of output picture height for sub picture
PIP border size:
39H
3AH
3BH
3CH
3DH
3EH
3FH
68H
1
79H
0
[7:0]
[0]
79H
0
40H
[7:0]
11H
[7:4] Border width / 2;
[3:0] Border height / 2.
41H
42H
PIP_PS_OBY [7:0]
PIP_PS_OBC [7:0]
[7:0]
[7:0]
80H
00H
PIP border luma, Y
PIP border chroma:
[7:4] Border U[7:4], U[3:0] = 0;
[3:0] Border V[7:4], V[3:0] = 0.
De-interlace Control Registers
Address
Signal
DIL_CTL
Bit Pos
Default
Description
[7:1] Reserved;
44H
[7:0]
0
[0] Disable movie mode.
45H
46H
DIL_DM_TH
DIL_DM_START
[7:0]
[7:0]
14H
2
Movie mode detection threshold
Movie mode start control. It is related to the number of tests the
chip conducts before going into the movie mode. The larger this
number is the harder to get into the movie mode.
Movie mode end control. It is related to the number of tests the
chip conducts before leaving the movie mode. The larger this
number is the harder to get out of the movie mode.
Reserved
47H
DIL_DM_END
[7:0]
2
48H
49H
4AH
4BH
4CH
4DH
4EH
DIL_TH1[7:0]
DIL_TH1[9:8]
DIL_TH2[7:0]
DIL_TH2[9:8]
DIL_TH3[7:0]
DIL_TH3[9:8]
DIL_MODE
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:6]
8
0
4
0
4
0
0
Reserved
Reserved
Reserved
Lower 8 bits of de-interlace threshold 3
Upper 2 bits of de-interlace threshold 3
00: 3D adaptive
01: 2D repeat
10: 2D adaptive
11: 3D merge
DIL_SEL
[5:0]
3CH
Controls for 3D de-interlace (when [7:6] = 00).
[5:4] 11: suggested;
[3] Combo select (when [0] = 1);
0: type 1,
[2] Reserved;
[1] Reserved;
1: type 2;
[0] 0: do not use combo mode, 1: use combo mode.
STV102 TV Video Processor
- 25 -
Data Sheet
www.smartasic.com
Adaptive Filter Control Registers
Address
50H
Signal
Bit Pos
Default
Description
AFT_DIFF_GAIN
[7:6]
0
Tag group control;
10: 8 groups;
01: 16 groups;
others: 32 groups.
Reserved
Adaptive filter edge gain.
[5]
[4:0]
0
14H
AFT_EDGE_GAIN
Edge mask result * gain > sum of data == edge
The larger the value the more edges will be preserved.
Lower 8 bits of separation between noise reduction and scaling
Upper 2 bits of separation between noise reduction and scaling
Tag threshold. If the difference between the max/min to median
is greater then this tag threshold and tagging is enabled, the
max/min will be tagged out.
51H
52H
53H
AFT_SEP[7:0]
AFT_SEP[9:8]
AFT_TAG_TH
[7:0]
[1:0]
[7:0]
8
0
24H
54H
AFT_SOB_TH
AFT_TAG_EN
AFT_MODE
[7:0]
8
1
8
SOBEL threshold for edge detection, the lower the threshold the
more edges will be preserved.
SOBEL mask has higher priority over EDGE mask (edges that
cannot pass SOBEL threshold will be tested against EDGE
threshold, non-edges need to pass both detection).
Tag enable;
55H
[7:6]
0x: no tag out;
10: tag one pixel;
11: tag two pixels.
[5:4]
[3:0]
Reserved
Adaptive filter selection (0: disable; 1: enable);
Bit 3: Adaptive filter enable
Bit 2: Mean filter enable
Bit 1: Median filter enable
Bit 0: No filter
Luma and Color Transient Improvement (LCTI) Registers
Address
Signal
Bit Pos
[7]
Default
Description
56H
Reserved.
SVM_DISABLE
SVM_POLARITY
[6]
0
0
0: SVM enabled;
Polarity of SVM signal.
0: original polarity;
1: SVM disabled.
1: inversed polarity.
SVM pulse position adjustment. The default value is 16; value
smaller than 16 results to earlier pulse; value bigger than 16
results to later pulse. Its range is from 0 to 31, and each unit is
for one pixel delay.
[5]
SVM_DELAY
[4:0]
16
57H
58H
[7:0]
[6]
[5:3]
[2:0]
[7:0]
Reserved.
CTI_BYPASS
CTI_WTHLD
CTI_GAIN
0
2
3
8
Bypass Color transient improvement
CTI half window width threshold (up to 7 pixels)
CTI gain (output slope = gain * I slope)
CTI threshold (U+V value – previous U+V value)
Find the window which the UV slope > CTI_THLD, if this
window Width > CTI_WTHLD, then do CTI within this window.
59H
CTI_THLD
STV102 TV Video Processor
- 26 -
Data Sheet
www.smartasic.com
Dynamic Peaking filter Registers
Address
Signal
Bit Pos
[7]
Default
Description
5AH
0
1
Reserved
DPF_BYPASS
LP_GAIN
[6]
Bypass Dynamic Peaking Filter
[5:0]
[7:6]
[5:0]
[7:6]
[5:0]
20H
0
Low pass gain /32 (default 20H /32 = 1, no gain)
Reserved
5BH
5CH
BP_GAIN
HP_GAIN
20H
0
Band pass gain/32 (default 20H /32 = 1, no gain)
Reserved
20H
High pass gain/32 (default 20H /32 = 1, no gain)
Black Level Expansion Registers
Address
Signal
BLE_BYPASS
BLE_GAIN
Bit Pos
[7]
Default
1
Description
Bypass Black level expansion
Black level expansion gain /32 (slope for the I luma below
BLE_THLD); output = B + gain * (input – B)
Black Level expansion threshold
5DH
[6:0]
20H
5EH
BLE_THLD
[7:0]
40H
Gamma Correction Registers
Address
Signal
Bit Pos
[4]
Default
Description
Y Gamma correction bypass
RGB Gamma correction bypass
RGB Gamma read enable (setup done)
Gamma correction threshold 1
Gamma correction threshold 2
Gamma correction threshold 3
Gamma correction threshold 4
Gamma correction threshold 5
Gamma correction threshold 6
Gamma correction threshold 7
Gamma correction gain 0
5FH
GMC_BYPASS
12H
[1]
[0]
60H
61H
62H
63H
64H
65H
66H
67H
GMC_TH1
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:6]
[5:4]
[3:2]
[1:0]
[7:6]
[5:4]
[3:2]
[1:0]
03H
0EH
20H
46H
96H
96H
96H
CH
3
GMC_TH2
GMC_TH3
GMC_TH4
GMC_TH5
GMC_TH6
GMC_TH7
GMC_GAIN0
GMC_GAIN1
GMC_GAIN2
GMC_GAIN3
GMC_GAIN4
GMC_GAIN5
GMC_GAIN6
GMC_GAIN7
GMC_SHIFT 0
GMC_SHIFT 1
GMC_SHIFT 2
GMC_SHIFT 3
GMC_SHIFT 4
GMC_SHIFT 5
GMC_SHIFT 6
GMC_SHIFT 7
Gamma correction gain 1
68H
69H
6AH
6BH
7
Gamma correction gain 2
9
Gamma correction gain 3
3
Gamma correction gain 4
1
Gamma correction gain 5
1
Gamma correction gain 6
1
Gamma correction gain 7
0
Gamma correction shift 0
0
Gamma correction shift 1
2
Gamma correction shift 2
3
Gamma correction shift 3
6CH
2
Gamma correction shift 3
1
Gamma correction shift 4
1
Gamma correction shift 5
1
Gamma correction shift 6
STV102 TV Video Processor
- 27 -
Data Sheet
www.smartasic.com
Address
6DH
6EH
6FH
70H
Signal
Bit Pos
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
Default
Description
GMC_OFST 0 [7:0]
GMC_OFST 1 [7:0]
GMC_OFST 2 [7:0]
GMC_OFST 3 [7:0]
GMC_OFST 4 [7:0]
GMC_OFST 5 [7:0]
GMC_OFST 6 [7:0]
GMC_OFST 7 [7:0]
GMC_OFST 0[11:8]
GMC_OFST 1[11:8]
GMC_OFST 2[11:8]
GMC_OFST 3[11:8]
GMC_OFST 4[11:8]
GMC_OFST 5[11:8]
GMC_OFST 6[11:8]
GMC_OFST 7[11:8]
0
16H
2DH
41H
56H
81H
81H
81H
0
Lower 8 bits of Gamma correction offset 0
Lower 8 bits of Gamma correction offset 1
Lower 8 bits of Gamma correction offset 2
Lower 8 bits of Gamma correction offset 3
Lower 8 bits of Gamma correction offset 4
Lower 8 bits of Gamma correction offset 5
Lower 8 bits of Gamma correction offset 6
Lower 8 bits of Gamma correction offset 7
Upper 2 bits of Gamma correction offset 0
Upper 2 bits of Gamma correction offset 1
Upper 2 bits of Gamma correction offset 2
Upper 2 bits of Gamma correction offset 3
Upper 2 bits of Gamma correction offset 4
Upper 2 bits of Gamma correction offset 5
Upper 2 bits of Gamma correction offset 6
Upper 2 bits of Gamma correction offset 7
71H
72H
73H
74H
75H
0
76H
77H
78H
0
0
0
0
0
0
General Filter Control Registers
Address
Signal
Bit Pos
Default
Description
General filter center pixel gain
Weight on the center pixel (#3) of the 5-pixel filter.
GAIN0 + 2 * GAIN1 + 2 * GAIN2 = 16
Sign of the gain 1
79H
GFT_GAIN0
[7:0]
10H
7AH
7BH
GFT_GAIN1_S
[7]
0
[6:4]
[3:0]
[7]
Must be 00
GFT_GAIN1
GFT_GAIN2_S
00H
0
Absolute value of general filter gain on pixels #2 and #4
Sign of the gain 2
[6:4]
[3:0]
Must be 00
GFT_GAIN2
00H
Absolute value of general filter gain on pixels #1 and #5
RGB Gamma Control Registers
Address
7FH
Signal
RGB_GAMMA
Bit Pos
[7:0]
Default
Description
Entrance to RGB gamma tables
All the RGB gamma control registers are accessed from this
address. The RGB gamma control registers are listed in the next
section.
Point Filter Control Registers
Address
Signal
DIS_SDAJ
DIS_HADJ
DIS_CADJ
DIS_LADJ
LUMA_OFST
Bit Pos
[3]
Default
Description
Disable Saturation adjustment (1 = disable)
Disable Hue adjustment (1 = disable)
Disable Contrast adjustment (1 = disable)
Disable Brightness adjustment (1 = disable)
Luminance offset
80H
1
1
1
1
0
[2]
[1]
[0]
81H
[7:0]
STV102 TV Video Processor
- 28 -
Data Sheet
www.smartasic.com
Address
82H
Signal
CONT_GAIN
HUE_SIN[7]
HUE_SIN[6:0]
HUE_COS[7]
HUE_COS{6:0}
SATU_GAIN
CB_GAIN
Bit Pos
[5:0]
[7]
[6:0]
[7:0]
[6:0]
[5:0]
[6:0]
[6:0]
Default
20H
0
Description
CONT_GAIN = Contrast gain * 32
Sign bit: 0: positive 1: negative
Absolute value of SIN of the adjusted HUE amount * 128
83H
0
84H
0
Sign bit:
0: positive 1: negative
7FH
20H
20H
20H
Absolute value of COS of the adjusted HUE amount * 128
SATU_GAIN = Saturation gain * 32
CB_GAIN = Cb gain * 32
85H
86H
87H
CR_GAIN
CR_GAIN = Cr gain * 32
Output Control Registers
Address
Signal
INT_OSD_EN
EXT_OSD_EN
EXT_OSD_PL
OFC_DBL_PXL
OFC_MODE
Bit Pos
[7]
Default
Description
Internal OSD enable
88H
0
0
0
0
1
0
[6]
External OSD enable
[5]
0: Pin OSD_EN active low
0: single pixel output
0: interlace
1: Pin OSD_EN active high
1: dual pixel output
1: progressive
[4]
[3]
OFC_FORMAT
[2:0]
000: RGB
001: 444 YUV
010: 422 YUV (-127 – +127)
011: 411 YUV
101: 444 YCbCr
110: 422 YCbCr (0 – 240)
111: 411 YCbCr
89H
8AH
8BH
8CH
8DH
OFC_HSIZE [7:0]
OFC_HSIZE [10:8]
OFC_VSIZE [7:0]
OFC_VSIZE [9:8]
O_OE_N
[7:0]
[2:0]
[7:0]
[1:0]
[6]
CFH
2
Lower 8 bits of output active pixels – 1
Upper 3 bits of output active pixels – 1
Lower 8 bits of output active lines – 1
Upper 2 bits of output active lines – 1
E3H
1
0
0: digital output enable
0: same phase output
1: digital output disabled
O_CLOCK_PL
O_FIELD_PL
O_VREF_PL
O_VSYNC_PL
O_HREF_PL
O_HSYNC_PL
O_F_SL[7:0]
O_F_SL[9:8]
O_F_SP[7:0]
O_F_SP[10:8]
O_F_EL[7:0]
O_F_EL[9:8]
O_F_EP[7:0]
O_F_EP[10:8]
O_NL[7:0]
[5]
0
1: inversed phase output
[4]
1
0: active low
0: active low
0: active low
0: active low
0: active low
1: active high between edges
1: active high
[3]
1
[2]
1
1: active high
[1]
1
1: active high
[0]
1
1: active high
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
[7:0]
[1:0]
[7:0]
[2:0]
[7:0]
[1:0]
[7:0]
[2:0]
[7:0]
[1:0]
[7:0]
[2:0]
6
Lower 8 bits (line position of field front edge within a frame)
Upper 2 bits (line position of field front edge within a frame)
Lower 8 bits (pixel position of field front edge within a frame)
Upper 3 bits (pixel position of field front edge within a frame)
Lower 8 bits (line position of field back edge within a frame)
Upper 2 bits (line position of field back edge within a frame)
Lower 8 bits (pixel position of field back edge within a frame)
Upper 3 bits (pixel position of field back edge within a frame)
Lower 8 bits (Output total line number - 1)
0
F4H
1
3FH
1H
5EH
0
70H
2
5FH
3
O_NL[9:8]
Upper 2 bits (Output total line number - 1)
Lower 8 bits (Output total pixel number per line - 1)
Upper 3 bits (Output total pixel number per line - 1)
O_NP[7:0]
O_NP[10:8]
STV102 TV Video Processor
- 29 -
Data Sheet
www.smartasic.com
Address
9AH
9BH
9CH
9DH
9EH
9FH
Signal
Bit Pos
[7:0]
[7:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[1:0]
[7:0]
[2:0]
[7:0]
[1:0]
[7:0]
[2:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
Default
80H
80H
0
Description
O_DL
O_DP
Output line delay
Output pixel delay
O_HSSP[7:0]
O_HSSP[10:8]
O_HSEP[7:0]
O_HSEP[10:8]
O_HRSP[7:0]
O_HRSP[10:8]
O_HREP[7:0]
O_HREP[10:8]
O_VS0SL[7:0]
O_VS0SL[9:8]
O_VS0SP[7:0]
O_VS0SP[10:8]
O_VS1SL[7:0]
O_VS1SL[9:8]
O_VS1SP[7:0]
O_VS1SP[10:8]
O_VSLW
O_VR0SL[7:0]
O_VR0SL[9:8]
O_VR0EL[7:0]
O_VR0EL[9:8]
O_VR1SL[7:0]
O_VR1SL[9:8]
O_VR1EL[7:0]
O_VR1EL[9:8]
Lower 8 bits (Hsync start pixel position)
Upper 3 bits (Hsync start pixel position)
0
46H
0
Lower 8 bits of output H sync end pixel position
Upper 3 bits of output H sync end pixel position
Lower 8 bits of output H ref start pixel position
Lower 3 bits of output H ref start pixel position
Lower 8 bits of output Ref end pixel position
Lower 3 bits of output H ref end pixel position
Lower 8 bits of output F0 V sync start line position
Lower 2 bits of output F0 V sync start line position
Lower 8 bits of output F0 V sync start pixel position
Lower 3 bits of output F0 V sync start pixel position
Lower 8 bits of output F1 V sync start line position
Lower 2 bits of output F1 V sync start line position
Lower 8 bits of output F1 V sync start pixel position
Lower 3 bits of output F1 V sync start pixel position
VSYNC line width
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
B0H
B1H
B2H
B3H
B4H
ABH
0
1BH
0
0
0
F4H
1
39H
1
5EH
0
6
16H
0
Lower 8 bits of output F0 V ref start line position
Lower 2 bits of output F0 V ref start line position
Lower 8 bits of output F0 V ref end line position
Lower 2 bits of output F0 V ref start line position
Lower 8 bits of output F1 V ref start line position
Lower 2 bits of output F1 V ref start line position
Lower 8 bits of output F1 V ref end line position
Lower 2 bits of output F1 V ref end line position
36H
1
4EH
1
6FH
2
Timing Generation Registers
Address
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H
C5H
Signal
TG_NRVS_E
TG_NRVS_E
TG_NRVS_O
TG_NRVS_O
TG_SCVS_E
TG_SCVS_E
TG_SCVS_O
TG_SCVS_O
TG_SCVE_E
TG_SCVE_E
TG_SCVE_O
TG_SCVE_O
TG_SCHS[7:0]
TG_SCHS[9:8]
Bit Pos
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[1:0]
Default
Description
2
Lower 8 bits of V start for noise reduction for even field
Upper 2 bits of V start for noise reduction for even field
Lower 8 bits of V start for noise reduction for odd field
Lower 2 bits of V start for noise reduction for odd field
Lower 8 bits of V start for scaling in even field
Upper 2 bits of V start for scaling in even field
Lower 8 bits of V start for scaling in odd field
Upper 2 bits of V start for scaling in odd field
Lower 8 bits of V end for scaling in even field
Upper 2 bits of V end for scaling in even field
Lower 8 bits of V end for scaling in odd field
Upper 2 bits of V end for scaling in odd field
Lower 8 bits of H start for scaling
0
2
0
2
0
4
0
E2H
1
E4H
1
12H
0
Upper 2 bits of H start for scaling
STV102 TV Video Processor
- 30 -
Data Sheet
www.smartasic.com
RAM Control Registers
Address
Signal
RAM_TRC
Bit Pos
[7:4]
[3]
Default
Description
C8H
8
RAM Trc
Reserved
RAM_TRP
[2:0]
[7:6]
[5:3]
[2:0]
[7:0]
[4:0]
[7:5]
[4:0]
2
RAM Trp
RAM Tmrd
RAM Trcd
RAM Trdum
C9H
RAM_TMRD
2
2
RAM_TRCD
RAM_TRDUM
RAM_REF_DEF[7:0]
RAM_REF_DEF [12:8]
RAM_DE_DLY
RAM_CLK_DLY
2
CAH
CBH
CCH
D9H
8
Lower 8 bits of RAM refresh time control
Upper 5 bits of RAM refresh time control
RAM data enable delay
2
0AH
RAM clock delay
Scaling Control Registers
Address
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
Signal
Bit Pos
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[3]
Default
Description
SC_STEP_Xb [7:0]
SC_STEP_Xb[15:8]
SC_STEP_Xd [7:0]
SC_STEP_Xd [7:0]
SC_STEP_Xc [7:0]
SC_STEP_Xc [15:8]
SC_WIN_S [7:0]
SC_WIN_S [7:0]
SC_WIN_E [7:0]
SC_WIN_E [7:0]
SC_STEP_Y [7:0]
SC_STEP_Y [15:8]
SC_DATA
FFH Lower 8 bits of horizontal base step for scaling
FFH Upper 8 bits of horizontal base step for scaling
0
0
Lower 8 bits of horizontal increment/decrement step
Upper 8 bits of horizontal increment/decrement step
FFH Lower 8 bits of horizontal constant step for center window
FFH Upper 8 bits of horizontal constant step for center window
0
0
0
0
Lower 8 bits of center window starting point
Upper 8 bits of center window starting point
Lower 8 bits of center window end point
Upper 8 bits of center window end point
FFH Lower 8 bits of vertical step for scaling
FFH Upper 8 bits of vertical step for scaling
00H
0
0
Data port to scaling parameter table
1: Load offset address to read parameter table
When Bit 1 is set, set this bit to read parameter table, must clear
it after check
Must set when CPU initialization of parameter table is done
1: Bypass scaling
Offset address to start reading from scaling parameter table
SC_CTL
[2]
[1]
[0]
[7:0]
0
0
00H
DEH
SC_TAB_OFFSET
Output Color Control Registers
Address
E0H
E1H
E2H
E3H
E6H
E8H
E9H
Signal
Bit Pos
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[5:0]
[7:0]
Default
Description
Lower 8 bits of Cb gain
Upper 2 bits of Cb gain
Lower 8 bits of Cr gain
Upper 2 bits of Cr gain
Internal OSD control entrance
Output R gain * 32
OFC_CB_GAIN [7:0]
OFC_CB_GAIN [9:8]
OFC_CR_GAIN [7:0]
OFC_CR_GAIN [9:8]
INT_OSD_CNTRL
OFC_R_GAIN [5:0]
OFC_R_OFST [7:0]
0
0
0
0
0
20H
0
Output R offset
STV102 TV Video Processor
- 31 -
Data Sheet
www.smartasic.com
Address
EAH
Signal
Bit Pos
[5:0]
Default
20H
0
20H
0
Description
OFC_G_GAIN [5:0]
OFC_G_OFST [7:0]
OFC_B_GAIN [5:0]
OFC_B_OFST [7:0]
Output G gain * 32
Output G offset
Output B gain * 32
Output B offset
EBH
[7:0]
ECH
EDH
[5:0]
[7:0]
DAC and PLL Control Registers
Address
Signal
Bit Pos
Default
Description
F0H
DAC1_CONTROL
[6:4]
1
SVM DAC controls;
[6]
[5]
[4]
0: use DE,
1: use DE bar;
1: use internal Vref;
1: use DAC.
0: use external Vref,
0: DAC power down,
DAC3_CONTROL
[2:0]
1
RGB DAC controls;
[2]
0: use DE,
1: use DE bar;
1: use internal Vref;
1: use DAC.
[1]
0: use external Vref,
[0]
0: DAC power down,
F1H
F2H
F3H
F4H
PLL_OUT_CNTRL
PLL_INT_CNTRL
PLL_RAM_CNTRL
PLL_CONTROL
[7:0]
[7:0]
[7:0]
[6:0]
0
0
0
[7:4]
[3:2]
[1:0]
[7:4]
[3:2]
[1:0]
[7:4]
[3:2]
[1:0]
N [3:0];
M;
R.
N [3:0];
M;
R.
N [3:0];
M;
R.
0FH [6]
pll_ram N [4];
pll_int N [4];
pll_out N [4];
[5]
[4]
[3]
[2]
[1]
[0]
1: use internal ref clock, 0: use external ref clock;
1: use pll_ram,
1: use pll_int,
1: use pll_out,
0: use external ram clock;
0: use external int clock;
0: use external output clock.
PAD Control Registers
Address
FDH
FEH
Signal
PAD_CTL [7:0]
PAD_CTL [11:8]
Bit Pos
[7:4]
[3:0]
Default
Description
DBH Pad current drive strength control;
6
[2:0]
[5:3]
[8:6]
{e4b, e4a, e2} for
{e4b, e4a, e2} for
{e4b, e4a, e2} for
[11:9] {e4b, e4a, e2} for
STV102 TV Video Processor
- 32 -
Data Sheet
www.smartasic.com
Start Register (CPU read/write)
Address
FFH
Signal
Bit Pos
Default
Description
RST_N
START
[1]
1
Data path reset; active low. This bit resets only the data path;
all the control registers are not disturbed and therefore still
contain the programmed values.
[0]
0
When EEP_DONE is active high and initialization by CPU is
done, start chip by writing one to this bit.
DEFINITION OF THE SUB-ADDRESSED REGISTERS
RGB Gamma Control Registers
The following control registers share a common entrance address, 7FH:
Sub-Address
00H
Signal
Bit Pos Default
03H
Description
Gamma correction threshold 1
R_TH1
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[0:1]
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
01H
R_TH2
0FH Gamma correction threshold 2
02H
R_TH3
19H
26H
Gamma correction threshold 3
Gamma correction threshold 4
03H
R_TH4
04H
R_TH5
3DH Gamma correction threshold 5
05H
R_TH6
62H
Gamma correction threshold 6
06H
R_TH7
9DH Gamma correction threshold 7
07H
R_GAIN0
CH
3
Gamma correction gain 0
Gamma correction gain 1
Gamma correction gain 2
Gamma correction gain 3
Gamma correction gain 4
Gamma correction gain 5
Gamma correction gain 6
Gamma correction gain 7
Gamma correction shift 0
Gamma correction shift 1
Gamma correction shift 2
Gamma correction shift 3
Gamma correction shift 3
Gamma correction shift 4
Gamma correction shift 5
Gamma correction shift 6
Lower 8 bits of Gamma correction offset 0
R_GAIN1
08H
09H
0AH
0BH
R_GAIN2
E
A
8
R_GAIN3
R_GAIN4
R_GAIN5
7
R_GAIN6
6
R_GAIN7
4
R_SHIFT 0
R_SHIFT 1
R_SHIFT 2
R_SHIFT 3
R_SHIFT 4
R_SHIFT 5
R_SHIFT 6
R_SHIFT 7
R_OFST 0 [7:0]
R_OFST 1 [7:0]
R_OFST 2 [7:0]
R_OFST 3 [7:0]
R_OFST 4 [7:0]
R_OFST 5 [7:0]
R_OFST 6 [7:0]
0
0
3
3
0CH
3
3
3
3
0DH
0EH
0FH
10H
11H
12H
13H
0
1BH Lower 8 bits of Gamma correction offset 1
2EH Lower 8 bits of Gamma correction offset 2
3BH Lower 8 bits of Gamma correction offset 3
45H
Lower 8 bits of Gamma correction offset 4
4DH Lower 8 bits of Gamma correction offset 5
59H
Lower 8 bits of Gamma correction offset 6
STV102 TV Video Processor
- 33 -
Data Sheet
www.smartasic.com
Sub-Address
14H
Signal
R_OFST 7 [7:0]
R_OFST 0[11:8]
R_OFST 1[11:8]
R_OFST 2[11:8]
R_OFST 3[11:8]
R_OFST 4[11:8]
R_OFST 5[11:8]
R_OFST 6[11:8]
R_OFST 7[11:8]
G_TH1
Bit Pos Default
Description
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[0:1]
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
80H
Lower 8 bits of Gamma correction offset 7
Upper 2 bits of Gamma correction offset 0
Upper 2 bits of Gamma correction offset 1
Upper 2 bits of Gamma correction offset 2
Upper 2 bits of Gamma correction offset 3
Upper 2 bits of Gamma correction offset 4
Upper 2 bits of Gamma correction offset 5
Upper 2 bits of Gamma correction offset 6
Upper 2 bits of Gamma correction offset 7
Gamma correction threshold 1
15H
0
0
16H
17H
18H
0
0
0
0
0
0
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
03H
G_TH2
0FH Gamma correction threshold 2
G_TH3
19H
26H
Gamma correction threshold 3
Gamma correction threshold 4
G_TH4
G_TH5
3DH Gamma correction threshold 5
G_TH6
62H
Gamma correction threshold 6
G_TH7
9DH Gamma correction threshold 7
G_GAIN0
CH
3
Gamma correction gain 0
Gamma correction gain 1
Gamma correction gain 2
Gamma correction gain 3
Gamma correction gain 4
Gamma correction gain 5
Gamma correction gain 6
Gamma correction gain 7
Gamma correction shift 0
Gamma correction shift 1
Gamma correction shift 2
Gamma correction shift 3
Gamma correction shift 3
Gamma correction shift 4
Gamma correction shift 5
Gamma correction shift 6
Lower 8 bits of Gamma correction offset 0
G_GAIN1
21H
22H
23H
24H
G_GAIN2
E
A
8
G_GAIN3
G_GAIN4
G_GAIN5
7
G_GAIN6
6
G_GAIN7
4
G_SHIFT 0
0
G_SHIFT 1
0
G_SHIFT 2
3
G_SHIFT 3
3
25H
G_SHIFT 4
3
G_SHIFT 5
3
G_SHIFT 6
3
G_SHIFT 7
3
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
G_OFST 0 [7:0]
G_OFST 1 [7:0]
G_OFST 2 [7:0]
G_OFST 3 [7:0]
G_OFST 4 [7:0]
G_OFST 5 [7:0]
G_OFST 6 [7:0]
G_OFST 7 [7:0]
G_OFST 0[11:8]
G_OFST 1[11:8]
G_OFST 2[11:8]
G_OFST 3[11:8]
G_OFST 4[11:8]
G_OFST 5[11:8]
G_OFST 6[11:8]
G_OFST 7[11:8]
0
1BH Lower 8 bits of Gamma correction offset 1
2EH Lower 8 bits of Gamma correction offset 2
3BH Lower 8 bits of Gamma correction offset 3
45H
Lower 8 bits of Gamma correction offset 4
4DH Lower 8 bits of Gamma correction offset 5
59H
Lower 8 bits of Gamma correction offset 6
Lower 8 bits of Gamma correction offset 7
Upper 2 bits of Gamma correction offset 0
Upper 2 bits of Gamma correction offset 1
Upper 2 bits of Gamma correction offset 2
Upper 2 bits of Gamma correction offset 3
Upper 2 bits of Gamma correction offset 4
Upper 2 bits of Gamma correction offset 5
Upper 2 bits of Gamma correction offset 6
Upper 2 bits of Gamma correction offset 7
80H
0
0
2FH
30H
31H
0
0
0
0
0
0
STV102 TV Video Processor
- 34 -
Data Sheet
www.smartasic.com
Sub-Address
32H
Signal
Bit Pos Default
03H
Description
Gamma correction threshold 1
B_TH1
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[0:1]
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
33H
B_TH2
0FH Gamma correction threshold 2
34H
B_TH3
19H
26H
Gamma correction threshold 3
Gamma correction threshold 4
35H
B_TH4
36H
B_TH5
3DH Gamma correction threshold 5
37H
B_TH6
62H
Gamma correction threshold 6
38H
B_TH7
9DH Gamma correction threshold 7
39H
B_GAIN0
CH
3
Gamma correction gain 0
Gamma correction gain 1
Gamma correction gain 2
Gamma correction gain 3
Gamma correction gain 4
Gamma correction gain 5
Gamma correction gain 6
Gamma correction gain 7
Gamma correction shift 0
Gamma correction shift 1
Gamma correction shift 2
Gamma correction shift 3
Gamma correction shift 3
Gamma correction shift 4
Gamma correction shift 5
Gamma correction shift 6
B_GAIN1
3AH
3BH
3CH
3DH
B_GAIN2
E
A
8
B_GAIN3
B_GAIN4
B_GAIN5
7
B_GAIN6
6
B_GAIN7
4
B_SHIFT 0
B_SHIFT 1
B_SHIFT 2
B_SHIFT 3
B_SHIFT 4
B_SHIFT 5
B_SHIFT 6
B_SHIFT 7
B_OFST 0 [7:0]
B_OFST 1 [7:0]
B_OFST 2 [7:0]
B_OFST 3 [7:0]
B_OFST 4 [7:0]
B_OFST 5 [7:0]
B_OFST 6 [7:0]
B_OFST 7 [7:0]
B_OFST 0[11:8]
B_OFST 1[11:8]
B_OFST 2[11:8]
B_OFST 3[11:8]
B_OFST 4[11:8]
B_OFST 5[11:8]
B_OFST 6[11:8]
B_OFST 7[11:8]
0
0
3
3
3EH
3
3
3
3
3FH
40H
41H
42H
43H
44H
45H
46H
47H
0
Lower 8 bits of Gamma correction offset 0
1BH Lower 8 bits of Gamma correction offset 1
2EH Lower 8 bits of Gamma correction offset 2
3BH Lower 8 bits of Gamma correction offset 3
45H
Lower 8 bits of Gamma correction offset 4
4DH Lower 8 bits of Gamma correction offset 5
59H
80H
0
0
0
Lower 8 bits of Gamma correction offset 6
Lower 8 bits of Gamma correction offset 7
Upper 2 bits of Gamma correction offset 0
Upper 2 bits of Gamma correction offset 1
Upper 2 bits of Gamma correction offset 2
Upper 2 bits of Gamma correction offset 3
Upper 2 bits of Gamma correction offset 4
Upper 2 bits of Gamma correction offset 5
Upper 2 bits of Gamma correction offset 6
Upper 2 bits of Gamma correction offset 7
48H
49H
4AH
0
0
OSD Control Registers
The following control registers are accessed from address E6H.
Sub-Address
00H
Signal
STARTX [7:0]
STARTX [10:8]
Bit Pos Default
Description
Lower 8 bits of OSD x start address
Upper 3 bits of OSD x start address
[7:0]
[2:0]
02H
0
01H
STV102 TV Video Processor
- 35 -
Data Sheet
www.smartasic.com
Sub-Address
02H
Signal
STARTY [7:0]
STARTY [10:8]
WIN_EN
Bit Pos Default
Description
[7:0]
[2:0]
[0]
02H
0
Lower 8 bits of OSD y start address
Upper 3 bits of OSD y start address
OSD window enable
03H
04H
0
WIN_SCALE
[1]
OSD window scaled up by 2 in both horizontal and vertical
directions
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
BLINK_RATE
FG_ALPHA
BG_ALPHA
FG_HLIGHT_R
FG_HLIGHT_G
FG_HLIGHT_B
BG_HLIGHT_R
BG_HLIGHT_G
BG_HLIGHT_B
DPRAM_REF
REF_FG_COLOR [4:0]
REF_BG_COLOR [7:5]
REFM_FGM
REFM_BGM
REF_INVERSE
REF_BLINK
REF_HLIGHT
[5:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSD blinking rate, in terms of number of output frames
OSD foreground transparency factor
OSD background transparency factor
OSD foreground high light color R
OSD foreground high light color G
OSD foreground high light color B
OSD background high light color R
OSD background high light color G
OSD background high light color B
OSD display RAM refresh enable
OSD refresh value for foreground color index
OSD refresh value for background color index
OSD refresh mask for foreground color index
OSD refresh mask for background color index
OSD refresh value for inverse
OSD refresh value for blinking
OSD refresh value for high light
10H
11H
[0]
[1]
[0]
[1]
[2]
[4:3]
[5]
[6]
Reserved
REF_FG_TR
REF_BG_TR
OSD refresh value for foreground transparency/opaque
OSD refresh value for background transparency/opaque
OSD refresh mask for inverse
OSD refresh mask for blinking
OSD refresh mask for high light
12H
REFM_INVERSE [0]
REFM_BLINK
[1]
[2]
REFM_HLIGHT
[4:3]
[5]
Reserved
REFM_FG_TR
REFM_BG_TR
0
0
OSD refresh mask for foreground transparency/opaque
OSD refresh mask for background transparency/opaque
When the corresponding attribute mask bit is set, during the
refresh cycle the original display RAM value is used as the
refresh value; otherwise, the refresh attribute value in register
11H will be used.
[6]
STV102 TV Video Processor
- 36 -
Data Sheet
www.smartasic.com
ELECTRICAL SPECIFICATIONS
This section presents the electrical specifications of the STV102.
Absolute Maximum Ratings
Symbol
VCC
Parameter
Power Supply
Rating
Units
V
-0.3 to 3.6
Vin
Input Voltage
-0.3 to VCC + 0.3
-0.3 to VCC +0.3
-0.3 to 6.0
-0.3 to VCC5 + 0.3
-0.3 to VCC5 +0.3
-55 to 150
V
Vout
Output Voltage
V
VCC5
Vin5
Power Supply for 5V
Input Voltage for 5V
Output Voltage for 5V
Storage Temperature
V
V
Vout5
TSTG
V
°C
Recommended Operating Conditions
Symbol
VCC
Parameter
Power Supply
Input Voltage
Min. Typ. Max. Units
3.0
0
3.3
3.6
VCC
5.25
V
V
V
V
Vin
VCC5
VIN5
Commercial Power Supply for 5V 4.75
5.0
-
Input Voltage for 5V
Commercial Junction
Operating Temperature
0
0
VCC5
TJ
25
115
°C
General DC Characteristics
Symbol
Parameter
Input Leakage
Current
Conditions
no pull – up or
pull - down
Min. Typ. Max. Units
IIL
-1
1
µA
TRI-state Leakage
Current
IOZ
-1
1
µA
CIN3
3.3V Input Capacitance
2.8
2.8
ρF
ρF
COUT3 3.3V Output Capacitance
2.7
2.7
4.9
4.9
3.3V Bi-directional
CBID3
ρF
Buffer Capacitance
CIN5
COUT5
5V Input Capacitance
5V Output Capacitance
5V Bi-directional
ρF
ρF
2.7
2.7
5.6
5.6
CBID5
ρF
Buffer Capacitance
Note: The capacitance above does not include PAD capacitance and package capacitance. One can estimate pin capacitance
by adding pad capacitance, which is about 0.5 ρF, and the package capacitance.
STV102 TV Video Processor
- 37 -
Data Sheet
www.smartasic.com
DC Electrical Characteristics for 3.3 V Operation
(Under Recommended Operating Conditions and VCC = 3.0 ~ 3.6V, TJ = 0°C to +115°C)
Symbol
VIL
Parameter
Input low voltage
Input high voltage
Schmitt trigger
Conditions
CMOS
Min.
Typ.
Max.
0.3*VCC
Units
V
V
VIH
CMOS
0.7*VCC
VT-
negative going
COMS
1.20
2.10
V
threshold voltage
Schmitt trigger positive
going threshold voltage
VT+
VOL
VOH
RI
COMS
V
V
IOH=2,4,8,12,
16,24 mA
Output low voltage
0.4
IOH=2,4,8,12,
16,24 mA
Output high voltage
2.4
V
Input
VIL=0V or
VIH=VCC
75
KΩ
pull-up /down resistance
DC Electrical Characteristics for 5V Operation
(Under Recommended Operation Conditions and VCC=4.75~5.25,TJ=0°C to +115°C)
Symbol
VIL
Parameter
Conditions
COMS
COMS
TTL
Min.
0.7*VCC
2.0
Typ.
Max.
Units
V
Input low voltage
0.3*VCC
VIH
Input high voltage
V
VIL
Input low voltage
0.8
V
VIH
Input high voltage
TTL
V
VT-
Schmitt trigger negative
going threshold voltage
Schmitt trigger positive
going threshold voltage
Schmitt trigger negative
going threshold voltage
Schmitt trigger positive
going threshold voltage
Output low voltage
Output high voltage
Input pull-up /
CMOS
1.78
3.00
1.10
1.90
V
VT+
VT-
VT+
COMS
TTL
V
V
V
TTL
VOL
VOH
RI
IOL=2,4,8,16,24mA
IOH=2,4,8,16,24mA
VIL=0V or
0.4
V
V
KΩ
3.5
50
down resistance
VIH=VCC
ORDER INFORMATION
Order Code
STV102
Temperature
Commercial 0°C ~ 70°C
Package
Speed
STV102 TV Video Processor
- 38 -
Data Sheet
相关型号：
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