SUB70N03-09BP [ETC]


型号：	SUB70N03-09BP
厂家：	ETC
描述：	TRANSISTOR \| MOSFET \| N-CHANNEL \| 30V V(BR)DSS \| 70A I(D) \| TO-263AB 晶体管\| MOSFET \| N沟道\| 30V V（ BR ） DSS \| 70A I（ D） \| TO- 263AB\n 晶体晶体管
文件：	总3页 (文件大小：206K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPICE Device Model SUP/SUB70N03-09BP

Vishay Siliconix

N-Channel 30-V (D-S), 175°C MOSFET PWM Optimized

CHARACTERISTICS

• N- and P-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical

electrical characteristics of the n-channel vertical

A novel gate-to-drain feedback capacitance network is

used to model the gate charge characteristics while

avoiding convergence difficulties of the switched C_gd

model. All model parameter values are optimized to

provide a best fit to the measured electrical data and

are not intended as an exact physical interpretation of

the device.

DMOS.

The subcircuit model is extracted and

optimized over the −55 to 125°C temperature ranges

under the pulsed 0-to10V gate drive. The saturated

output impedance is best fit at the gate bias near the

threshold voltage.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

Document Number: 71701

02-Oct-01

www.vishay.com

SPICE Device Model SUP/SUB70N03-09BP

Vishay Siliconix

SPECIFICATIONS (T_J= 25°C UNLESS OTHERWISE NOTED)

Symbo

Simulate

d Data

Measured

Data

Parameter

Test Condition

Unit

Static

Gate Threshold Voltage

On-State Drain Current^a

V_GS(th)

I_D(on)

1.5

V_DS= V_GS, I_D= 250µA

V_DS= 5 V, V_GS= 10V

604

V_GS= 10V, I_D= 30A

V_GS= 4.5V, I_D= 20A

V_GS= 10V, I_D= 30A,

T_J= 125°C

V_GS= 10V, I_D= 30A,

T_J= 175°C

0.007

0.010

0.007

0.010

Drain-Source On-State

Resistance^a

r_DS(on)

Ω

0.0085

0.0095

Forward Transconductance^a

Forward Voltage ^a

g_fs

V_SD

V_DS= 15V, I_D= 30A

I_S= 70A, V_GS= 0 V

0.92

1.1

Dynamic ^b

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge^c

Gate-Source Charge^c

Gate-Drain Charge^c

Turn-On Delay Time ^c

Rise Time ^c

C_iss

C_oss

C_rss

Q_g

Q_gs

Q_gd

t_d(on)

t_r

1484

465

153

1500

530

240

15.5

V_GS= 0V, V_DS= 25V,

f = 1 MHz

V_DS= 15V, V_GS= 5V,

I_D= 70A

V_DD= 15V, R_L= 0.21Ω

I_D≅ 70A, V_GEN= 10V,

Turn-Off Delay Time ^c

Fall Time ^c

t_d(off)

t_f

t_rr

R_G= 2.5Ω

Reverse Recovery Time

I_F= 70A, di/dt = 100 A/µs

Notes

a.Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.

b. Guaranteed by design, not subject to production testing.

Independent of operating temperature.

www.vishay.com

Document Number: 71701

02-Oct-01

SPICE Device Model SUP/SUB70N03-09BP

Vishay Siliconix

COMPARISON OF MODEL WITH MEASURED DATA (T_J=25°C UNLESS OTHERWISE NOTED)

Document Number: 71701

02-Oct-01

www.vishay.com

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