SX20AA75-I/PQ_技术文档

January 19, 2000

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Configurable Communications Controllers with EE/Flash Program

Memory, In-System Programming Capability and On-Chip Debug

1.0 PRODUCT OVERVIEW

teristics enables the device to implement hard real-time

functions as software modules (Virtual Peripheral™) to

replace traditional hardware functions.

1.1 Introduction

The Scenix SX family of configurable communications

controllers are fabricated in an advanced CMOS process

technology. The advanced process, combined with a

RISC-based architecture, allows high-speed computa-

tion, flexible I/O control, and efficient data manipulation.

Throughput is enhanced by operating the device at fre-

quencies up to 50/75 MHz and by optimizing the instruc-

tion set to include mostly single-cycle instructions. In

addition, the SX architecture is deterministic and totally

reprogramable. The unique combination of these charac-

On-chip functions include a general-purpose 8-bit timer

with prescaler, an analog comparator, a brown-out detec-

tor, a watchdog timer, a power-save mode with multi-

source wakeup capability, an internal R/C oscillator, user-

selectable clock modes, and high-current outputs.

RTCC

OSC1

OSC2

OSC

8-bit Watchdog

Tim er (W DT)

8-bit Tim er

RTCC

Driver

Clock

Select

4M Hz

Internal

RC OSC

÷

4 or 1

÷

Interrupt Stack

8

System Clock

M CLR

Prescaler for RTCC

or

Prescaler for W DT

Power-On

Reset

Analog

Comp

3

Interrupt

RESET

MIW U

8

Port B

8

Brown-Out

8

System

Clock

MIW U

Internal Data Bus

8

W

In-System

PC

3 Level

Stack

Debugging

Port A

4

8

Port C

8

ALU

FSR

PC

Address

Fetch

In-System

Programm ing

Instruction

Pipeline

Decode

136 Bytes

SRAM

STATUS

OPTION

M ODE

Executive

2k Words

EEPROM

Address

12

Write Back

W rite Data

Read Data

Instruction

8

12

IREAD

Figure 1-1. Block Diagram

Scenix™ and the Scenix logo are trademarks of Scenix Semiconductor, Inc.

I²C™ is a trademark of Philips Corporation

All other trademarks mentioned in this document are property of their respec-

tive companies.

Microwire™ is a trademark of National Semiconductor Corporation

- 1 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Table of Contents

1.0

Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

10.0 Real Time Clock (RTCC)/Watchdog Timer . . . . . . . . . . . . .23

1.1

1.2

1.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

10.1

10.2

10.3

RTCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . .23

The Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.3.1

1.3.2

The Virtual Peripheral Concept . . . . . . . . 4

The Communications Controller . . . . . . . . 4

11.0 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

12.0 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

13.0 Brown-Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

14.0 Register States Upon DiffeRent reset operations . . . . . . .29

15.0 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

1.4

1.5

Programming and Debugging Support . . . . . . . . . . 4

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.0

3.0

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

15.1

15.2

15.3

15.4

15.5

15.6

15.7

15.8

15.9

15.10

Instruction Set Features . . . . . . . . . . . . . . . . . . . . .30

Instruction Execution . . . . . . . . . . . . . . . . . . . . . . .30

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . .30

RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . .31

The Bank Instruction . . . . . . . . . . . . . . . . . . . . . . .31

Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Input/Output Operation . . . . . . . . . . . . . . . . . . . . . .31

Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . .31

Loop Counting and Data Pointing Testing . . . . . . .31

Branch and Loop Call Instructions . . . . . . . . . . . . .31

15.10.1 Jump Operation . . . . . . . . . . . . . . . . . . .31

15.10.2 Page Jump Operation . . . . . . . . . . . . . .32

15.10.3 Call Operation . . . . . . . . . . . . . . . . . . . .32

15.10.4 Page Call Operation . . . . . . . . . . . . . . . .32

Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . .32

Subroutine Operation . . . . . . . . . . . . . . . . . . . . . . .33

15.12.1 Push Operation . . . . . . . . . . . . . . . . . . .33

15.12.2 Pop Operation . . . . . . . . . . . . . . . . . . . .33

Comparison and Conditional Branch Instructions .34

Logical Instruction . . . . . . . . . . . . . . . . . . . . . . . . .34

Shift and Rotate Instructions . . . . . . . . . . . . . . . . .34

Complement and SWAP . . . . . . . . . . . . . . . . . . . .34

Key to Abbreviations and Symbols . . . . . . . . . . . . .34

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

Reading and Writing the Ports . . . . . . . . . . . . . . . . .7

3.1.1 Read-Modify-Write Considerations . . . . . 9

Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.2

3.2.1

3.2.2

3.2.3

MODE Register . . . . . . . . . . . . . . . . . . . . 9

Port Configuration Registers . . . . . . . . . . 9

Port Configuration Upon Reset . . . . . . . 10

4.0

5.0

Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

PC Register (02h) . . . . . . . . . . . . . . . . . . . . . . . . .11

STATUS Register (03h) . . . . . . . . . . . . . . . . . . . . . 11

OPTION Register . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.11

15.12

Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . 13

5.1

5.2

5.3

FUSE Word (Read/Program at FFFh in main memory

map) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

FUSEX Word (Read/Program via Programming

Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DEVICE Word (Hard-Wired Read-Only) . . . . . . . . 14

15.13

15.14

15.15

15.16

15.17

6.0

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1.1

6.1.2

Program Counter . . . . . . . . . . . . . . . . . .15

Subroutine Stack . . . . . . . . . . . . . . . . . .15

16.0 Instruction Set Summary Table . . . . . . . . . . . . . . . . . . . . . .35

16.1 Equivalent Assembler Mnemonics . . . . . . . . . . . . .38

17.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.2

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2.1 File Select Register (04h) . . . . . . . . . . . 15

Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

17.1

17.2

17.3

17.4

17.5

17.6

17.7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .39

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .40

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .41

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .42

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .43

Comparator DC and AC Specifications . . . . . . . . .43

Typical Performance Characteristics. . . . . . . . . . . .44

7.0

7.1

7.2

Multi-Input Wakeup . . . . . . . . . . . . . . . . . . . . . . . . 17

Port B MIWU/Interrupt Configuration . . . . . . . . . . . 18

8.0

9.0

Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.1

9.2

9.3

XT, LP or HS modes . . . . . . . . . . . . . . . . . . . . . . .21

External RC Mode . . . . . . . . . . . . . . . . . . . . . . . . .23

Internal RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23

18.0 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

- 2 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Hardware Peripheral Features

1.2 Key Features

• One 8-bit Real Time Clock/Counter (RTCC) with pro-

gramable 8-bit prescaler

50 MIPS Performance

• Watchdog Timer (shares the RTCC prescaler)

• Analog comparator

• SX18AC/SX20AC/SX28AC: DC - 50 MHz operation

SX18AC75/SX20AC75/SX28AC75: DC - 75 MHz

• Brown-out detector

• SX18AC/SX20AC/SX28AC: 20 ns instruction cycle,

60 ns internal interrupt response

• Multi-Input Wakeup logic on 8 pins

SX18AC75/SX20AC75/SX28AC75: 13.3 ns instruction

cycle, 39.9 ns internal interrupt response

• Internal RC oscillator with configurable rate from 31.25

kHz to 4 MHz

• 1 instruction per clock (branches 3)

• Power-On-Reset

EE/FLASH Program Memory and SRAM Data Memory

• Access time of < 10 ns provides single cycle access

• EE/Flash rated for > 10,000 rewrite cycles

• 2048 Words EE/Flash program memory

• 136x8 bits SRAM data memory

Packages

• 18-pin SOP/DIP, 20-pin SSOP, 28-pin SOP/DIP/SSOP

Programming and Debugging Support

• On- chip in-system programming support with serial

and parallel interfaces

CPU Features

• In-system serial programming via oscillator pins

• On-chip in-System debugging support logic

• Compact instruction set

• All instructions are single cycle except branch

• Real-time emulation, full program debug, and integrat-

ed development environment offered by third party tool

vendors

• Eight-level push/pop hardware stack for subroutine

linkage

• Fast table lookup capability through run-time readable

code (IREAD instruction)

• Totally predictable program execution flow for hard

real-time applications

Fast and Deterministic Interrupt

• Jitter-free 3-cycle internal interrupt response

• Hardware context save/restore of key resources such

as PC, W, STATUS, and FSR within the 3-cycle inter-

rupt response time

• External wakeup/interrupt capability on Port B (8 pins)

Flexible I/O

• All pins individually programmable as I/O

• Inputs are TTL or CMOS level selectable

• All pins have selectable internal pull-ups

• Selectable Schmitt Trigger inputs on Ports B, and C

• All outputs capable of sourcing/sinking 30 mA

• Port A outputs have symmetrical drive

• Analog comparator support on Port B (RB0 OUT, RB1

IN-, RB2 IN+)

• Selectable I/O operation synchronous to the oscillator

clock

- 3 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

• Delta/Sigma ADC

1.3 Architecture

• DTMF generation/detection

• PSK/FSK generation/detection

• FFT/DFT based algorithms

1.3.2 The Communications Controller

The SX devices use a modified Harvard architecture.

This architecture uses two separate memories with sepa-

rate address buses, one for the program and one for

data, while allowing transfer of data from program mem-

ory to SRAM. This ability allows accessing data tables

from program memory. The advantage of this architec-

ture is that instruction fetch and memory transfers can be

overlapped with a multi-stage pipeline, which means the

next instruction can be fetched from program memory

while the current instruction is being executed using data

from the data memory.

The combination of the Scenix hardware architecture and

the Virtual Peripheral concept create a powerful, creative

platform for the communications design communities: SX

communications controller. Its high processing power,

recofigurability, cost-effectiveness, and overall design

freedom give the designer the power to build products for

the future with the confidence of knowing that they can

keep up with innovation in standards and other areas.

Scenix has developed a revolutionary RISC-based archi-

tecture and memory design techniques that is 20 times

faster than conventional MCUs, deterministic, jitter free,

and totally reprogramable.

1.4 Programming and Debugging Support

The SX devices are currently supported by third party

tool vendors. On-chip in-system debug capabilities have

been added, allowing tools to provide an integrated

development environment including editor, macro assem-

bler, debugger, and programmer. Un-obtrusive in-system

programming is provided through the OSC pins. There is

no need for a bon-out chip, so the user does not have to

worry about the potential variations in electrical charac-

teristics of a bond-out chip and the actual chip used in the

target applications. the user can test and revise the fully

debugged code in the actual SX, in the actual application,

and get to production much faster.

The SX family implements a four-stage pipeline (fetch,

decode, execute, and write back), which results in execu-

tion of one instruction per clock cycle. For example, at

the maximum operating frequency of 50 MHz, instruc-

tions are executed at the rate of one per 20-ns clock

cycle.

1.3.1 The Virtual Peripheral Concept

Virtual Peripheral concept enables the “software system

on a chip” approach. Virtual Peripheral, a software mod-

ule that replaces a traditional hardware peripheral, takes

advantage of the Scenix architecture’s high performance

and deterministic nature to produce same results as the

hardware peripheral with much greater flexibility.

1.5 Applications

Emerging applications and advances in existing ones

require higher performance while maintaining low cost

and fast time-to-production.

The speed and flexibility of the Scenix architecture com-

plemented with the availability of the Virtual Peripheral

library, simultaneously address a wide range of engineer-

ing and product development concerns. They decrease

the product development cycle dramatically, shortening

time to production to as little as a few days.

The device provides solutions for many familiar applica-

tions such as process controllers, electronic appli-

ances/tools, security/monitoring systems, consumer

automotive, sound generation, motor control, and per-

sonal communication devices. In addition, the device is

suitable for applications that require DSP-like capabili-

ties, such as closed-loop servo control (digital filters), dig-

ital answering machines, voice notation, interactive toys,

and magnetic-stripe readers.

Scenix’s time-saving Virtual Peripheral library gives the

system designers a choice of ready-made solutions, or a

head start on developing their own peripherals. So, with

Virtual Peripheral modules handling established func-

tions, design engineers can concentrate on adding value

to other areas of the application.

Furthermore, the growing Virtual Peripheral library fea-

tures new components, such as the Internet Protocol

stack, and communication interfaces, that allow design

engineers to embed Internet connectivity into all of their

products at extremely low cost and very little effort.

The concept of Virtual Peripheral combined with in-sys-

tem re-programmability provides a power development

platform ideal for the communications industry because

of the numerous and rapidly evolving standards and pro-

tocols.

Overall, the concept of Virtual Peripheral provides bene-

fits such as using a more simple device, reduced compo-

nent count, fast time to market, increased flexibility in

design, customization to your application, and ultimately

overall system cost reduction.

Some examples of Virtual Peripheral modules are:

2

• Communication interfaces such as I C™, Microwire™

(µ-Wire), SPI, IrDA Stack, UART, and Modem func-

tions

• Frequency generation and measurement

• PPM/PWM output

- 4 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

2.0 CONNECTION DIAGRAMS

2.1 Pin Assignments

SX 28-PIN

28

1

SX 20-PIN

28

1

Vss

RTCC

MCLR

OSC1

OSC2

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RTCC

MCLR

OSC1

OSC2

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

SX 18-PIN

27

2

27

2

V

dd

26

3

26

25

24

23

n.c.

Vss

n.c.

3

4

5

6

V

20

19

18

RA2

RA3

RTCC

MCLR

Vss

1

2

3

4

RA1

RA0

OSC1

dd

RA2

RA3

RTCC

MCLR

Vss

RB0

RB1

RB2

RB3

1

2

3

4

5

6

7

8

9

RA1

17 RA0

18

25

4

24

5

RA0

RA1

RA2

RA3

RB0

OSC1

OSC2

16

15

14

13

12

11

10

23

6

17 OSC2

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

22

7

22

21

20

19

18

17

16

15

16

15

5

6

V

7

8

9

10

11

12

13

14

dd

V

dd

21

8

Vss

RB7

RB6

RB5

RB4

20

9

RB7

RB6

RB5

RB4

7

8

9

10

14

13

12

11

RB0

RB1

RB2

RB3

19

RB1 10

RB2 11

RB3 12

RB4 13

Vss 14

18

17

16

15

RB6

RB5

RB6

RB5

DIP/SOP

SSOP

DIP/SOP

2.2 Pin Descriptions

Name

RA0

Pin Type Input Levels

Description

I/O

I

TTL/CMOS

TTL/CMOS/ST

Bidirectional I/O Pin; symmetrical source / sink capability

Bidirectional I/O Pin; comparator output; MIWU input

RA1

RA2

RA3

RB0

RB1

TTL/CMOS/ST Bidirectional I/O Pin; comparator negative input; MIWU input

RB2

TTL/CMOS/ST

Bidirectional I/O Pin; comparator positive input; MIWU input

Bidirectional I/O Pin; MIWU input

RB3

RB4

TTL/CMOS/ST Bidirectional I/O Pin; MIWU input

RB5

TTL/CMOS/ST

Bidirectional I/O Pin; MIWU input

RB6

RB7

TTL/CMOS/ST Bidirectional I/O Pin; MIWU input

RC0

TTL/CMOS/ST

Bidirectional I/O pin

RC1

RC2

TTL/CMOS/ST Bidirectional I/O pin

RC3

TTL/CMOS/ST

Bidirectional I/O pin

RC4

RC5

TTL/CMOS/ST Bidirectional I/O pin

RC6

TTL/CMOS/ST

Bidirectional I/O pin

RC7

TTL/CMOS/ST

Bidirectional I/O pin

RTCC

MCLR

OSC1/In/Vpp

ST

Input to Real-Time Clock/Counter

Master Clear reset input – active low

Crystal oscillator input – external clock source input

I

Crystal oscillator output – in R/C mode, internally pulled to V through weak

pull-up

dd

OSC2/Out

O

CMOS

V

Positive supply pin

Ground pin

P

–

dd

Vss

Note:I = input, O = output, I/O = Input/Output, P = Power, TTL = TTL input, CMOS = CMOS input,

ST = Schmitt Trigger input, MIWU = Multi-Input Wakeup input

- 5 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

2.3 Part Numbering

Table 2-1. Ordering Information

Operating

Frequency (MHz)

EE/Flash

(Words)

RAM

(Bytes)

Device

SX18AC/SO

SX18AC-I/SO

SX18AC75/SO

Pins

I/O

Temp. ( C)

°

18

12

50

75

2K

136

⁰°C to +70°C

^-40°C to +85°C

⁰°C to +70°C

SX18AC/DP

SX18AC-I/DP

SX18AC75/DP

18

12

50

75

2K

136

⁰°C to +70°C

^-40°C to +85°C

⁰°C to +70°C

SX20AC/SS

SX20AC-I/SS

SX20AC75/SS

20

12

50

75

2K

136

⁰°C to +70°C

^-40°C to +85°C

⁰°C to +70°C

SX28AC/SO

SX28AC-I/SO

SX28AC75/SO

28

20

50

75

2K

136

⁰°C to +70°C

^-40°C to +85°C

⁰°C to +70°C

SX28AC/DP

SX28AC-I/DP

SX28AC75/DP

28

20

50

75

2K

136

⁰°C to +70°C

^-40°C to +85°C

⁰°C to +70°C

SX28AC/SS

SX28AC-I/SS

SX28AC75/SS

28

20

50

75

2K

136

⁰°C to +70°C

^-40°C to +85°C

⁰°C to +70°C

DP = DIP

SX18ACXX-I/SO

SO = SOP

SS = SSOP

TQ = Tiny PQFP

PQ = PQFP

Package Type

Extended Temperature

Speed

Blank =

0°C to +70°C

I = -40°C to +85°C

Memory Size

Feature Set

Blank =

75 =

50 MHz

75 MHz

100 = 100 MHz

Pin Count

SceniX

A = 512 word

B =

C =

D =

1k word

2k word

4k word

Figure 2-1. Part Number Reference Guide

- 6 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

3.0 PORT DESCRIPTIONS

The device contains a 4-bit I/O port (Port A) and two 8-bit

I/O ports (Port B, Port C). Port A provides symmetrical

drive capability. Each port has three associated 8-bit reg-

isters (Direction, Data, TTL/CMOS Select, and Pull-Up

Enable) to configure each port pin as Hi-Z input or output,

to select TTL or CMOS voltage levels, and to enable/dis-

able the weak pull-up resistor. The upper four bits of the

registers associated with Port A are not used. The least

significant bit of the registers corresponds to the least

significant port pin. To access these registers, an appro-

priate value must be written into the MODE register.

The associated registers allow for each port bit to be indi-

vidually configured under software control as shown

below:

Table 3-1. Port Configuration

Data Direction

Registers:

TTL/CMOS

Select Registers: Registers:

Pullup Enable

RA, RB, RC

LVL_A, LVL_B,

LVL_C

PLP_A, PLP_B,

PLP_C

0

1

0

1

0

1

Hi-Z

Input

Output

CMOS

TTL

Enable Disable

Upon power-up, all bits in these registers are initialized to

“1”.

MODE

WR

V

dd

RA

Direction

0 = Output

1 = Hi-Z Input

Pullup

WR

PLP_A

0 = Pullup Enable

1 = Pullup Disable

WR

RA Data

Port A PIN

WR

LVL_A

0 = CMOS

1 = TTL

TTL Buffer

M

U

X

RD

CMOS Buffer

Port A INPUT

Figure 3-1. Port A Configuration

3.1 Reading and Writing the Ports

The three ports are memory-mapped into the data mem-

ory address space. To the CPU, the three ports are avail-

able as the RA, RB, and RC file registers at data memory

addresses 05h, 06h, and 07h, respectively.

Writing to a port data register sets the voltage levels of

the corresponding port pins that have been configured to

operate as outputs. Reading from a register reads the

voltage levels of the corresponding port pins that have

been configured as inputs.

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

MODE

V

dd

WR

RB or RC

Direction

Pullup Resistor

⁽~^20kΩ)

0 = Output

1 = Hi-Z Input

PLP_B or PLP_C

0 = Pullup Enable

1 = Pullup Disable

WR

Port B or

Port C PIN

RB or RC

Data

LVL_B or LVL_C

0 = CMOS

1 = TTL

WR

TTL Buffer

ST_B or ST_C

M

U

X

CMOS Buffer

0 = Schmitt Trigger Enable

1 = Schmitt Trigger Disable

M

U

X

RD

~

Port B: Input, MIWU, Comparator

Port C: Input Only

Schmitt Trigger Buffer

Figure 3-2. Port B, Port C Configuration

For example, suppose all four Port A pins are configured

as outputs and with RA0 and RA1 to be high, and RA2

and RA3 to be low:

When a write is performed to a bit position for a port that

has been configured as an input, a write to the port data

register is still performed, but it has no immediate effect

on the pin. If later that pin is configured to operate as an

output, it will reflect the value that has been written to the

data register.

mov

W,#$03

;load W with the value 03h

;(bits 0 and 1 high)

mov

$05,W

;write 03h to Port A data

;register

When a read is performed from a bit position for a port,

the operation is actually reading the voltage level on the

pin itself, not necessarily the bit value stored in the port

data register. This is true whether the pin is configured to

operate as an input or an output. Therefore, with the pin

configured to operate as an input, the data register con-

tents have no effect on the value that you read. With the

pin configured to operate as an output, what is read gen-

erally matches what has been written to the register.

The second “mov” instruction in this example writes the

Port A data register (RA), which controls the output levels

of the four Port A pins, RA0 through RA3. Because Port

A has only four I/O pins, only the four least significant bits

of this register are used. The four high-order register bits

are “don’t care” bits. Port B and Port C are both eight bits

wide, so the full widths of the RB and RC registers are

used.

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

3.1.1 Read-Modify-Write Considerations

After a value is written to the MODE register, that setting

remains in effect until it is changed by writing to the

MODE register again. For example, you can write the

value 0Eh to the MODE register just once, and then write

to each of the three pullup configuration registers using

the three “mov !rx,W” instructions.

Caution must be exercised when performing two succes-

sive read-modify-write instructions (SETB or CLRB oper-

ations) on I/O port pin. Input data used for an instruction

must be valid during the time the instruction is executed,

and the output result from an instruction is valid only after

that instruction completes its operation. Unexpected

results from successive read-modify-write operations on

I/O pins can occur when the device is running at high

speeds. Although the device has an internal write-back

section to prevent such conditions, it is still recom-

mended that the user program include a NOP instruction

as a buffer between successive read-modify-write

instructions performed on I/O pins of the same port.

Table 3-3. MODE Register and Port

Control Register Access

MODE Reg. mov !RA,W mov !RB,W mov !RC,W

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

not used

LVL_A

CMP_B

WKPND_B

WKED_B

WKEN_B

ST_B

not used

ST_C

Also note that reading an I/O port is actually reading the

pins, not the output data latches. That is, if the pin output

driver is enabled and driven high while the pin is held low

externally, the port pin will read low.

3.2 Port Configuration

Each port pin offers the following configuration options:

LVL_B

LVL_C

• data direction

PLP_A

PLP_B

PLP_C

• input voltage levels (TTL or CMOS)

• pullup type (pullup resistor enable or disable)

• Schmitt trigger input (for Port B and Port C only)

RA Direction RB Direction RC Direction

The following code example shows how to program the

pullup control registers.

Port B offers the additional option to use the port pins for

the Multi-Input Wakeup/Interrupt function and/or the ana-

log comparator function.

mov M,#$0E ;MODE=0Eh to access port pullup

;registers

Port configuration is performed by writing to a set of con-

trol registers associated with the port. A special-purpose

instruction is used to write these control registers:

mov W,#$03 ;W = 0000 0011

mov !RA,W

;disable pullups for A0 and A1

• mov !RA,W (move W to Port A control register)

• mov !RB,W (move W to Port B control register)

• mov !RC,W (move W to Port C control register)

mov W,#$FF ;W = 1111 1111

mov !RB,W

;disable all pullups for B0-B7

Each one of these instructions writes a port control regis-

ter for Port A, Port B, or Port C. There are multiple control

registers for each port. To specify which one you want to

access, you use another register called the MODE regis-

ter.

mov W,#$00 ;W = 0000 0000

mov !RC,W

;enable all pullups for C0-C7

First the MODE register is loaded with 0Eh to select

access to the pullup control registers (PLP_A, PLP_B,

and PLP_C). Then the MOV !rx,W instructions are used

to specify which port pins are to be connected to the

internal pullup resistors. Setting a bit to 1 disconnects the

corresponding pullup resistor, and clearing a bit to 0 con-

nects the corresponding pullup resistor.

3.2.1 MODE Register

The MODE register controls access to the port configura-

tion registers. Because the MODE register is not mem-

ory-mapped, it is accessed by the following special-

purpose instructions:

3.2.2 Port Configuration Registers

• mov M, #lit (move literal to MODE register)

• mov M,W (move W to MODE register)

• mov W,M (move MODE register to W)

The port configuration registers that you control with the

MOV !rx,W instruction operate as described below.

RA, RB, and RC Data Direction Registers (MODE=0Fh)

The value contained in the MODE register determines

which port control register is accessed by the “mov !rx,W”

instruction as indicated in Table 3-3. MODE register val-

ues not listed in the table are reserved for future expan-

sion and should not be used. Therefore, the MODE

register should always contain a value from 08h to 0Fh.

Upon reset, the MODE register is initialized to 0Fh, which

enables access to the port direction registers.

Each register bit sets the data direction for one port pin.

Set the bit to 1 to make the pin operate as a high-imped-

ance input. Clear the bit to 0 to make the pin operate as

an output.

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

PLP_A, PLP_B, and PLP_C: Pullup Enable Registers

(MODE=0Eh)

WKPND_B: Wakeup Pending Bit Register

(MODE=09h)

Each register bit determines whether an internal pullup

resistor is connected to the pin. Set the bit to 1 to discon-

nect the pullup resistor or clear the bit to 0 to connect the

pullup resistor.

When you access the WKPND_B register using MOV

!RB,W, the CPU does an exchange between the contents

of W and WKPND_B. This feature lets you read the

WKPND_B register contents. Each bit indicates the sta-

tus of the corresponding MIWU pin. A bit set to 1 indi-

LVL_A, LVL_B, and LVL_C: Input Level Registers

(MODE=0Dh)

cates that

a

valid edge has occurred on the

corresponding MIWU pin, triggering a wakeup or inter-

rupt. A bit set to 0 indicates that no valid edge has

occurred on the MIWU pin.

Each register bit determines the voltage levels sensed on

the input port, either TTL or CMOS, when the Schmitt

trigger option is disabled. Program each bit according to

the type of device that is driving the port input pin. Set the

bit to 1 for TTL or clear the bit to 0 for CMOS.

CMP_B: Comparator Register (MODE=08h)

When you access the CMP_B register using MOV

!RB,W, the CPU does an exchange between the contents

of W and CMP_B. This feature lets you read the CMP_B

register contents. Clear bit 7 to enable operation of the

comparator. Clear bit 6 to place the comparator result on

the RB0 pin. Bit 0 is a result bit that is set to 1 when the

voltage on RB2 is greater than RB1, or cleared to 0 oth-

erwise. (For more information using the comparator, see

Section 11.0.)

ST_B and ST_C: Schmitt Trigger Enable Registers

(MODE=0Ch)

Each register bit determines whether the port input pin

operates with a Schmitt trigger. Set the bit to 1 to disable

Schmitt trigger operation and sense either TTL or CMOS

voltage levels; or clear the bit to 0 to enable Schmitt trig-

ger operation.

WKEN_B: Wakeup Enable Register (MODE=0Bh)

3.2.3 Port Configuration Upon Reset

Each register bit enables or disables the Multi-Input

Wakeup/Interrupt (MIWU) function for the corresponding

Port B input pin. Clear the bit to 0 to enable MIWU opera-

tion or set the bit to 1 to disable MIWU operation. For

more information on using the Multi-Input Wakeup/Inter-

rupt function, see Section 7.0.

Upon reset, all the port control registers are initialized to

FFh. Thus, each pin is configured to operate as a high-

impedance input that senses TTL voltage levels, with no

internal pullup resistor connected. The MODE register is

initialized to 0Fh, which allows immediate access to the

data direction registers using the “MOV !rx,W” instruction.

WKED_B: Wakeup Edge Register (MODE=0Ah)

Each register bit selects the edge sensitivity of the Port B

input pin for MIWU operation. Clear the bit to 0 to sense

rising (low-to-high) edges. Set the bit to 1 to sense falling

(high-to-low) edges.

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

4.0 SPECIAL-FUNCTION REGISTERS

The CPU uses a set of special-function registers to con-

trol the operation of the device.

the STATUS register with a result that is different than

intended.

The CPU registers include an 8-bit working register (W),

which serves as a pseudo accumulator. It holds the sec-

ond operand of an instruction, receives the literal in

immediate type instructions, and also can be program-

selected as the destination register.

PA2

PA1

PA0

TO

PD

Z

DC

C

Bit 7

Bit 0

Bit 7-5: Page select bits PA2:PA0

000 = Page 0 (000h – 01FFh)

001 = Page 1 (200h – 03FFh)

010 = Page 2 (400h – 05FFh)

011 = Page 3 (600h – 07FFh)

A set of 31 file registers serves as the primary accumula-

tor. One of these registers holds the first operand of an

instruction and another can be program-selected as the

destination register. The first eight file registers include

the Real-Time Clock/Counter register (RTCC), the lower

eight bits of the 11-bit Program Counter (PC), the 8-bit

STATUS register, three port control registers for Port A,

Port B, Port C, the 8-bit File Select Register (FSR), and

INDF used for indirect addressing.

Bit 4: Time Out bit, TO

1 = Set to 1 after power up and upon exe-

cution of CLRWDT or SLEEP instructions

0 = A watchdog time-out occurred

Bit 3: Power Down bit, PD

The five low-order bits of the FSR register select one of

the 31 file registers in the indirect addressing mode. Call-

ing for the file register located at address 00h (INDF) in

any of the file-oriented instructions selects indirect

addressing, which uses the FSR register. It should be

noted that the file register at address 00h is not a physi-

cally implemented register. The CPU also contains an 8-

level, 11-bit hardware push/pop stack for subroutine link-

age.

1= Set to a 1 after power up and upon ex-

ecution of the CLRWDT instruction

0 = Cleared to a ‘0’ upon execution of

SLEEP instruction

Bit 2: Zero bit, Z

1 = Result of math operation is zero

0 = Result of math operation is non-zero

Bit 1: Digit Carry bit, DC

Table 4-1. Special-Function Registers

After Addition:

Addr

00h

Name

INDF

Function

1 = A carry from bit 3 occurred

0 = No carry from bit 3 occurred

After Subtraction:

Used for indirect addressing

Real Time Clock/Counter

Program Counter (low byte)

Holds Status bits of ALU

File Select Register

01h

02h

03h

04h

05h

06h

07h

RTCC

PC

1 = No borrow from bit 3 occurred

0 = A borrow from bit 3 occurred

STATUS

FSR

RA

Bit 0: Carry bit, C

After Addition:

Port RA Control register

Port RB Control register

Port RC Control register

1 = A carry from bit 7 of the result occurred

RB

0 = No carry from bit 7 of the result oc-

curred

RC*

After Subtraction:

*In the SX18 package, Port C is not used, and address

07h is available as a general-purpose RAM location.

1 = No borrow from bit 7 of the result oc-

curred

4.1 PC Register (02h)

The PC register holds the lower eight bits of the program

counter. It is accessible at run time to perform branch

operations.

0 = A borrow from bit 7 of the result oc-

curred

Rotate (RR or RL) Instructions:

The carry bit is loaded with the low or high

order bit, respectively. When CF bit is

cleared, Carry bit works as input for ADD

and SUB instructions.

4.2 STATUS Register (03h)

The STATUS register holds the arithmetic status of the

ALU, the page select bits, and the reset state. The

STATUS register is accessible during run time, except

that bits PD and TO are read-only. It is recommended

that only SETB and CLRB instructions be used on this

register. Care should be exercised when writing to the

STATUS register as the ALU status bits are updated

upon completion of the write operation, possibly leaving

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

4.3 OPTION Register

Table 4-2. Prescaler Divider Ratios

RTE

_IE

RTE

_ES

RTCC

Divide Rate

Watchdog Timer

RTW

RTS

PSA

PS2

PS1

PS0

PS2, PS1, PS0

Divide Rate

Bit 7

Bit 0

000

001

010

011

100

101

110

111

1:2

1:1

When the OPTIONX bit in the FUSE word is cleared, bits

7 and 6 of the OPTION register function as described

below.

1:4

1:2

1:8

1:4

When the OPTIONX bit is set, bits 7 and 6 of the

OPTION register read as ‘1’s.

1:16

1:32

1:64

1:128

1:256

1:8

1:16

RTW

RTCC/W register selection:

1:32

0 = Register 01h addresses W

1 = Register 01h addresses RTCC

RTCC edge interrupt enable:

1:64

1:128

RTE_IE

RTS

0 = RTCC roll-over interrupt is enabled

1 = RTCC roll-over interrupt is disabled

RTCC increment select:

Upon reset, all bits in the OPTION register are set to 1.

0 = RTCC increments on internal instruction

cycle

1 = RTCC increments upon transition on

RTCC pin

RTE_ES RTCC edge select:

0 = RTCC increments on low-to-high transi-

tions

1 = RTCC increments on high-to-low transi-

tions

PSA

Prescaler Assignment:

0 = Prescaler is assigned to RTCC, with di-

vide rate determined by PS0-PS2 bits

1 = Prescaler is assigned to WDT, and divide

rate on RTCC is 1:1

PS2-PS0 Prescaler divider (see Table 4-2)

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

5.0 DEVICE CONFIGURATION REGISTERS

The SX device has three registers (FUSE, FUSEX,

DEVICE) that control functions such as operating the

device in Turbo mode, extended (8-level deep) stack

operation, and speed selection for the internal RC oscilla-

tor. These registers are not programmable “on the fly”

during normal device operation. Instead, the FUSE and

FUSEX registers can only be accessed when the SX

device is being programmed. The DEVICE register is a

read-only, hard-wired register, programmed during the

manufacturing process.

5.1 FUSE Word (Read/Program at FFFh in main memory map)

DIV1/

IFBD

DIV0/

FOSC2

Re-

served

TURBO

SYNC

Reserved

IRC

CP

WDTE

FOSC1

FOSC0

Bit 11

Bit 0

TURBO

SYNC

Turbo mode enable:

0 =

1 =

turbo (instruction clock = osc/1)

instr clock = osc/4

Synchronous input enable (for turbo mode): This bit synchronizes the signal presented at the input pin

to the internal clock through two internal flip-flops.

0 =

1 =

enabled

disabled

IRC

Internal RC oscillator enable:

0 =

1 =

enabled - OSC1 pulled low by weak pullup, OSC2 pulled high by weak pullup

disabled - OSC1 and OSC2 behave according to FOSC2: FOSC0

DIV1: DIV0

Internal RC oscillator divider:

00b

01b

10

=

4 MHz

1 MHz

128 KHz

32 KHz

11b

IFBD

CP

Internal crystal/resonator oscillator feedback resistor:

0=

1=

disabled

enabled

Internal feedback resistor disable (external feedback required)

Internal feedback resistor enabled (valid when IRC = 1)

Code protect enable:

0 =

1 =

enabled (FUSE, code, and ID memories read back as garbled data)

disabled (FUSE, code, and ID memories can be read normally)

WDTE

Watchdog timer enable:

0 =

1 =

disabled

enabled

FOSC2: FOSC0 External oscillator configuration (valid when IRC = 1):

000b = LP1 – low power crystal (32KHz)

001b = LP2 – low power crystal/resonator (32 KHz to 1 MHz)

010b = XT1 – normal crystal/resonator (32 KHz to 10 MHz)

011b = XT2 – normal crystal/resonator (1MHz to 24 MHz)

100b = HS1 – high speed crystal/resonator (1MHz to 50 MHz)

101b = HS2 – high speed crystal/resonator (1 MHz to 50 MHz)

110b = HS3 – high speed crystal/resonator (1 MHz to 50 MHz)

111b = RC network - OSC2 is pulled high with a weak pullup (no CLKOUT output)

Note:

The frequencies are target values.

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

5.2 FUSEX Word (Read/Program via Programming Command)

OPTIONX/

STACKX

IRCTRIM2 PINS IRCTRIM1

IRCTRIM0

CF BOR1 BOR0 BORTRIM1

BORTRIM0 BP1 BP0

Bit 11

Bit 0

IRCTRIM2:

IRCTRIM0

Internal RC oscillator trim bits. This 3-bit field adjusts the operation of the internal RC oscillator to make

it operate within the target frequency range 4 MHz plus or minus 8%. Parts are shipped from the factory

untrimmed. The device relies on the programming toll to provide the trimming function.

000b = minimum frequency

111b = maximum frequency

each step about 3%

Selects the number of pins.

0 = 18/20 pins

PINS

0 = 28 pins

OPTIONX/

STACKX

OPTION Register Extension and Stack Extension. Set to 1 to disable the programmability of bit 6 and

bit 7 in the OPTION register, the RTW and RTE_IE bits (in other words, to force these two bits to 1) and

to limit the program stack size to two locations. Clear to 0 to enable programming of the RTW and

RTE_IE bits in the OPTION register, and to extend the stack size to eight locations.

CF

active low – makes carry bit input to ADD and SUB instructions.

BOR1: BOR0 Brown-Out Reset;These bits enable or disable the brown-out reset function and set the brown-out

threshold voltage as follows:

00b = 4.2V

01b = 2.6V

10b = 2.2V

11b = Brown-Out disabled

BORTRIM1: Brown-Out trim bits (parts are shipped out of factory untrimmed).

BORTRIM2

BP1:BP0

Configure Memory Size:

00b =

01b =

10b =

11b =

1 page, 1 bank

1 page, 2 banks

4 pages, 4 banks

4 pages, 8 banks (default configuration)

5.3 DEVICE Word (Hard-Wired Read-Only)

1

0

1

0

Bit 11

Bit 0

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

6.0 MEMORY ORGANIZATION

6.1 Program Memory

6.2 Data Memory

The program memory is organized as 2K, 12-bit wide

words. The program memory words are addressed

sequentially by a binary program counter. The program

counter starts at zero. If there is no branch operation, it

will increment to the maximum value possible for the

device and roll over and begin again.

The data memory consists of 136 bytes of RAM, orga-

nized as eight banks of 16 registers plus eight registers

which are not banked. Both banked and non-banked

memory locations can be addressed directly or indirectly

using the FSR (File Select Register). The special-func-

tion registers are mapped into the data memory.

Internally, the program memory has a semi-transparent

page structure. A page is composed of 512 contiguous

program memory words. The lower nine bits of the pro-

gram counter are zeros at the first address of a page and

ones at the last address of a page. This page structure

has no effect on the program counter. The program

counter will freely increment through the page bound-

aries.

6.2.1 File Select Register (04h)

Instructions that specify a register as the operand can

only express five bits of register address. This means

that only registers 00h to 1Fh can be accessed. The File

Select Register (FSR) provides the ability to access reg-

isters beyond 1Fh.

Figure 6-1 shows how FSR can be used to address RAM

locations. The three high-order bits of FSR select one of

eight SRAM banks to be accessed. The five low-order

bits select one of 32 SRAM locations within the selected

bank. For the lower 16 addresses, Bank 0 is always

accessed, irrespective of the three high-order bits. Thus,

RAM register addresses 00h through 0Fh are “global” in

that they can always be accessed, regardless of the con-

tents of the FSR.

6.1.1 Program Counter

The program counter contains the 11-bit address of the

instruction to be executed. The lower eight bits of the pro-

gram counter are contained in the PC register (02h) while

the upper bits come from the upper three bits of the STA-

TUS register (PA0, PA1, PA2). This is necessary to cause

jumps and subroutine calls across program memory

page boundaries. Prior to the execution of a branch oper-

ation, the user program must initialize the upper bits of

the STATUS register to cause a branch to the desired

page. An alternative method is to use the PAGE instruc-

tion, which automatically causes branch to the desired

page, based on the value specified in the operand field.

Upon reset, the program counter is initialized with 07FFh.

The entire data memory (including the dedicated-function

registers) consists of the lower 16 bytes of Bank 0 and

the upper 16 bytes of Bank 0 through Bank 7, for a total

of (1+8)*16 = 144 bytes. Eight of these bytes are for the

function registers, leaving 136 general-purpose memory

locations. In the 18-pin SX packages, register RC is not

used, which makes address 07h available as an addi-

tional general-purpose memory location.

6.1.2 Subroutine Stack

The subroutine stack consists of eight 11-bit save regis-

ters. A physical transfer of register contents from the pro-

gram counter to the stack or vice versa, and within the

stack, occurs on all operations affecting the stack, prima-

rily calls and returns. The stack is physically and logically

separate from data RAM. The program cannot read or

write the stack.

Below is an example of how to write to register 10h in

Bank 4:

mov

FSR,#$90

;Select Bank 4 by

;setting FSR<7:5>

;load register 10h with

;the literal 64h

mov

$10,#$64

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Function Registers

Bank 0

00

Bank 0 is always accessed for

the lower 16 addresses,

irrespective of the three high-

order bits of FSR.

INDF

Registers

(8 bytes)

RTCC

07

0F

PC

STATUS

FSR

RA

SRAM

(8 bytes)

RB

3

7

6

5

2

1

0

4

FSR

RC

F0

Bank 7

D0

Bank 6

B0

Bank 5

90

Bank 4

70

Bank 3

50

Bank 2

FF

30

Bank 1

DF

10

Bank 0

BF

9F

SRAM

(16 bytes

each bank

128 bytes

total)

7F

5F

3F

1F

Figure 6-1. Data Memory Organization

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

7.0 POWER DOWN MODE

The power down mode is entered by executing the

SLEEP instruction.

feature. The WKEN_B register (Wakeup Enable Regis-

ter) allows any Port B pin or combination of pins to cause

the wakeup. Clearing a bit in the WKEN_B register

enables the wakeup on the corresponding Port B pin. If

multi-input wakeup is selected to cause a wakeup, the

trigger condition on the selected pin can be either rising

edge (low to high) or falling edge (high to low). The

WKED_B register (Wakeup Edge Select) selects the

desired transition edge. Setting a bit in the WKED_B reg-

ister selects the falling edge on the corresponding Port B.

Clearing the bit selects the rising edge. The WKEN_B

and WKED_B registers are set to FFh upon reset.

In power down mode, only the Watchdog Timer (WDT) is

active. If the Watchdog Timer is enabled, upon execution

of the SLEEP instruction, the Watchdog Timer is cleared,

the TO (time out) bit is set in the STATUS register, and

the PD (power down) bit is cleared in the STATUS regis-

ter.

There are three different ways to exit from the power

down mode: a timer overflow signal from the Watchdog

Timer (WDT), a valid transition on any of the Multi-Input

Wakeup pins (Port B pins), or through an external reset

input on the MCLR pin.

Once a valid transition occurs on the selected pin, the

WKPND_B register (Wakeup Pending Register) latches

the transition in the corresponding bit position. A logic ‘1’

indicates the occurrence of the selected trigger edge on

the corresponding Port B pin.

To achieve the lowest possible power consumption, the

Watchdog Timer should be disabled and the device

should exit the power down mode through the Multi-Input

Wakeup (MIWU) pins or an external reset.

Upon exiting the power down mode, the Multi-Input

Wakeup logic causes program counter to branch to the

maximum program memory address (same as reset).

7.1 Multi-Input Wakeup

Multi-Input Wakeup is one way of causing the device to

exit the power down mode. Port B is used to support this

Figure 7-1 shows the Multi-Input Wakeup block diagram.

RB7 RB6

RB1 RB0

Port B

Configured

as Input

8

WKED_B

W

0 1

WKPND_B

MODE

MODE = 09

8

Wake-up : Exit Power Down

WKEN_B

8

0 = Enable

1 = Disable

Figure 7-1. Multi-Input Wakeup Block Diagram

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Here is an example of a program segment that config-

ures the RB0, RB1, and RB2 pins to operate as Multi-

Input Wakeup/Interrupt pins, sensitive to falling edges:

7.2 Port B MIWU/Interrupt Configuration

The WKPND_B register comes up with a random value

upon reset. The user program must clear the register

prior to enabling the wake-up condition or interrupts. The

proper initialization sequence is:

mov M,#$0F ;prepare to write port data

;direction registers

mov W,#$07 ;load W with the value 07h

1. Select the desired edge (through WKED_B register).

2. Clear the WKPND_B register.

mov !RB,W

;configure RB0-RB2 to be inputs

3. Enable the Wakeup condition (through WKEN_B regis-

ter).

mov M,#$0A ;prepare to write WKED_B

;(edge) register

Below is an example of how to read the WKPND_B regis-

ter to determine which Port B pin caused the wakeup or

interrupt, and to clear the WKPND_B register:

;W contains the value 07h

mov !RB,W

;configure RB0-RB2 to sense

;falling edges

mov M,#$09

mov M,#$09 ;prepare to access WKPND_B

;(pending) register

mov W,#$00 ;clear W

clr

W

mov !RB,W

;W contains WKPND_B

;contents of W exchanged

;with contents of WKPND_B

mov !RB,W

;clear all wakeup pending bits

mov M,#$0B ;prepare to write WKEN_B (enable)

;register

mov W,#$F8h ;load W with the value F8h

The final “mov” instruction in this example performs an

exchange of data between the working register (W) and

the WKPND_B register. This exchange occurs only with

Port B accesses. Otherwise, the “mov” instruction does

not perform an exchange, but only moves data from the

source to the destination.

mov !RB,W

;enable RB0-RB2 to operate as

;wakeup inputs

To prevent false interrupts, the enabling step (clearing

bits in WKEN_B) should be done as the last step in a

sequence of Port B configuration steps. After this pro-

gram segment is executed, the device can receive inter-

rupts on the RB0, RB1, and RB2 pins. If the device is put

into the power down mode (by executing the SLEEP

instruction), the device can then receive wakeup signals

on those same pins.

- 18 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

8.0 INTERRUPT SUPPORT

The device supports both internal and external maskable

interrupts. The internal interrupt is generated as a result

of the RTCC rolling over from 0FFh to 00h. This interrupt

source has an associated enable bit located in the

OPTION register. There is no pending bit associated with

this interrupt.

edge to be either positive or negative. The WKEN_B and

WKED_B registers are set to FFh upon reset. Setting a

bit in the WKED_B register selects the falling edge while

clearing the bit selects the rising edge on the correspond-

ing Port B pin.

The WKPND_B register serves as the external interrupt

pending register.

Port B provides the source for eight external software

selectable, edge sensitive interrupts. These interrupt

sources share logic with the Multi-Input Wakeup circuitry.

The WKEN_B register allows interrupt from Port B to be

individually enabled or disabled. Clearing a bit in the

WKEN_B register enables the interrupt on the corre-

sponding Port B pin. The WKED_B selects the transition

The WKPND_B register comes up a with random value

upon reset. The user program must clear the WKPND_B

register prior to enabling the interrupt. The proper

sequence is described in Section 7.2

.

Figure 8-1 shows the structure of the interrupt logic.

Port B PIN

WKED_B

RTCC

Overflow

From MODE

(MODE = 0A)

WKPND_B

From MODE

(MODE = 09)

Interrupt

STATUS

Register

PC

000

Interrupt Stack

PC

1 = Ext. Interrupt through Port B

PD bit

0 = Power Down Mode, no Ext. Interrupt

RTE_IE

OPTION

WKEN_B

Figure 8-1. Interrupt Structure

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

All interrupts are global in nature; that is, no interrupt has

priority over another. Interrupts are handled sequentially.

Figure 8-2 shows the interrupt processing sequence.

Once an interrupt is acknowledged, all subsequent global

interrupts are disabled until return from servicing the cur-

rent interrupt. The PC is pushed onto the single level

interrupt stack, and the contents of the FSR, STATUS,

and W registers are saved in their corresponding shadow

registers. The status bits PA0, PA1, and PA2 bits are

cleared after the STATUS register has been saved in its

shadow register. The interrupt logic has its own single-

level stack and is not part of the CALL subroutine stack.

The vector for the interrupt service routine is address 0.

If an external interrupt occurs during the interrupt routine,

the pending register will be updated but the trigger will be

ignored unless interrupts are disabled at the beginning of

the interrupt routine and enabled again at the end. This

also requires that the new interrupt does not occur before

interrupts are disabled in the interrupt routine. If there is a

possibility of additional interrupts occurring before they

can be disabled, the device will miss those interrupt trig-

gers. In other words, using more than one interrupt, such

as multiple external interrupts or both RTCC and external

interrupts, can result in missed or, at best, jittery interrupt

handling should one occur during the processing of

another. When handling external interrupts, the interrupt

routine should clear at least one pending register bit. The

bit that is cleared should represent the interrupt being

handled in order for the next interrupt to trigger.

Once in the interrupt service routine, the user program

must check all external interrupt pending bits (contained

in the WKPND_B register) to determine the source of the

interrupt. The interrupt service routine should clear the

corresponding interrupt pending bit. If both internal and

external interrupts are enabled, the user program may

also need to read the contents of RTCC to determine any

recent RTCC rollover. This is needed since there is no

interrupt pending bit associated with the RTCC rollover.

Upon return from the interrupt service routine, the con-

tents of PC, FSR, STATUS, and W registers are restored

from their corresponding shadow registers. The interrupt

service routine should end with instructions such as RETI

and RETIW. RETI pops the interrupt stack and the spe-

cial shadow registers used for storing W, STATUS, and

FSR (preserved during interrupt handling). RETIW

behaves like RETI but also adds W to RTCC. The inter-

rupt return instruction enables the global interrupts.

Normally it is a requirement for the user program to pro-

cess every interrupt without missing any. To ensure this,

the longest path through the interrupt routine must take

less time than the shortest possible delay between inter-

rupts.

Program

Memory

Interrupt

Service

Routine

Address 000h

PC

RETI

Interrupt

Stack

000h

PC

Interrupt

Stack

PC

W

Register

W

Register

Shadow Register

STATUS

Shadow Register

STATUS

Register

STATUS

Shadow Register

STATUS

Register

FSR

Shadow Register

FSR

Register

FSR

Shadow Register

FSR

Register

Note: The interrupt logic has its own single-level

stack and is not part of the CALL subroutine stack.

Figure 8-2. Interrupt Processing

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

9.0 OSCILLATOR CIRCUITS

SX Device

The device supports several user-selectable oscillator

modes. The oscillator modes are selected by program-

ming the appropriate values into the FUSE Word register.

These are the different oscillator modes offered:

Internal

Circuitry

SLEEP

LP: Low Power Crystal

XT: Crystal/Resonator

HS: High Speed Crystal/Resonator

RC: External Resistor/Capacitor

Internal Resistor/Capacitor

OSC1

OSC2

RS

RF

9.1 XT, LP or HS modes

In XT, LP or HS, modes, you can use either an external

resonator network or an external clock signal as the

device clock.

XTAL

C

2

1

To use an external resonator network, you connect a

crystal or ceramic resonator to the OSC1/CLKIN and

OSC2/CLKOUT pins according to the circuit configura-

tion shown in Figure 9-1. A parallel resonant crystal type

is recommended. Use of a series resonant crystal may

result in a frequency that is outside the crystal manufac-

turer specifications. Table 9-1 shows the recommended

external components associated with a crystal-based

oscillator. Table 9-2 shows the recommended external

component values for a resonator-based oscillator.

Figure 9-1. Crystal Operation (or Ceramic Resonator)

(HS, XT or LP OSC Configuration)

SX Device

Bits 0, 1 and 5 of the FUSE register (FOSC1:FOSC2) are

used to configure the different external resonator/crystal

oscillator modes. These bits allow the selection of the

appropriate gain setting for the internal driver to match

the desired operating frequency. If the XT, LP, or HS

mode is selected, the OSC1/CLKIN pin can be driven by

an external clock source rather than a resonator network,

as long as the clock signal meets the specified duty

cycle, rise and fall times, and input levels (Figure 9-2). In

this case, the OSC2/CLKOUT pin should be left open.

OSC2

OSC1

Open

Externally

Generated Clock

Figure 9-2. External Clock Input Operation

(HS, XT or LP OSC Configuration)

Table 9-1. External Component Selection for Crystal Oscillator(Vdd=5.0V)

Crystal

Frequency

R

S

FOSC2:FOSC0

C1

C2

F

010

011

100

4 MHz

8 MHz

15 pF

56 pF

33 pF

15 pF

22 pF

33 pF

22 pF

15 pF

1 MΩ

0 Ω

20 MHz

32 MHz

50* MHz

* 50 MHz fundamental crystal

- 21 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Table 9-2. External Component Selection for Murata Ceramic Resonators (Vdd=5.0V)

Resonator

R

S

FOSC2:FOSC0

Resonator Part Number

C1

C2

F

Frequency

011

4 MHz

CSA4.00MG

30 pF

1MΩ

0 Ω

Internal

(30 pF)

Internal

(30 pF)

4 MHz

CST4.00MGW

1 MΩ

Internal

(47 pF)

Internal

(47 pF)

011

4 MHz

8 MHz

CSTCC4.00G0H6

CSA8.00MTZ

1 MΩ

0 Ω

30 pF

Internal

(30 pF)

Internal

30 pF)

CST8.00MTW

Internal

(47 pF)

Internal

47pF)

011

100

101

8 MHz

20 MHz

33 MHz

50 MHz

CSTCC8.00MG0H6

CSA20.00MXZ040

CST20.00MXW0H1

CSACV20.00MXJ040

CSTCV20.00MXJ0H1

CSA33.00MXJ040

1 MΩ

22 kΩ

1 MΩ

10 kΩ

0 Ω

0Ω

5 pF

Internal

(5 pF)

Internal

(5 pF)

5 pF

Internal

(5 pF)

Internal

(5 pF)

5 pF

Internal

(5 pF)

Internal

(5 pF)

CST33.00MXW040

CSACV33.00MXJ040

CSTCV33.00MXJ040

CSA50.00MXZ040

CST50.00MXW0H3

CSACV50.00MXJ040

CSTCV50.00MXJ0H3

5 pF

Internal

(5 pF)

Internal

(5 pF)

15 pF

Internal

(15 pF)

Internal

(15 pF)

15 pF

0 Ω

Internal

(15 pF)

Internal

(15 pF)

- 22 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

9.2 External RC Mode

9.3 Internal RC Mode

The external RC oscillator mode provides a cost-effective

approach for applications that do not require a precise

operating frequency. In this mode, the RC oscillator fre-

quency is a function of the supply voltage, the resistor (R)

and capacitor (C) values, and the operating temperature.

In addition, the oscillator frequency will vary from unit to

unit due to normal manufacturing process variations. Fur-

thermore, the difference in lead frame capacitance

between package types also affects the oscillation fre-

quency, especially for low C values. The external R and

C component tolerances contribute to oscillator fre-

quency variation as well.

The internal RC mode uses an internal oscillator, so the

device does not need any external components. At 4

MHz, the internal oscillator provides typically +/–8%

accuracy over the allowed temperature range. The inter-

nal clock frequency can be divided down to provide one

of eight lower-frequency choices by selecting the desired

value in the FUSE Word register. The frequency range is

from 31.25 KHz to 4 MHz. The default operating fre-

quency of the internal RC oscillator may not be 4 MHz.

This is due to the fact that the SX device requires trim-

ming to obtain 4 MHz operation. The parts shipped out of

the factory are not trimmed. The device relies on the pro-

gramming tool provided by the third party vendors to sup-

port trimming.

Figure 9-3 shows the external RC connection diagram.

The recommended R value is from 3kΩ to 100kΩ. For R

values below 2.2kΩ, the oscillator may become unstable,

or may stop completely. For very high R values (such as

1 MΩ), the oscillator becomes sensitive to noise, humid-

ity, and leakage.

10.0 REAL TIME CLOCK

(RTCC)/WATCHDOG TIMER

The device contains an 8-bit Real Time Clock/Counter

(RTCC) and an 8-bit Watchdog Timer (WDT). An 8-bit

programmable prescaler extends the RTCC to 16 bits. If

the prescaler is not used for the RTCC, it can serve as a

postscaler for the Watchdog Timer. Figure 10-1 shows

the RTCC and WDT block diagram.

Although the oscillator will operate with no external

capacitor (C = 0pF), it is recommended that you use val-

ues above 20 pF for noise immunity and stability. With no

or small external capacitance, the oscillation frequency

can vary significantly due to variation in PCB trace or

package lead frame capacitances.

10.1 RTCC

RTCC is an 8-bit real-time timer that is incremented once

each instruction cycle or from a transition on the RTCC

pin. The on-board prescaler can be used to extend the

RTCC counter to 16 bits.

SX Device

The RTCC counter can be clocked by the internal instruc-

tion cycle clock or by an external clock source presented

at the RTCC pin.

Internal

Circuitry

~

To select the internal clock source, bit 5 of the OPTION

register should be cleared. In this mode, RTCC is incre-

mented at each instruction cycle unless the prescaler is

selected to increment the counter.

N

To select the external clock source, bit 5 of the OPTION

register must be set. In this mode, the RTCC counter is

incremented with each valid signal transition at the RTTC

pin. By using bit 4 of the OPTION register, the transition

can be programmed to be either a falling edge or rising

edge. Setting the control bit selects the falling edge to

increment the counter. Clearing the bit selects the rising

edge.

OSC1

OSC2

V

dd

R

C

The RTCC generates an interrupt as a result of an RTCC

rollover from 0FF to 000. There is no interrupt pending bit

to indicate the overflow occurrence. The RTCC register

must be sampled by the program to determine any over-

flow occurrence.

Figure 9-3. RC Oscillator Mode

- 23 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

10.2 Watchdog Timer

RTCC

Interrupt

Enable

The watchdog logic consists of a Watchdog Timer which

shares the same 8-bit programmable prescaler with the

RTCC. The prescaler actually serves as a postscaler if

used in conjunction with the WDT, in contrast to its use as

a prescaler with the RTCC.

WDTE (from FUSE Word)

RTW

RTE_IE

RST

RTE_ES

PSA

WDT

F

M

U

X

OSC

RTCC pin

10.3 The Prescaler

MUX

The 8-bit prescaler may be assigned to either the RTCC

or the WDT through the PSA bit (bit 3 of the OPTION reg-

ister). Setting the PSA bit assigns the prescaler to the

WDT. If assigned to the WDT, the WDT clocks the pres-

caler and the prescaler divide rate is selected by the

PS0, PS1, and PS2 bits located in the OPTION register.

Clearing the PSA bit assigns the prescaler to the RTCC.

Once assigned to the RTCC, the prescaler clocks the

RTCC and the divide rate is selected by the PS0, PS1,

and PS2 bits in the OPTION register. The prescaler is not

mapped into the data memory, so run-time access is not

possible.

PS2

PS1

PS0

8-Bit Prescaler

MUX (8 to 1)

OPTION

Register

M

U

X

RTCC Rollover

Interrupt

RTCC

MUX

8-Bits

The prescaler cannot be assigned to both the RTCC and

WDT simultaneously.

WDT Time-out

Data Bus

Figure 10-1. RTCC and WDT Block Diagram

- 24 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

11.0 COMPARATOR

The final “mov” instruction in this example performs an

exchange of data between the working register (W) and

the CMP_B register. This exchange occurs only with Port

B accesses. Otherwise, the “mov” instruction does not

perform an exchange, but only moves data from the

source to the destination.

The device contains an on-chip differential comparator.

Ports RB0-RB2 support the comparator. Ports RB1 and

RB2 are the comparator negative and positive inputs,

respectively, while Port RB0 serves as the comparator

output pin. To use these pins in conjunction with the com-

parator, the user program must configure Ports RB1 and

RB2 as inputs and Port RB0 as an output. The CMP_B

register is used to enable the comparator, to read the out-

put of the comparator internally, and to enable the output

of the comparator to the comparator output pin.

Figure 11-1 shows the comparator block diagram.

CMP_B - Comparator Enable/Status Register

The comparator enable bits are set to “1” upon reset,

thus disabling the comparator. To avoid drawing addi-

tional current during the power down mode, the compara-

tor should be disabled before entering the power down

mode. Here is an example of how to setup the compara-

tor and read the CMP_B register.

CMP_EN

Bit 7

CMP_OE

Bit 6

Reserved

Bits 5–1

CMP_RES

Bit 0

CMP_RES

Comparator result: 1 for RB2>RB1 or 0

for RB2<RB1. Comparator must be en-

abled (CMP_EN = 0) to read the result.

The result can be read whether or not the

CMP_OE bit is cleared.

mov M,#$08

;set MODE register to access

;CMP_B

mov W,#$00

mov !RB,W

;clear W

CMP_OE

CMP_EN

When cleared to 0, enables the compar-

ator output to the RB0 pin.

;enable comparator and its

;output

When cleared to 0, enables the compar-

ator.

...

;delay after enabling

;comparator for response

mov M,#$08

;set MODE register to access

;CMP_B

mov W,#$00

mov !RB,W

;clear W

;enable comparator and its

;output and also read CMP_B

;(exchange W and CMB_B)

and W,#$01

snb $03.2

;set/clear Z bit based on

;comparator result

;test Z bit in STATUS reg

;(0 => RB2<RB1)

jmp rb2_hi

...

;jump only if RB2>RB1

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Internal Data Bus

CMP_B

7

6

CMP_EN

W

CMP_OE

RB0

R

E

S

E

R

V

E

D

-

RB1

MODE

MODE = 08h

+

RB2

CMP_RES

0

Point to CMP_B

Figure 11-1. Comparator Block Diagram

- 26 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Figure 12-2 shows a power-up sequence where MCLR is

12.0 RESET

Power-On-Reset, Brown-Out reset, watchdog reset, or

external reset initializes the device. Each one of these

reset conditions causes the program counter to branch to

the top of the program memory. For example, on the

device with 2048K words of program memory, the pro-

gram counter is initialized to 07FF.

not tied to the V pin and V signal is allowed to rise

dd

and stabilize before MCLR pin is brought high. The

device will actually come out of reset T msec after

drt

MCLR goes high.

The brown-out circuitry resets the chip when device

The device incorporates an on-chip Power-On Reset

power (V ) dips below its minimum allowed value, but

dd

(POR) circuit that generates an internal reset as V rises

not to zero, and then recovers to the normal value.

dd

during power-up. Figure 12-1 is a block diagram of the

circuit. The circuit contains an 10-bit Delay Reset Timer

(DRT) and a reset latch. The DRT controls the reset time-

out delay. The reset latch controls the internal reset sig-

nal. Upon power-up, the reset latch is set (device held in

reset), and the DRT starts counting once it detects a valid

logic high signal at the MCLR pin. Once DRT reaches the

end of the timeout period (typically 72 msec), the reset

latch is cleared, releasing the device from reset state.

.

V

dd

MCLR

POR

Tdrt

drt_time_out

RESET

MIWU

POR

Figure 12-2. Time-Out Sequence on Power-Up

(MCLR not tied to V

BROWN-OUT

V

dd

)

dd

MCLR/Vpp pin

wdt_time_out

10-Bit Asynch

enable

Q

S

R

Ripple

Counter

(DRT Start-Up

Timer)

RESET

QN

rc_clk

drt_time

_out

Note:Ripple counter is 10 bits for Power on Reset (POR)

only.

Figure 12-1. Block Diagram of On-Chip Reset Circuit

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Figure 12-3 shows the on-chip Power-On Reset

sequence where the MCLR and V

pins are tied

dd

V

dd

together. The V signal is stable before the DRT time-

dd

out period expires. In this case, the device will receive a

proper reset. However, Figure 12-4 depicts a situation

D

R

C

R1

where V rises too slowly. In this scenario, the DRT will

dd

MCLR

time-out prior to V reaching a valid operating voltage

dd

level (V min). This means the device will come out of

dd

reset and start operating with the supply voltage not at a

valid level. In this situation, it is recommended that you

use the external RC circuit shown in Figure 12-5. The RC

Figure 12-5. External Power-On Reset Circuit

delay should exceed the time period it takes V to reach

dd

(For Slow V Power-up)

dd

a valid operating voltage

Note 1: The external Power-On Reset circuit is required

only if V power-up is too slow. The diode D helps dis-

dd

charge the capacitor quickly when V powers down.

dd

V

Note 2: R < 40 kΩ is recommended to make sure that

voltage drop across R does not violate the device electri-

cal specifications.

dd

MCLR

POR

Note 3: R1 = 100Ω to 1kΩ will limit any current flowing

into MCLR from external capacitor C. This helps prevent

MCLR pin breakdown due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

Tdrt

drt_time_out

RESET

13.0 BROWN-OUT DETECTOR

The on-chip brown-out detection circuitry resets the

Figure 12-3. Time-out Sequence on Power-up

(MCLR tied to V ): Fast V Rise Time

dd

device when V dips below the specified brown-out volt-

dd

age. The device is held in reset as long as V stays

dd

below the brown-out voltage. The device will come out of

reset when V rises above the brown-out voltage. The

dd

V1

brown-out level is preset to approximately 4.2V at the

factory. The brown-out circuit can be disabled through

BOR0 and BOR1 bits contained in the FUSEX Word reg-

ister.

V

dd

MCLR

POR

Tdrt

drt_time_out

RESET

Figure 12-4. Time-out Sequence on Power-up

(MCLR tied to V ): Slow Rise Time

dd

- 28 -

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

A register that starts with an unknown value should be

initialized by the software to a known value; you cannot

simply test the initial state and rely on it starting in that

state consistently.

14.0 REGISTER STATES UPON

DIFFERENT RESET OPERATIONS

The effect of different reset operation on a register

depends on the register and the type of reset operation.

Some registers are initialized to specific values, some

are left unchanged, some are undefined, and some are

initialized to an unknown value.

Table 14-1 lists the SX registers and shows the state of

each register upon different reset.

Table 14-1. Register States Upon Different Resets

Watchdog

Timeout

Register

Power-On

Undefined

Wakeup

Brown-out

Undefined

MCLR

W

Unchanged

FFh

Unchanged

FFh

Unchanged

FFh

OPTION

FFh

MODE

0Fh

RTCC (01h)

PC (02h)

Undefined

FFh

Unchanged

FFh

Undefined

FFh

Unchanged

FFh

Unchanged

FFh

STATUS (03h)

Bits 0-2: Unde- Bits 0-2: Un-

Bits 0-4: Unde- Bits 0-2: Un-

Bits 0-2: Un-

changed

fined

changed.

fined

changed

Bits 3-4: 11

Bits 5-7: 000

Bits 3-4: Unch.

Bits 5-7: 000

Bits 3-4: (Note 1) Bits 3-4: (Note 2)

Bits 5-7: 000

FSR (04h)

Undefined

Bits 0-6: Un-

changed

Bits 0-6: Unde- Bits 0-6: Un-

Bits 0-6: Un-

changed

fined

changed

Bit 7: 1

FFh

Bit 7: 1

FFh

RA/RB/RC

Direction

FFh

RA/RB/RC Data

Undefined

Unchanged

Undefined

Unchanged

Other File Registers -

SRAM

CMP_B

Bits 0, 6-7: 1

Bits 1-5: Unde- Bits 1-5: Unde- Bits 1-5: Unde- Bits 1-5: Unde-

Bits 1-5: Unde-

fined

Undefined

FFh

fined

WKPND_B

Unchanged

FFh

Undefined

FFh

Unchanged

FFh

Unchanged

FFh

WKED_B

WKEN_B

FFh

ST_B/ST_C

LVL_A/LVL_B/LVL_C

FFh

PLP_A/PLP_B/PLP_C FFh

Watchdog Counter Undefined

FFh

Unchanged

Undefined

Unchanged

NOTE: 1. Watchdog reset during power down mode: 00 (TO, PD)

Watchdog reset during Active mode: 01 (TO, PD)

NOTE: 2. External reset during power down mode: 10 (TO, PD)

External reset during Active mode: Unchanged (TO, PD)

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SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

fetched. Once the pipeline is full, instructions are exe-

cuted at the rate of one per clock cycle.

15.0 INSTRUCTION SET

As mentioned earlier, the SX family of devices uses a

modified Harvard architecture with memory-mapped

input/output. The device also has a RISC type architec-

ture in that there are 43 single-word basic instructions.

The instruction set contains byte-oriented file register, bit-

oriented file register, and literal/control instructions.

Instructions that directly affect the contents of the pro-

gram counter (such as jumps and calls) require that the

pipeline be cleared and subsequently refilled. Therefore,

these instruction take more than one clock cycle.

The instruction execution time is derived by dividing the

oscillator frequency by either one (turbo mode) or four

(non-turbo mode). The divide-by factor is selected

through the FUSE Word register.

Working register W is one of the CPU registers, which

serves as a pseudo accumulator. It is a pseudo accumu-

lator in a sense that it holds the second operand,

receives the literal in the immediate type instructions, and

also can be program-selected as the destination register.

The bank of 31 file registers can also serve as the pri-

mary accumulators, but they represent the first operand

and may be program-selected as the destination regis-

ters.

Fetch

Decode

Execute

Write

15.1 Instruction Set Features

1. All single-word (12-bit) instructions for compact code

efficiency.

Clock

Cycle

1

Cycle

2

Cycle

3

Cycle

4

2. All instructions are single cycle except the jump type in-

structions (JMP, CALL) and failed test instructions

(DECSZ fr, INCSZ fr, SB bit, SNB bit), which are two-

cycle.

Pipeline and Clock Scheme

Figure 15-1.

3. A set of File registers can be addressed directly or indi-

rectly, and serve as accumulators to provide first oper-

and; W register provides the second operand.

15.3 Addressing Modes

The device support the following addressing modes:

4. Many instructions include a destination bit which se-

lects either the register file or the accumulator as the

destination for the result.

Data Direct

Data Indirect

Immediate

5. Bit manipulation instructions (Set, Clear, Test and Skip

if Set, Test and Skip if Clear).

Program Direct

Program Indirect

Relative

6. STATUS Word register memory-mapped as a register

file, allowing testing of status bits (carry, digit carry, ze-

ro, power down, and timeout).

Both direct and indirect addressing modes are available.

The INDF register, though physically not implemented, is

used in conjunction with the indirect data pointer (FSR) to

perform indirect addressing. An instruction using INDF as

its operand field actually performs the operation on the

register pointed by the contents of the FSR. Conse-

quently, processing two multiple-byte operands requires

alternate loading of the operand addresses into the FSR

pointer as the multiple byte data fields are processed.

7. Program Counter (PC) memory-mapped as register file

allows W to be used as offset register for indirect ad-

dressing of program memory.

8. Indirect addressing data pointer FSR (file select regis-

ter) memory-mapped as a register file.

9. IREAD instruction allows reading the instruction from

the program memory addressed by W and upper four

bits of MODE register.

10.Eight-level, 11-bit push/pop hardware stack for sub-

routine linkage using the Call and Return instructions.

Examples:

Direct addressing:

11.Six addressing modes provide great flexibility.

mov

RA,#01

;move “1” to RA

15.2 Instruction Execution

Indirect Addressing:

An instruction goes through a four-stage pipeline to be

executed (Figure 15-1). The first instruction is fetched

from the program memory on the first clock cycle. On the

second clock cycle, the first instruction is decoded and

the second instruction is fetched. On the third clock cycle,

the first instruction is executed, the second instruction is

decoded, and the third instruction is fetched. On the

fourth clock cycle, the first instruction’s results are written

to its destination, the second instruction is executed, the

third instruction is decoded, and the fourth instruction is

mov

FSR,#RA

;FSR = address of RA

;move “1” to RA

INDF,#$01

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15.4 RAM Addressing

15.6 Bit Manipulation

The instruction set contains instructions to set, reset, and

test individual bits in data memory. The device is capable

of bit addressing anywhere in data memory.

Direct Addressing

The FSR register must initialized with an appropriate

value in order to address the desired RAM register. The

following table and code example show how to directly

access the banked registers.

15.7 Input/Output Operation

The device contains three registers associated with each

I/O port. The first register (Data Direction Register), con-

figures each port pin as a Hi-Z input or output. The sec-

ond register (TTL/CMOS Register), selects the desired

input level for the input. The third register (Pull-Up Regis-

ter), enables a weak pull-up resistor on the pin configured

as a input. In addition to using the associated port regis-

ters, appropriate values must be written into the MODE

register to configure the I/O ports.

Bank

FSR Value

010h

0

1

2

3

4

5

6

7

030h

050h

070h

090h

0B0h

When two successive read-modify-write instructions are

used on the same I/O port with a very high clock rate, the

“write” part of one instruction might not occur soon

enough before the “read” part of the very next instruction,

resulting in getting “old” data for the second instruction.

To ensure predictable results, avoid using two successive

read-modify-write instructions that access the same port

data register if the clock rate is high.

0D0h

0F0h

mov

clr

FSR,#$070

$010

;Select RAM Bank 3

;Clear register 10h on

;Bank 3

mov

clr

FSR,#$D0

$010

;Select RAM Bank 6

;Clear register 10h on

;Bank 6

15.8 Increment/Decrement

The bank of 31 registers serves as a set of accumulators.

The instruction set contains instructions to increment and

decrement the register file. The device also includes both

INCSZ fr (increment file register and skip if zero) and

DECSZ fr (decrement file register and skip if zero)

instructions.

Indirect Addressing

To access any register via indirect addressing, simply

move the eight-bit address of the desired register into the

FSR and use INDF as the operand. The example below

shows how to clear all RAM locations from 10h to 1Fh in

all eight banks:

15.9 Loop Counting and Data Pointing

Testing

The device has specific instructions to facilitate loop

counting. The DECSZ fr (decrement file register and skip

if zero) tests any one of the file registers and skips the

next instruction (which can be a branch back to loop) if

the result is zero.

clr

FSR

;clear FSR to 00h (at address

;04h)

setb SFR.4 ;set bit 4: address 10h-1Fh,

;30-3Fh, etc

:loop

clr

incsz FSR

jmp

INDF

;clear register pointed to by

;FSR

;increment FSR and test, skip

;jmp if 00h

:loop ;jump back and clear next

;register

15.10 Branch and Loop Call Instructions

The device contains an 8-level hardware stack where the

return address is stored with a subroutine call. Multiple

stack levels allow subroutine nesting. The instruction set

supports absolute address branching.

15.5 The Bank Instruction

Often it is desirable to set the bank select bits of the FSR

register in one instruction cycle. The Bank instruction

provides this capability. This instruction sets the upper

bits of the FSR to point to a specific RAM bank without

affecting the other FSR bits.

15.10.1 Jump Operation

When a JMP instruction is executed, the lower nine bits

of the program counter is loaded with the address of the

specified label. The upper two bits of the program

counter are loaded with the page select bits, PA1:PA0,

contained in the STATUS register. Therefore, care must

be exercised to ensure the page select bits are pointing

to the correct page before the jump occurs.

Example:

bank $F0

inc $1F

;Select Bank 7 in FSR

;increment file register

;1Fh in Bank 7

STATUS<6:5>

PC<10:9>

JMP LABEL

PC<8:0>

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15.10.2 Page Jump Operation

15.10.4 Page Call Operation

When a JMP instruction is executed and the intended

destination is on a different page, the page select bits

must be initialized with appropriate values to point to the

desired page before the jump occurs. This can be done

easily with SETB and CLRB instructions or by writing a

value to the STATUS register. The device also has the

PAGE instruction, which automatically selects the page in

a single-cycle execution.

When a subroutine that resides on a different page is

called, the page select bits must contain the proper val-

ues to point to the desired page before the call instruction

is executed. This can be done easily using SETB and

CLRB instructions or writing a value to the STATUS reg-

ister. The device also has the PAGE instruction, which

automatically selects the page in a single-cycle execu-

tion.

PAGE N

STATUS<6:5>

PC<10:9>

JMP LABEL

PC<8:0>

STATUS<6:5>

PC<10:9>

0

CALL LABEL

PC<7:0>

PC<8>

Note: “N” must be 0, 1, 2, or 3.

Note:“N” must be 0, 1, 2, or 3.

15.10.3 Call Operation

15.11 Return Instructions

The following happens when a CALL instruction is exe-

cuted:

The device has several instructions for returning from

subroutines and interrupt service routines. The return

from subroutine instructions are RET (return without

affecting W), RETP (same as RET but affects PA1:PA0),

RETI (return from interrupt), RETIW (return and add W to

RTCC), and RETW #literal (return and place literal in W).

The literal serves as an immediate data value from mem-

ory. This instruction can be used for table lookup opera-

tions. To do table lookup, the table must contain a string

of RETW #literal instructions. The first instruction just in

front of the table calculates the offset into the table. The

table can be used as a result of a CALL.

• The current value of the program counter is increment-

ed and pushed onto the top of the stack.

• The lower eight bits of the label address are copied into

the lower eight bits of the program counter.

• The ninth bit of the Program Counter is cleared to zero.

• The page select bits (in STATUS register) are copied

into the upper two bits of the Program Counter.

This means that the call destination must start in the

lower half of any page. For example, 00h-0FFh, 200h-

2FFh, 400h-4FFh, etc.

STATUS<6:5>

0

CALL LABEL

PC<10:9>

PC<8>

PC<7:0>

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15.12.2 Pop Operation

15.12 Subroutine Operation

When a return instruction is executed the subroutine

stack is popped. Specifically, the contents of Stack 1 are

copied into the program counter and the contents of each

stack level are moved to the next higher level. For exam-

ple, Stack 1 receives the contents of Stack 2, etc., until

Stack 7 is overwritten with the contents of Stack 8. Stack

8 is left unchanged, so the contents of Stack 8 are dupli-

cated in Stack 7.

15.12.1 Push Operation

When a subroutine is called, the return address is

pushed onto the subroutine stack. Specifically, each

address in the stack is moved to the next lower level in

order to make room for the new address to be stored.

Stack 1 receives the contents of the program counter.

Stack 8 is overwritten with what was in Stack 7. The con-

tents of stack 8 are lost.

PC<10:0>

STACK 1

STACK 2

STACK 3

STACK 4

STACK 5

STACK 6

STACK 7

STACK 8

STACK 1

STACK 2

STACK 3

STACK 4

STACK 5

STACK 6

STACK 7

STACK 8

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15.13 Comparison and Conditional Branch

Instructions

15.17 Key to Abbreviations and Symbols

Symbol

Description

The instruction set includes instructions such as DECSZ

fr (decrement file register and skip if zero), INCSZ fr

(increment file register and skip if zero), SNB bit (bit test

file register and skip if bit clear), and SB bit (bit test file

register and skip if bit set). These instructions will cause

the next instruction to be skipped if the tested condition is

true. If a skip instruction is immediately followed by a

PAGE or BANK instruction (and the tested condition is

true) then two instructions are skipped and the operation

consumes three cycles. This is useful for conditional

branching to another page where a PAGE instruction pre-

cedes a JMP. If several PAGE and BANK instructions

immediately follow a skip instruction then they are all

skipped plus the next instruction and a cycle is consumed

for each.

W

Working register

File register (memory-mapped register in the

range of 00h to FFh)

fr

Lower eight bits of program counter (file regis-

ter 02h)

PC

STATUS STATUS register (file register 03h)

FSR

C

File Select Register (file register 04h)

Carry bit in STATUS register (bit 0)

Digit Carry bit in STATUS register (bit 1)

Zero bit in STATUS register (bit 2

DC

Z

PD

Power Down bit in STATUS register (bit 3)

Watchdog Timeout bit in STATUS register (bit

4)

15.14 Logical Instruction

TO

The instruction set contain a full complement of the logi-

cal instructions (AND, OR, Exclusive OR), with the W

register and a selected memory location (using either

direct or indirect addressing) serving as the two oper-

ands.

PA2:PA0 Page select bits in STATUS register (bits 7:5)

OPTION

OPTION register (not memory-mapped)

Watchdog Timer register (not memory-

mapped)

WDT

15.15 Shift and Rotate Instructions

The instruction set includes instructions for left or right

rotate-through-carry.

MODE

MODE register (not memory-mapped)

Port control register pointer (RA, RB, or RC)

Non-memory-mapped register designator

File register address bit in opcode

Constant value bit in opcode

rx

!

15.16 Complement and SWAP

f

The device can perform one’s complement operation on

the file register (fr) and W register. The MOV W,<>fr

instruction performs nibble-swap on the fr and puts the

value into the W register.

k

n

b

Numerical value bit in opcode

Bit position selector bit in opcode

File register / bit selector separator in assem-

bly language instruction

.

Immediate literal designator in assembly lan-

guage instruction

#

lit

Literal value in assembly language instruction

addr8 8-bit address in assembly language instruction

addr9

9-bit address in assembly language instruction

12-bit address in assembly language instruc-

tion

addr12

/

Logical 1’s complement

Logical OR

|

^

Logical exclusive OR

&

Logical AND

<>

<<

>>

- -

++

Swap high and low nibbles (4-bit segments)

Rotate left through carry bit

Rotate right through carry bit

Decrement file register

Increment file register

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16.0 INSTRUCTION SET SUMMARY TABLE

Table 16-1 lists all of the instructions, organized by cate-

gory. For each instruction, the table shows the instruction

mnemonic (as written in assembly language), a brief

description of what the instruction does, the number of

instruction cycles required for execution, the binary

opcode, and the status bits affected by the instruction.

cycles depends on the outcome of the instruction (such

as the test-and-skip instructions) or the clocking mode

(Compatible or Turbo). In those cases, all possible num-

bers of cycles are shown in the table.

The instruction execution time is derived by dividing the

oscillator frequency by either one (Turbo mode) or four

(Compatible mode). The divide-by factor is selected

through the FUSE Word register.

The “Cycles” column typically shows a value of 1, which

means that the overall throughput for the instruction is

one per clock cycle. In some cases, the exact number of

Table 16-1. The SX Instruction Set

Cycles

Mnemonic,

Operands

Cycles

(Compatible) (Turbo)

Bits

Affected

Description

Opcode

Logical Operations

1

0001 011f ffff

0001 010f ffff

1110 kkkk kkkk

0010 011f ffff

0001 001f ffff

0001 000f ffff

1101 kkkk kkkk

0001 101f ffff

0001 100f ffff

1111 kkkk kkkk

Z

AND fr, W

AND W, fr

AND W,#lit

NOT fr

AND of fr and W into fr (fr = fr & W)

AND of W and fr into W (W = W & fr)

AND of W and Literal into W (W = W & lit)

Complement of fr into fr (fr = fr ^ FFh)

OR of fr and W into fr (fr = fr | W)

OR fr,W

OR W,fr

OR of W and fr into fr (W = W | fr)

OR W,#lit

XOR fr,W

XOR W,fr

XOR W,#lit

OR of W and Literal into W (W = W | lit)

XOR of fr and W into fr (fr = fr ^ W)

XOR of W and fr into W (W = W ^ fr)

XOR of W and Literal into W (W = W ^ lit)

Arithmetic and Shift Operations

ADD fr,W

Add W to fr (fr = fr + W); carry bit is added if CF

bit in FUSEX register is cleared to 0

0001 111f ffff

0001 110f ffff

1

C, DC, Z

ADD W,fr

Add fr to W (W = W + fr); carry bit is added if CF

bit in FUSEX register is cleared to 0

CLR fr

Clear fr (fr = 0)

1

0000 011f ffff

0000 0100 0000

0000 0000 0100

Z

CLR W

Clear W (W = 0)

CLR !WDT

Clear Watchdog Timer, clear prescaler if as-

signed to the Watchdog (TO = 1, PD = 1)

1

TO, PD

Z

DEC fr

Decrement fr (fr = fr - 1)

0000 111f ffff

0010 111f ffff

DECSZ fr

Decrement fr and Skip if Zero (fr = fr - 1 and skip

next instruction if result is zero)

1 or

2 (skip)

1 or

2 (skip)

none

Z

INC fr

Increment fr (fr = fr + 1)

1

0010 101f ffff

0011 111f ffff

INCSZ fr

Increment fr and Skip if Zero (fr = fr + 1 and skip

next instruction if result is zero)

1 or

2 (skip)

1 or

2 (skip)

none

1

0011 011f ffff

0011 001f ffff

0000 101f ffff

C

RL fr

Rotate fr Left through Carry (fr = << fr)

Rotate fr Right through Carry (fr = >> fr)

RR fr

SUB fr,W

Subtract W from fr (fr = fr - W); complement of

the carry bit is subtracted if CF bit in FUSEX

register is cleared to 0

1

C, DC, Z

SWAP fr

Swap High/Low Nibbles of fr (fr = <> fr)

0011 101f ffff none

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Table 16-1. The SX Instruction Set (Continued)

Mnemonic,

Operands

Cycles

(Compatible) (Turbo)

Cycles

Bits

Affected

Description

Opcode

Bitwise Operations

CLRB fr.bit

SB fr.bit

Clear Bit in fr (fr.bit = 0)

1

0100 bbbf ffff

0111 bbbf ffff

0101 bbbf ffff

0110 bbbf ffff

none

Test Bit in fr and Skip if Set (test fr.bit and skip

next instruction if bit is 1)

1 or

2 (skip)

1 or

2 (skip)

1

SETB fr.bit

SNB fr.bit

Set Bit in fr (fr.bit = 1)

Test Bit in fr and Skip if Clear (test fr.bit and skip

next instruction if bit is 0)

1 or

2 (skip)

1 or

2 (skip)

Data Movement Instructions

1

0000 001f ffff none

MOV fr,W

Move W to fr (fr = W)

Z

MOV W,fr

MOV W,fr-W

Move fr to W (W = fr)

0010 000f ffff

0000 100f ffff

Move (fr-W) to W (W = fr - W); complement of

carry bit is subtracted if CF bit in FUSEX register

is cleared to 0

1

C, DC, Z

MOV W,#lit

MOV W,/fr

Move Literal to W (W = lit)

1

1100 kkkk kkkk none

0010 010f ffff

0000 110f ffff

0010 100f ffff

0011 010f ffff

Z

Move Complement of fr to W (W = fr ^ FFh)

Move (fr-1) to W (W = fr - 1)

MOV W,--fr

MOV W,++fr

MOV W,<<fr

Move (fr+1) to W (W = fr + 1)

Rotate fr Left through Carry and Move to W

(W = << fr)

1

C

MOV W,>>fr

MOV W,<>fr

MOV W,M

Rotate fr Right through Carry and Move to W

(W = >> fr)

0011 000f ffff

0011 100f ffff

0000 0100 0010

0010 110f ffff

0011 110f ffff

C

Swap High/Low Nibbles of fr and move to W

(W = <> fr)

none

Move MODE Register to W (W = MODE), high

nibble is cleared

MOVSZ W,--fr

MOVSZ W,++fr

Move (fr-1) to W and Skip if Zero (W = fr -1 and

skip next instruction if result is zero)

1 or

2 (skip)

1

2 (skip)

Move (fr+1) to W and Skip if Zero (W = fr + 1 and

skip next instruction if result is zero)

1 or

2 (skip)

1

2 (skip)

1

0000 0100 0011 none

0000 0101 kkkk none

0000 0000 0fff

none

MOV M,W

MOV M,#lit

MOV !rx,W

Move W to MODE Register (MODE = W)

Move Literal to MODE Register (MODE = lit)

Move W to Port Rx Control Register:rx <=> W

(exchange W and WKPND_B or CMP_B) or rx

= W (move W to rx for all other port control reg-

isters)

1

0000 0000 0010 none

MOV !OPTION, W Move W to OPTION Register (OPTION = W)

TEST fr Test fr for Zero (fr = fr to set or clear Z bit)

0010 001f ffff

Z

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Table 16-1. The SX Instruction Set (Continued)

Mnemonic,

Operands

Cycles

(Compatible) (Turbo)

Cycles

Bits

Affected

Description

Opcode

Program Control instruction

CALL addr8

Call Subroutine:

1001 kkkk kkkk

top-of-stack = program counter + 1

PC(7:0) = addr8

program counter (8) = 0

2

3

none

program counter (10:9) = PA1:PA0

JMP addr9

Jump to Address:

PC(7:0) = addr9(7:0)

program counter (8) = addr9(8)

program counter (10:9) = PA1:PA0

101k kkkk kkkk

1

2

1

3

none

NOP

RET

No Operation

0000 0000 0000

0000 0000 1100

Return from Subroutine

(program counter = top-of-stack)

RETP

Return from Subroutine Across Page Boundary

(PA1:PA0 = top-of-stack (10:9) and

program counter = top-of-stack)

0000 0000 1101

0000 0000 1110

0000 0000 1111

1000 kkkk kkkk

2

3

PA1, PA0

all STA-

TUS, ex-

cept TO,

PD

RETI

Return from Interrupt (restore W, STATUS,

FSR, and program counter from shadow regis-

ters)

all STA-

TUS, ex-

cept TO,

PD

RETIW

RETW lit

Return from Interrupt and add W to RTCC (re-

store W, STATUS, FSR, and program counter

from shadow registers; and add W to RTCC)

2

3

Return from Subroutine with Literal in W

(W = lit and program counter = top-of-stack)

none

System Control Instructions

BANK addr8

Load Bank Number into FSR(7:5)

FSR(7:5) = addr8(7:5)

0000 0001 1nnn

0000 0100 0001

0000 0001 0nnn

0000 0000 0011

1

4

1

none

IREAD

Read Word from Instruction Memory

MODE:W = data at (MODE:W)

PAGE addr12

SLEEP

Load Page Number into STATUS(7:5)

STATUS(7:5) = addr12(11:9)

PA1, PA0

Power Down Mode

1

TO, PD

WDT = 00h, TO = 1, stop oscillator

(PD = 0, clears prescaler if assigned)

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carry), which is interpreted the same as the instruction

“clrb $03.0” (clear bit 0 in the STATUS register). Some of

the commonly supported equivalent assembler mnemon-

ics are described in Table 16-2.

16.1 Equivalent Assembler Mnemonics

Some assemblers support additional instruction mne-

monics that are special cases of existing instructions or

alternative mnemonics for standard ones. For example,

an assembler might support the mnemonic “CLC” (clear

Table 16-2. Equivalent Assembler Mnemonics

Syntax

Description

Clear Carry bit

Equivalent

CLRB $03.0

Cycles

1

CLC

1

CLZ

Clear Zero bit

CLRB $03.2

MOV $02,W

ADD $02,W

JMP W

Jump Indirect W

4 or 3 (note 1)

JMP PC+W

Jump Indirect W Relative

MODE imm4

Move Immediate to MODE MOV M,#lit

Register

1

NOT W

SC

Complement W

XOR W,#$FF

1 or 2 (note 2)

4 or 2 (note 3)

Skip if Carry bit Set

Skip Next Instruction

SB $03.0

SKIP

SNB $02.0 or SB $02.0

Note 1: The JMP W or JMP PC+W instruction takes 4 cycles in the “compatible” clocking mode or 3 cycles in the

“turbo” clocking mode.

Note 2: The SC instruction takes 1 cycle if the tested condition is false or 2 cycles if the tested condition is true.

Note 3: The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit

of the program counter, choosing SNB or SB so that the tested condition is always true. The instruction takes 4 cycles

in the “compatible” clocking mode or 2 cycles in the “turbo” clocking mode.

- 38 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.0 ELECTRICAL CHARACTERISTICS

17.1 Absolute Maximum Ratings

Ambient temperature under bias

Storage temperature

-40°C to +85°C

-65°C to +150°C

0 V to +7.0V

Voltage on V with respect to V

dd

ss

Voltage on OSC1 with respect to V

0 V to +13.5V

ss

Voltage on MCLR with respect to V

ss

Voltage on all other pins with respect to V

Total power dissipation

-0.6 V to (V + 0.6V)V

ss

dd

700 mW

130 mA

Max. current out of V pin

ss

Max. current into V pin

dd

Max. DC current into an input pin (with internal protection diode forward

biased)

+500 µA

Max. allowable sink current per I/O pin

Max. allowable source current per I/O pin

45 mA

- 39 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.2 DC Characteristics

SX18/20/28AC (Temp Range: 0°C <= Ta <= +70°C) and SX18/20/28AC-I (Temp Range: -40°C <= Ta <= +85°C)

Symbol

Parameter

Conditions

= 32 MHz

Min

Typ

Max

Units

Supply Voltage (Note 1)

F

2.7

3.0

-

5.5

V

osc

V

dd

= 50 MHz

S

V

rise rate

0.05

-

V/ms

Vdd

dd

Supply Current, active

V

= 5.0V, F

= 2.7V, F

= 50 MHz (Crystal)

= 4 MHz (Crystal)

= 20 MHz (Crystal)

77

7.5

17

82

8

mA

dd

osc

I

dd

pd

18

Supply Current, power down

V

= 3.0V, WDT enabled

= 3.0V, WDT disabled

-

10

20

µA

dd

I

1.0

9.0

Input Levels

MCLR, OSC1, RTCC

Logic High

0.8V

V

dd

Logic Low

V

0.2V

dd

ss

All Other Inputs

CMOS

V

ih, il

Logic High

Logic Low

TTL

V

0.7V

V

dd

V

0.3V

dd

ss

Logic High

Logic Low

2.0

V

dd

V

0.8

ss

I

Input Leakage Current

Weak Pullup Current

V = V or V

-1.0

+1.0

µA

il

in

dd

ss

V

= 5.5V, V = 0V

100

25

190

50

µA

dd

in

I

ip

= 3.0V, V = 0V

in

Output High Voltage

OSC2, Ports B, C

Ioh = 20mA, Vdd = 4.5V

Ioh = 12mA, Vdd = 3.0V

Ioh = 30mA, Vdd = 4.5

Ioh = 20mA, Vdd = 3.0V

Vdd-0.7

V

oh

Port A

Output Low Voltage

All Ports, OSC2

Iol = 30mA, Vdd = 4.5V

Iol = 20mA, Vdd = 3.0V

0.6

V

ol

Note 1: Vdd must start rising from Vss to ensure proper Power-On-Reset when relying on the internal Power-On-Reset

circuitry.

- 40 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.3 AC Characteristics

SX18/20/28AC (Temp Range: 0°C <= Ta <= +70°C) and SX18/20/28AC-I (Temp Range: -40°C <= Ta <= +85°C)

Symbol

Parameter

Min

Typ

Max

Units

Conditions

External CLKIN Frequency

DC

-

4.0

10

24

50

32

1.0

MHz

KHz

MHz

RC

XT1

XT2

F

osc

HS1/HS2/HS3

LP1

LP2

Oscillator Frequency

External CLKIN Period

Oscillator Period

DC

0.032

1.0

DC

-

4.0

10.0

24.0

50

32

1.0

MHz

KHz

MHz

RC

XT1

XT2

HS1/HS2/HS3

LP1

0.032

LP2

250

100

41.7

20

31.25

1.0

-

ns

µs

RC

XT1

XT2

T

osc

HS1/HS2/HS3

LP1

LP2

250

0.1

41.7

20

31.25

1.0

-

ns

µs

ns

µs

RC

XT1

XT2

31.25

1000.0

-

HS1/HS2/HS3

LP1

31.25

LP2

Clock in (OSC1) Low or High Time

Clock in (OSC1) Rise or Fall Time

50

8.0

2.0

-

ns

µs

XT1/XT2

HS1/HS2/HS3

LP1/LP2

T

, T

osL osH

-

25

50

ns

µs

XT1/XT2

HS1/HS2/HS3

LP1/LP2

, T

osR osF

Note:Data in the Typical (“TYP”) column is at 5V, 25°C unless otherwise stated.

- 41 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.4 DC Characteristics

SX18/20/28AC75 (Temp Range: 0°C <= Ta <= +70°C)

Symbol

Parameter

Conditions

Min

4.5

Typ

Max

5.5

-

Units

V

F

= 75 MHz

Supply Voltage (Note 1)

-

dd

osc

S

V

rise rate

dd

0.05

V/ms

Vdd

I

Supply Current, active

V

= 5.0V, F

= 75 MHz (Ext.)

-

100

105

mA

dd

osc

Supply Current, power down

V

= 4.5V, WDT enabled

= 4.5V, WDT disabled

110

100

µA

dd

I

pd

Input Levels

MCLR, OSC1, RTCC

Logic High

V

0.8V

V

dd

Logic Low

V

0.2V

dd

ss

All Other Inputs

CMOS

V

ih, il

Logic High

Logic Low

TTL

V

0.7V

V

dd

V

0.3V

dd

ss

Logic High

Logic Low

2.0

V

dd

V

0.8

ss

I

Input Leakage Current

Weak Pullup Current

V = V or V

-1.0

100

+1.0

160

µA

il

in

dd

ss

I

V

= 5.5V, V = 0V

in

ip

dd

Output High Voltage

OSC2, Ports B, C

Port A

V

Ioh = 20mA, Vdd = 4.5V

Ioh = 30mA, Vdd = 4.5

Vdd-0.7

V

oh

Output Low Voltage

All Ports, OSC2

Iol = 30mA, Vdd = 4.5V

V

0.6

V

ol

Note:Data in the Typical (“TYP”) column is at 5V, 25°C unless otherwise stated.

- 42 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.5 AC Characteristics

SX18/20/28AC75 (Temp Range: 0°C <= Ta <= +70°C)

Symbol

Parameter

External CLKIN Frequency

Oscillator Frequency

Min

DC

13.3

8.0

-

Typ

Max

Units

MHz

ns

Conditions

HS1/HS2/HS3

F

75

-

osc

-

T

External CLKIN Period

osc

-

ns

Oscillator Period

T

, T

Clock in (OSC1) Low or High Time

Clock in (OSC1) Rise or Fall Time

-

ns

osL osH

T

, T

25

ns

osR osF

Note:Data in the Typical (“TYP”) column is at 5V, 25°C unless otherwise stated.

17.6 Comparator DC and AC Specifications

Parameter

Input Offset Voltage

Conditions

Min

Typ

Max

Units

mV

V

0.4V < Vin < Vdd – 1.5V

+/- 10

+/- 25

0.4

Vcc – 1.3

Input Common Mode Voltage Range

Voltage Gain

300k

V/V

µA

Vdd = 5.5V

120

250

DC Supply Current (enabled)

Response Time

V

= 25mV

ns

overdrive

- 43 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.7 Typical Performance Characteristics (Room Temp)

Active Supply Current Vs Operating Frequency

(Crystal Clock)

Active Supply Current Vs Operating Frequency

(External Clock)

_

90

80

_

80

_

70

60

50

40

30

20

10

_

60

_

50

_

40

_

30

_

20

_

10

20

30

40

50

10

20

30

40

50

Operating Frequency (MHz)

- 44 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.7 Typical Performance Characteristics (continued)

Active Supply Current Vs Operating Frequency

(External Clock)

Active Supply Current Vs V

(Crystal Clock)

dd

SX18AC75/SX20AC75/SX28AC75

_

90

80

_

110

70

60

50

40

30

20

10

_

100

90

80

5.5

4 MHz

2.5

4.5

5.0

3.5

4.5

(V)

5.5

V

(V)

dd

V

dd

Active Supply Current Vs V

(External Clock)

Active Supply Current Vs V

(32 kHz Crystal Clock)

dd

_

90

_

80

700

600

500

400

300

200

100

70

60

50

40

30

20

10

3

3.5

4

4.5

(V)

5

5.5

6

4 MHz

2.5

3.5

4.5

5.5

V

dd

V

(V)

dd

- 45 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

17.7 Typical Performance Characteristics (continued)

Active Supply Current Vs V

(32 kHz External Clock)

dd

Port A/B/C Weak Pull-Up Source Current

_

160

120

80

_

600

500

400

300

200

100

40

2

2.5

3

3.5

4

4.5

5

5.5

1

2

3

4

5

6

V

(V)

V

(V)

dd

oh

Port A/B/C Source Current

Port A/B/C Sink Current

_

40

_

40

30

_

30

20

10

_

20

10

6

1.0

0.5

1

2

3

4

5

V (V)

ol

V

(V)

oh

- 46 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

18.0 PACKAGE DIMENSIONS (DIMENSIONS ARE IN INCHES/(MILLIMETERS)

0.035 - 0.045

(0.890 - 1.143)

SX18AC/SO

SX18AC75/SO

1

9

0.400 - 0.410

(10.16 - 10.41)

0.045 - 0.055

(1.143 - 1.397)

0.292 - 0.299

7.42 - 7.59)

0.090 - 0.094

(2.29 - 2.39)

10

28

0.014 - 0.019

(0.35 - 0.48)

0.292 - 0.299

(7.42 - 7.59)

0.050 BSC

(1.27 BSC)

0.090 - 0.094

(2.29 - 2.39)

0.451 - 0.461

(11.46 - 11.71)

0.0050 - 0.0115

(0.127 - 0.292)

SX18AC/DP

SX18AC75/DP

0.895 - 0.905

(22.73 - 22.99)

9

1

0.240 - 0.260

(6.10 -6.60)

10

18

0.008 - 0.012

(0.20 - 0.31)

0.015 min.

(0.38 min.)

0.130 nom.

(3.3 nom.)

0.430 max.

(10.92 max.)

0.170 max.

(4.32 max.)

0.300 BSC at 90^o

(7.62 BSC at 90 )

0.125 - 0.135

(3.17 - 3.43)

o

[

]

0.100 BSC

(2.54 BSC)

0.055 -0.065

(1.39 - 1.65)

0.015 - 0.022

(0.38 - 0.56)

- 47 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

0.039

(1.00)

SX20AC/SS

SX20AC75/SS

1

10

0.301 - 0.311

(7.65 - 7.90)

0.039

(1.00)

0.205 - 0.212

(5.20 - 5.38)

12^o- 16^o

11

20

0.066 - 0.070

(1.68 - 1.78)

0.010 - 0.015

(0.25 - 0.38)

0.205 - 0.212

(5.20 - 5.38)

0.0256 BSC

(0.65 BSC)

0.066 - 0.070

(1.68 - 1.78)

0.278 - 0.289

(7.07 - 7.33)

0.002 - 0.008

(0.05 - 0.21)

- 48 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

0.035 - 0.045

(0.890 - 1.143)

SX28AC/SO

SX28AC75/SO

14

1

0.40 - 0.41

(10.16 - 10.41)

0.045 - 0.055

(1.143 - 1.397)

0.292 - 0.299

7.42 - 7.59)

0.090 - 0.094

(2.29 - 2.39)

15

28

0.292 - 0.299

(7.42 - 7.59)

0.014 - 0.019

(0.35 - 0.48)

0.050 BSC

(1.27 BSC)

0.090 - 0.094

(2.29 - 2.39)

0.0050 - 0.0115

(0.127 - 0.292)

0.701 - 0.710

(17.81 - 18.06)

- 49 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

SX28AC/DP

SX28AC75/DP

1.360 - 1.370

(34.54 - 34.80)

1

14

0.280 - 0.295

(7.11 - 7.49)

28

15

0.009 - 0.014

(0.23 - 0.36)

0.020 min.

(0.51 min.)

0.430 max.

(10.92 max.)

0.130 nom.

(3.3 nom.)

0.180 max.

(4.57 max.)

0.300 BSC at 90^o

(7.62 BSC at 90 )

o

[

]

0.120 - 0.135

(3.05 - 3.43)

0.100 BSC

(2.54 BSC)

0.045 - 0.055

(1.14 - 1.40)

0.015 - 0.021

(0.38 - 0.53)

- 50 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

SX28AC/SS

SX28AC75/SS

0.039

(1.00)

14

1

0.301 - 0.311

(7.65 - 7.90)

0.039

(1.00)

12^o- 16^o

0.205 - 0.212

(5.20 - 5.38)

15

28

0.066 - 0.070

(1.68 - 1.78)

0.205 - 0.212

(5.20 - 5.38)

0.010 - 0.015

(0.25 - 0.38)

0.0256 BSC

(0.65 BSC)

0.002 - 0.008

(0.05 - 0.21)

0.066 - 0.070

(1.68 - 1.78)

0.397 - 0.407

(10.07 - 10.33)

- 51 -

www.scenix.com

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Lit #: SXL-DS01-04

Sales and Tech Support Contact Information

For the latest contact and support information on SX devices, please visit the Scenix Semiconductor website at

www.scenix.com. The site contains technical literature, local sales contacts, tech support and many other features.

1330 Charleston Road

Mountain View, CA 94043

E-Mail: sales@scenix.com

Web site: www.scenix.com

Tel.: (650) 210-1500

Fax: (650) 210-8715

- 52 -

www.scenix.com


型号：	SX20AA75-I/PQ
厂家：	ETC
描述：	Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug 可配置通信控制器与EE /闪存程序存储器，在系统编程能力和片上调试闪存存储通信控制器
文件：	总52页 (文件大小：337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SX20AA75-I/PQ [ETC]

相关型号：

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SX20AA75-I/SS

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SX20AB100-I/PQ

SX20AB100-I/SO

SX20AB100-I/SS

SX20AB100-I/TQ

SX20AB75-I/DP

SX20AB75-I/PQ

SX20AB75-I/SO

SX20AB75-I/SS