SYNCHRONOUS [ETC]
Synchronous DC/DC Controller for Distributed Power Applications (131k) ; 分布式电源应用的同步DC / DC控制器（ 131K ）\n
| 型号： | SYNCHRONOUS |
| 厂家： | 
ETC |
| 描述： | Synchronous DC/DC Controller for Distributed Power Applications (131k)
|
| 文件： | 总7页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
APPLICATION NOTE FOR SC1102
FEATURES
INTRODUCTION
DESCRIPTION
The SC1102 is a low-cost, full featured, syn-
chronous voltage-mode controller designed
for use in single ended power supply applica-
tions where efficiency is of primary concern.
Synchronous operation allows for the elimi-
nation of heat sinks in many applications.
The SC1102 is ideal for implementing DC/DC
converters needed to power advanced micro-
processors in low cost systems, or in dis-
tributed power applications where efficiency
is important. Internal level-shift, high-side
drive circuitry, and preset shoot-thru control,
allows the use of inexpensive N-channel
power switches.
• 1.265V Reference available
• Synchronous operation
• Over current fault monitor
• On-chip power good and OVP functions
• Small size with minimum external compo-
nents
• Soft Start
• RDS(ON) Current sensing
BLOCK DIAGRAM
SC1102 features include temperature com-
pensated voltage reference, triangle wave os-
cillator and current sense comparator cir-
cuitry. Power good signaling, shutdown, and
over voltage protection are also provided.
The SC1102 operates at a fixed 200kHz, pro-
viding an optimum compromise between effi-
ciency, external component size, and cost.
The SC1102’s manufacturing process has
been optimized for 12V operation and is
capable of handling up to 26V at it’s BST
pin.
APPLICATIONS
• Microprocessor core supply
• Low cost synchronous applications
• Voltage Regulator Modules (VRM)
1
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
Theory of Operation
Power Good
The power good function is to confirm that the regula-
tor outputs are within +/-10% of the programmed level.
PWRGD remains high as long as this condition is met.
PWRGD is connected to an internal open collector
NPN transistor.
Synchronous Buck Converter
Primary VCORE power is provided by a synchronous,
voltage-mode pulse width modulated (PWM) controller.
This section has all the features required to build a
high efficiency synchronous buck converter, including
“Power Good” flag, shut-down, and cycle-by-cycle cur-
rent limit.
Soft Start
Initially, SS/SHDN sources 10µA of current to charge
an external capacitor. The outputs of the error ampli-
fiers are clamped to a voltage proportional to the volt-
age on SS/SHDN. This limits the on-time of the high-
side MOSFETs, thus leading to a controlled ramp-up of
the output voltages.
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier. The
external resistive divider reference voltage is derived
from an internal trimmed-bandgap voltage reference
(See Fig. 1). The inverting input of the error amplifier
receives its voltage from the SENSE pin.
RDS(ON) Current Limiting
The current limit threshold is set by connecting an ex-
ternal resistor from the VCC supply to OCSET. The volt-
age drop across this resistor is due to the 200µA inter-
nal sink sets the voltage at the pin. This voltage is
compared to the voltage at the PHASE node. This
comparison is made only when the high-side drive is
high to avoid false current limit triggering due to uncon-
tributing measurements from the MOSFET’s off-
voltage. When the voltage at PHASE is less than the
voltage at OCSET, an overcurrent condition occurs
and the soft start cycle is initiated. The synchronous
switcher turns off and SS/SHDN starts to sink 2µA.
When SS/SHDN reaches 0.8V, it then starts to source
10µA and a new cycle begins.
The internal oscillator uses an on-chip capacitor and
trimmed precision current sources to set the oscillation
frequency to 200kHz. The triangular output of the os-
cillator sets the reference voltage at the inverting input
of the comparator. The non-inverting input of the com-
parator receives it’s input voltage from the error ampli-
fier. When the oscillator output voltage drops below the
error amplifier output voltage, the comparator output
goes high. This pulls DL low, turning off the low-side
FET, and DH is pulled high, turning on the high-side
FET (once the cross-current control allows it). When
the oscillator voltage rises back above the error ampli-
fier output voltage, the comparator output goes low.
This pulls DH low, turning off the high-side FET, and
DL is pulled high, turning on the low-side FET (once
the cross-current control allows it).
Hiccup Mode
During power up, the SS/SHDN pin is internally pulled
low until VCC reaches the undervoltage lockout level of
4.2V. Once VCC has reached 4.2V, the SS/SHDN pin
is released and begins to source 10µA of current to the
external soft-start capacitor. As the soft-start voltage
rises, the output of the internal error amplifier is
clamped to this voltage. When the error signal
reaches the level of the internal triangular oscillator,
which swings from 1V to 2V at a fixed frequency of 200
kHz, switching occurs. As the error signal crosses
over the oscillator signal, the duty cycle of the PWM
signal continues to increase until the output comes into
regulation. If an over-current condition has not oc-
curred the soft-start voltage will continue to rise and
level off at about 2.2V.
As SENSE increases, the output voltage of the error
amplifier decreases. This causes a reduction in the on-
time of the high-side MOSFET connected to DH,
hence lowering the output voltage.
Under Voltage Lockout
The under voltage lockout circuit of the SC1102 as-
sures that the high-side MOSFET driver outputs re-
main in the off state whenever the supply voltage drops
below set parameters. Lockout occurs if VCC falls below
4.1V. Normal operation resumes once VCC rises above
4.2V.
Over-Voltage Protection
The over-voltage protection pin (OVP) is high only
when the voltage at SENSE is 20% higher than the tar-
get value programmed by the external resistor divider.
The OVP pin is internally connected to an NPN emitter
follower.
An over-current condition occurs when the high-side
drive is turned on, but the PHASE node does not
2
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
Theory of Operation (Cont.)
CHARACTERISTIC CURVES
reach the voltage level set at the OCSET pin. The
PHASE node is sampled only once per cycle during the
valley of the triangular oscillator. Once an over-current
occurs, the high-side drive is turned off and the low-
side drive turns on and the SS/SHDN pin begins to
sink 2uA. The soft-start voltage will begin to decrease
as the 2uA of current discharges the external capaci-
tor. When the soft-start voltage reaches 0.8V, the SS/
SHDN pin will begin to source 10uA and begin to
charge the external capacitor causing the soft-start
voltage to rise again. Again, when the soft-start volt-
age reaches the level of the internal oscillator, switch-
ing will occur.
SC1102 Voltage Regulation, Vin=5V
2%
1%
3.3V
2.5V
2.0V
1.3V
0%
-1%
-2%
0
1
2
3
4
5
6
7
8
9
10 11 12
Current, A
SC1102 Effiency, Vin=5V
If the over-current condition is no longer present, nor-
mal operation will continue. If the over-current condi-
tion is still present, the SS/SHDN pin will again begin to
sink 2uA. This cycle will continue indefinitely until the
over-current condition is removed.
100%
90%
80%
70%
60%
3.3V
2.5V
2.0V
1.3V
0
1
2
3
4
5
6
7
8
9
10 11 12
Current, A
TYPICAL APPLICATION
+5V
+
C2
820/16V
C3
820/16V
C5
0.1
C1
820/16V
C4
820/16V
Vin 12V
R3
10
R2
1k
R1
620
_
C7
1.0
LL42
U1
SC1102
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
GND
SS/SHDN
VREF
C8
0.3
PWRGD
OVP
SHDN
VREF
PWRGD
OVP
R4
1k
R9
124*
OCSET
PHASE
DRVH
PGND
SENSE
BSTH
R8
C9
0.1
127
C11
0.1
L1
4uH
Q1
STP40NE
BSTL
+
R7
3.9
Q2
STP40NE
LL42
8
DRVL
C15
0.1
D4
C11
1500/6.3
C12
1500/6.3
C13
1500/6.3V
C14
1500/6.3V
Vout +2.5V
_
R
3.9
NOTE:
*) Vout = 1.265 x (1+R9/R8)
3
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
Component View
Bottom
Top
Copper Layer
Bottom
Top
4
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
TYPICAL PLOTS & WAVEFORMS
Output Ripple Voltage
Gate Drive Waveforms
1. VIN = 5V; VO = 3.3V; IOUT = 12A
Ch1: Vo_rpl
Ch1: Top FET
Ch2: Bottom FET
2. VIN = 5V; VOUT = 1.3V; IOUT = 12A
Ch1: Vo_rpl
Ch1: Top FET
Ch2: Bottom FET
5
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
Start Up
Ch1: Vin
Ch2: Vss
Ch3: Top Gate
Ch4: Vout
Vin = 5V
Vout = 3.3V
Iout = 2A
Vbst = 12V
Hiccup Mode
Ch1: Vin
Ch2: Vss
Ch3: Top Gate
Ch4: Vout
Vin = 5V
Vout = 3.3V
Vbst = 12V
Iout = S.C.
6
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Synchronous DC/DC Controller for
Distributed Power Supply Applications
AN99-7
January 4, 2000
OUTLINE DRAWING SO-14
7
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
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