T68K1MGI-8 [ETC]

Low Power 1M (128Kx8)-Bits Static RAM; 低功耗1M （ 128Kx8 ） -Bits静态RAM


型号：	T68K1MGI-8
厂家：	ETC
描述：	Low Power 1M (128Kx8)-Bits Static RAM 低功耗1M （ 128Kx8 ） -Bits静态RAM
文件：	总14页 (文件大小：145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

T68 K/S/R 1M Family

Low Power 1M (128Kx8)-Bits Static RAM

DESCRIPTION

The T68K1M, T68S1M, and T68R1M device family is a low power and high performance

CMOS SRAM organized as 131,072 words by 8 bits. It operates from 2.7V to 3.6V, 2.2V to

2.7V, and 1.65V to 2.2V. Easy memory expansion is provided by an active LOW chip enable 1

(/CE1), active HIGH chp enable 2 (CE2) and active LOW output enable (/OE) and three-state

I/O drivers. Four control pins (/CE1, CE2, /OE, and /WE) fully control the operation mode of the

T68 K/S/R 1M device family. An active LOW write enable signal (/WE active low) controls the

write/read operation of the memory. When /CE1 and /WE inputs go LOW and CE2 input goes

HIGH simultaneously, the device is in write mode and data on the 8 data pins (IO1~IO8) is

written into the memory location specified by the address on address pins (A0~A16). When

/CE1 and /OE inputs go LOW and CE2 and /WE input stay in HIGH state, the device is in read

mode and data in the specified memory address is driven onto the 8 data pins. The 8 data pins

will be in high-impedance state if both /OE and /WE pins are in HIGH (inactive) state. The T68

K/S/R 1M device family has an automatically power-down feature when the chip is deselected

(/CE1 pin HIGH or CE2 pin LOW). The T68 K/S/R 1M device family is available in JEDEC

standard 32-pin 450-mil SOP, 32-pin 8mmx20mm plastic TSOP, 32-pin 8mmx13.4mm plastic

STSOP, and 36-ball 6mmx8mm BGA package, also for DICE.

FEATURES

—

Operation voltage……………… T68K1M…………………………….................2.7V ~ 3.6V

T68S1M……………………………………….. 2.2V ~ 2.7V

T68R1M………………………….................. 1.65V ~ 2.2V

Low active power and standby power

—

High access times: 70ns/85ns/100ns

TTL-compatible inputs and outputs

Easy memory expansion with /CE1, CE2 and /OE

Low data retention voltage…………………………..2.0V (for K), 1.5V (for S), 1.0V (for R)

Auto power down when deselected

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T68 K/S/R 1M

PRODUCT FAMILY

Power Dissipation

Package

Type

Operating

Part Number

V_CCRange

Speed

Operating

Standby

Temperature

(I_CC2, Max.)

(I_SB1, Max.)

T68K1MGC -7/-8

T68K1MTC -7/-8

T68K1MSC -7/-8

T68K1MBC -7/-8

T68K1MDC -7/-8

T68S1MGC -7/-8

T68S1MTC -7/-8

T68S1MSC -7/-8

T68S1MBC -7/-8

T68S1MDC -7/-8

T68R1MGC -8/-10

T68R1MTC -8/-10

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

2.7V~3.6V

20mA

3uA

2uA

70ns/ 85ns

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

Commercial

(+0^oC~+70^oC)

2.2V~2.7V

20mA

15mA

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

T68R1MSC -8/-10 1.65V~2.2V 85ns/ 100ns

T68R1MBC -8/-10

T68R1MDC -8/-10

Power Dissipation

Operating

Package

Type

Part Number

V_CCRange

Speed

Operating

(I_CC2, Max.)

Standby

Temperature

(I_SB1, Max.)

T68K1MGE -7/-8

T68K1MTE -7/-8

T68K1MSE -7/-8

T68K1MBE -7/-8

T68K1MDE -7/-8

T68S1MGE -7/-8

T68S1MTE -7/-8

T68S1MSE -7/-8

T68S1MBE -7/-8

T68S1MDE -7/-8

T68R1MGE -8/-10

T68R1MTE -8/-10

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

2.7V~3.6V

20mA

15mA

3uA

2uA

70ns/ 85ns

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

Extended

(-25^oC~+85^oC)

2.2V~2.7V

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

T68R1MSE -8/-10 1.65V~2.2V 85ns/ 100ns

T68R1MBE -8/-10

T68R1MDE -8/-10

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T68 K/S/R 1M

Power Dissipation

Package

Type

Operating

Part Number

V_CCRange

Speed

Operating

(I_CC2, Max.)

Standby

Temperature

(I_SB1, Max.)

T68K1MGI -7/-8

T68K1MTI -7/-8

68K1MSI -7/-8

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

2.7V~3.6V

20mA

15mA

3uA

2uA

T68K1MBI -7/-8

T68K1MDI -7/-8

T68S1MGI -7/-8

T68S1MTI -7/-8

T68S1MSI -7/-8

T68S1MBI -7/-8

T68S1MDI -7/-8

T68R1MGI -8/-10

T68R1MTI -8/-10

70ns/ 85ns

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

Industrial

(-40^oC~+85^oC)

2.2V~2.7V

SOP-32

TSOP-32

STSOP-32

BGA-36

Dice

T68R1MSI -8/-10 1.65V~2.2V 85ns/ 100ns

T68R1MBI -8/-10

T68R1MDI -8/-10

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T68 K/S/R 1M

PIN CONFIGURATION

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T68 K/S/R 1M

LOGIC BLOCK

(PIN DESCRIPTION)

Pin Name

Function

A0 ~ A16

IO1 ~ IO8

/CE1

CE2

Address Input Pins

Data Input/Output Pins

Chip Enable 1 Input Pin

Chip Enable 2 Input Pin

Output Enable Input Pin

Write Enable Input Pin

Power Supply Pin

/OE

/WE

V_CC

V_SS

Ground Pin

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T68 K/S/R 1M

TRUTH TABLE

Mode

Deselected

Write

/CE1

CE2

(1)

/WE

/OE

I/O1~8

High-Z

Input

Power

Standby

Active

Read

Output

High-Z

Output Disabled

1. ’ X’ means don’ t care. Must be in high or low state.

ABSOLUTE MAXINUM RATINGS⁽¹⁾

Symbol

V_CC

Parameter

Rating

Unit

-0.5 ~ Vcc.max+1V⁽²⁾

-0.5 ~ Vcc.max+0.3V⁽³⁾

-0.5 ~ Vcc+0.5V⁽²⁾

-0.5 ~ Vcc+0.3V⁽³⁾

Power Supply Voltage (toV_SS

)

V_IN/V_OUTInput / Output Voltage

I_OUT

P_D

Output Current into Outputs (LOW)

Power Dissipation

1.0

T_STG

Storage Temperature

-65 ~ +150

^OC

T_SOLDERSoldering Temperature and Time

260 ^OC , 10sec (Lead Only)

C-Grade

E-Grade

I-Grade

0 ~ 70

T_A

Operating Temperature

-25 ~ 85

^OC

-40 ~ 85

1. Stresses greater than those listed in the Absolute Maximum Ratings table may cause permanent damage

to the device.Functional operation should be restricted to recommended operating condition. Exposure to

absolute maximum ratings conditions for extended periods may affect reliability.

2. For K and S family.

3. For R family.

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T68 K/S/R 1M

RECOMMENDED DC OPERATING RANGE

Symbol

T68K1M

Parameter

Rating

Unit

2.7 ~ 3.6

2.2 ~ 2.7

V_CC

V_SS

V_IH

Supply Voltage

Ground

T68S1M

T68R1M

1.65 ~ 2.2

T68K1M

T68S1M

T68R1M

T68K1M

T68S1M

T68R1M

2.2 ~ V_CC+0.5

2.0 ~ V_CC+0.5

1.4 ~ V_CC+0.5

-0.5 ~ 0.6

-0.5 ~ 0.4

Input High Voltage

V_IL

Input Low Voltage

CAPACITANCES⁽¹⁾

Symbol

Parameter

Min.

Max.

Condition

C_IN

Input Capacitance

8pF

Unmeasured pins set

to 0V

C_IO

Input/Output Capacitance

10pF

1. The Capacitances listed in the above table are sampled, not 100% tested.

DATA RENTATION CHARACTERISTICS

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

T68K1M

T68S1M

T68R1M

2.0

3.6

2.7

2.2

V_CCfor Data

V_DR

Standby Mode

1.5

Retention

1.0

C-Grade

E-Grade

I-Grade

C-Grade

E-Grade

I-Grade

C-Grade

E-Grade

I-Grade

V_CC=2.0V and

CMOS Standby mode⁽¹⁾

T68K1M

T68S1M

T68R1M

Data Retention

Current

V_CC=1.5V and

CMOS Standby mode⁽¹⁾

I_DR

V_CC=1.0V and

CMOS Standby mode⁽¹⁾

T_SDR

T_RDR

Data Retention Setup Time

See data retention waveform

Data Retention Recovery Time

T_RC

Note: 1. Standby mode: /CE1³ Vcc-0.2V or CE2£ Vss+0.2V

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T68 K/S/R 1M

DC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Input Leakage Current

Test Condition

V_IN= V_SSto V_CC

Min

Typ

Max Unit

I_LI

-1

/CE1=V_IHCE2=V_ILor /OE=V_IH

or /WE=V_IL, V_IO=V_SSto V_CC

/CE1£0.2V, CE2³ V_CC-0.2V,

I_LO

Output Leakage Current

-1

T68K1M

T68S1M

T68R1M

T68K1M

T68S1M

T68R1M

3⁽¹⁾

V_IN£0.2V or V_IN³ V_CC-0.2V

I_CC1

Cycle time = 1ms, 100%duty,

I_IO=0mA

2⁽¹⁾

Average Operating Current

15⁽¹⁾

10⁽¹⁾

/CE1=V_IL, CE2=V_IH, V_IN=V_IHor

V_IN=V_IL,

I_CC2

Cycle time = min, 100% duty,

I_IO=0mA

T68K1M IOL = 2.0mA

T68S1M IOL = 0.5mA

T68R1M IOL = 0.2mA

T68K1M IOH = -1.0mA

T68S1M IOH = -0.5mA

T68R1M IOH = -0.1mA

T68K1M

0.4

V_OL

V_OH

I_SB

Output Low Voltage

Output High Voltage

TTL Standby Current

CMOS Standby Current

2.2

2.0

1.4

0.2

/CE1=V_IHor CE2= V ,

T68S1M

T68R1M

T68K1M

T68S1M

T68R1M

other inputs = V_IHor V

1.0⁽¹⁾

0.8⁽¹⁾

/CE1³ V_CC-0.2V or

CE2£V_SS+0.2V ,

I_SB1

other inputs = 0 to V_CC

Note: 1. Ta=25^oC, V_CC=3.0V (K), V_CC=2.5V (S), and V_CC=1.8V (R), not 100% tested.

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T68 K/S/R 1M

AC ELECTRICAL CHARACTERISTICS

˜ TEST CONDITIONS

Input Pulse Level: 0.2Vcc(≦V_iL), 0.8Vcc(≧V_IH

)

Input Rising and Falling Time: 5ns

Input and Output Reference Voltage: 0.9V(R), 1.1V(S), 1.5V (K)

Output Load: C_L= 30pF + one TTL gate

READ CYCLE

Speed Bin

-8(85ns)

Units

Symbol

Parameter List

-7 (70ns)

-10(100ns)

Min

Max

Min

Max

Min

Max

t_RC

t_AA

Read Cycle Time

100

Address Access Time

100

t_CO

t_OE

t_LZ

Chip Select to Output

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold From Address

t_OLZ

t_HZ

t_OHZ

t_OH

WRITE CYCLE

Speed Bin

-8(85ns)

Symbol

Parameter List

Units

-7 (70ns)

-10 (100ns)

Min

Max

Min

Max

Min

100

Max

t_WC

t_CW

t_AS

Write Cycle Time

Chip Select to End of Write

Address Setup Time

t_AW

t_WP

t_WR

t_WHZ

t_DW

t_DH

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

t_OW

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T68 K/S/R 1M

TIMING DIAGRAMS

˜ TIMEING WAVEFORM OF READ CYCLE (1)

(Address Controlled, /CE1=/OE=VIL, CE2=/WE=VIH)

˜ TIMEING WAVEFORM OF READ CYCLE (2) (/WE=VIH)

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T68 K/S/R 1M

TIMING WAVEFORM OF WRITE CYCLE (1) (/WE Controlled)

TIMING WAVEFORM OF WRITE CYCLE (2) (/CE1 OR CE2 Controlled)

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T68 K/S/R 1M

DATA RETENTION WAVEFORM (1) (/CE1 Controlled)

DATA RETENTION WAVEFORM (2) (CE2 Controlled)

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T68 K/S/R 1M

PACKAGE DIMENSION

32L PIN SOP (445 mil)

3 2 L P I N T S O P ( 8 x 2 0 )

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T68 K/S/R 1M

32L PIN TSOP (8x13.4)

36 BALL BGA ( 6mm x 8mm)

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T68K1MGI-8 [ETC]

相关型号：

T68K1MSC-7

T68K1MSC-8

T68K1MSE-7

T68K1MSE-8

T68K1MTC-7

T68K1MTC-8

T68K1MTE-7

T68K1MTE-8

T68K1MTI-7

T68K1MTI-8

T68R1M

T68R1MBC-10