TA2021-100_技术文档

T E C H N I C A L I N F O R M A T I O N

Absolute Maximum Ratings

SYMBOL

Vs

PARAMETER

Supply Voltage (Vspos & Vsneg)

Value

+/-50

UNITS

V

V5

Positive 5 V Bias Supply

6

VGG

T_STORE

T_A

Internally generated voltage

Storage Temperature Range

Operating Free-air Temperature Range

12

V

-40 to 150

-20 to +80

ºC

Notes:

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Damage will occur to the device if VN10 is not supplied or falls below the recommended

operating voltage when V_Sis within its recommended operating range.

Operating Conditions

SYMBOL

PARAMETER

MIN.

TYP.

MAX. UNITS

Vs

Supply Voltage (Vspos & Vsneg)

+/- 25 +/- 35 +/- 45

V

V5

Positive 5 V Bias Supply

4.5

10

5

5.5

12

VGG

Internally Generated Voltage

11

Note: Recommended Operating Conditions indicate conditions for which the device is functional. See

Electrical Characteristics for guaranteed specific performance limits.

Electrical Characteristics

T_A= 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.

SYMBOL

PARAMETER

MIN.

TYP.

MAX. UNITS

I_q

Quiescent Current

(no load)

+35V

-35V

+5V

mA

A

VN12

I_S

Source Current @ P_OUT= 100W, R = 4 V_SPOS= +35V

Ω

L

A

@ 10% THD+N

V_SNEG= -35V

I5

mA

Source Current for 5V Bias Supply @ P_OUT= 100W, R = 4

Ω

L

IVGG

Vu

mA

Source Current for VGG Supply @ P_OUT= 100W, R_L= 4Ω

Under Voltage (Vspos & Vsneg)

25

1

V

Vo

Over Voltage (Vspos & Vsneg)

45

V_IH

High-level Input Voltage (MUTE & SLEEP)

Low-level Input Voltage (MUTE & SLEEP)

3.5

V_IL

I_DDMUTE

Mute Supply Current

(no load)

+35V

-35V

+5V

mA

V

VGG

V_OH

V_OL

High-level Output Voltage (HMUTE/SDA, OVERLOAD/SCL &

PSMUTE)

Low-level Output Voltage (HMUTE/SDA, OVERLOAD/SCL &

PSMUTE)

3.5

1

V

V_TOC

A_V

Over Current Sense Voltage Threshold

1.2

V

V/V

mV

Gain Ratio V_OUT/V_IN, R_IN= 0Ω

Voffset

Offset Voltage, no load, MUTE = Logic low

2

T E C H N I C A L I N F O R M A T I O N

Minimum and maximum limits are guaranteed but may not be 100% tested.

Performance Characteristics – Single Ended

Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T_A= 25°C.

See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.

SYMBOL

PARAMETER

Output Power

(continuous RMS/Channel)

CONDITIONS

MIN.

TYP.

MAX. UNITS

P_OUT

W

THD+N = 0.1%, R_L= 8Ω

R_L= 4Ω

THD+N = 10%, R_L= 8Ω

R_L= 4Ω

100

90

125

THD + N Total Harmonic Distortion Plus

Noise

.02

0.08

110

%

P_OUT= 4W/Channel, R_L= 4Ω

IHF-IM

IHF Intermodulation Distortion

%

19kHz, 20kHz, 1:1 (IHF), R_L= 4Ω

P

_OUT= 1W/Channel

SNR

Signal-to-Noise Ratio

dB

A Weighted, R_L= 4Ω,

P_OUT= 100W/Channel

CS

Channel Separation

80

65

dB

%

0dBr = __W, R_L= 4Ω, f = 1kHz

Input Referenced, 30kHz Bandwidth

P_OUT= 90W/Channel, R_L= 8Ω

PSRR

Power Supply Rejection Ratio

Power Efficiency

90

η

e_NOUT

Output Noise Voltage

A Weighted, no signal, input shorted,

DC offset nulled to zero

150

µV

Minimum and maximum limits are guaranteed but may not be 100% tested.

Notes:

1) VP1=VP2=+35V, VN1=VN2=-35V, V5 = +5V, VGG = +11V referenced to PGND

3

T E C H N I C A L I N F O R M A T I O N

Serial Bus Timing

Unless otherwise specified, _____________

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNITS

t _CL

SCL (Clock) Period

µs

t _SETUP

t _STABLE

t _START

t _STOP

Data In Set-up Time to SCL Low

µs

Data Out Stable after SCL Low

SDA Low Set-up Time to SCL Low (Start Condition)

SDA High Hold Time after SCL High (Stop Condition)

t_CL

OVERLOAD/SCL

t _START

t_STOP

HMUTE/SDA

(Data In)

t_SETUP

HMUTE/SDA

(Data Out)

t _STABLE

4

T E C H N I C A L I N F O R M A T I O N

Pin Description

1,13

2

Function

VB2,VB1

VGG

Description

Bootstrapped voltages supply drive to gates of high-side FET’s

Regulated output of onboard switching regulator

Power ground

3

PGND

4,12

5

6,11

7,10

8,9

14

VP2,VP1

SW12V

VS2,VS1

OUT2,OUT1

VN2,VN1

SWFB

Positive power supply connections

Switching node

Source voltage for high side FET’s

Power FET outputs

Negative power supply connections

Feedback for onboard regulator

15

SLEEP

When set to logic high, both amplifiers are muted and in low power (idle)

mode. When low (grounded), both amplifiers are fully operational. If left

floating, the device stays in the mute mode. Ground if not used.

A logic high output indicates the amplifiers are muted

Dual function pin:

16

17

PSMUTE

OVRLD/SCL

OVRLD – A logic high output indicates that the level of the input signal has

overloaded the amplifiers, signifying increased distortion

SCL – When tied to V5 through a pull-up resistor, this pin becomes the serial

clock line of the serial control bus

18

HMUTE/SDA

Dual function pin:

HMUTE – A logic high output indicates that the output stages of both

amplifiers are shut off and muted.

SDA – When OVRLD/SCL is tied to V5 through a pull up resistor, this pin

becomes the serial data line of the serial control bus

When set to logic high, both amplifiers are muted. When set to logic low or

grounded both amplifiers are fully operational. Ground if not used.

Dual function pin:

19

20

MUTE

MIS/ADDR

MIS – When control/status of the device is via analog pins, the voltage level

ion this pint sets the Mute-in –silence threshold

ADDR – When OVRLD/SCL is tied to V5 through a pull up resistor, the voltage

on this pin selects the chip address of the device for the serial control bus

5V power supply

21

22

V5

AGND

Analog Ground

23,24

25,26

INP1,INP2

AUXOUT1,AUXOUT2

Inputs for channels 1 and 2

Auxiliary outputs that provide a low impedance, buffered audio output

where the signal level is set by the volume control

Bandgap reference

When control/status of the device is via analog pins, the voltage level on this

pin sets the output signal volume

27

28

V2BG

DCVOL

29,31

30,32

FDBKN1,FDBKN2

GNDKELVIN1

GNDKELVIN2

Feedback for channels 1 and 2

Kelvin connection to speaker ground channels 1 and 2

5

T E C H N I C A L I N F O R M A T I O N

32-pin SSIP Package

(Top View)

VB2

VGG

1

2

PGND

3

VP2

4

SW12

5

VS2

6

OUT2

7

VN2

8

VN1

9

OUT1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

VS1

VP1

VB1

SWFB

SLEEP

PSMUTE

OVRLD/SCL

HMUTE/SDA

MUTE

MIS/ADDR

V5

GA

INP1

INP2

AUXOUT1

AUXOUT2

V2BG

DCVOL

FDBKN1

GNDKELVIN1

FDBKN2

GNDKELVIN2

6

T E C H N I C A L I N F O R M A T I O N

Test/Application Circuit

TA2021-100

25

AUXOUT1

26

AUXOUT2

Positive Supply Star

29 FDBKN1

C_IN

INP1

VP1

23

12

R_IN

VS1

VN1

11

9

V5

OUT1

10

13

15

19

SLEEP

MUTE

L_F

R_D

C_D

VB1

R_L

C_F

R_G

GNDKELVIN1

30

Negative Supply Star

Positive Supply Star

16

17

FDBKN2

VP2

PSMUTE

OVRLD/SCL

HMUTE/SDA

31

4

6

VS2

18

8

7

VN2

OUT2

L_F

1

VB2

R_D

C_D

C_IN

R_L

C_F

INP2

24

21

R_IN

R_G

GNDKELVIN2

32

Negative Supply Star

V5

+5V

14

SW-FB

MIS/ADDR 19

SW12

VGG

5

2

27

28

V2BG

VN

VB1 VB2

PGND

3

DCVOL

Power Supply Ground Star

AGND

24

Note - Heavy Lines Indicate High-Current Paths

7

T E C H N I C A L I N F O R M A T I O N

Modes of Operation

The TA2021-100 has two modes of operation: Mode 1, where control/status of the amplifier is

by signals on analog pins of the TA2021-100, and Mode 2, where control/status of the amplifier

is by registers accessed through a digital serial control bus. When OVRLD/SCL is tied to V5

through a 5 KΩ resistor and the TA2021-100 senses this during power-up it will go into Mode 2

operation. Otherwise the TA2021-100 will use Mode 1 operation. The operating description in

this section explains operation of the TA2021-100 in Mode 1. Mode 2 operation is described in

the next section.

TA2021-100 Basic Amplifier Operation

The audio input signal is fed to the processor internal to the TA2021-100, where a modulation

pattern is generated. This pattern is spread spectrum and varies between approximately

200kHz and 1.5MHz. Complementary copies of the switching pattern are level-shifted by

MOSFET drivers which drive the gates of internal power MOSFETs that are connected as a half

bridge. The output of the half bridge is a power-amplified version of the switching pattern

that switches between VP and VN. This signal is then low-pass filtered to obtain amplified

audio.

The processor portion of the TA2021-100 is operated from a 5-volt supply (between V5 and

GND). In the generation of the complementary modulation pattern for the output MOSFETs,

the processor inserts a “break-before-make” dead time between when it turns one transistor

off and it turns the other one on in order to minimize shoot-through currents in the MOSFETs.

Feedback information from the output of the half-bridge is supplied to the processor via

FDBKN1. Additional feedback information to account for ground bounce is supplied via

GNDKELVIN1.

The MOSFET drivers in the TA2021-100 are operated from voltages obtained from VGG for the

low-side driver, and VB1 for the high-side driver. VGG must be a stable 12V above VN. The

TA2021-100 provides switching regulator circuitry to supply VGG and VB1.

Over- and Under-Voltage Protection

The TA2021-100 senses the power rails for over- and under-voltage conditions. The over- and

under-voltage limits are Vo and Vu respectively as specified in the Electrical Characteristics

table. If the supply voltage exceeds Vo or drops below Vu, the TA2021-100 shuts off the

output stages of the amplifiers and asserts a logic level high on HMUTE/SDA. The removal of

the over-voltage or under-voltage condition returns the TA2021-100 to normal operation and

returns HMUTE/SDA to a logic level low. Please note that the limits specified in the Electrical

Characteristics table are at 25°C and these limits may change over temperature.

Over-current Protection

The TA2021-100 has over-current protection circuitry to protect itself and the output transistors

from short-circuit conditions. The TA2021-100 uses the voltage across a resistor that is in series

with each output MOSFET to detect an over-current condition.

8

T E C H N I C A L I N F O R M A T I O N

When the voltage drop becomes greater than V_OC-LIMIT(approximately 0.7V) the TA2021-100 will

try to limit the current by internally decreasing the gain of the input stage of the TA2021-100.

If the voltage drop continues to increase to greater than V_OC-SD(approximately 1.2V) the TA2021-

100 will shut off the output stages of its amplifiers and supply a logic level high on

HMUTE/SDA. The occurrence of an over-current condition is latched in the TA2021-100 and can

be cleared by toggling the MUTE input or cycling power.

Mute

When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high-

and low-side transistors are turned off) and a logic level high is output on the HMUTE/SDA pin.

When a logic level low is supplied to MUTE, both amplifiers are fully operational and a logic

level low is supplied on HMUTE/SDA. There is a delay of approximately 200 milliseconds

between the de-assertion of MUTE and the un-muting of the TA2021-100.

Mute-in-silence

The TA2021-100 will automatically mute both channels when the sum of the audio signal

supplied to both of its inputs is below a preset level for approximately 340 seconds. The preset

audio level is determined by the voltage on the MIS/ADDR pin according to the following table

(The MIS/ADDR pin also determines the input-limit level, as described in the next section):

MIS/ADDR Pin Voltage

(Fraction of V5)

0.00 – 0.05

0.05 – 0.10

0.10 – 0.15

0.15 – 0.20

0.20 – 0.25

0.25 – 0.30

0.30 – 0.35

0.35 – 0.40

0.40 – 0.45

0.45 – 0.50

0.50 – 0.55

0.55 – 0.60

0.60 – 0.65

0.65 – 0.70

0.70 – 0.75

0.75 – 0.80

0.80 – 0.85

0.85 – 0.90

0.90 – 0.95

0.95 – 1.00

MIS Level

Input-limit Level

-80dB

-74dB

-68dB

-62dB

MIS Off

76%

79%

85%

100%

76%

79%

85%

100%

75%

79%

85%

100%

75%

79%

85%

100%

75%

79%

85%

100%

9

T E C H N I C A L I N F O R M A T I O N

The TA2021-100 will quickly automatically come out of mute when it detects that the input

signal has gone above the preset level.

Input Limit

To “soften” the clipping characteristics of the TA2021-100 it will limit the audio signal to a pre-

determined, programmable input-limit level according to the voltage on the MIS/ADDR pin as

specified in the previous table. This limit is a percentage of the maximum possible output level.

Overload

When logic low, the OVRLD/SCL pin indicates that the level of the input signal has overloaded

the amplifier and that the audio output signal is starting to distort. The OVRLD/SCL signal is

active only while an overload is present. The OVRLD/SCL signal can be used to control a

distortion indicator light or LED through a simple buffer circuit.

Sleep

When a logic high signal is supplied to SLEEP, both amplifier channels are shut down and the

TA2021-100 is put into a low quiescent-current mode. When a logic level low is supplied to

MUTE, both amplifiers are fully operational.

Volume Control

A 5 MΩ potentiometer is used between V2BG, DCVOL and AGND (analog ground) to control

the output volume of both channels. When DCVOL is at the same level as V2BG, the output

volume is at –6 dB. When DCVOL is at the same level as GND, the output volume is at the

minimum, or –119.5 dB.

Auxiliary Outputs

The outputs AUXOUT1 and AUXOUT2 are analog-signal audio outputs in which the signal level

is controlled by the volume control. These outputs are capable of driving approximately 15mW

each into 20-ohm loads. These outputs are still active when the TA2021-100 is in mute mode,

even if the TA2021-100 is muted because no speaker is connected (see next section).

Speaker Detect

On power-up the TA2021-100 checks to make sure that speakers are connected to prevent

damage. If a speaker is not detected on either channel on power-up, the TA2021-100 keeps the

output stages of both amplifiers shut down (in mute) and signifies this fact by asserting a logic

level one on HMUTE/SDA. The TA2021-100 will come out of mute when speakers are

connected, even after a relatively long period of time (minutes after power-up).

10

T E C H N I C A L I N F O R M A T I O N

Functional Description – Mode 2

Serial Bus Operation

When OVRLD/SCL is tied to V5 to a 5 kΩ resistor and the TA2021-100 senses this during power-

up it will go into Mode 2 operation, where control/status of the amplifier is by registers

accessed through a digital serial control bus. This serial bus is compatible with Philips’ I²C^TMbus.

The TA2021-100 operates as a slave device on the bus. The OVRLD/SCL line is an input (no clock

is generated by the TA2021-100) and the HMUTE/SDA line is a bi-directional serial data path.

Six simple operations with the two lines of the serial bus are used for transmitting to or

receiving from a TA2021-100:

1. Start bit: A high-to-low transition of the data line while the clock line is in a high

state

2. Seven-bit slave address: The first seven bits following a start bit (MSB first)

3. Read/write bit which defines whether the slave is a transmitter or receiver: The next

bit immediately after the address is the direction of the transfer. A 0 indicates that

the master will write information to the slave. A 1 indicates that the master will

receive data from the slave.

4. Acknowledge bit: Every eight-bit byte transferred (including the eight bits

comprising the address and read/write bit) is followed by an acknowledge bit from

the receiver (the master generates all clock pulses). The transmitter releases the

data line during the acknowledge clock pulse. If there was no error detected, the

receiver will pull down the SDA line during the high period of the acknowledge

clock pulse. If a slave receiver is not able to acknowledge, the slave will keep the

SDA line high and the master can then generate a stop bit to abort the transfer. If a

master receiver keeps the SDA line high during the acknowledge clock pulse the

master is signaling the end of data transmission and the slave transmitter releases

the data line to allow the master to generate a stop bit.

5. Message bits divided into eight-bit bytes: One bit is transferred during each clock

pulse. The data must be stable during the high period of the clock. The data line

can only change when the clock line is low. The MSB of the byte is transmitted first.

6. Stop bit: A low-to-high transition of the data line while the clock line is in a high

state.

Slave ID Address

The TA2021-100 has a seven-bit slave ID address. The five most-significant bits of the slave

address are hardwired inside the TA2021-100 and are 10000. The two least-significant bits are

determined by the voltage on the MIS/ADDR pin according to the following table:

MIS/ADDR Pin Voltage

(Fraction of V5)

0.00 – 0.25

Address

A1 = 0, A0 = 0

A1 = 0, A0 = 1

A1 = 1, A0 = 0

A1 = 1, A0 = 1

0.25 – 0.50

0.50 – 0.75

0.75 – 1.00

11

T E C H N I C A L I N F O R M A T I O N

The complete slave address is:

1

0

A1

A0

MSB

LSB

Register Assignments

The registers in the TA2021-100 are selected by the eight-bit index register. At power-up the

Index register is set to zero. The seven least-significant bits of the Index register define the

register address space in the TA2021-100. When a 1 is written to the MSB of the Index register

the Index register value is auto-incremented (by 1) after each byte transfer is complete. If a 0 is

written to the MSB of the Index register the Index register value is not changed.

The following table indicates the Index register address of each register:

I6

0

X

I5

0

X

I4

0

X

I3

0

1

I2

0

1

0

1

I1

0

1

0

1

I0

0

1

0

1

0

1

0

1

Register Addressed

STATUS

FAULT

INITIAL STATE

VOLUME ADC

CONTROL

CONFIGURATION

VOLUME1 (Channel 1)

VOLUME2 (Channel 2)

Test

X

Reserved

X = Don’t care

All Test Registers/Bits should NOT be accessed as they are used for manufacturing test of the

TA2021-100 and can cause unexpected operation. All Reserved Registers/Bits are read-only with

a value of 0.

STATUS Register

ST7

ST6

ST5

ST4

ST3

ST2

ST1

ST0

Overload

Detect

Over-

current

Detect

Reserved Reserved Reserved

Mute In

Silence

Muted

Fault

ST7:

ST6:

Overload detect. When 0, indicates normal operation. When 1, indicates that

the level of the audio input signal has overloaded the amplifier and that the

audio signal is starting to distort. This bit is read/write. Writing a 0 to it will

clear it.

Over-current detect. When 0, indicates normal operation. When 1, indicates

that the voltage across R_Shas become greater than V_OC-LIMIT, indicating an over-

current condition and the TA2021-100 is attempting to limit the current by

decreasing the input level using the volume control. This bit is read/write.

Writing a 0 to it will clear it.

12

T E C H N I C A L I N F O R M A T I O N

ST5:

ST4:

ST3:

ST2:

Reserved. Read-only with a value of 0. Writing to it has no effect.

Mute In Silence. When 0, indicates normal operation. When 1, indicates the sum

of the input levels of both channels is below the specified level for the

specified duration. This bit is read-only. Writing to it has no effect.

Muted. When 0, indicates normal operation. When 1, indicates both outputs

are muted either due to an external control request or a fault condition has

been detected. This bit is read-only. Writing to it has no effect.

ST1:

ST0:

Fault. When 0, indicated normal operation. When 1, indicates a fault has been

Detected. This bit is read-only. Writing to it has no effect.

FAULT Register

F7

F6

F5

F4

F3

F2

F1

F0

Reserved Reserved Reserved Reserved

Over-

current

fault

Power

Supply

Mute

Over-

temp.

Fault

Voltage

Fault

F7:

F6:

F5:

F4:

F3:

Reserved. Read-only with a value of 0. Writing to it has no effect.

Over-current fault. When 0, indicates normal operation. When 1, indicates that

the voltage across R_Shas become greater than V_OC-SD, indicating an over-current

fault and the TA2021-100 has shut down the output stages of its amplifiers. This

bit is read-only. Writing to it has no effect.

F2:

Power supply mute. When 0, indicates normal operation. When 1, indicates an

over-current condition has occurred, the TA2021-100 has shut down the output

stages of its amplifiers and the over-current situation still exists. This bit is read-

only. Writing to it has no effect.

F1:

F0:

Over-temperature fault. When 0, indicates normal operation. When 1, indicates

that the die temperature of the TA2021-100 has exceeded TBD. This bit is read-

only. Writing to it has no effect.

Voltage fault. When 0, indicates normal operation. When 1, indicates an over-/

under- voltage condition has shut down the TA2021-100. This bit is read-only.

Writing to it has no effect.

INITIAL STATE Register

IS7 IS6

IS5

IS4

IS3

IS2

IS1

IS0

Reserved Reserved Speaker

Speaker Reserved

Test

Detect

Channel

2

Detect

Channel

1

IS7:

IS6:

IS5:

Reserved. Read-only with a value of 0. Writing to it has no effect.

Speaker detect channel 2. When 0, indicates that a speaker has been detected.

13

T E C H N I C A L I N F O R M A T I O N

When 1, indicates that a speaker has not been detected and the amplifier has

been muted. This bit is read-only. Writing to it has no effect.

Speaker detect channel 1. When 0, indicates that a speaker has been detected.

When 1, indicates that a speaker has not been detected and the amplifier has

been muted. This bit is read-only. Writing to it has no effect.

Reserved. Read-only with a value of 0. Writing to it has no effect.

Test. Should not be accessed.

IS4:

IS3:

IS2:

IS1:

IS0:

Test. Should not be accessed.

VOLUME ADC Register

V7

V6

V5

V4

V3

V2

V1

V0

MSB

LSB

V7-V0: Volume ADC. These bits provide a digital word value for the volume level set by

the voltage on the DCVOL pin. The resolution is 0.5dB per bit/step. All bits in

this register are read-only.

V7

1

V6

1

V5

1

V4

1

V3

1

V2

1

V1

1

V0

1

Volume/Gain

Maximum

X

0

X

0

X

0

1

X

0

X

0

X

0

X

0

Intermediate Level

Minimum

0

X

Minimum

CONTROL Register

CTL7

Mute

CTL6

Sleep

CTL5

Input

Select

CTL4

CTL3

CTL2

CTL1

CTL0

Reserved Reserved Reserved Reserved Reserved

CTL7: Mute. Writing a 0 to this bit (power-up initialization value) tells the TA2021-100

to operate normally. Writing a 1 to this bit tells the TA2021-100 to go into mute

mode, where the output stages of both amplifiers are shut down but all other

circuitry is still operational (including the volume control and AUXOUT audio

outputs. This bit is read/write.

CTL6: Sleep. Writing a 0 to this bit (power-up initialization value) tells the TA2021-100

to operate normally. Writing a 1 to this bit shuts down both amplifiers and

most other circuitry in the TA2021-100 and puts the device in a low-power

mode. This bit is read/write.

CTL5: Test. Should not be accessed.

CTL4: Test. Should not be accessed.

CTL3: Reserved. Read-only with a value of 0. Writing to it has no effect.

CTL2-CTL0: Input-limit level. The TA2021-100 will limit the audio signal to a percentage

of the maximum possible output level as specified by these bits in order to

“soften” its clipping characteristics. These bits are read/write.

14

T E C H N I C A L I N F O R M A T I O N

CTL2

CTL1

CTL0

Input-limit Level

1

0

1

0

1

0

1

0

1

0

1

0

1

0

73%

76%

78%

79%

82%

85%

88%

100%

CONFIGURATION Register

CFG7

Test

CFG6

Volume

Zero

CFG5

Volume

Ramp

CFG4

Volume

Control

Mode

CFG3

MIS

Time 1

CFG2

MIS

Time 0

CFG1

MIS

Level 1

CFG0

MIS

Level 0

Cross

CFG7: Test. Should not be accessed.

CFG6: Volume zero cross. Writing a 0 to this bit (power-up initialization value)

tells the TA2021-100 that volume changes can be made at any time. Writing a 1

to this bit tells. The TA2021-100 to only make volume changes at zero crossings

of the audio inputs.

CFG5: Volume ramp. Writing a 0 to this bit (power-up initialization value) tells the

TA2021-100 to implement any volume change requested immediately as

requested. Writing a 1 to this bit tells the TA2021-100 to implement any volume

at a rate of 40 msec per dB.

CFG4: Volume control mode. Writing a 0 to this bit (power-up initialization value) tells

the TA2021-100 to use the voltage on the DCVOL pin to directly control the

volume of both channels. Writing a 1 to this bit tells the TA2021-100 to use the

values in the VOLUME1 and VOLUME2 registers to set the output volumes of

the respective channels. This bit is read/write.

CFG3-CFG2: MIS time. These bits set the time interval during which the input

audio level must be below the specified level after which the TA2021-100 will

mute its outputs. These bits are read/write.

CFG3

CFG2

MIS Time

340 seconds (power-up initialization

value)

0

1

0

1

85 seconds

680 seconds

∞ (MIS disabled)

CFG1-CFG0: MIS level. These bits set the audio level below which the input signal must

be for the TA2021-100 to mute its outputs after the specified time interval.

These bits are read/write.

CFG1

CFG0

MIS Level

0

-80dB (power-up initialization value)

15

T E C H N I C A L I N F O R M A T I O N

0

1

0

1

-74dB

-68dB

-62dB

VOLUME1 Register

V1R7

MSB

V1R6

V1R5

V1R4

V1R3

V1R2

V1R1

V1R0

LSB

V1R7-V1R0: Volume 1 (Channel 1). These bits set the output volume level for Channel 1

when the CFG4 bit in the CONFIGURATION register is set to 1. The resolution is

0.5dB per bit/step. The power-up initialization value is all ones. All bits in this

register are read/write.

V1R7 V1R6 V1R5 V1R4 V1R3 V1R2 V1R1 V1R0

Volume/Gain

Maximum (+4dB)

Minimum (-119.5dB)

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

VOLUME2 Register

V2R7

MSB

V2R6

V2R5

V2R4

V2R3

V2R2

V2R1

V2R0

LSB

V2R7-V2R0: Volume 2 (Channel 2). These bits set the output volume level for Channel 2

when the CFG4 bit in the CONFIGURATION register is set to 1. The resolution is

0.5dB per bit/step. The power-up initialization value is all ones. All bits in this

register are read/write.

V2R7 V2R6 V2R5 V2R4 V2R3 V2R2 V2R1 V2R0

Volume/Gain

Maximum (+4dB)

Minimum (-119.5dB)

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

Bus Transfer Sequences

To Be Supplied.

16

T E C H N I C A L I N F O R M A T I O N

Application Information

Power Supplies

The TA2021-100 requires the split supply rails VP1(VP2) and VN1(VN2), and +5V(VA). It also uses

some additional voltages, VGG, V_BOOT1and V_BOOT2, that it generates internally. The selection of

components for the switching regulator … To Be Supplied

Supply Voltage and Output Power

The relationship between the bipolar power supply voltage needed, V_S, for a given RMS output

power, P_OUT, into a given load, R_L, at a given level of THD (total harmonic distortion) is

approximated by:

V_S= (2 x R_Lx P_OUT)^0.5/(K x R_L/(R_L+ R_ON+ R_S+ R_COIL))

where:

R_ON= The at-temperature R_DSONof the output transistors, M.

R_COIL= Resistance of the output filter inductor.

R_S= Sense Resistor

K = THD Factor, a number fixed by the algorithms in the TA2021-100’s signal processor

that provides the relationship between THD at full output power of the amplifier

and V_S. K corresponds to THD at full output power as follows:

THD

0.1%

1%

K

0.83

0.95

1.09

10%

Bridged Operation

Note that the two channels of a TA2021-100 amplifier can be used to provide a single, bridged

amplifier of almost four times the output power of one of the single-ended amplifier channels.

To configure a bridged amplifier, the input to one TA2021-100 channel must be the inverted

signal of the input to the other channel.

Low-frequency Power Supply Pumping

A potentially troublesome phenomenon in single-ended switching amplifiers is power supply

pumping. This is caused by current from the output filter inductor flowing into the power

supply output filter capacitors in the opposite direction as a DC load would drain current from

them. Under certain conditions (usually low-frequency input signals), this current can cause the

supply voltage to “pump” (increase) and eventually cause over-voltage/under-voltage shut

down. Moreover, since over/under-voltage are not “latched” shutdowns, the effect would be

an amplifier that oscillates between on and off states.

Even though the TA2021-100 has circuitry that nulls out any DC offset on power-up, a prudent

design will comprehend the power supply pumping issue. A no-cost solution uses the fact that

music has low frequency information that is correlated in both channels (it is in phase). This

17

T E C H N I C A L I N F O R M A T I O N

information can be used to eliminate boost by putting the two channels of a TA2021-100

amplifier out of phase with each other. This works because each channel is pumping out of

phase with the other, and the net effect is a cancellation of pumping currents in the power

supply. The phase of the audio signals needs to be corrected by connecting one of the speakers

in the opposite polarity as the other channel.

Amplifier Gain and Input Resistor Selection

The value of the input resistor, R_IN, is based on the required voltage gain, A_V, of the amplifier

according to:

A_V= 800 x10³/(R_IN+ 5000)

where R_IN= Input resistor value in ohms.

Input Capacitor Selection

C_INcan be calculated once a value for R_INhas been determined. C_INand R_INdetermine the input

low-frequency pole. Typically this pole is set at 10 Hz. C_INis calculated according to:

C_IN= 1/(2π x F_P)(R_IN+ 5000)

where:

R_IN= Input resistor value in ohms.

F_P= Input low frequency pole (typically 10Hz).

DC Offset

The TA2021-100 has circuitry that nulls out any DC offset on power-up and external circuitry to

perform this function, as was necessary with the TA0102A and TA0103A, is no longer necessary.

It should be noted that the DC voltage on the output of a TA2021-100 amplifier with no load in mute mode is

approximately 2.5V. This offset does not need to be nulled. The output impedance of the amplifier in mute

mode is approximately 10 KOhms. This means that the 2.5V drops to essentially zero when a typical load is

connected.

Clamping Diodes

The purpose of the diodes across each of the output MOSFETs is to clamp the voltages the

MOSFET experiences to levels within its rating to prevent damage. Tripath recommends that

fast-recovery or schottky diodes be used for this purpose. The breakdown voltage rating of

this diode should be similar to that of the MOSFET. Also, the forward voltage drop of this

diode should be less than that of the internal body diode of the MOSFET.

Turn-on & Turn-off Noise

If turn-on or turn-off noise is present in a TA2021-100 amplifier, the cause is frequently due to

other circuitry external to the TA2021-100. While the TA2021-100 has circuitry to suppress

turn-on and turn-off transients, the combination of the power supply and other audio circuitry

with the TA2021-100 in a particular application may exhibit audible transients. One solution

18

T E C H N I C A L I N F O R M A T I O N

that will completely eliminate turn-on and turn-off pops and clicks is to use a relay to

connect/disconnect the amplifier from the speakers with the appropriate timing at power

on/off. The relay can also be used to protect the speakers from a component failure (e.g.

shorted output MOSFET), which is a protection mechanism that some amplifiers have. Circuitry

external to the TA2021-100 would need to be implemented to detect these failures.

Output Filter Design

One advantage of Tripath amplifiers over PWM solutions is the ability to use higher-cutoff-

frequency filters. This means any load-dependent peaking/droop in the 20kHz audio band

potentially caused by the filter can be made negligible. This is especially important for

applications where the user may select a 4-Ohm or 8-Ohm speaker. Furthermore, speakers are

not purely resistive loads and the impedance they present changes over frequency and from

speaker model to speaker model.

Tripath recommends designing the filter as a 2nd order, 80kHz LC filter. Tripath has obtained

good results with L_F= 18uH and C_F= 0.22uF.

The core material of the output filter inductor has an effect on the distortion levels produced

by a TA2021-100 amplifier. Tripath recommends low-mu type-2 iron powder cores because of

their low loss and high linearity.

Tripath also recommends that an RC damper be used after the LC low-pass filter. No-load

operation of a TA2021-100 amplifier can create significant peaking in the LC filter, which

produces strong resonant currents that can overheat the output MOSFETs and/or other

components. The RC dampens the peaking and prevents problems. Tripath has obtained good

results with R_D= 33Ω and C_D= 0.1uF.

It is highly recommended that the design process for a TA2021-100 amplifier include an analysis

of the interaction of intended speaker(s) with the LC filter and RC damper to ensure the

desired frequency response is attained. Component values for the LC filter and RC damper may

need to be altered from the Tripath suggestions to achieve the required response.

Grounding

To Be Supplied

Circuit Board Layout

Considerable care needs to be taken in the layout of the circuit board for a TA2021-100

amplifier. The high currents flowing through PCB traces and the inductive effects due to the

switching frequencies involved can cause large overshoot and undershoot voltages if care is not

taken. A general rule to follow is to keep the PCB trace of each signal path to/from each lead

of each output MOSFET as short as physically possible.

Certain circuit functions in a TA2021-100 amplifier cannot share PCB return paths with other

functions because of the resistive and inductive effects of the switching currents and

frequencies used. These so-called ‘Kelvin’ paths must each have a dedicated PCB trace from the

TA2021-100 to their destination. GNDKELVIN1 and GNDKELVIN2 should be treated as Kelvin

paths.

19

T E C H N I C A L I N F O R M A T I O N

Performance Measurements of a TA2021-100 Amplifier

Tripath amplifiers operate by modulating the input signal with a high-frequency switching

pattern. This signal is sent through a low-pass filter (external to the Tripath amplifier) that

demodulates it to recover an amplified version of the audio input. The frequency of the

switching pattern is spread spectrum and typically varies between 200kHz and 1.5MHz, which is

well above the 20Hz – 22kHz audio band. The pattern itself does not alter or distort the audio

input signal but it does introduce some inaudible noise components.

The measurements of certain performance parameters, particularly those that have anything to

do with noise, like THD+N, are significantly affected by the design of the low-pass filter used

on the output of the TA2021-100 and also the bandwidth setting of the measurement

instrument used. Unless the filter has a very sharp roll-off just past the audio band or the

bandwidth of the measurement instrument ends there, some of the inaudible noise

components introduced by the Tripath amplifier switching pattern will get integrated into the

measurement, degrading it.

One advantage of Tripath amplifiers is that they do not require large multi-pole filters to

achieve excellent performance in listening tests, usually a more critical factor than performance

measurements. Though using a multi-pole filter may remove high-frequency noise and

improve THD+N type measurements (when they are made with wide-bandwidth measuring

equipment), these same filters can increase distortion due to inductor non-linearity. Multi-pole

filters require relatively large inductors, and inductor non-linearity increases with inductor

value.

Efficiency Of A TA2021-100 Amplifier

The efficiency, η, of an amplifier is:

η = P_OUT/P_IN

The power dissipation of a TA2021-100 amplifier is primarily determined by the on resistance,

R_ON, of the output transistors used, and the switching losses of these transistors, P_SW. For a

TA2021-100 amplifier, P_IN(per channel) is approximated by:

P_IN= P_DRIVER+ P_SW+ P_OUT((R_S+ R_ON+ R_COIL+ R_L)/R_L)²

where:

P

_DRIVER= Power dissipated in the TA2021-100 = 1.6W/channel

P_SW= 2 x (0.015) x Q_g(Q_gis the gate charge of M, in nano-coulombs)

_COIL= Resistance of the output filter inductor (typically around 50mΩ)

R

For a 100W RMS per channel, 8Ω load amplifier using an R_Sof 50mΩ,

P_IN= P_DRIVER+ P_SW+ P_OUT((R_S+ R_ON+ R_COIL+ R_L)/R_L)²

= 1.6 + 2 x (0.015) x (95) + 100 x ((0.025 + 0.11 + 0.05 + 8)/8)²

= 1.6 + 2.85 + 104.6

= 109.05

20

T E C H N I C A L I N F O R M A T I O N

In the above calculation the R_{DS (ON)}of 0.065Ω was multiplied by a factor of 1.7 to obtain R_ONin

order to account for some temperature rise of the MOSFETs. (R_DS

typically increases by a

(ON)

factor of 1.7 for a typical MOSFET as temperature increases from 25ºC to 170ºC.)

So,

η = P_OUT/P_IN= 100/109.05 = 92%

This compares favorably to the measured efficiency (see Typical Performance graphs).

21

T E C H N I C A L I N F O R M A T I O N

Package Information

32-pin SSIP

22

T E C H N I C A L I N F O R M A T I O N

ADVANCED DEVELOPMENT – This is a product in development. Tripath Technology Inc. reserves

the right to make any changes without further notice to improve reliability, function or design.

This data sheet contains the design specifications for a product in development. Specifications may

change in any manner without notice. Tripath and Digital Power Processing are trademarks of

Tripath Technology Inc. Other trademarks referenced in this document are owned by their

respective companies.

Tripath Technology Inc. reserves the right to make changes without further notice to any products

herein to improve reliability, function or design. Tripath does not assume any liability arising out of

the application or use of any product or circuit described herein; neither does it convey any license

under its patent rights, nor the rights of others.

TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH

TECHNOLOGY INC.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical

implant into the body, or (b) support or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in this labeling, can be reasonably expected

to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to

perform can be reasonably expected to cause the failure of the life support device or system, or to

affect its safety or effectiveness.

TRIPATH TECHNOLOGY INC.

3900 Freedom Circle, Santa Clara, California 95054, 1-408-567-3000.

WWW.TRIPATH.COM

23


型号：	TA2021-100
厂家：	ETC
描述：	STEREO 100W (4-ohm) CLASS-T DIGITAL AUDIO AMPLIFIER DRIVER USING DPP-TM TECHNOLOGY STEREO 100W （ 4欧姆） CLASS -T数字音频放大器驱动器使用DPP -TM技术驱动器音频放大器
文件：	总23页 (文件大小：136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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