THAT2155 [ETC]

IC Voltage-Controlled Amplifiers; IC电压控制放大器


型号：	THAT2155
厂家：	ETC
描述：	IC Voltage-Controlled Amplifiers IC电压控制放大器放大器
文件：	总10页 (文件大小：143K)
中文：	中文翻译
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IC Volt age-Con t rolled

Am plifiers

T H A T C o r p o r a t i o n

THAT 2151, 2150A, 2155

F E ATUR E S

AP P LICATIONS

•

Wide Dyn am ic Range: >116 dB

Wide Gain Range: >130 dB

Expon en tial (dB) Gain Con trol

•

Faders

Pann ers

Com pressors

Expan ders

Equ alizers

Filters

Low Distortion : (0.008% @ 0 dB

gain, 0.035% @15dB gain )

•

Wide Gain -Bandwidth: 6 MHz

Low Cost: $2.20 in ’000s (2155)

Sin gle In -Line Package

Oscillators

Au tom ation System s

Du al Gain -Con trol Ports (pos/ neg)

De s c r ip t io n

Th e THAT 2150 Series in tegrated-circu it volta ge-

qu ire m in im a l s u pport circu itry. Fabrica ted in a

con trolled a m plifiers (VCAs) are h igh -perform a n ce

cu rren t-in / cu rren t-ou t devices with two opposin g-

polarity, voltage-sen s itive con trol ports. Ba sed on

dbx tech n ology, th ey offer wide-ran ge expon en tial

con trol of gain an d a tten u a tion with low sign al dis-

tortion . Th e pa rts a re h ou s ed in a space-efficien t,

pla stic 8-pin s in gle-in -lin e (SIP) package, an d re-

s u per low-n ois e process u tilizin g h igh h _FE, com ple-

m en ta ry NPN/ PNP pairs, th e 2150 Series VCAs

com bin e h igh gain -ban dwidth produ ct with low

n ois e, low distortion , a n d low offs et to offer discrete

perform an ce a t IC prices. Th ey are available in

th ree gra des , selected for distortion , a llowin g th e

u ser to optim ize cost vs . perform an ce.

PIN 1

MODEL NO.

THAT

TYP.

BIAS CURRENT

COMPENSATION

ITEM MILLIMETERS

INCHES

0.8 MAX.

Vbe

20.32 MAX.

0.043 MIN.

1.1 MIN.

MULTI-

PLIER

.004

0.02

0.01

0.1

0.5

0.25

2.54

0.05 MAX.

0.02 MIN.

0.2 MAX.

1.27 MAX.

0.51 MIN.

5.08 MAX.

.008

2.8

0.11

5.75 MAX.

1.5 MAX.

0.227 MAX.

0.058 MAX.

+.10

.04

.002

0.01 ^+.004

0.25

.02

3.2

0.126

0.043 MIN.

1.1 MIN.

Figu re 1. 2150 Series Equ ivalen t Circu it Diagra m

Figu re 2. 2150 Series Ph ysical Ou tlin e

dbx is a registered tradema rk of Carillon Electron ics Corporation

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Page 2

2150 Series IC VCAs

S P E CIF ICATIONS ¹

Ab s o lu t e -Ma x im u m R a t in gs (T_A= 2 5 ˚C)

Positive Su pply Voltage (V_CC

)

+18 V

Power Dissipation (P_D) (T_A= 75˚C)

330 m W

Negative Su pply Voltage (V_EE

)

-18 V

Operatin g Tem peratu re Ran ge (T_OP

)

-20 to +75˚C

-40 to +125˚C

Su pply Cu rren t (I_CC

)

10 m A

Storage Tem peratu re Ran ge (T_ST)

R e c o m m e n d e d Op e r a t in g Co n d it io n s

2151

2150A

2155

Min Typ Max

Parameter

Symbol

V_CC

Conditions

Min Typ Max

Units

Positive Supply Voltage

Negative Supply Voltage

Bias Current

-5

+12 +15

-5

+12 +15

-5

+12 +15

V_EE

-12

2.4

-15

-12

2.4

-15

-12

2.4

-15

I_SET

V_CC-V_EE= 24 V

I_SET= 2.4 mA

—

Signal Current

I_IN+I_OUT

175 750

125 550

µArms

E le c t r ic a l Ch a r a c t e r is t ic s ²

2151

2150A

Min Typ Max

2155

Parameter

Symbol

I_CC

Conditions

No Signal

Min Typ Max

Units

Supply Current

—

2.4

—

2.4

—

2.4

Equiv. Input Bias Current

Input Offset Voltage

I_B

No Signal

V_OFF(IN)

V_OFF(OUT)

+10

—

+10

—

+10

—

Output Offset Voltage

R_out=20 kΩ

0 dB gain

—

+15 dB gain

+40 dB gain

Gain Cell Idling Current

Gain-Control Constant

I_IDLE

—

µA

T_A=25˚C (T_CHIP35˚C)

-60 dB < gain < +40 dB

E_C+/Gain (dB) Pins 2 & 4 (Fig. 14)

6.0

6.1

6.2

6.0

6.1

6.2

6.0

6.1

6.2

mV/dB

E_C-/Gain (dB)

Pin 3

-6.0 -6.1 -6.2

Gain-control TempCo

Gain-Control Linearity

Off Isolation (Fig. 14)

Output Noise

∆ E_C/ ∆ T_CHIP

Ref T_CHIP= 27˚C

—

+0.33

0.5

—

+0.33

0.5

—

+0.33

0.5

—

%/˚C

-60 to +40 dB gain

E_C+=-360mV, E_C-=+360mV

110

115

—

110

115

110

115

—

e_n(OUT)

20 Hz-20 kHz

R_out= 20kΩ

0 dB gain

—

-98

-88

-97

-86

—

-98

-88

-96

-86

—

-98

-88

-96

-86

dBV

+15 dB gain

1. All specification s su bject to ch an ge with ou t n otice.

2. Un less oth erwis e n oted, T =25˚C, V = +15V, V = -15V. Tes t circu it is a s sh own in Figu re 3. SYM is ad-

ADJ

ju sted for m in im u m THD @ V =1 V, 1 kHz, 0 dB gain .

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Rev. 10/ 25/ 96

Page 3

E le c t r ic a l Ch a r a c t e r is t ic s (Co n t ’d . )

2151

2150A

2155

Parameter

Symbol

THD

Conditions

I_IN+ I_OUT= 180 µA, 1 kHz

0 dB gain

Min Typ Max

Units

Total Harmonic Distortion

—

0.004 0.02

0.025 0.045

—

0.005 0.03

0.05 0.07

—

±15 dB gain

I_IN+ I_OUT= 150 µA, 1 kHz

0 dB gain

—

0.006 0.03

0.05 0.07

±15 dB gain

Symmetry Control Voltage

Gain at 0 V Control Voltage

V_SYM

A_V= 0 dB, THD < 0.07%

E_C–= 0 mV

-1.6

-0.1

+1.6

-2

-2.5

-0.2

+2.5

0.0 +0.1

-0.15 0.0 +0.15

0.0 +0.2

+15V

47p

Ec-

2150

Series

VCA

20k

V+

Ec-

OUT

INPUT

-IN

Ec+

GND

LF351

OUTPUT

+15V

V-

10u

20k

Rsym

5.1k

50k

SYM

ADJ

150k

300k (2155)

390k (2150A)

470k (2151)

-15V

Figu re 3. Typical Application Circu it

Figu re 4. Frequ en cy Respon se Vs. Gain (2150A)

Figu re 5. Noise (20kHz NBW) Vs. Gain (2150A)

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Page 4

2150 Series IC VCAs

Th e o r y o f Op e r a t io n

Th e THAT 2150 Series VCAs are design ed for h igh

perform an ce in a u dio-frequ en cy a pplication s requ irin g

expon en tial gain con trol, low distortion , wide dyn a m ic

ran ge an d low dc bia s m odu lation . Th ese parts con trol

ga in by con vertin g an in pu t cu rren t sign al to a bipola r

logged voltage, a ddin g a dc con trol volta ge, an d re-con -

vertin g th e s u m m ed volta ge ba ck to a cu rren t th rou gh

a bipola r an tilog circu it.

V_Tis th e th erm a l voltage,

; I_C3is th e collector cu r-

ren t of Q3; a n d I_Sis th e revers e-satu ration cu rren t of

Q3. It is a ss u m ed th a t D3 m atch es Q3 (an d will be a s-

su m ed th at th ey m atch Q4 a n d D4, as well).

In typica l a pplication s (s ee Figu re 3, Pa ge 3), pin 4

is con n ected to a voltage s ou rce a t grou n d or n ea rly

grou n d poten tial. Pin

8 is con n ected to a virtu al

grou n d (u s u a lly th e in vertin g in pu t of a n op am p with

n ega tive feedback a rou n d it). With pin 4 n ear grou n d,

a n d pin 8 a t virtu al grou n d, th e voltage at th e cath odes

of D3 a n d D4 will ca u s e an expon en tially-related cu r-

ren t to flow in D4 an d Q4, an d ou t via pin 8. A sim ila r

equ ation govern s th is beh avior:

Figu re 6 presen ts a con s idera bly sim plified in tern al

circu it diagra m of th e IC. Th e ac in pu t sign al cu rren t

flows in pin 1, th e in pu t pin . Th e in tern al op am p

works to m a in tain pin 1 at a virtu a l grou n d poten tial

by drivin g th e em itters of Q1 a n d (th rou gh th e Volta ge

Bia s Genera tor) Q3. For pos itive in pu t cu rren ts (I_inde-

fin ed as flowin g in to pin 1), th e op a m p drives th e em it-

ter of Q1 n ega tive, tu rn in g off its collector cu rren t,

wh ile sim u lta n eou sly drivin g th e em itter of Q3 n ega-

I_C4

V₃= E_C+− 2V_Tln

I_S

Expon en tial Gain Con trol

Th e sim ila rity between th e two preceedin g equ ation s

begs fu rth er exploration . Accordin gly:

I_C4

I_S

I_C3

I_S

V₃= E_C+− 2V_Tln

= E_C−− 2V_Tln

I_C4

I_S

I_C3

− 2V_Tln

I_S

Ec+

Ec-

_C+− E_C−= 2V_Tln

Voltage

Bias

OUT

Generator

I_C4

I_C3

Ec+

(SYM)

= 2V_Tln

Rea rran gin g term s,

−E

C+ C−

I_C4= I_C3

If pin 3 an d pin 4 are at grou n d poten tia l, th e cu r-

ren t in Q4/ D4 will precisely m irror th at in Q3/ D3.

Wh en pin 3 is positive with res pect to pin 4, th e voltage

a cross th e bas e-em itter ju n ction of Q3 is h igh er th an

th a t a cross th e bas e-em itter ju n ction of Q4, so th e

Q4/ D4 cu rren t rem ain s proportion a l to, bu t less th a n ,

th e cu rren t in Q3/ D3. In th e sa m e m an n er, a n egative

V-

Figu re 6. Sim plified In tern al Circu it Diagram

tive, tu rn in g it on . Th e in pu t s ign a l cu rren t, th erefore,

is forced to flow th rou gh Q3 an d D3.

volta ge at pin

3 with respect to pin 4 cau ses th e

Q4/ D4 cu rren t to be proportion al to, bu t greater th an

th at in Q3/ D3.

Logging & Antilogging

Becau s e th e voltage a cros s a bas e-em itter ju n ction

is loga rith m ic with collector cu rren t, th e voltage from

th e bas e of Q3 to th e cath ode of D3 is proportion al to

th e log of th e pos itive in pu t cu rren t. Th e voltage at th e

cath odes of D3 a n d D4 is th erefore proportion al to th e

log of th e positive in pu t cu rren ts plu s th e voltage a t

pin 3, th e n egative con trol port. Ma th em atically,

Th e ra tio of cu rren ts is expon en tial with th e differ-

en ce in th e volta ges E_C+an d E_C–, providin g con ven ien t

“deci-lin ear” con trol. Ma th em atically, th is is:

−E

C−

C+

I_C4

I_C3

A_V

= e

, wh ere A_Vis th e cu rren t gain .

For pin 4 a t or very n ear grou n d, at room tem pera-

tu re (25˚C), allowin g for a 10˚C in tern al tem peratu re

ris e, a n d con vertin g to a ba se of 10 for th e expon en tia l,

th is redu ces to:

I_C3

V₃= E_C−− 2V_Tln

I_S

wh ere V₃is th e voltage at th e ju n ction of D3 an d D4;

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Rev. 10/ 25/ 96

Page 5

−E

C−

Transistor Matching

A_V= 10 ^0.122

Th e bias cu rren t flows down wa rds in th e core (from

Q1 to Q3, an d from Q2 to Q4) so lon g a s th ere is good

m atch in g between a ll fou r com pou n d tran sis tors (tran -

s istors plu s diodes). Mis m a tch es will cau se a dc ou tpu t

cu rren t to flow in pin 8, wh ich will u ltim ately m a n ifes t

itself as a dc offset voltage. Sta tic offs ets a re of little

con sequ en ce in m os t au dio application s , bu t a n y m is-

m atch -cau sed dc ou tpu t cu rren t will be m odu la ted by

ga in com m an ds , an d m a y becom e au dible as “th u m ps”

if la rge, fas t gain ch an ges a re com m an ded in th e pres-

en ce of sign ifican t m is m atch es.

Wh en pin 3 is a t O V, th e cu rren t ratio is u n ity.

Wh en pin 3 is a t +122 m V, th e ou tpu t cu rren t (Q4) is

10 tim es (20 dB) les s th an th e in pu t cu rren t. At

–122 m V, th e ou tpu t cu rren t is 10 tim es (20 dB)

greater th a n th e in pu t cu rren t. An oth er wa y of ex-

pres sin g th is rela tion sh ip is:

−E_C−

0.0061

Gain =

, wh ere Gain is th e gain in decibels.

Negative In pu t Cu rren ts

Tran sis tor m atch in g als o a ffects dis tortion . If th e

top h a lf of th e ga in cell is perfectly m atch ed, wh ile th e

bottom h alf is sligh tly off, th en th e gain com m an ded by

th e voltage a t pin 3 will affect th e two h a lves of th e core

differen tly. Sin ce positive an d n egative h alves of ac

in pu t s ign a ls are h a n dled by separate pa rts of th e core,

th is gives rise to even -order distortion produ cts.

For n ega tive in pu t cu rren ts, Q1/ D1 operate with

Q2/ D2 to m irror th e lower -h a lf-core beh a vior. Pin 2 is

n orm a lly at or very n ear grou n d (see th e section below

on Symmetry Adjus tment for m ore detail), so th e sa m e

ga in s ca lin g applied to th e base of Q3 is a pplied to th e

bas e of Q2. Th e pola rity (pos itive/ n egative, in dB) of

th e gain is th e s am e for th e top pair vers u s th e bottom

pair of th e fou r “core” tran s is tors beca u se th eir sexes

(NPN/ PNP) a re in verted in th e top versu s th e bottom ,

wh ile th e ba ses are cross -con n ected between th e in pu t

(left) h alf an d th e ou tpu t (righ t) h alf of each pair.

Sym m etry Adju stm ent

Th e m on olith ic con stru ction of th e devices a ss u res

relatively good m atch in g between th e pa ired tran s is-

tors , bu t even sm all V_BEm ism atch es can cau s e u n a c-

ceptable a sym m etries in th e ou tpu t. For th is reason ,

th e bas es of Q1 an d Q4 a re brou gh t ou t separately to

pin 2 an d pin 4, res pectively. Th is allows a sm all s tatic

volta ge differen tial to be applied to th e two bas es. Th e

a pplied volta ge m u s t be s et to equ a l th e su m of th e V_BE

m is m atch es arou n d th e core (w hich va ries from s a mple

to s a mple). Figu re 3 (Page 3) in clu des a typical circu it

to apply th is sym m etry voltage. R_SYMcon trols prim a rily

even -order h arm on ic dis tortion , a n d is u s u ally ad-

ju s ted for m in im u m THD at th e ou tpu t. Figu re 8 plots

THD vs. th e voltage between pin s 2 an d 4 (th e two E_C+

ports) for variou s gain s ettin gs of a typical pa rt.

Th e resu ltin g con trol over ga in is extrem ely con s is-

ten t from u n it to u n it, s in ce it derives from th e ph ys ics

of sem icon du ctors. Figu re 7 sh ows actu al data from a

typica l 2150 Series VCA, taken at 25˚C.

Opposite Polarity Con trol

As m ay be seen from th e m ath em a tics , th e ba ses of

Q1 an d Q4 can als o be u s ed a s an addition a l con trol

Figu re 7. Gain Vers u s Con trol Voltage (Pin 3) at 25˚C

Core Bias Cu rrents

A qu iescen t bias cu rren t in th e core tran sis tors is

establish ed by th e Volta ge Bia s Genera tor sh own in

Figu re 6. Th is cu rren t acts like crossover bias in th e

ou tpu t sta ge of a com plem en tary class AB power a m -

plifier, s m ooth in g th e tra n sition between tu rn in g on

th e top (PNP) pa ir an d th e bottom (NPN) pa ir of tran s is-

tors in th e core. Th is lowers distortion greatly a t som e

cos t to n ois e perform an ce, as th e cu rren t n ois e of th e

core tra n sistors (wh ich ru n at approxim ately 20 µA) is

th e dom in an t n ois e s ou rce in th e 2150 Series VCAs .

Figu re 8. Typical THD Versu s Sym m etry Volta ge

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Page 6

2150 Series IC VCAs

port, with an opposite sen se of con trol from th at a t

pin 3. To u se th is port, both pin s m u s t be driven with

th e con trol voltage, wh ile a s m all differen tia l voltage is

a ccom m odated between th e two pin s . (Figu re 14,

Page 9, s h ows th e typical con n ection .) Eith er pin 3, or

pin s 2 a n d 4, or both ports togeth er m ay be u sed for

ga in con trol. Math em a tica lly, th is relation sh ip is as fol-

lows:

ven t s u ch dc term s, a c in pu t cou plin g is stron gly rec-

om m en ded. A plot of typical ou tpu t offs et voltage ver-

s u s ga in for th e circu it of Figu re

3 is s h own in

Figu re 9. (Th e LF351’s offs et wa s a dju s ted to 0 V for

th is plot.)

−E

C+ C−

0.122

A_V= 10

_c+− E_c−

0.0061

, wh ere A_Vis th e gain in volts/ volt, or

, wh ere Ga in is th e gain in decibels.

Gain =

Con trol Port Sou rce Im pedan ce

Th e con trol ports (pin s 2 th rou gh 4) are con n ected

directly to th e ba ses of th e loggin g an d/ or an tiloggin g

tran s is tors. As wa s im plied in th e ea rlier dis cu s sion on

Logging a nd Antilogging (Pa ge 4) th e a ccu ra cy of th e

loggin g a n d an tiloggin g is depen den t on th e E_C+a n d

E_C-volta ges bein g exactly as des ired to con trol ga in .

Th e ba se cu rren t in th e tra n sistors will follow th e col-

lector cu rren ts, of cou rse. Sin ce th e collector cu rren ts

a re s ign a l-rela ted, th e ba se cu rren ts will a lso be s ign al-

related. Sh ou ld th e sou rce im pedan ce of th e con trol

volta ge(s) be large, th e s ign al-related ba se cu rren ts will

cau se s ign al-related voltages to appea r at th e con trol

ports , wh ich will in terfere with precis e loggin g a n d

an tiloggin g, in tu rn cau sin g distortion .

Figu re 9. DC Offset Vs . Gain , After Sym m etry

Adju s tm en t

Cu rren t Program m ing

Th e size of th e cu rren t s ou rce a t th e bottom of th e

core (Figu re 6, Pa ge 4) is progra m m ed extern ally via

I_SET, wh ich is n orm a lly determ in ed by a resis tor from

pin 5 to V–. Th e voltage at pin 5 is typically –2.7 V. I_SET

divides in to two portion s : approxim a tely 400 µA is u sed

for in tern al bia sin g, an d th e rest is available for th e

cu rren t s ou rce at th e bottom of th e core. I_SETs h ou ld

th erefore be 400 µA larger th an th e total of th e pea k

in pu t an d ou tpu t sign al cu rren ts .

Th e 2150 Series VCAs are des ign ed to be operated

with zero s ou rce im pedan ce a t pin s 2 a n d 3, an d a 50Ω

s ou rce im peda n ce at pin 4. (Pin 4 is in ten ded for con -

n ection to th e sym m etry con trol, h en ce th e h igh er de-

s ign -cen ter sou rce im pedan ce.) On e can estim ate th e

dis tortion ca u sed by a specific, n on -zero s ou rce im ped-

a n ce by determ in in g th e bas e volta ge m odu lation du e

to sign a l cu rren t ba sed on a core-tra n sistor β of ap-

proxim a tely 300 (NPN) or 100 (PNP), an d con vertin g th e

Note th at th e ou tpu t im pedan ce of th e in tern al op-

a m p is a pproxim a tely 2 kΩ, an d u n der peak dem an ds ,

th e s u m of th e in pu t an d ou tpu t cu rren ts plu s I_SET

m u s t be s u pplied th rou gh th is im pedan ce, lowerin g th e

volta ge available to drive th e core. For m ore in form a-

tion , see th e Power Supplies section on Page 8.

res u ltin g decibel ga in m odu la tion to

a percen tage.

Even 100Ω can spoil th e good perform an ce of th ese

Headroom

parts at h igh s ign al levels.

Maxim u m sign al cu rren ts a re also lim ited by th e

loga rith m ic ch aracteris tics of th e core tran sis tors. In

th e 2150 Series , th ese devices are specially con -

stru cted to con form to an ideal log-lin ear cu rve over a

wide ran ge of cu rren ts, bu t th ey reach th eir lim it a t ap-

proxim ately 1 m A. Th e sym ptom of fa ilin g log con for-

m an ce is in creas in g distortion with in creasin g cu rren t

levels . Th e on s et of distortion is gradu al at low cu rren t

levels , a n d th en m ore rapid as cu rren t becom es h igh .

Figu res 10 th rou gh 12 sh ow dis tortion vers u s sign al

level for th e th ree pa rts in th e 2150 Series for -15 dB,

0 dB, a n d +15 dB ga in . Th e a ccepta ble distortion will

determ in e th e m axim u m s ign al level for a pa rticu la r

design .

DC In pu t Sign als

An y dc cu rren ts in th e feedba ck loop of th e in tern al

op am p will s h ow u p as dc term s in th e ou tpu t sign a l,

a n d will be m odu lated by ga in com m an ds . In pu t bias

cu rren ts will cau s e a dc cu rren t to flow in th e feedback

loop provided by th e in pu t s ide of th e core. For th is

rea son , in pu t bias cu rren ts in th e in tern al op am p

m u s t be kept very low. Th e bias cu rren t com pen sation

a t th e in pu t s ta ge provides excellen t ca n cellation of th e

bia s cu rren t requ ired by th e in pu t differen tial am pli-

fier. Of cou rse, th is good perform an ce can be n egated

by a dc cu rren t s u pplied from ou tside th e VCA. To pre-

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Rev. 10/ 25/ 96

Page 7

Figu re 10. 1kHz THD+Noise Vs . In pu t, -15 dB Gain

Figu re 11. 1kHz THD+Noise Vs. Level, 0 dB Gain

Figu re 12. 1kHz THD+Noise Vs. In pu t, +15 dB Gain

Ap p lic a t io n s

th e open -loop gain n a tu rally fa lls off at h igh frequ en -

cies , a skin g for too m u ch gain will lead to in creased

h igh -frequ en cy dis tortion . For bes t resu lts, th is res is-

tor sh ou ld be kept to 10 kΩ or above. Dis tortion vs. fre-

qu en cy for a 1 V s ign al at 0 dB ga in with a 20 kΩ in pu t

resistor is plotted in Figu re 13.

In pu t

As m en tion ed a bove, in pu t a n d ou tpu t sign als are

cu rren ts , n ot volta ges. Wh ile th is often cau ses som e

con ceptu al difficu lty for design ers first exposed to th is

con ven tion , th e cu rren t in pu t/ ou tpu t m ode provides

great flexibility in a pplication .

Th e qu iescen t dc volta ge level at th e in pu t is ap-

proxim ately +10 m V. As m en tion ed above, an y dc in pu t

cu rren ts will cau se dc sign als in th e ou tpu t wh ich will

be m odu lated by gain , ca u sin g a u dible th u m p. Th ere-

Th e in pu t pin (pin 1) is a virtu a l grou n d with n ega-

tive feedback provided in tern ally (see Figu re 6, Page 4).

Th e in pu t resistor (sh own as 20 kΩ in Figu re 3, Page 3)

s h ou ld be s ca led to con vert th e a va ila ble ac in pu t volt-

a ge to a cu rren t with in th e lin ear ran ge of th e device.

(Peak in pu t cu rren ts sh ou ld be kept u n der 1 m A for

bes t distortion perform a n ce.) An addition al con s ider-

a tion is stability: th e in tern al op am p is in ten ded for

operation with sou rce im pedan ces of less th a n 30 kΩ

a t h igh frequ en cies. For m ost au dio application s, th is

will presen t n o problem .

Th e ch oice of in pu t resistor h as a n addition al, su b-

tle effect on dis tortion . Sin ce th e feedback im pedan ces

a rou n d th e in tern al opa m p (essen tially Q1/ D1 a n d

Q3/ D3) a re fixed, low valu es for th e in pu t res istor will

requ ire m ore clos ed-loop gain from th e opa m p. Sin ce

Figu re 13. THD Vs . Frequ en cy, 0 dB Gain

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

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Page 8

2150 Series IC VCAs

fore, capacitive cou plin g is a lm os t m a n datory for qu al-

ity au dio application s . Ch oos e a ca pa citor wh ich will

give accepta ble low frequ en cy perform an ce for th e ap-

plication .

th is s ou rce m u st s u pply th e s u m of th e in pu t a n d ou t-

pu t sign al cu rren ts, plu s th e bias to ru n th e rest of th e

IC. Th e m in im u m va lu e for th is cu rren t is 430 µA over

th e su m of th e requ ired sign al cu rren ts. 2.4 m A is rec-

om m en ded for m os t pro a u dio application s wh ere

+15 V su pplies are com m on an d h eadroom is im port-

an t.

Mu ltiple s ign als m a y be s u m m ed by m u ltiple res is-

tors, ju s t as with an in vertin g op am p con figu ration . In

s u ch a ca se, a sin gle cou plin g ca pa citor m ay be located

n ext to pin 1 rath er th an m u ltiple ca pa citors at th e

driven en ds of th e s u m m in g res istors . However, take

care th a t th e capacitor does n ot act a s an an ten n a for

stra y sign a ls.

High er bia s levels are of lim ited valu e, partly be-

cau se th e res istor m en tion ed in th e positive s u pply dis-

cu s sion m u st s u pply all th e cu rren t devoted to th e

core, a n d pa rtly beca u s e th e core tran s istors becom e

in effective at loggin g an d a n tiloggin g at cu rren ts over

1 m A.

Ou tpu t

Sin ce pin 5 is in ten ded as a cu rren t su pply, n ot a

volta ge s u pply, bypas sin g a t pin 5 is n ot n ecessary.

Th e ou tpu t pin (pin 8) is in ten ded to be con n ected to

a virtu al grou n d n ode, s o th at cu rren t flowin g in it m ay

be con verted to a voltage (s ee Figu res 3, 14, & 15).

Ch oose th e extern al op am p for good au dio perfor-

m an ce. Th e feedback resistor s h ou ld be ch osen based

on th e desired cu rren t-to-voltage con vers ion con stan t.

Sin ce th e in pu t resis tor determ in es th e volta ge-to-cu r-

ren t con version a t th e in pu t, th e fam iliar ratio of R_f/ R_i

for an in vertin g op a m p will determ in e th e overall volt-

a ge gain wh en th e VCA IC is s et for 0 dB cu rren t ga in .

Sin ce th e VCA perform s best at settin gs n ea r u n ity

ga in , u s e th e in pu t a n d feedback resistors to provide

design -cen ter gain or los s, if n ecessary.

Pin 6 is u sed as a grou n d referen ce for th e VCA. Th e

n on -in vertin g in pu t of th e in tern al op a m p is con -

n ected h ere, a s a re variou s portion s of th e in tern al bias

n etwork. It m ay n ot be u sed a s a n addition a l in pu t pin .

Voltage Con trol

Th e prim a ry voltage-con trol pin is pin 3. Th is poin t

con trols gain in versely with applied volta ge: positive

volta ge cau s es los s, n ega tive voltage cau ses gain . As

des cribed on Page 6, th e cu rren t ga in of th e VCA is

u n ity wh en pin 3 is at 0 V with respect to pin s 2 an d 4,

a n d va ries with voltage a t approxim a tely -6.1 m V/ dB,

at room tem peratu re.

A s m a ll feedback ca pa citor arou n d th e ou tpu t op

a m p is n eces sa ry to ca n cel th e ou tpu t capacitan ce of

th e VCA. With ou t it, th is ca pa cita n ce will destabilize

m os t op am ps . Th e capa cita n ce at pin 8 is typica lly

30 pf.

As im plied by th e equ a tion for A_V(a t th e foot of

Page 4), th e gain is sen sitive to tem peratu re, in propor-

tion to th e am ou n t of gain or loss com m an ded. Th e

con stan t of proportion ality is 0.33% of th e decibel gain

com m a n ded, per degree Celsiu s , referen ced to 27°C

(300°K). Th is m ea n s th a t at 0 dB gain , th ere is n o

ch an ge in gain with tem pera tu re. However, a t -122 m V,

th e gain will be +20 dB at room tem peratu re, bu t will

be 20.66 dB a t a tem peratu re 10˚C lower. Th e form u la

is:

Power Su pplies

Th e positive su pply is con n ected directly to pin 7.

No specia l bypa ss in g is n eces sa ry, bu t it is good pra c-

tice to in clu de a sm all (~1 µf) electrolytic clos e to th e

VCA IC on th e PCB. Perform an ce is n ot particu larly de-

pen den t on s u pply voltage. Th e lowest perm issible su p-

ply volta ge is determ in ed by th e su m of th e in pu t a n d

ou tpu t cu rren ts plu s I_SET, wh ich m u s t be su pplied

th rou gh th e res istor a t th e top of th e core tran sistors

(s ee Figu re 1) wh ile s till allowin g en ou gh voltage swin g

to bia s th e in tern a l op a m p a n d th e core tran sistors

th em s elves . Th is resis tor is approxim a tely 2 kΩ. Re-

du cin g sign al cu rren ts m ay h elp accom m oda te low

su pply voltages.

E_C+−E_C−

Gain =

(0.0061) (1+0.0033) ∆T

wh ere E_Cis in volts , a n d ∆T is th e differen ce between

th e a ctu al tem peratu re a n d room tem pera tu re (25˚C).

For m ost a u dio a pplica tion s, th is ch a n ge with tem -

pera tu re is of little con sequ en ce. However, if n eces sary,

it m ay be com pen sa ted by a res istor wh ich varies its

valu e by .33%/ ˚C. Su ch pa rts a re ava ilable from RCD

Com pon en ts , In c, 3301 Bedford St., Man ch es ter, NH,

USA [(603) 669-0054], a n d KOA/ Speer Electron ics , PO

Box 547, Bradford, PA, 16701 USA [(814)362-5536].

Th e h igh est perm is sible s u pply volta ge is fixed by

th e process ch a racteristics an d in tern al power con -

su m ption . +15 V is th e n om in al lim it.

Th e n egative s u pply term in al is in ten ded to be con -

n ected to a resis tive cu rren t s ou rce, wh ich determ in es

th e cu rren t available for th e core. As m en tion ed before,

Wh en pin 3 is u s ed for voltage con trol, pin 2 is con -

n ected to grou n d an d pin 4 is u s ed to a pply a s m all

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

Rev. 10/ 25/ 96

Page 9

s ym m etry voltage (<±2.5 m V) to correct for V_BEm is-

m atch es with in th e VCA IC. For th is pu rpose, th e 2150

s eries devices were design ed for optim u m perform a n ce

with an im pedan ce of a pproxim ately 50Ω at pin 4. A

trim pot is u sed to adju s t th e voltage between pin 4

a n d pin 2 a s sh own in Figu re 3, Page 3. For s u pply

volta ges oth er th a n s h own , scale R_SYMto provide th e

requ ired a dju stm en t ra n ge.

erwise requ ired to com m an d h igh a tten u ation

(+610 m V for -100 dB gain at pin 3 alon e, vs. ±305 m V

wh en u s in g both pin 3 an d pin s 2 an d 4).

Con trol Port Drive Im pedan ce

It h a s a lrea dy been n oted th a t th e con trol port

s h ou ld be driven by a low sou rce im peda n ce for m in i-

m u m dis tortion . Th is often su ggests drivin g th e con trol

port directly with an opam p (see below u n der Nois e

Cons idera tions ). However, th e closed-loop ou tpu t im -

peda n ce of an opa m p typically rises a t h igh frequ en cies

du e to fallin g loop gain . Th e ou tpu t im peda n ce is

th erefore in du ctive at h igh frequ en cies. Excessive in -

du ctan ce in th e con trol port sou rce im peda n ce can

cau se th e VCA to oscillate in tern ally. In su ch cases , a

51 Ω resistor in series with a 1.5 n f capacitor from th e

con trol port to grou n d will u su a lly s u ffice to preven t

th e in s tability.

It is als o pos sible to u se pin 2 an d pin 4 togeth er as

a n oppos ite-sen s e voltage con trol port. A typica l circu it

u sin g th is a pproach is s h own in Figu re 14. Pin 3 m ay

be grou n ded, an d pin 2 driven a gain st th e sym m etry-

a dju s tm en t voltage. Th e ch an ge in volta ge a t pin

does h a ve a sm all effect on th e s ym m etry voltage, bu t

th is is of little pra ctical con sequ en ce in m ost applica-

tion s . Usin g th e opposite sen se of con trol ca n som e-

tim es save a n in verter in th e con trol path .

It is a lso possible (an d advan tageou s) to com bin e

both con trol ports with differen tial drive (s ee Fig-

u re 15). Wh ile th e drivin g circu itry is m ore com plex,

th is con figu ration offers better perform an ce at h igh

a tten tu a tion levels (<-90 dB) wh ere th e sin gle-con trol-

port circu its begin to sa tu rate Q1 (for E_C–drive) or Q3

(for E_C+drive). Wh en eith er of th es e tran s istors s atu -

rates, th e in tern al opam p will accom odate th e ch an ge

in cu rren t dem an d by respon din g with a sm all ch a n ge

in its in pu t offs et voltage. Th is lea ds to a n a ccu m u la-

tion of ch a rge on th e in pu t ca pacitor, wh ich in tu rn

can ca u s e th u m p wh en th e h igh atten u ation is su d-

den ly rem oved (e.g., wh en a m u ted ch an n el is open ed).

Differen tia l con trol drive avoids th e large dc levels oth -

Noise Consideration s

It is s econ d n atu re am on g good a u dio design ers to

con sider th e effects of n oisy devices on th e sign al path .

As is well kn own , th is in clu des n ot on ly a ctive devices

s u ch a s op am ps a n d tran s istors , bu t exten ds to th e

ch oice of im pedan ce levels as well. High va lu e resistors

h a ve in h eren t th erm al n oise associated with th em , a n d

th e n ois e perform a n ce of a n oth erwise qu iet circu it can

be eas ily spoiled by th e wron g ch oice of im pedan ce lev-

els .

Less well kn own , h owever, is th e effect of n oisy cir-

cu itry an d h igh im peda n ce levels in th e con trol path of

+15V

47p

2150

Series

VCA

Series

20k

V+

Ec-

OUT

INPUT

-IN

V-

Ec+

GND

LF351

OUTPUT

+15V

10u

20k

Rsym

5.1k

50k

SYM

ADJ

240k

300k (2155)

390k (2150A)

470k (2151)

Ec+

-15V

Figu re 14. Pos itive Con trol Port Usin g Pin s 2 an d 4

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

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Page 10

2150 Series IC VCAs

volta ge-con trol circu itry. Th e 2150 Series VCAs act like

dou ble-bala n ced m u ltipliers: wh en n o sign al is presen t

a t th e sign al in pu t, n ois e at th e con trol in pu t is re-

jected. So, wh en m eas u rin g n ois e (in th e a bsen ce of

s ign a l — as m ost everyon e does), even very n oisy con -

trol circu itry often goes u n n oticed. However, n oise a t

th e con trol port of th ese parts will cau se n ois e m odu la-

tion of th e sign al. Th is ca n becom e sign ifican t if care

is n ot taken to drive th e con trol ports with qu iet sig-

n als .

To avoid exces sive n ois e, on e m u st ta ke care to u se

qu iet electron ics th rou gh ou t th e con trol-volta ge cir-

cu itry. On e u s efu l tech n iqu e is to proces s con trol volt-

a ges at a m u ltiple of th e even tu al con trol con sta n t

(e.g., 61 m V/ dB — ten tim es h igh er th a n th e VCA re-

qu ires ), a n d th en atten u ate th e con trol s ign al ju s t be-

fore th e fin al drive a m plifier. With carefu l atten tion to

im pedan ce levels, rela tively n oisy op am ps m a y be

u sed for all bu t th e fin al s tage.

Closing Thou gh ts

Th e 2150 Series VCAs h ave a sm all am ou n t of in -

h eren t n oise m odu la tion beca u s e of its class AB bia s-

in g sch em e, wh ere th e s h ot n ois e in th e core

tran sistors reach es a m in im u m with n o sign a l, an d in -

creas es with th e squ are root of th e in sta n tan eou s sig-

n a l cu rren t. However, in an optim u m circu it, th e n oise

floor ris es on ly to -94 dBV with a 50 µA s ign a l at u n ity

ga in — 4 dB of n oise m odu lation . By con trast, if a

u n ity-ga in con n ected, in vertin g 5534 opam p is u sed to

directly drive th e con trol port, th e n oise floor will rise

to 92 dBV — 6 dB of n oise m odu lation .

Th e des ign an d a pplica tion of Voltage-Con trolled

Am plifiers h a s tra dition ally been pa rtly black art, in -

volvin g as m u ch m a gic as scien ce. We h ope th at th e

foregoin g dis cu s sion will h elp to de-m ys tify th e s u bject.

THAT Corporation welcom es com m en ts, qu estion s

a n d s u gges tion s rega rdin g th ese devices, th eir design

a n d a pplica tion . Please feel free to con ta ct u s with you r

th ou gh ts.

+15V

2150

Series

VCA

47p

20k

Series

V+

Ec-

OUT

INPUT

-IN

V-

Ec+

GND

LF351

OUTPUT

+15V

10u

20k

Rsym

150k

5.1k

50k

SYM

ADJ

240k

300k (2155)

390k (2150A)

470k (2151)

Ec+

-15V

Figu re 15. Usin g Both Con trol Ports (Differen tial Drive)

THAT Corporation ; 734 Fores t Street; Marlborou gh , Mas sach u setts 01752; USA

Tel: (508) 229-2500; Fax: (508) 229-2590; Web: h ttp:/ / www.th atcorp.com

THAT2155 [ETC]

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THAT2180B

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THAT2181B

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