TLC155ED_技术文档

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TLC

TLC156

EPROM/ROM-Based 8-Bit Microcontroller Series

Devices Included in this Data Sheet:

• TLC154/155/156/157 : EPROM devices

• TLC154/155/156/157 : Mask ROM devices

FEATURES

• Only 42 single word instructions

• All instructions are single cycle except for program branches which are two-cycle

• 13-bit wide instructions

• 8-bit wide data path

• 5-level deep hardware stack

• Operating speed: DC-20 MHz clock input

DC-100 ns instruction cycle

Device

Pins # I/O # EPROM/ROM (Byte) RAM (Byte)

TLC154

18

28

18

28

12

20

12

20

512

1K

49

48

49

96

TLC155

TLC156

TLC157

2K

• Direct, indirect addressing modes for data accessing

• 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler

• Internal Power-on Reset (POR)

• Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)

• Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)

• On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog

enable/disable control

• Three I/O ports IOA, IOB and IOC with independent direction control

• Soft-ware I/O pull-high/pull-down or open-drain control

• One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change

• Wake-up from SLEEP by INT pin or Port B input change

• Power saving SLEEP mode

• Programmable Code Protection

• Selectable oscillator options:

- RC: Resistor/Capacitor Oscillator

- XT: Crystal/Resonator Oscillator

- HF: High Frequency Crystal/Resonator Oscillator

- LF: Low Frequency Crystal Oscillator

• Wide-operating voltage range:

- EPROM : 2.3V to 5.5V

- ROM : 2.3V to 5.5V

This datasheet contains new product inform99032685ation. TLC reserves the rights to modify the product specification without notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

Rev0.95 Nov 20, 2003

P.1/TLC156

TLC

GENERAL DESCRIPTION

TLC156

The TLC156 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS

microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except

for program branches which take two cycles. The easy to use and easy to remember instruction set reduces

development time significantly.

The TLC156 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),

Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O

pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,

Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are four oscillator

configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.

The TLC154 and TLC155 address 512×13 of program memory, the TLC156 address 1K×13 of

program memory, and the TLC157 address 2K×13 of program memory.

The TLC156 can directly or indirectly address its register files and data memory. All special function registers

including the program counter are mapped in the data memory.

BLOCK DIAGRAM

5-level

STACK

Oscillator

Circuit

SRAM

FSR

Watchdog

Timer

Program

Counter

PORTA

PORTB

EPROM

/ ROM

Instruction

Decoder

ALU

Interrupt

Control

Timer0

Accumulator

PORTC

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TLC

PIN CONNECTION

TLC156

PDIP, SOP

SSOP

IOA2

IOA3

1

2

3

4

5

6

7

8

9

18 IOA1

17 IOA0

16 OSCI

15 OSCO

14 Vdd

IOA2

IOA3

1

2

3

4

5

6

7

8

9

20 IOA1

19 IOA0

18 OSCI

17 OSCO

T0CKI

RSTB

Vss

T0CKI

RSTB

Vss

TLC154

TLC156

16 Vdd

15 Vdd

14 IOB7

13 IOB6

12 IOB5

11 IOB4

TLC154

TLC156

IOB0/INT

IOB1

13 IOB7

12 IOB6

11 IOB5

10 IOB4

Vss

IOB0/INT

IOB1

IOB2

IOB3

IOB2

IOB3 10

PDIP, SOP

SSOP

Vss

T0CKI

Vdd

1

2

3

4

5

6

7

8

9

28 RSTB

27 OSCI

26 OSCO

25 IOC7

24 IOC6

23 IOC5

22 IOC4

21 IOC3

20 IOC2

19 IOC1

18 IOC0

17 IOB7

16 IOB6

15 IOB5

1

2

3

4

5

6

7

8

9

28 RSTB

27 OSCI

26 OSCO

25 IOC7

24 IOC6

23 IOC5

22 IOC4

21 IOC3

20 IOC2

19 IOC1

18 IOC0

17 IOB7

16 IOB6

15 IOB5

T0CKI

Vdd

NC

Vss

Vdd

NC

IOA0

IOA1

IOA2

IOA3

IOA1

IOA2

TLC155

TLC157

TLC155

TLC157

IOA3

IOB0/INT

IOB0/INT 10

IOB1 11

IOB2 12

IOB3 13

IOB4 14

IOB1 10

IOB2 11

IOB3 12

IOB4 13

Vss 14

PIN DESCRIPTIONS

Name

I/O

I/O IOA0 ~ IOA3 as bi-direction I/O port

I/O Bi-direction I/O pin with system wake-up function / External interrupt input

I/O Bi-direction I/O port with system wake-up function

I/O Bi-direction I/O port

Description

IOA0 ~ IOA3

IOB0/INT

IOB1 ~ IOB7

IOC0 ~ IOC7

Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current

consumption

T0CKI

RSTB

OSCI

I

System clear (RESET) input. This pin is an active low RESET to the device.

X’tal type: Oscillator crystal input

RC type: Clock input of RC oscillator

X’tal type: Oscillator crystal output.

RC mode: Outputs with the instruction cycle rate

Positive supply

OSCO

O

Vdd

Vss

-

Ground

Legend: I=input, O=output, I/O=input/output

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TLC

1.0 MEMORY ORGANIZATION

TLC156

TLC156 memory is organized into program memory and data memory.

1.1 Program Memory Organization

The TLC154/155 have a 9-bit Program Counter (PC) capable of addressing a 512×13 program memory

space. The TLC156 have a 10-bit Program Counter capable of addressing a 1K×13 program memory space.

The TLC157 have an 11-bit Program Counter capable of addressing a 2K×13 program memory space.

The RESET vector for the TLC154/155 is at 1FFh. The RESET vector for the TLC156 is at 3FFh. The

RESET vector for the TLC157 is at 7FFh.

The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.

TLC157 has program memory size greater than 1K words, but the CALL and GOTO instructions only have a

10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow

CALL and GOTO instructions to address the entire 2K program memory address range for TLC157, there is

another one bit to specify the program memory page. This paging bit comes from the PCHBUF<2> bit. When doing

a CALL or GOTO instruction, the user must ensure that page bit PCHBUF<2> are programmed so that the desired

program memory page is addressed. When one of the return instructions is executed, the entire 11-bit PC is POPed

from the stack. Therefore, manipulation of the PCHBUF <2> is not required for the return instructions.

FIGURE 1.1: Program Memory Map and STACK

PC<10:0>

Stack 1

Stack 2

PC<9:0>

Stack 3

Stack 4

Stack 5

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

7FFh

Reset Vector

PC<8:0>

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

3FFh

Reset Vector

:

1FFh

Reset Vector

:

008h H/W Interrupt Vector

002h S/W Interrupt Vector

000h

008h H/W Interrupt Vector

002h S/W Interrupt Vector

000h

008h H/W Interrupt Vector

002h S/W Interrupt Vector

000h

TLC154/155

TLC156

TLC157

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TLC

TLC156

1.2 Data Memory Organization

Data memory is composed of Special Function Registers and General Purpose Registers.

The General Purpose Registers are accessed either directly or indirectly through the FSR register.

The Special Function Registers are registers used by the CPU and peripheral functions to control the

operation of the device.

In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1

and RP0 bits in the FSR register to be configured for the desired bank.

TABLE 1.1: Operational Registers Map

Address

N/A (w)

Name

OPTION

IOSTA

IOSTB

IOSTC

INDF

B7

-

B6

B5

B4

B3

B2

B1

B0

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

Port A I/O Control Register

Port B I/O Control Register

Port C I/O Control Register

N/A (w)

00h (r/w)

01h (r/w)

02h (r/w)

03h (r/w)

04h (r/w)

05h (r/w)

06h (r/w)

07h (r/w)

08h (r/w)

09h (r/w)

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

TMR0

PCL

Low order 8 bits of PC

STATUS

FSR

GP2

RP1 ⁽³⁾

-

GP1

RP0 ⁽³⁾

-

GP0

TO

PD

Z

DC

C

Indirect data memory address pointer

PORTA

PORTB

PORTC ⁽¹⁾

PCON

WUCON

-

IOA3

IOB3

IOC3

-

WUB3

-

IOA2

IOB2

IOC2

-

IOA1

IOB1

IOC1

-

IOA0

IOB0

IOC0

-

IOB7

IOC7

WDTE

WUB7

-

IOB6

IOC6

EIS

WUB6

-

IOB5

IOC5

LVDTE

WUB5

-

IOB4

IOC4

ROC

WUB4

-

WUB2

WUB1

WUB0

0Ah (r/w) PCHBUF ⁽²⁾

Upper 3 bits Buffer of PC

0Bh (r/w)

0Ch (r/w)

0Dh (r/w)

0Eh (r/w)

0Fh (r/w)

PDCON

ODCON

PHCON

INTEN

/PDB3

ODB7

/PHB7

GIE

/PDB2

ODB6

/PHB6

-

/PDB1

ODB5

/PHB5

-

/PDB0

ODB4

/PHB4

-

/PDA3

ODB3

/PHB3

-

/PDA2

ODB2

/PHB2

INTIE

INTIF

/PDA1

ODB1

/PHB1

PBIE

/PDA0

ODB0

/PHB0

T0IE

INTFLAG

-

PBIF

T0IF

Legend: - = unimplemented, read as ‘0’,

Note 1 : PORTC is an 8-bit I/O Register for TLC155/157.

PORTC is a General Purpose Register for TLC154/156.

2 : There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in

TLC157.

3 : For TLC154/155/156, these bits are not used, read as ‘1’

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P.2/TLC156

TLC

TLC156

TABLE 1.2: Registers File Map for TLC154/155/156

Address

Description

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

|

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCON

WUCON

PCHBUF

PDCON

ODCON

PHCON

INTEN

INTFLAG

General

Purpose

Registers

3Fh

TABLE 1.3: Registers File Map for TLC157

FSR<7:6>

Description

0 0

Bank 0

0 1

Bank 1

1 0

Bank 2

1 1

Bank 3

Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

|

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCON

WUCON

PCHBUF

PDCON

ODCON

PHCON

INTEN

Memory back to address in Bank 0

INTFLAG

General

Purpose

Registers

General

Purpose

Registers

2Fh

30h

|

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

3Fh

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TLC

2.0 FUNCTIONAL DESCRIPTIONS

TLC156

2.1 Operational Registers

2.1.1 INDF (Indirect Addressing Register)

Address

00h (r/w)

Name

INDF

B7

B6

B5

B4

B3

B2

B1

B0

Uses contents of FSR to address data memory (not a physical register)

The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the

register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the

INDF register indirectly results in a no-operation (although status bits may be affected).

The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh).

In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1

and RP0 bits in the FSR register to be configured for the desired bank. The lower locations of each bank are

reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers.

All Special Function Registers and some of General Purpose Registers from bank 0 are mirrored in other banks for

code reduction and quicker access.

Accessed

RP1:RP0

Bank

0

1

2

3

0 0

0 1

1 0

1 1

EXAMPLE 2.1: INDIRECT ADDRESSING

• Register file 38 contains the value 10h

• Register file 39 contains the value 0Ah

• Load the value 38 into the FSR Register

• A read of the INDF Register will return the value of 10h

• Increment the value of the FSR Register by one (@FSR=39h)

• A read of the INDR register now will return the value of 0Ah.

FIGURE 2.1: Direct/Indirect Addressing for TLC154/155/156

Direct Addressing

Indirect Addressing

5

from opcode

0

5

from FSR register 0

location select

00h

3Fh

location select

addressing INDF register

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TLC

TLC156

FIGURE 2.2: Direct/Indirect Addressing for TLC157

Direct Addressing

Indirect Addressing

5 from FSR register 0

RP1:RP0

5

from opcode

0

bank select

location select

0 0

0 1

1 0

1 1

00h

location select

addressing INDF register

3Fh

2.1.2 TMR0 (Time Clock/Counter register)

Address

01h (r/w)

Name

TMR0

B7

B6

B5

B4

B3

B2

B1

B0

8-bit real-time clock/counter

The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an

external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is

increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).

The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared

when TMR0 register is written with a value.

2.1.3 PCL (Low Bytes of Program Counter) & Stack

Address

02h (r/w)

Name

PCL

B7

B6

B5

B4

B3

B2

B1

B0

Low order 8 bits of PC

TLC156 devices have a 9-bit (for TLC154/155) or 10-bit (for TLC156) or 11-bit (for TLC157)

wide Program Counter (PC) and five-level deep 9-bit (10-bit, or 11-bit) hardware push/pop stack. The low byte of PC

is called the PCL register. This register is readable and writable. The high byte of PC is called the PCH register. This

register contains the PC<10:8> bits and is not directly readable or writable. All updates to the PCH register go

through the PCHBUF register. As a program instruction is executed, the Program Counter will contain the address

of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an

instruction changes the PC.

For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<10> is updated from the

PCHBUF<2>. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated.

For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<10> is updated from the

PCHBUF<2>. The next PC will be loaded (PUSHed) onto the top of STACK. The PCL register is mapped to

PC<7:0>, and the PCHBUF register is not updated.

For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL

register is mapped to PC<7:0>, and the PCHBUF register is not updated.

For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word. However, the

PC<10:8> will come from the PCHBUF<2:0> register (PCHBUF à PCH).

PCHBUF register is never updated with the contents of PCH.

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TLC

TLC156

FIGURE 2.2: Loading of PC in Different Situations

Situation 1: GOTO Instruction

PCH

10 9

PCL

8

7

0

PC

PCHBUF<2>

Opcode<9:0>

-

PCHBUF

PCL

Situation 2: CALL Instruction

PCH

STACK<10:0>

Opcode<9:0>

10 9

8

7

PC

PCHBUF<2>

-

PCHBUF

Situation 3: RETIA, RETFIE, or RETURN Instruction

STACK<10:0>

PCH

10 9

PCL

8

-

7

-

PC

-

PCHBUF

Situation 4: Instruction with PCL as destination

PCH

10 9

PCL

8

7

PC

ALU result<7:0>

or Opcode<7:0>

PCHBUF<2:0>

-

PCHBUF

Note: 1. Bits PC<10:9> and PCHBUF<2:1> are unimplemented for TLC154/155.

Bits PC<10> and PCHBUF<2> are unimplemented for TLC156.

2. PCHBUF is used only for instruction with PCL as destination for TLC154/155/156.

PCHBUF is used for instruction with PCL as destination, GOTO and CALL instructions for TLC157.

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TLC156

2.1.4 STATUS (Status Register)

Address

03h (r/w)

Name

B7

B6

B5

B4

B3

B2

Z

B1

B0

C

STATUS

GP2

GP1

GP0

TO

PD

DC

This register contains the arithmetic status of the ALU, the RESET status.

If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these

three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits

are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different

than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the

STATUS Register as 000u u1uu (where u = unchanged).

C : Carry/borrow bit.

ADDAR, ADDIA

= 1, a carry occurred.

= 0, a carry did not occur.

SUBAR, SUBIA

= 1, a borrow did not occur.

= 0, a borrow occurred.

Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)

instructions, this bit is loaded with either the high or low order bit of the source register.

DC : Half carry/half borrow bit.

ADDAR, ADDIA

= 1, a carry from the 4th low order bit of the result occurred.

= 0, a carry from the 4th low order bit of the result did not occur.

SUBAR, SUBIA

= 1, a borrow from the 4th low order bit of the result did not occur.

= 0, a borrow from the 4th low order bit of the result occurred.

Z : Zero bit.

= 1, the result of a logic operation is zero.

= 0, the result of a logic operation is not zero.

PD : Power down flag bit.

= 1, after power-up or by the CLRWDT instruction.

= 0, by the SLEEP instruction.

TO : Time overflow flag bit.

= 1, after power-up or by the CLRWDT or SLEEP instruction.

= 0, a watch-dog time overflow occurred.

GP2:GP0 : General purpose read/write bits.

2.1.5 FSR (Indirect Data Memory Address Pointer)

Address

04h (r/w)

Name

FSR

B7

B6

B5

B4

B3

B2

B1

B0

RP1

RP0

Indirect data memory address pointer

Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.

RP1:RP0 : For TLC154/155/156, these bits are not used. Read as “1”s.

For TLC157, these bits are used to switching the bank of four data memory banks. See 2.1.1 for

detail description.

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TLC156

2.1.6 PORTA, PORTB & PORTC (Port Data Registers)

Address

05h (r/w)

06h (r/w)

07h (r/w)

Name

PORTA

PORTB

PORTC

B7

-

IOB7

IOC7

B6

-

IOB6

IOC6

B5

-

IOB5

IOC5

B4

-

IOB4

IOC4

B3

B2

B1

B0

IOA3

IOB3

IOC3

IOA2

IOB2

IOC2

IOA1

IOB1

IOC1

IOA0

IOB0

IOC0

Reading the port (PORTA, PORTB, PORTC register) reads the status of the pins independent of the pin’s

input/output modes. Writing to these ports will write to the port data latch.

PORTA is a 4-bit port data Register. Only the low order 4 bits are used (PORTA<3:0>). Bits 7-4 are unimplemented

and read as ‘0’s.

PORTB is a 8-bit port data register.

PORTC is a 8-bit port data register for TLC155/157, or a General Purpose Register for

TLC154/156.

2.1.7 PCON (Power Control Register)

Address

08h (r/w)

Name

PCON

B7

B6

B5

B4

B3

-

B2

-

B1

-

B0

-

WDTE

EIS

LVDTE

ROC

Bit3:Bit0 : Not used. Read as “0”s.

ROC : R-option function of IOA0 and IOA1 pins enable bit.

= 0, Disable the R-option function.

= 1, Enable the R-option function. In this case, if a 430KΩ external resister is connected/disconnected to Vss,

the status of IOA0 (IOA1) is read as “0”/”1”.

LVDTE : LVDT (low voltage detector) enable bit.

= 0, Disable LVDT.

= 1, Enable LVDT.

EIS : Define the function of IOB0/INT pin.

= 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked.

= 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path

of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way

of reading PORTB.

WDTE : WDT (watch-dog timer) enable bit.

= 0, Disable WDT.

= 1, Enable WDT.

2.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register)

Address

09h (r/w)

Name

B7

B6

B5

B4

B3

B2

B1

B0

WUCON

WUB7

WUB6

WUB5

WUB4

WUB3

WUB2

WUB1

WUB0

WUB0 : = 0, Disable the input change interrupt/wake-up function of IOB0 pin.

= 1, Enable the input change interrupt/wake-up function of IOB0 pin.

WUB1 : = 0, Disable the input change interrupt/wake-up function of IOB1 pin.

= 1, Enable the input change interrupt/wake-up function of IOB1 pin.

WUB2 : = 0, Disable the input change interrupt/wake-up function of IOB2 pin.

= 1, Enable the input change interrupt/wake-up function of IOB2 pin.

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TLC

TLC156

WUB3 : = 0, Disable the input change interrupt/wake-up function of IOB3 pin.

= 1, Enable the input change interrupt/wake-up function of IOB3 pin.

WUB4 : = 0, Disable the input change interrupt/wake-up function of IOB4 pin.

= 1, Enable the input change interrupt/wake-up function of IOB4 pin.

WUB5 : = 0, Disable the input change interrupt/wake-up function of IOB5 pin.

= 1, Enable the input change interrupt/wake-up function of IOB5 pin.

WUB6 : = 0, Disable the input change interrupt/wake-up function of IOB6 pin.

= 1, Enable the input change interrupt/wake-up function of IOB6 pin.

WUB7 : = 0, Disable Enable the input change interrupt/wake-up function of IOB7 pin.

= 1, Enable the input change interrupt/wake-up function of IOB7 pin.

2.1.9 PCHBUF (High Byte Buffer of Program Counter)

Address

Name

B7

-

B6

-

B5

-

B4

-

B3

-

B2

B1

B0

0Ah (r/w)

PCHBUF

Upper 3 bits Buffer of PC

There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in

TLC157.

See 2.1.3 for detail description.

2.1.10 PDCON (Pull-down Control Register)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

0Bh (r/w)

PDCON

/PDB3

/PDB2

/PDB1

/PDB0

/PDA3

/PDA2

/PDA1

/PDA0

/PDA0 : = 0, Enable the internal pull-down of IOA0 pin.

= 1, Disable the internal pull-down of IOA0 pin.

/PDA1 : = 0, Enable the internal pull-down of IOA1 pin.

= 1, Disable the internal pull-down of IOA1 pin.

/PDA2 : = 0, Enable the internal pull-down of IOA2 pin.

= 1, Disable the internal pull-down of IOA2 pin.

/PDA3 : = 0, Enable the internal pull-down of IOA3 pin.

= 1, Disable the internal pull-down of IOA3 pin.

/PDB0 : = 0, Enable the internal pull-down of IOB0 pin.

= 1, Disable the internal pull-down of IOB0 pin.

/PDB1 : = 0, Enable the internal pull-down of IOB1 pin.

= 1, Disable the internal pull-down of IOB1 pin.

/PDB2 : = 0, Enable the internal pull-down of IOB2 pin.

= 1, Disable the internal pull-down of IOB2 pin.

/PDB3 : = 0, Enable the internal pull-down of IOB3 pin.

= 1, Disable the internal pull-down of IOB3 pin.

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2.1.11 ODCON (Open-drain Control Register)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

0Ch (r/w)

ODCON

ODB7

ODB6

ODB5

ODB4

ODB3

ODB2

ODB1

ODB0

ODB0 : = 0, Disable the internal open-drain of IOB0 pin.

= 1, Enable the internal open-drain of IOB0 pin.

ODB1 : = 0, Disable the internal open-drain of IOB1 pin.

= 1, Enable the internal open-drain of IOB1 pin.

ODB2 : = 0, Disable the internal open-drain of IOB2 pin.

= 1, Enable the internal open-drain of IOB2 pin.

ODB3 : = 0, Disable the internal open-drain of IOB3 pin.

= 1, Enable the internal open-drain of IOB3 pin.

ODB4 : = 0, Disable the internal open-drain of IOB4 pin.

= 1, Enable the internal open-drain of IOB4 pin.

ODB5 : = 0, Disable the internal open-drain of IOB5 pin.

= 1, Enable the internal open-drain of IOB5 pin.

ODB6 : = 0, Disable the internal open-drain of IOB6 pin.

= 1, Enable the internal open-drain of IOB6 pin.

ODB7 : = 0, Disable the internal open-drain of IOB7 pin.

= 1, Enable the internal open-drain of IOB7 pin.

2.1.12 PHCON (Pull-high Control Register)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

0Dh (r/w)

PHCON

/PHB7

/PHB6

/PHB5

/PHB4

/PHB3

/PHB2

/PHB1

/PHB0

/PHB0 : = 0, Enable the internal pull-high of IOB0 pin.

= 1, Disable the internal pull-high of IOB0 pin.

/PHB1 : = 0, Enable the internal pull-high of IOB1 pin.

= 1, Disable the internal pull-high of IOB1 pin.

/PHB2 : = 0, Enable the internal pull-high of IOB2 pin.

= 1, Disable the internal pull-high of IOB2 pin.

/PHB3 : = 0, Enable the internal pull-high of IOB3 pin.

= 1, Disable the internal pull-high of IOB3 pin.

/PHB4 : = 0, Enable the internal pull-high of IOB4 pin.

= 1, Disable the internal pull-high of IOB4 pin.

/PHB5 : = 0, Enable the internal pull-high of IOB5 pin.

= 1, Disable the internal pull-high of IOB5 pin.

/PHB6 : = 0, Enable the internal pull-high of IOB6 pin.

= 1, Disable the internal pull-high of IOB6 pin.

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/PHB7 : = 0, Enable the internal pull-high of IOB7 pin.

= 1, Disable the internal pull-high of IOB7 pin.

2.1.13 INTEN (Interrupt Mask Register)

Address

Name

B7

B6

-

B5

-

B4

-

B3

-

B2

B1

B0

0Eh (r/w)

INTEN

GIE

INTIE

PBIE

T0IE

T0IE : Timer0 overflow interrupt enable bit.

= 0, Disable the Timer0 overflow interrupt.

= 1, Enable the Timer0 overflow interrupt.

PBIE : Port B input change interrupt enable bit.

= 0, Disable the Port B input change interrupt.

= 1, Enable the Port B input change interrupt .

INTIE : External INT pin interrupt enable bit.

= 0, Disable the External INT pin interrupt.

= 1, Enable the External INT pin interrupt.

Bit6:BIT3 : Not used. Read as “0”s.

GIE : Global interrupt enable bit.

= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue

execution at the instruction after the SLEEP instruction.

= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device

will branch to the interrupt address (008h).

Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are

all set, the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE

instruction will exit the interrupt routine and set the GIE bit to re-enable interrupt.

2.1.14 INTFLAG (Interrupt Status Register)

Address

0Fh (r/w)

Name

B7

-

B6

-

B5

-

B4

-

B3

-

B2

B1

B0

INTFLAG

INTIF

PBIF

T0IF

T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.

PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software.

INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin,

reset by software.

Bit7:BIT3 : Not used. Read as “0”s.

2.1.15 ACC (Accumulator)

Address

N/A (r/w)

Name

ACC

B7

B6

B5

B4

B3

B2

B1

B0

Accumulator

Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed.

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2.1.16 OPTION Register

Address

N/A (w)

Name

B7

-

B6

B5

B4

B3

B2

B1

B0

OPTION

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.

The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the

Timer0/WDT prescaler, Timer0, and the external INT interrupt.

The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.

PS2:PS0 : Prescaler rate select bits.

PS2:PS0

Timer0 Rate

WDT Rate

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

PSA : Prescaler assign bit.

= 1, WDT (watch-dog timer).

= 0, TMR0 (Timer0).

T0SE : TMR0 source edge select bit.

= 1, Falling edge on T0CKI pin.

= 0, Rising edge on T0CKI pin.

T0CS : TMR0 clock source select bit.

= 1, External T0CKI pin.

= 0, internal instruction clock cycle.

INTEDG : Interrupt edge select bit.

= 1, interrupt on rising edge of INT pin.

= 0, interrupt on falling edge of INT pin.

Bit7 : Not used.

2.1.17 IOSTA, IOSTB & IOSTC (Port I/O Control Registers)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

N/A (w)

IOSTA

IOSTB

IOSTC

Port A I/O Control Register

Port B I/O Control Register

Port C I/O Control Register

The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~07h)

instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode).

A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode).

The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.

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2.2 I/O Ports

Port A, port B and port C are bi-directional tri-state I/O ports. Port A is a 4-pin I/O port. Port B and port C are 8-pin I/O

ports.

All I/O pins (IOA<3:0>, IOB<7:0> and IOC<7:0>) have data direction control registers (IOSTA, IOSTB, IOSTC)

which can configure these pins as output or input.

IOB<7:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high. The

weak pull-high is automatically turned off when the pin is configured as an output pin.

IOA<3:0> and IOB<3:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal

pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.

IOB<7:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when

these pins are configured to be an output pin.

IOA0 and IOA1 are the R-option pins enabled by setting the ROC bit (PCON<4>). When the R-option function is

used, it is recommended that IOA0 and IOA1 are used as output pins, and read the status of IOA0 and IOA1 before

these pins are configured to be an output pin.

IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change

interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source.

The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input change

interrupt/wake-up function will be disabled by hardware even if it is enabled by software.

FIGURE 2.3: Block Diagram of I/O PINs

IOA3 ~ IOA0, IOC7 ~ IOC0 :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Pull-down is not shown in the figure

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IOB0/INT :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Q

D

Set PBIF

Latch

EN<

WUBn

EIS

INTEDG

EIS

INT

Pull-high/pull-down and open-drain are not shown in the figure

IOB7 ~ IOB1 :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Q

D

Set PBIF

Latch

EN<

WUBn

Pull-high/pull-down and open-drain are not shown in the figure

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2.3 Timer0/WDT & Prescler

2.3.1 Timer0

The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external

clock source (T0CKI pin).

2.3.1.1 Using Timer0 with an Internal Clock : Timer mode

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will

increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the

following two cycles.

2.3.1.2 Using Timer0 with an External Clock : Counter mode

Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on every

rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select the rising edge.

The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the

actual incrementing of Timer0 after synchronization.

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of

T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of

the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 T_OSCand low for at least 2

Tosc.

When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external clock

to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for

T0CKI to have a period of at least 4Tosc divided by the prescaler value.

2.3.2 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components.

So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode. During

normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS<4>) will

be cleared.

The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”.

The WDT has a nominal time-out period of 18 ms (without prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register. Thus,

the longest time-out period is approxmately 2.3 seconds.

The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out

and generating a device reset.

The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum SLEEP

time before a WDT Wake-up Reset.

2.3.3 Prescaler

An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog Timer

(WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a

prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa.

The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine

prescaler ratio.

When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the

prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.

The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s.

To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the

prescaler assignment from Timer0 to the WDT, and vice-versa.

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FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler

Instruction Cycle

(Fosc/4 or Fosc/2 or Fosc/8)

0

1

8

MUX

Data Bus

TMR0

Register

Sync

2 Cycles

T0CKI

1

MUX

PSA

0

Set T0IF flag

on overflow

T0SE

T0CS

0

1

0

8-Bit

Prescaler

MUX

PSA

Watchdog

Timer

MUX

PSA

WDT Time-out

PS2:PS0

2.4 Interrupts

The TLC156 series has up to three sources of interrupt:

1. External interrupt INT pin.

2. TMR0 overflow interrupt.

3. Port B input change interrupt (pins IOB7:IOB0).

INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.

A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all

interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register

regardless of the status of the GIE bit.

When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will

be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h.

The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.

The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.

The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.

Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.

When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.

2.4.1 External INT Interrupt

External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).

When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled by

clearing INTIE bit (INTEN<2>).

The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If

GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the

program will execute next PC after wake-up.

2.4.2 Timer0 Interrupt

An overflow (FFh à 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be

disabled by clearing T0IE bit (INTEN<0>).

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2.4.3 Port B Input Change Interrupt

An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit

(INTEN<1>).

Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including

read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared to “0” or

configured as output or IOB0 pin configured as INT pin will be excluded from this function.

The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before

going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following

wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared,

the program will execute next PC after wake-up.

2.5 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will

be cleared and keeps running, and the oscillator driver is turned off.

All I/O pins maintain the status they had before the SLEEP instruction was executed.

2.5.1 Wake-up from SLEEP Mode

The device can wake-up from SLEEP mode through one of the following events:

1. RSTB reset.

2. WDT time-out reset (if enabled).

3. Interrupt from RB0/INT pin, or PORTB change interrupt.

External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to

determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is

executed. The TO bit is cleared if a WDT time-out occurred.

For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up

is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP

instruction. If the GIE bit is set, the device will branch to the interrupt address (008h).

The system wake-up delay time is 18ms plus 128 oscillator cycle time.

2.6 Reset

TLC156 devices may be RESET in one of the following ways:

1. Power-on Reset (POR)

2. Brown-out Reset (BOR)

3. RSTB Pin Reset

4. WDT time-out Reset

Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and

unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT

Reset.

A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely ties

the RSTB pin to Vdd.

On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures

that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is

typically used in AC line or heavy loads switched applications.

A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before

SLEEP.

The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.

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2.6.1 Power-up Reset Timer(PWRT)

The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR),

RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.

The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.

2.6.2 Oscillator Start-up Timer(OST)

The OST timer provides a 128 oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This

delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as

long as the OST is active.

This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds.

2.6.3 Reset Sequence

When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset

sequence is as follows:

1. The reset latch is set and the PWRT & OST are cleared.

2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins

counting.

3. After the PWRT time-out, the OST is activated.

4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.

The totally system reset delay time is 18ms plus 128 oscillator cycle time.

FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit

WDT

Time-out

WDT

Module

S

R

Q

RSTB

Vdd

Reset

Latch

Low Voltage

Detector

(LVD)

BOR

POR

CHIP RESET

Power-on

Reset

(POR)

RESET

On-Chip

RC OSC

Power-up

Reset Timer

(PWRT)

Oscillator

Start-up Timer

(OST)

OSCI

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TABLE 2.1: Reset Conditions for All Registers

Power-on Reset

Brown-out Reset

RSTB Reset

WDT Reset

Register

Address

ACC

OPTION

IOSTA

N/A

xxxx xxxx

-011 1111

---- 1111

1111 1111

xxxx xxxx

1111 1111

0001 1xxx

xxxx xxxx

---- xxxx

xxxx xxxx

1010 ----

0000 0000

---- -000

1111 1111

0000 0000

1111 1111

0--- -000

---- -000

xxxx xxxx

uuuu uuuu

-011 1111

---- 1111

1111 1111

uuuu uuuu

1111 1111

000# #uuu

uuuu uuuu

---- uuuu

uuuu uuuu

1010 ----

0000 0000

---- -000

1111 1111

0000 0000

1111 1111

0--- -000

---- -000

uuuu uuuu

N/A

IOSTB

N/A

IOSTC

N/A

INDF

00h

TMR0

01h

PCL

02h

STATUS

FSR

03h

04h

PORTA

05h

PORTB

06h

PORTC

PCON

07h

08h

WUCON

PCHBUF

PDCON

ODCON

PHCON

INTEN

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10 ~ 3Fh

INTFLAG

General Purpose Registers

Legend: u = unchanged, x = unknown, - = unimplemented,

# = refer to the following table for possible values.

TABLE 2.2: TO /PD Status after Reset

TO

1

PD

1

RESET was caused by

Power-on Reset

1

Brown-out reset

u

RSTB Reset during normal operation

RSTB Reset during SLEEP

WDT Reset during normal operation

WDT Reset during SLEEP

1

0

1

0

Legend: u = unchanged

TABLE 2.3: Events AffectingTO /PD Status Bits

Event

TO

1

PD

1

Power-on

WDT Time-Out

0

u

SLEEP instruction

CLRWDT instruction

Legend: u = unchanged

1

0

1

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2.7 Hexadecimal Convert to Decimal (HCD)

Decimal format is another number format for TLC156. When the content of the data memory has been assigned as

decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions. When

the decimal converting operation is processing, all of the operand data (including the contents of the data memory

(RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the results of

conversion will be incorrect.

Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and

restored to ACC.

The conversion operation is illustrated in example 2.2.

EXAMPLE 2.2: DAA CONVERSION

MOVIA

MOVAR 30h

MOVIA

ADDAR

90h

;Set immediate data = decimal format number “90” (ACC ß 90h)

;Load immediate data “90” to data memory address 30H

;Set immediate data = decimal format number “10” (ACC ß 10h)

;Contents of the data memory address 30H and ACC are binary-added

;the result loads to the ACC (ACC ß A0h, C ß 0)

10h

30h, 0

DAA

;Convert the content of ACC to decimal format, and restored to ACC

;The result in the ACC is “00” and the carry bit C is “1”. This represents the

;decimal number “100”

Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction

operation and restored to ACC.

The conversion operation is illustrated in example 2.3.

EXAMPLE 2.3: DAS CONVERSION

MOVIA

MOVAR 30h

MOVIA

SUBAR

10h

;Set immediate data = decimal format number “10” (ACC ß 10h)

;Load immediate data “10” to data memory address 30H

;Set immediate data = decimal format number “20” (ACC ß 20h)

;Contents of the data memory address 30H and ACC are binary-subtracted

;the result loads to the ACC (ACC ß F0h, C ß 0)

20h

30h, 0

DAS

;Convert the content of ACC to decimal format, and restored to ACC

;The result in the ACC is “90” and the carry bit C is “0”. This represents the

;decimal number “ -10”

2.8 Oscillator Configurations

TLC156 can be operated in four different oscillator modes. Users can program two configuration bits (Fosc<1:0>)

to select the appropriate modes:

• LF: Low Frequency Crystal Oscillator

• XT: Crystal/Resonator Oscillator

• HF: High Frequency Crystal/Resonator Oscillator

• RC: Resistor/Capacitor Oscillator

In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish

oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.

The RC device option offers additional cost savings for timing insensitive applications. The RC oscillator frequency

is a function of the supply voltage, the resistor (Rext) and capacitor (Cext), the operating temperature, and the

process parameter.

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P.2/TLC156

TLC

TLC156

FIGURE 2.6: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)

TLC156

C1

C2

OSCI

X’TAL

RS

SLEEP

RF

OSCO

Internal

Circuit

FIGURE 2.7: HF, XT or LF Oscillator Modes (External Clock Input Operation)

TLC156

OSCI

Clock from

External System

OSCO

Open

FIGURE 2.8: RC Oscillator Mode

Rext

TLC156

OSCI

Internal

Circuit

Cext

OSCO

/2, /4, /8

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TLC156

2.9 Configurations Word

TABLE 2.4: Configurations Word

bit

Name

Description

Oscillator Selection Bits

= 1, 1 à RC mode (default)

= 1, 0 à HF mode

1, 0

Fosc<1:0>

= 0, 1 à XT mode

= 0, 0 à LF mode

Watchdog Timer Enable Bit

= 1, WDT enabled (default)

= 0, WDT disabled

2

3

WDTEN

Code Protection Bit

PROTECT = 1, EPROM code protection off (default)

= 0, EPROM code protection on

Low Voltage Detector Selection Bit

= 1, 1 à disable (default)

= 0, 1 à enable, LVDT voltage = 2.0V

= 0, 0 à enable, LVDT voltage = 3.6V

Instruction Period Selection Bits

= 1, 1 à four oscillator periods (default)

= 1, 0 à two oscillator periods

5, 4

7, 6

LVDT<1:0>

OSCD<1:0>

= 0, 0 à eight oscillator periods

Power Mode Selection Bits

= 1, 1 à Power Mode 3, non-power saving (default)

PMOD<1:0> = 1, 0 à Power Mode 2, power saving

= 0, 1 à Power Mode 1, power saving

9, 8

= 0, 0 à Power Mode 0, power saving

12, 11, 10

-

Unused

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TLC156

3.0 INSTRUCTION SET

Mnemonic,

Operands

Status

Affected

Description

Operation

Cycles

BCR

BSR

R, bit Clear bit in R

R, bit Set bit in R

0 à R

1 à R

1

-

BTRSC R, bit Test bit in R, Skip if Clear

BTRSS R, bit Test bit in R, Skip if Set

Skip if R = 0

Skip if R = 1

No operation

1/2 ⁽¹⁾

1

NOP

No Operation

00h à WDT,

00h à WDT prescaler

CLRWDT

OPTION

SLEEP

Clear Watchdog Timer

Load OPTION register

Go into power-down mode

1

TO PD

,

ACC à OPTION

-

00h à WDT,

TO PD

,

00h à WDT prescaler

PC + 1 à Top of Stack,

002h à PC

INT

S/W interrupt

3/2 ⁽²⁾

-

Adjust ACC’s data format from

DAA

HEX to DEC after any addition ACC(hex) à ACC(dec)

1

C

operation

Adjust ACC’s data format from

HEX to DEC after any subtraction ACC(hex) à ACC(dec)

operation

DAS

1

-

RETURN

RETFIE

Return from subroutine

Top of Stack à PC

2

-

Top of Stack à PC,

1 à GIE

Return from interrupt, set GIE bit

CLRA

IOST

Clear ACC

00h à ACC

ACC à IOST register

00h à R

1

Z

-

R

Load IOST register

Clear R

CLRR

MOVAR

MOVR

DECR

Z

-

Move ACC to R

ACC à R

R, d Move R

R à dest

Z

R, d Decrement R

R - 1 à dest

R - 1 à dest,

Skip if result = 0

DECRSZ R, d Decrement R, Skip if 0

INCR R, d Increment R

1/2 ⁽¹⁾

1

-

Z

-

R + 1 à dest

R + 1 à dest,

Skip if result = 0

INCRSZ R, d Increment R, Skip if 0

1/2 ⁽¹⁾

ADDAR R, d Add ACC and R

R + ACC à dest

R - ACC à dest

R + ACC + C à dest

ACC and R à dest

ACC or R à dest

R xor ACC à dest

R à dest

1

C, DC, Z

SUBAR R, d Subtract ACC from R

ADCAR R, d Add ACC and R with Carry

SBCAR R, d Subtract ACC from R with Carry

ANDAR R, d AND ACC with R

C, DC, Z

Z

IORAR

R, d Inclusive OR ACC with R

XORAR R, d Exclusive OR ACC with R

COMR

RLR

R, d Complement R

R<7> à C,

R<6:0> à dest<7:1>,

C à dest<0>

R, d Rotate left f through Carry

1

C

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TLC

TLC156

C à dest<7>,

RRR

R, d Rotate right f through Carry

R<7:1> à dest<6:0>,

R<0> à C

1

C

R<3:0> à dest<7:4>,

R<7:4> à dest<3:0>

SWAPR R, d Swap R

1

-

MOVIA

ADDIA

SUBIA

ANDIA

IORIA

I

Move Immediate to ACC

Add ACC and Immediate

Subtract ACC from Immediate

AND Immediate with ACC

OR Immediate with ACC

I à ACC

1

-

I + ACC à ACC

I - ACC à ACC

ACC and I à ACC

ACC or I à ACC

C, DC, Z

Z

XORIA

Exclusive OR Immediate to ACC ACC xor I à ACC

I à ACC,

Return, place Immediate in ACC

Top of Stack à PC

RETIA

CALL

GOTO

I

2

-

PC + 1 à Top of Stack,

Call subroutine

I à PC<9:0>

PCHBUF<2> à PC<10>

I à PC<9:0>

PCHBUF<2> à PC<10>

Unconditional branch

Note: 1. 2 cycles for skip, else 1 cycle

2. 3 cycles for TLC154/156

2 cycles for TLC155/157

3. bit : Bit address within an 8-bit register R

R : Register address (00h to 3Fh)

I : Immediate data

ACC : Accumulator

d : Destination select;

=0 (store result in ACC)

=1 (store result in file register R)

dest : Destination

PC : Program Counter

PCHBUF : High Byte Buffer of Program Counter

WDT : Watchdog Timer Counter

GIE : Global interrupt enable bit

TO : Time-out bit

PD : Power-down bit

C : Carry bit

DC : Digital carry bit

Z : Zero bit

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TLC156

ADCAR

Add ACC and R with Carry

ADCAR R, d

Syntax:

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

Status Affected:

Description:

R + ACC + C à dest

C, DC, Z

Add the contents of the ACC register and register‘R’ with Carry. If ‘d’ is 0 the result is stored

in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

1

Cycles:

ADDAR

Syntax:

Add ACC and R

ADDAR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

ACC + R à dest

Status Affected:

Description:

C, DC, Z

Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC

register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

1

Cycles:

ADDIA

Add ACC and Immediate

Syntax:

ADDIA I

Operands:

Operation:

Status Affected:

Description:

0 £ I £ 255

ACC + I à ACC

C, DC, Z

Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the

ACC register.

1

Cycles:

ANDAR

Syntax:

AND ACC and R

ANDAR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

ACC and R à dest

Status Affected:

Description:

Z

The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in

the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

1

Cycles:

ANDIA

AND Immediate with ACC

Syntax:

ANDIA I

Operands:

Operation:

Status Affected:

Description:

0 £ I £ 255

ACC AND I à ACC

Z

The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed

in the ACC register.

1

Cycles:

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TLC

TLC156

BCR

Clear Bit in R

BCF R, b

0 £ R £ 63

0 £ b£ 7

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 à R

None

Clear bit ‘b’ in register ‘R’.

1

BSR

Set Bit in R

BSR R, b

0 £ R £ 63

0 £ b£ 7

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

1 à R

None

Set bit ‘b’ in register ‘R’.

1

BTRSC

Test Bit in R, Skip if Clear

Syntax:

BTRSC R, b

Operands:

0 £ R £ 63

0 £ b£ 7

Operation:

Skip if R = 0

Status Affected:

Description:

None

If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.

If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,

and a NOP is executed instead making this a 2-cycle instruction..

1(2)

Cycles:

BTRSS

Test Bit in R, Skip if Set

Syntax:

BTRSS R, b

Operands:

0 £ R £ 63

0 £ b£ 7

Operation:

Skip if R = 1

Status Affected:

Description:

None

If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is

discarded and a NOP is executed instead, making this a 2-cycle instruction.

1(2)

Cycles:

CALL

Subroutine Call

Syntax:

CALL I

Operands:

Operation:

0 £ I £ 1023

PC +1 à Top of Stack;

I à PC<9:0>

PCHBUF<2> à PC<10>

Status Affected:

Description:

None

Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate

address is loaded into PC bits <10:0>. CALL is a two-cycle instruction.

2

Cycles:

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TLC

TLC156

CLRA

Clear ACC

Syntax:

CLRA

Operands:

Operation:

None

00h à ACC;

1 à Z

Status Affected:

Description:

Cycles:

Z

The ACC register is cleared. Zero bit (Z) is set.

1

CLRR

Clear R

Syntax:

CLRR R

Operands:

Operation:

0 £ R £ 63

00h à R;

1 à Z

Status Affected:

Description:

Cycles:

Z

The contents of register ‘R’ are cleared and the Z bit is set.

1

CLRWDT

Syntax:

Clear Watchdog Timer

CLRWDT

Operands:

Operation:

None

00h à WDT;

00h à WDT prescaler (if assigned);

1 à TO;

1 à PD

Status Affected:

Description:

TO PD

,

The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is

assigned to the WDT and not Timer0. Status bitsTO and PD are set.

1

Cycles:

COMR

Complement R

Syntax:

COMR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

R à dest

Status Affected:

Description:

Z

The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC

register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

DAA

Adjust ACC’s data format from HEX to DEC

Syntax:

DAA

Operands:

Operation:

Status Affected:

Description:

None

ACC(hex) à ACC(dec)

C

Convert the ACC data from hexadecimal to decimal format after any addition

operation and restored to ACC.

1

Cycles:

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TLC

TLC156

DAS

Adjust ACC’s data format from HEX to DEC

Syntax:

DAS

Operands:

Operation:

Status Affected:

Description:

None

ACC(hex) à ACC(dec)

None

Convert the ACC data from hexadecimal to decimal format after any subtraction operation

and restored to ACC.

1

Cycles:

DECR

Decrement R

Syntax:

Operands:

DECR R, d

0 £ R £ 63

dÎ [0,1]

Operation:

R - 1 à dest

Status Affected:

Description:

Z

Decrement register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is

stored back in register ‘R’.

1

Cycles:

DECRSZ

Syntax:

Decrement R, Skip if 0

DECRSZ R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

R - 1 à dest; skip if result =0

Status Affected:

Description:

None

The contents of register ‘R’ are decremented. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is placed back in register ’R’.

If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is

executed instead making it a two-cycle instruction.

Cycles:

1(2)

GOTO

Unconditional Branch

Syntax:

GOTO I

Operands:

Operation:

0 £ I £ 1023

I à PC<9:0>

PCHBUF<2> à PC<10>

Status Affected:

Description:

None

GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.

GOTO is a two-cycle instruction.

2

Cycles:

INCR

Increment R

Syntax:

Operands:

INCR R, d

0 £ R £ 63

dÎ [0,1]

Operation:

R + 1 à dest

Status Affected:

Description:

Z

The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.

If ‘d’ is 1 the result is placed back in register ‘R’.

1

Cycles:

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TLC

TLC156

INCRSZ

Increment R, Skip if 0

INCRSZ R, d

0 £ R £ 63

Syntax:

Operands:

dÎ [0,1]

Operation:

Status Affected:

Description:

R + 1 à dest, skip if result = 0

None

The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.

If ‘d’ is the result is placed back in register ‘R’.

If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is

executed instead making it a two-cycle instruction.

Cycles:

1(2)

INT

S/W Interrupt

Syntax:

Operands:

Operation:

INT

None

PC + 1 à Top of Stack,

002h à PC

Status Affected:

Description:

None

Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address

002h is loaded into PC bits <10:0>.

Cycles:

2 for TLC155/157; 3 for TLC154/156

IORAR

OR ACC with R

Syntax:

IORAR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

ACC or R à dest

Status Affected:

Description:

Z

Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is placed back in register ‘R’.

1

Cycles:

IORIA

OR Immediate with ACC

Syntax:

IORIA I

Operands:

Operation:

Status Affected:

Description:

0 £ I £ 255

ACC or I à ACC

Z

The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed

in the ACC register.

1

Cycles:

IOST

Load IOST Register

Syntax:

IOST R

Operands:

Operation:

Status Affected:

Description:

Cycles:

R = 5,6 or 7

ACC à IOST register R

None

IOST register ‘R’ (R= 5,6 or7) is loaded with the contents of the ACC register.

1

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

MOVAR

Move ACC to R

Syntax:

MOVAR R

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 £ R £ 63

ACC à R

None

Move data from the ACC register to register ‘R’.

1

MOVIA

Move Immediate to ACC

MOVIA I

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 £ I £ 255

I à ACC

None

The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.

1

MOVR

Move R

Syntax:

MOVR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

R à dest

Status Affected:

Description:

Z

The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC

register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since

status flag Z is affected.

1

Cycles:

NOP

No Operation

NOP

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

None

No operation

None

No operation.

1

OPTION

Load OPTION Register

Syntax:

OPTION

Operands:

Operation:

Status Affected:

Description:

Cycles:

None

ACC à OPTION

None

The content of the ACC register is loaded into the OPTION register.

1

RETFIE

Return from Interrupt, Set ‘GIE’ Bit

Syntax:

RETFIE

Operands:

Operation:

Status Affected:

Description:

None

Top of Stack à PC

None

The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is

set to 1. This is a two-cycle instruction.

2

Cycles:

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TLC

TLC156

RETIA

Return with Immediate in ACC

RETIA I

Syntax:

Operands:

Operation:

0 £ I £ 255

I à ACC;

Top of Stack à PC

None

Status Affected:

Description:

The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from

the top of the stack (the return address). This is a two-cycle instruction.

2

Cycles:

RETURN

Return from Subroutine

Syntax:

RETURN

Operands:

Operation:

Status Affected:

Description:

None

Top of Stack à PC

None

The program counter is loaded from the top of the stack (the return address). This is a

two-cycle instruction.

2

Cycles:

RLR

Rotate Left f through Carry

Syntax:

Operands:

RLR R, d

0 £ R £ 63

dÎ [0,1]

Operation:

R<7> à C;

R<6:0> à dest<7:1>;

C à dest<0>

Status Affected:

Description:

C

The contents of register ‘R’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0 the

result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

RRR

Rotate Right f through Carry

Syntax:

Operands:

RRR R, d

0 £ R £ 63

dÎ [0,1]

Operation:

C à dest<7>;

R<7:1> à dest<6:0>;

R<0> à C

Status Affected:

Description:

C

The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0

the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.

1

Cycles:

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

SLEEP

Enter SLEEP Mode

SLEEP

Syntax:

Operands:

Operation:

None

00h à WDT;

00h à WDT prescaler;

1 à TO;

0 à PD

Status Affected:

Description:

TO PD

,

Time-out status bit ( TO) is set. The power-down status bit ( PD ) is cleared. The WDT and its

prescaler are cleared.

The processor is put into SLEEP mode.

1

Cycles:

SBCAR

Syntax:

Subtract ACC from R with Carry

SBCAR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

R + ACC + C à dest

Status Affected:

Description:

C, DC, Z

Add the 2’s complement method of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the

result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

SUBAR

Syntax:

Subtract ACC from R

SUBAR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

R - ACC à dest

Status Affected:

Description:

C, DC, Z

Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is

stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

SUBIA

Subtract ACC from Immediate

Syntax:

SUBAR R, d

Operands:

Operation:

Status Affected:

Description:

0 £ I £ 255

I - ACC à ACC

C, DC, Z

Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is

placed in the ACC register.

1

Cycles:

SWAPR

Syntax:

Swap nibbles in R

SWAPR R, d

Operands:

0 £ R £ 63

dÎ [0,1]

Operation:

R<3:0> à dest<7:4>;

R<7:4> à dest<3:0>

Status Affected:

Description:

None

The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in

ACC register. If ‘d’ is 1 the result in placed in register ‘R’.

1

Cycles:

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P.2/TLC156

TLC

TLC156

XORAR

Exclusive OR ACC with R

XORAR R, d

0 £ R £ 63

Syntax:

Operands:

dÎ [0,1]

Operation:

Status Affected:

Description:

ACC xor R à dest

Z

Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored

in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

XORIA

Exclusive OR Immediate with ACC

Syntax:

XORIA I

Operands:

Operation:

Status Affected:

Description:

0 £ I £ 255

ACC xor I à ACC

Z

The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed

in the ACC register.

1

Cycles:

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

4.0 ABSOLUTE MAXIMUM RATINGS

TLC156

Ambient Operating Temperature

Store Temperature

0℃ to +70℃

-65℃ to +150℃

0V to +6.0V

DC Supply Voltage (Vdd)

Input Voltage with respect to Ground (Vss)

-0.3V to (Vdd + 0.3)V

5.0 OPERATING CONDITIONS

DC Supply Voltage

+2.3V to +5.5V

Operating Temperature

0℃ to +70℃

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

6.0 ELECTRICAL CHARACTERISTICS

TLC156

6.1 ELECTRICAL CHARACTERISTICS of TLC154/156

Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled

Sym

Description

Conditions

HF mode, Vdd=5V

Min.

1

Typ.

Max.

20

Unit

F_HF

X’tal oscillation range

MHz

HF mode, Vdd=3V

1

15

XT mode, Vdd=5V

0.5

32

10

F_XT

F_LF

F_RC

X’tal oscillation range

RC oscillation range

MHz

KHZ

MHz

XT mode, Vdd=3V

10

LF mode, Vdd=5V

4000

1000

15

LF mode, Vdd=3V

32

RC mode, Vdd=5V

RC mode, Vdd=3V

I/O ports, Vdd=5V

DC

2.0

4.0

1.5

2.4

7

RSTB, T0CKI pins, Vdd=5V

I/O ports, Vdd=3V

V_IH

Input high voltage

Input low voltage

V

RSTB, T0CKI pins, Vdd=3V

I/O ports, Vdd=5V

1.0

0.6

RSTB, T0CKI pins, Vdd=5V

I/O ports, Vdd=3V

V_IL

RSTB, T0CKI pins, Vdd=3V

I_OH=-5.4mA, Vdd=5V

I_OL=8.7mA, Vdd=5V

Input pin at Vss, Vdd=5V

Input pin at Vdd, Vdd=5V

Vdd=5V

V_OH

V_OL

I_PH

Output high voltage

Output low voltage

Pull-high current

Pull-down current

3.6

V

0.6

V

-45

35

9

uA

I_PD

12

4

I_WDT

WDT current

uA

Vdd=3V

2

Vdd=3V

20.4

17.9

16.2

30

T_WDTWDT period

I_LVDTLVDT current

mS

Vdd=4V

Vdd=5V

Vdd=5V LVDT = 3.6V

Vdd=5V LVDT = 2V

Vdd=3V LVDT = 2V

40

30

23

uA

6.8

8.0

Sleep mode, Vdd=5V, WDT enable

20

3

Sleep mode, Vdd=5V, WDT disable

I_SB

Power down current

Sleep mode, Vdd=3V, WDT enable

2.5

1.1

Sleep mode, Vdd=3V, WDT disable

HF mode, Vdd=5V, 4 clock instruction

20MHz

15MHz

10MHz

4MHz

2.04

1.68

1.28

0.78

0.62

I_DD

Operating current

mA

2MHz

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

HF mode, Vdd=3V, 4 clock instruction

20MHz

0.92

15MHz

0.72

0.54

0.30

0.19

I_DD

Operating current

mA

10MHz

4MHz

2MHz

HF mode, Vdd=5V, 2 clock instruction

20MHz

2.94

2.34

1.74

0.96

0.68

15MHz

Operating current

10MHz

4MHz

2MHz

HF mode, Vdd=3V, 2 clock instruction

20MHz

1.38

1.07

0.77

0.38

0.24

15MHz

10MHz

4MHz

2MHz

XT mode, Vdd=5V, 4 clock instruction

20MHz

1.69

1.36

1.04

0.64

0.49

15MHz

10MHz

4MHz

2MHz

XT mode, Vdd=3V, 4 clock instruction

20MHz

0.78

0.60

0.44

0.24

0.17

15MHz

10MHz

4MHz

2MHz

XT mode, Vdd=5V, 2 clock instruction

20MHz

2.81

2.20

1.60

0.87

0.61

15MHz

10MHz

4MHz

2MHz

XT mode, Vdd=3V, 2 clock instruction

20MHz

15MHz

10MHz

4MHz

1.36

1.05

0.73

0.36

0.23

2MHz

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

LF mode, Vdd=5V, 4 clock instruction

2MHz

290

1MHz

208

167

118

101

I_DD

Operating current

uA

500KHz

100KHz

32KHz

LF mode, Vdd=3V, 4 clock instruction

2MHz

105

73

54

33

26

1MHz

Operating current

500KHz

100KHz

32KHz

LF mode, Vdd=5V, 2 clock instruction

2MHz

371

269

194

130

108

1MHz

Operating current

500KHz

100KHz

32KHz

LF mode, Vdd=3V, 2 clock instruction

2MHz

158

100

67

1MHz

I_DD

Operating current

uA

500KHz

100KHz

38

32KHz

29

I_DD

mA

RC mode, Vdd=5V, 4 clock instruction

R=1Kohm

R=3.3Kohm F=11.06MHz

R=10Kohm F=5.80MHz

F=14.96MHz

4.572

1.845

0.761

0.170

0.119

4.226

1.519

0.613

0.147

0.109

3.429

1.163

0.454

0.126

0.100

3.024

C=3P

R=100Kohm F=808KHz

R=300Kohm F=276KHz

R=1Kohm

R=3.3Kohm F=6.35MHz

R=10Kohm F=2.73MHz

F=11.7MHz

C=20P

R=100Kohm F=320KHz

R=300Kohm F=108KHz

R=1Kohm

R=3.3Kohm F=2.05MHz

R=10Kohm F=748KHz

F=5.23MHz

C=100P

C=300P

R=100Kohm F=80KHz

R=300Kohm F=26.4KHz

R=1Kohm

F=2.5MHz

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

R=3.3Kohm F=900KHz

R=10Kohm F=316KHz

1.021

0.403

0.119

0.098

R=100Kohm F=32KHz

R=300Kohm F=10.67KHz

RC mode, Vdd=3V, 4 clock instruction

R=1Kohm

R=3.3Kohm F=7.2MHz

R=10Kohm F=4.58MHz

F=8.29MHz

2.280

0.913

0.396

0.071

0.040

2.214

0.837

0.327

0.058

0.035

2.060

0.688

0.253

0.047

0.030

1.890

0.630

0.226

0.043

0.028

C=3P

R=100Kohm F=900KHz

R=300Kohm F=316KHz

R=1Kohm

R=3.3Kohm F=5.1MHz

R=10Kohm F=2.71MHz

F=7MHz

C=20P

C=100P

C=300P

R=100Kohm F=374KHz

R=300Kohm F=128KHz

I_DD

Operating current

mA

R=1Kohm

R=3.3Kohm F=2.11MHz

R=10Kohm F=848KHz

F=4.14MHz

R=100Kohm F=96KHz

R=300Kohm F=32KHz

R=1Kohm

R=3.3Kohm F=972KHz

R=10Kohm F=360KHz

F=2.36MHz

R=100Kohm F=38KHz

R=300Kohm F=12.71KHz

RC mode, Vdd=5V, 2 clock instruction

R=1Kohm F=15.16MHz

R=3.3Kohm F=11.27MHz

R=10Kohm F=5.77MHz

5.435

2.358

986

C=3P

R=100Kohm F=826KHz

R=300Kohm F=274KHz

0.183

0.108

4.835

1.808

0.701

0.138

0.092

3.680

1.234

0.479

0.110

0.081

3.107

1.057

0.398

0.102

0.077

R=1Kohm

R=3.3Kohm F=6.12MHz

R=10Kohm F=2.72MHz

F=11.56MHz

C=20P

C=100P

C=300P

R=100Kohm F=308KHz

R=300Kohm F=105KHz

I_DD

Operating current

mA

R=1Kohm

R=3.3Kohm F=1.99MHz

R=10Kohm F=722KHz

F=5.32MHz

R=100Kohm F=77KHz

R=300Kohm F=25.0KHz

R=1Kohm

R=3.3Kohm F=892KHz

R=10Kohm F=312KHz

F=2.52MHz

R=100Kohm F=32KHz

R=300Kohm F=11KHz

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

RC mode, Vdd=3V, 2 clock instruction

R=1Kohm F=8.306MHz

R=3.3Kohm F=7.29MHz

R=10Kohm F=4.81MHz

2.552

1.130

0.518

0.084

0.039

2.445

0.986

0.393

0.061

0.031

2.197

0.745

0.270

0.043

0.025

1.953

0.648

0.231

0.038

0.022

C=3P

R=100Kohm F=904KHz

R=300Kohm F=338KHz

R=1Kohm

R=3.3Kohm F=5.07MHz

R=10Kohm F=2.68MHz

F=7.08MHz

C=20P

C=100P

C=300P

R=100Kohm F=362KHz

R=300Kohm F=123KHz

I_DD

Operating current

mA

R=1Kohm

R=3.3Kohm F=2.03MHz

R=10Kohm F=810KHz

F=4.11MHz

R=100Kohm F=91KHz

R=300Kohm F=30KHz

R=1Kohm

R=3.3Kohm F=964KHz

R=10Kohm F=354KHz

F=2.37MHz

R=100Kohm F=38KHz

R=300Kohm F=13KHz

6.2 ELECTRICAL CHARACTERISTICS of TLC155/157

To be defined

6.3 ELECTRICAL CHARACTERISTICS of TLC154/156

To be defined

6.4 ELECTRICAL CHARACTERISTICS of TLC155/157

To be defined

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

7.0 PACKAGE DIMENSION

TLC156

7.1 18-PIN PDIP 300mil

D

C

TOP E-PIN INDENT £ 0.079

BOTTOM E-PIN INDENT £ 0.118

0.727

e

B

B1

D1

Dimension In Millimeters

Nom

Dimension In Inches

Symbols

Min

Max

Min

Nom

Max

A

A1

A2

B

-

4.57

-

0.180

-

0.13

-

0.005

-

3.30

0.46

1.52

0.25

22.96

0.56

-

3.56

0.56

1.78

0.33

23.11

0.69

8.26

6.65

-

0.130

0.018

0.060

0.010

0.904

0.022

-

0.140

0.022

0.070

0.013

0.910

0.027

0.325

0.262

-

0.36

1.27

0.20

22.71

0.43

7.62

6.40

-

0.014

0.050

0.008

0.894

0.017

0.300

0.252

-

B1

C

D

D1

E

E1

e

6.50

2.54

-

0.256

0.100

-

L

3.18

-

0.125

-

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

7.2 18-PIN SOP 300mil

“

View

A

D

“

View

A

7^o(4x)

e

B

£

L

Dimension In Millimeters

Nom

Dimension In Inches

Symbols

Min

Max

Min

Nom

Max

A

A1

A2

B

2.36

0.10

-

2.49

-

2.64

0.30

-

0.093

0.04

-

0.098

-

0.104

0.012

-

2.31

0.41

0.23

-

0.091

0.016

0.009

-

0.33

0.18

11.35

7.39

-

0.51

0.28

0.013

0.007

0.447

0.291

-

0.020

0.011

0.463

0.299

-

C

D

E

11.76

7.59

-

7.49

1.27

10.31

0.81

-

0.295

0.050

0.406

0.032

-

e

H

L

10.01

0.38

0°

10.64

1.27

8°

0.394

0.015

0°

0.419

0.050

8°

θ

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

7.3 20-PIN SSOP 209mil

D

“

View

A

C

b

e

-H-

GAUGE PLANE

SEATING PLANE

0.004max.

o

£

L

“

View

A

L1

Dimension In Millimeters

Nom

Symbols

Min

Max

A

A1

A2

b

-

2.00

-

0.05

1.65

0.22

0.09

6.90

7.40

5.00

-

1.75

-

1.85

0.38

0.21

7.50

8.20

5.60

-

c

-

D

7.20

7.80

5.30

0.65

0.75

1.25

4^o

E

E1

e

L

0.55

-

0^o

0.95

-

8^o

L1

θ^o

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

7.4 28-PIN PDIP 600mil

D

e

B1

B

Dimension In Millimeters

Dimension In Inches

Symbols

Min

Nom

Max

Min

Nom

Max

A

-

0.38

3.81

-

5.59

-

0.220

A1

A2

B

-

0.015

0.150

-

3.94

1.52

0.46

37.08

15.24

13.84

2.54

-

4.06

0.155

0.06

0.018

1.460

0.600

0.545

0.100

-

0.160

-

B1

-

D

E

36.96

-

37.34

1.455

-

1.470

-

E1

e

13.72

-

13.97

0.540

-

0.550

-

L

3.18

16.00

0.125

0.630

eB

16.51

17.02

0.650

0.670

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

7.5 28-PIN Skinny PDIP 300mil

D

C

1.000¡

PIN 1 INDENT

e

B

B1

B2

Dimension In Millimeters

Nom

Dimension In Inches

Symbols

Min

Max

Min

Nom

Max

A

A1

A2

B

-

4.57

-

0.180

-

0.38

-

3.30

-

0.015

-

3.56

1.65

0.58

1.12

0.33

35.43

8.38

7.52

-

0.130

0.140

0.065

0.023

0.044

0.013

1.395

0.330

0.296

-

1.02

0.41

0.71

0.20

35.13

7.87

7.26

-

0.0040

0.016

0.028

0.008

1.383

0.310

0.284

-

B1

B2

C

-

0.25

35.18

8.31

7.32

2.54

-

0.010

1.385

0.327

0.288

0.100

-

D

E

E1

e

L

3.18

8.64

-

0.125

0.340

-

eB

-

9.65

-

0.380

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

7.6 28-PIN SOP 300mil

“

View

A

D

“

View

A

7^o(4x)

e

D1

B

£

L

Dimension In Millimeters

Nom

Dimension In Inches

Nom

Symbols

Min

Max

Min

-

Max

A

A1

A2

B

-

2.488

-

2.743

-

0.098

-

0.108

-

0.152

2.21

0.006

0.087

0.012

0.008

0.700

0.290

0.048

0.404

0.025

0°

2.336

0.406

0.254

17.91

7.493

1.270

10.42

-

2.464

0.508

0.304

18.42

7.62

1.321

10.57

-

0.091

0.016

0.010

0.705

0.295

0.050

0.410

-

0.097

0.020

0.012

0.725

0.300

0.052

0.416

-

0.305

0.204

17.78

7.366

1.219

10.26

0.635

0°

C

D

E

e

eB

L

θ

4°

8°

4°

8°

D1

0.356

0.508

-

0.014

0.020

-

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

TLC156

7.7 28-PIN SSOP 209mil

D

“

View

A

C

b

e

R

-H-

GAUGE PLANE

SEATING PLANE

0.10

o

£

L

“

View

A

Dimension In Millimeters

Symbols

Min

-

Nom

Max

A

A1

A2

b

-

2.00

-

0.05

1.62

0.22

0.09

9.90

7.40

5.00

1.75

-

1.85

0.38

0.25

10.50

8.20

5.60

10.57

0.95

-

c

-

D

10.20

7.80

5.30

E

E1

e

0.65 BSC

0.55

10.42

0.75

-

L

R

0.09

θ^o

0^o

4^o

8^o

Rev0.95 Nov 20, 2003

P.2/TLC156

TLC

8.0 ORDERING INFORMATION

TLC156

OTP Type MCU

TLC154EP

TLC154ED

TLC154ER

TLC155EP

TLC155EM

TLC155ED

TLC155ER

TLC156EP

TLC156ED

TLC156ER

TLC157EP

TLC157EM

TLC157ED

TLC157ER

Package Type

Pin Count

18

Package Size

300 mil

209 mil

600 mil

300 mil

209 mil

300 mil

209 mil

600 mil

300 mil

209 mil

PDIP

SOP

18

SSOP

PDIP

20

28

Skinny PDIP

SOP

28

SSOP

PDIP

28

18

SOP

18

SSOP

PDIP

20

28

Skinny PDIP

SOP

28

SSOP

28

Mask Type MCU

TLC154P

TLC154D

TLC154R

TLC155P

TLC155M

TLC155D

TLC155R

TLC156P

TLC156D

TLC156R

TLC157P

TLC157M

TLC157D

TLC157R

Package Type

PDIP

Pin Count

18

Package Size

300 mil

209 mil

600 mil

300 mil

209 mil

300 mil

209 mil

600 mil

300 mil

209 mil

SOP

18

SSOP

20

PDIP

28

Skinny PDIP

SOP

28

SSOP

28

PDIP

18

SOP

18

SSOP

20

PDIP

28

Skinny PDIP

SOP

28

SSOP

28

Rev0.95 Nov 20, 2003

P.2/TLC156


型号：	TLC155ED
厂家：	ETC
描述：	EPROM/ROM-Based 8-Bit Microcontroller Series EPROM / ROM基于8位微控制器系列微控制器可编程只读存储器电动程控只读存储器
文件：	总50页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC155ED [ETC]

相关型号：

TLC155EM

TLC155EP

TLC155ER

TLC155M

TLC155P

TLC155R

TLC156

TLC156D

TLC156ED

TLC156EP

TLC156ER

TLC156P