TM50S116T-7G [ETC]
SDRAM; SDRAM
| 型号： | TM50S116T-7G |
| 厂家： | 
ETC |
| 描述： | SDRAM |
| 文件： | 总7页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
晶揚科技股份有限公司
Taiwan Micropaq Corporation
承 認 書
SPECIFICATION FOR APPROVAL
TM50S116T-7G
新竹縣新竹工業區文化路 4 號
No.4 Wenhua Rd. HsinChu Industrial Park
HuKou , Taiwan, R.O.C.
TEL：886-3-597-9402 ˙ FAX：886-3-597-0775
http://www.tmc.com.tw
TMC
TM50S116T-7G
SDRAM
Description
The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16),
fabricated with high performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
Features
Package 400-mil 50-pin TSOP(II)
JEDEC PC133/PC100 compatible
Single 3.3V Power Supply
Bytecontrol(DQM L andDQM U)
Auto and Self Refresh
64ms refresh period (4K cycles)
11-Row x8-Columnorganization
LVTTL Signal Compatible
2-BankoperationcontrolledbyBA0
Pin33 and 37 are “No Connected”
Fully synchronous operation referenced
to clock rising edge
Programmable
- CAS Latency (3 or 2 clocks)
- Burst Length (1,2,4,8 & full page)
- Burst type (Sequential & Interleave)
Burstread/writeandburstread/single
writeoperationscapability
Frequency vs. AC Parameter
Symbol
Parameter
- 6G - 7G - 75G Unit
tCK
Min. clock cycle time @CL=3
6
7
7.5
133
5.4
20
ns
Mhz
ns
fCK
tAC
trcd
Max. operating frequency @CL=3
Max. access time from clock @CL=3
Min. row to column delay
166
5.0
18
143
5.4
18
ns
For reference only.
2
TMC
Rev:1.0
TMC
TM50S116T-7G SDRAM
Pin Description
Pin Name
Function
Pin Name
Function
CLK
CKE
/CS
Master Clock
Clock Enable
DQML/DQMU Output Disable(Write Mask)
A0-10
BA0
Address Input
Bank Address
Chip Select
/RAS
/CAS
/WE
Row Address Strobe
Vdd
Power Supply
Power Supply for Output
Ground
Column Address Strobe VddQ
Write Enable Vss/VssQ
NC
DQ0~DQ15 Data I/O
No Connection
For reference only.
3
TMC
Rev:1.0
TMC
TM50S116T-7G SDRAM
Pin Function
Pin
Name
System clock
Pin Function
CLK
/CS
Active on the positive going edge to sample all
inputs.
Chip select
Disables or enables device operation by masking
or enabling all inputs except CLK,CKE and
DQML/DQMU.
CKE
Clock enable
Masks system clock to freeze operation from the
next clock cycle. CKE should be enabled at least
one cycle prior to new command. Disable input
buffers for power down in standby.
A0~A10
BA0
Address input
Row/column addresses are multiplexed on the
same pins. Row address:A0~A10, Column
address:A0~A7
Bank address
Selects bank to be activated during row address
latch time. Selects bank for read/write during
column address latch time.
/RAS
/CAS
/WE
Row address strobe
Latches row addresses on the positive going edge
of the CLK with /RAS low. Enables rows access
& pre-charge.
Column address strobe Latches column addresses on the positive going
edge of the CLK with /CAS low. Enables column
access.
Write enable
Enables write operation and row pre-charge.
Latches data in starting from /CAS,/WE active.
DQMU/DQM Data I/O mask
Makes data output Hi-Z, tSHZ after the clock and
masks the output. Blocks data input when
DQML/DQMU active.
L
(Byte controll)
DQ0~15
Vdd/Vss
Data input/output
Data inputs/outputs are multiplexed on the same
pins.
Power supply/ground Power and ground for the input buffers and the
core logic.
VddQ/VssQ Data output power /
ground
Isolated power supply and ground for the output
buffers to provide improved noise immunity.
NC/RFU
No connection /
This pin is recommended to be left no connection
reserved for future use on the device.
For reference only.
4
TMC
Rev:1.0
TMC
TM50S116T-7G SDRAM
Absolute maximum ratings
Parameter
Voltage on any pin relative to Vss
Voltage supply relative to Vss(VssQ) Vdd,VddQ
Operating temperature
Symbol
VIN, VOUT
Ratings
-0.5 to 4.6
-0.5 to 4.6
0 to +70
1
Unit
V
V
℃
Topr
Power dissipation
PD
W
Output Shorted current
DC OPERATING CONDITIONS
IOS
50
mA
Recommended operating conditions(Referenced to Vss=0V,TA=0℃ to 70℃)
Min.
Typ.
Max.
Parameter
Symbol
Unit
Power Supply Voltage
Input Logic High Voltage
Input Logic Low Voltage
Output Logic High Voltage
Output Logic Low Voltage
Input/Output Leakage Current
DC Characteristics
Vdd, VddQ
VIH
3.0
2.0
-0.3
2.4
-
3.3
3.6
V
V
-
-
-
-
-
Vdd +0.3
VIL
0.8
-
V
VOH
V
VOL
0.4
5
V
μA
IIL, IOL
-5
(Recommended operating condition TA = 0℃ to 70℃, unless otherwise noted.)
Parameter
Symbol
Test Conditions
Limits
-6G -7G -75G
Unit
mA
mA
Operating Current
(One bank active)
Pre-charge Standby
Current in Power Down
Mode
Pre-charge Standby
Current in Non-Power
Down Mode
Burst length=1, CL=3,
tRC = tRC(min), tCK = tCK(min)
CKE=VIL(max), tCK = 15ns
95 85
85
ICC1
2
ICC2
ICC2PS
ICC2
P
CKE & CLK=VIL(max)
2
CKE>=VIH(min),/CS> = VIH
(min) , tCK = 15ns
CKE>=VIH(min),/CS> = VIH
(min), CLK<= VIL(max) ,
CKE<=VIL(max), tCK =10ns
20
mA
mA
N
20
7
ICC2NS
Active Standby Current
in Power Down Mode
ICC3
P
CKE & CLK<=VIL(max)
/CS=CKE=VIH(min),
CK =15ns
/CS=CKE=VIH(min),
CLK= VIL(max )
5
ICC3PS
Active Standby Current
in Non-Power Down
Mode
35
mA
mA
mA
ICC3
N
t
35
ICC3NS
Operating Current (Burst
mode)
BL=4,CL=3,All Banks Active 130 100 100
ICC4
Auto Refresh Current
CBR Command cycling
CKE<= 0.2V
150 130 130
2
mA
mA
ICC5
ICC6
Self Refresh Current
For reference only.
5
TMC
Rev:1.0
TMC
TM50S116T-7G SDRAM
AC Characteristics
Recommended operating conditions(Vdd=VddQ=3.3V,Vss=0V,TA= 0 to 70℃)
Parameter
-6G
-7G
-75G
Unit
Symbol
Min Max Min Max Min Max
1
2
Clock Cycle Time,CL=3
Clock Frequency,CL=3
6.0
7.0
7.5
ns
tCK
fCK
166
5.0
143
5.4
133
5.4
Mhz
3
4
5
6
7
Clock Access Time,CL=3
Clock High Pulse Width
Clock Low Pulse Width
Input Setup time(all inputs)
Input Hold time(all inputs)
Transition time of clock
/RAS to /CAS delay
Row Cycle time
Row active time
Pre-charge time
Row active to active delay
Refresh time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tAC
tCH
tCL
tIS
tIH
tT
tRCD
tRC
tRAS
tRP
tRRD
tREF
2.5
2.5
1.5
0.8
1.0
18
60
42
15
12
2.5
2.5
1.5
0.8
1.0
18
63
42
18
14
2.5
2.5
1.5
0.8
1.0
20
67
45
20
15
8
9
10
10
10
10
11
12
13
14
64
64
64
For reference only.
6
TMC
Rev:1.0
TMC
TM50S116T SDRAM
For reference only.
7
TMC
Rev:1.0
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