TMP90C800N [ETC]

8-Bit Microcontroller ; 8位微控制器\n


型号：	TMP90C800N
厂家：	ETC
描述：	8-Bit Microcontroller 8位微控制器\n 微控制器
文件：	总14页 (文件大小：397K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TOSHIBA

TLCS-90 Series

TMP90C800/801

CMOS 8–Bit Microcontrollers

TMP90C800N/TMP90C801N

TMP90C800F/TMP90C801F

1. Outline and Characteristics

The TMP90C800 is a high-speed advanced 8-bit microcontroller

applicable to a variety of equipment.

(3)

Internal ROM: 8K bytes (The TMP90C801 does not

have a built-in ROM)

With its 8-bit CPU, ROM, RAM, timer/event counter and gen-

eral-purpose serial interface integrated into a single CMOS chip,

the TMP90C800 allows the expansion of external

memories for programs and data (up to 56K bytes). The function of

TMP90C800 is exactly same as the TMP90C400 except the

internal ROM/RAM size.

The TMP90C801 is the same as the TMP90C800 but

without the ROM.

The TMP90C800N/801N is in a shrink Dual Inline Package

(SDIP64-P-750).

(4)

(5)

Internal RAM: 256 bytes

Memory expansion

External memory: 56K bytes

General-purpose serial interface (1 channel)

Asynchronous mode, I/O interface mode

8-bit timers (4 channel): (2 external clock input)

Port with zero-cross detection circuit (4 input)

Input/Output ports (56 pins)

(6)

(7)

(8)

(9)

- Ports with programmable pull-up resistor (22 pins)

- Allows I/O selection on bit basis

The TMP90C800F/801F is in a Quad Flat package

(QFP64-P-1420A)

The characteristics of the TMP90C800 include:

- Multiplexer ports of address data bus

(10) Interrupt function: 7 internal interrupts and 3 external

interrupts

(11) Micro Direct Memory Access (DMA) function (8 channels)

(12) Standby function (4 HALT modes)

(1)

(2)

Powerful instructions: 163 basic instructions, including

Multiplication, division, 16-bit arithmetic operations, bit

manipulation instructions

Minimum instruction executing time: 320ns (at

12.5MHz oscillation frequency)

The information contained here is subject to change without notice.

The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties

which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic

equipments (ofﬁce equipment, communication equipment, measuring equipment, domestic electriﬁcation, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-

ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, trafﬁc signal, combustion control, all types

of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.

TOSHIBA CORPORATION

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TMP90C800/801

Figure 1. TMP90C800 Block Diagram

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TMP90C800/801

2.1 Pin Assignment

Figure 2.1 shows pin assignment of the TMP90C800N/801N.

2. Pin Assignment and Functions

This section describes the assignment of input/output pins, their

names and functions.

Figure 2.1 (1). Pin Assignment (Shrink Dual Inline Package)

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TMP90C800/801

Figure 2.1 (2) shows Pin Assignment of the TMP90C800F/

801F.

Figure 2.1 (2). Pin Assignment (Flat Package)

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TMP90C800/801

2.2 Pin Names and Functions

The names of input/output pins and their functions are summarized in Table 2.2.

Table 2.2 Pin Names and Functions (1/2)

Pin Name

No. of pins

I/O 3 states

Function

I/O

Port 0: 8-bit I/O port that allows selection of input/output on byte basis

P00 ~ P07

/AD0 ~ AD7

Address/Data bus: Functions as 8-bit bidirectional address/data bus for external memory (For 401, fixed to

address/data bus)

3 states

I/O

Port 1: 8-bit I/O port that allows selection on byte basis

P10 ~ P17

/A8 ~ A15

Address bus: Functions as address bus (upper 8 bits) by EXT1 set for external memory (For 401, fixed to

address bus

Output

Port 20 ~ 23: 4-bit I/O port with a pull-up resistor that can be programmed, and allows selection of

input/output on bit basis

P20 ~ P23

I.O

I/O

Port 24: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of

input/output on bit basis

P24

/NMI

Non-maskable interrupt request pin: Falling edge interrupt register pin

Input

I/O

Port 25: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

P25

/WAIT

Input

Wait: Input pin for connecting slow speed memory of peripheral LSI

Port 26: 1-bit output port

Output

P26

/RD

Read: Generates strobe signal for reading external memory (For 401, fixed to RD)

Port 27: 1-bit output port

P27

/WR

Read: Generates strobe signal for writing into external memory (For 401, fixed to WR)

Port 30: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

I/O

P30

/INTO

Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)

Input

Port 31: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

P31

/INT1

Input

Interrupt request pin 1: Rising edge interrupt request pin

Port 32: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

I/O

P32

/TI0

Input

Timer input 0: Counter input pin for Timer 0

Port 33: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

P33

/TI2

Output

Timer input 2: Counter input pin for Timer 2

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TMP90C800/801

Table 2.2 Pin Names and Functions (2/2)

Port 35: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

I/O

P35

/RxD

Receive serial data

Port 36: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

I/O

P36

/SCLK

Output

I/O

Serial clock output

Port 37: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on

bit basis

P37

TxD

Output

I/O

Transmitter serial data

P40 ~ P47

P50 ~ P57

P60 ~ P67

ALE

Port 4: 8-bit I/O port that allows I/O selection on bit basis

Port 5: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit

basis

I/O

Port 6: 8-bit I/O port that allows I/O selection on bit basis

Address latch enable signal: The negative edge ALE supplies an address latch timing on AD0 ~ A07 for

external memory

Output

External access: Connects with V pin in the TMP90C400 using internal ROM, and with GND pin in the

TMP90C401 with no internal ROM

Input

CLK

Output

Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting.

RESET

X1/X2

Input

Reset: Initializes the TMP90C400/401 (Built-in pull-up resistor)

Pin for quartz crystal or ceramic resonator (1 ~ 12.5MHz)

Power supply (+5V)

Input/Output

–

Ground (0V)

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TMP90C800/801

(2)

Internal RAM

3. Operation

This chapter describes the functions and the basic operations

of the TMP90C400/401 in every block.

The function of TMP90C800 is exactly same as that of

TMP90C400 except the internal ROM/RAM size. Refer to the

TMP90C400 except the function which are not described this

section.

The TMP90C800 also contains a 256-byte RAM,

which is allocated to the address space from FF80H to

FF7FH. The CPU allows the access to a certain RAM

area (FF00H to FF7FH, 256 bytes) by a short operation

code (opcode) in a “direct addressing mode”.

The addresses from FF20H to FF5FH in this RAM area

can be used as parameter area for micro DMA processing

(and for any other purposes when the micro DMA

function is not used).

3.1 CPU

The TMP90C800 includes a high performance 8-bit CPU. For

the function of the CPU, see the book TLCS Series CPU

Core Architecture concerning CPU operation.

(3)

Internal I/O

3.2 Memory Map

The TMP90C800 supports a program memory of up to 56K

bytes.

The program and data memory may be assigned to the

address space from 0000H to FFFFH.

The TMP90C800 provides a 32-byte address space as

an internal I/O area, whose addresses range from FF80H

to FF9FH. This I/O area can be accessed by the CPU

using a short opcode in the “direct addressing mode”.

Figure 3.1 is a memory map indicating the areas

accessible by the CPU in the respective addressing

mode.

(1)

Internal ROM

The TMP90C800 internally contains an 8K-byte ROM.

The address space from 0000H to 1FFFH is provided

to the ROM. The CPU starts executing a program from

0000H by resetting.

The addresses 0010H to 005FH in this internal ROM area

are used for the entry area for the interrupt processing.

The TMP90C801 does not have a built-in ROM; therefore,

the address space 0000H to 1FFFH is used as exter-

nal memory space.

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TMP90C800/801

Figure 3.2 (a). Memory Map of TMP90C800

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TMP90C800/801

Figure 3.2 (b). Memory Map of TMP90C801

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TMP90C800/801

4. Electrical Characteristics (Preliminary)

TMP90C800N/TMP90C800F/

TMP90C801N/TMP90C801F

4.1 Absolute Maximum Ratings

Symbol

Parameter

Rating

Unit

Supply voltage

Input voltage

-0.5 ~ + 7

-0.5 ~ V + 0.5

F 500

N 600

Power dissipation (Ta = 85°C)

Soldering temperature (10s)

Storage temperature

260

°C

SOLDER

-65 ~ 150

-40 ~ 85

STG

OPR

Operating temperature

4.2 DC Characteristics

V_CC= 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)

TA = -20 ~ 70°C (1 ~ 12.5MHz)

Symbol

Parameter

Min

Max

Unit

Test Conditions

Input Low Voltage (P0)

-0.3

2.2

0.8

–

P1, P2, P3, P4, P5, P6

0.3V

IL1

IL2

IL3

IL4

RESET, NMI

0.25V

0.3

0.2V

Input High Voltage (P0)

P1, P2, P3, P4, P5, P6

RESET, NMI

+ 0.3

0.7V

IH1

IH2

IH3

IH4

0.75V

- 0.3

0.8V

–

Output Low Voltage

0.45

= 1.6mA

2.4

= -400µA

= -100µA

= -20µA

Output High Voltage

0.75V

–

OH1

OH2

0.9V

Darlington Drive Current

(8 I/O pins) (Note)

= 1.5V

= 1.1kΩ

EXT

-0.1

-3.5

DAR

Input Leakage Current

Output Leakage Current

0.02 (Typ)

0.05 (Typ)

±5

µA

0.0 ≤ Vin ≤ V

±10

0.2 ≤ Vin ≤ V - 0.2

Operating Current (RUN)

Idle 1

Idle 2

20 (Typ)

1.5 (Typ)

6 (Typ)

tosc = 10MHz

(25%Up @12.5MHz)

STOP (TA = -40 ~ 85°C)

STOP (TA = 0 ~ 50°C)

µA

0.05 (Typ)

0.2 ≤ Vin ≤ V - 0.2

= 0.2V ,

IL2

Power Down Voltage (@STOP)

STOP

RAM BACK UP

= 0.8V

IH2

RESET Pull Up Register

Pin Capacitance

–

150

KΩ

–

RST

CIO

testfreq = 1MHz

Schmitt width RESET, NMI

0.4

1.0 (Typ)

Note: I

is guaranteed for a total of up to 8 optional ports.

DAR

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TMP90C800/801

4.3 AC Characteristics

V_CC= 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)

CL = 50pF TA = -20 ~ 70°C (1 ~ 12.5MHz)

Variable

10MHz Clock

12.5MHz Clock

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

Oscillation cycle ( = x)

CLK Period

1000

100

400

160

100

–

320

120

–

OSC

CYC

CLK High width

CLK Low width

2x - 40

–

A0 ~ 7 effective address→ALE fall

ALE fall →A0 ~ 7 hold

0.5x - 15

x - 40

0.5x - 30

0.5x - 20

x - 25

1.5x - 50

0.5x - 20

–

ALE Pulse width

–

ALE fall RD/WR fall

–

RD/WR →ALE rise

–

A0 ~ 7 effective address →RD/WR fall

Upper effective address →RD/WR fall

RD/WR fall →Upper address hold

A0 ~ 7 effective address →Effective data input

Upper effective address →Effective data input

RD fall →Effective data input

RD Pulse width

–

ACL

ACH

–

3.0x - 35

265

295

150

–

205

225

110

–

ADL

ADH

–

3.5x - 55

–

2.0x - 50

–

2.0x - 40

–

160

120

RD rise →Data hold

–

RD rise→ Address enable

WR pulse width

x - 15

2.0x - 40

2.0x - 50

0.5x - 10

2.5x - 50

2.0x - 50

1.5x - 80

x - 25

x - 60

x - 50

–

160

150

200

150

–

120

110

150

110

–

RAE

–

Effective data→WR rise

–

WR rise→Effective data hold

Upper address→CLK fall

Lower address →CLK fall

CLK fall→Upper address hold

RD/WR→CLK fall

–

ACKH

–

ACKL

CKHA

–

CCK

CLK fall→RD/WR rise

–

CKHC

Valid data CLK fall

–

x - 40

2.0x - 70

–

DCK

RD/WR fall→Valid WAIT

Lower address →Valid WAIT

CLK fall →Valid WAIT hold

Upper address →Valid WAIT

CLK fall →Port Data Output

Port Data Input →CLK fall

CLK fall →Port Data hold

130

–

CWA

–

AWAL

WAH

–

2.5x - 70

x + 200

–

180

300

–

130

280

–

AWAH

–

CPW

200

100

200

100

PRC

CPR

100

–

AC Measuring Conditions

• Output level: High 2.2V/Low 0.8V, C = 50pF

(However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR)

• Input level: High 2.4V/Low 0.45V (AD0 ~ AD7)

High 0.8V /Low 0.2V (excluding AD0 ~ AD7)

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TMP90C800/801

4.4 Zero-Cross Characteristics

V_CC= 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)

TA = -20 ~ 70°C (1 ~ 12.5MHz)

Symbol

Parameter

Condition

Min

Max

Unit

Zero-cross detection input

Zero-cross accuracy

AC coupling C = 0.1µF

50/60Hz sine wave

–

1.8

135

VAC p-p

Zero-cross detection input frequency

0.04

kHz

4.5 Serial Channel Timing-I/O Interface Mode

V_CC= 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)

CL = 50pF TA = -20 ~ 70°C (1 ~ 12.5MHz)

Variable

Max

10MHz Clock

12.5MHz Clock

Symbol

Parameter

Serial Port Clock Cycle Time

Unit

Min

Max

Min

Max

6x - 150

2x - 120

–

800

450

–

640

330

–

SCY

OSS

OHS

Output Data Setup SCLK Rising Edge

Output Data Hold After SCLK Rising Edge

Input Data Hold After SCLK Rising Edge

SCLK Rising Edge to Input DATA Valid

–

HSR

SRD

–

6x - 150

–

450

–

330

4.6 8-bit Event Counter

V_CC= 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)

TA = -20 ~ 70°C (1 ~ 12.5MHz)

Variable

10MHz Clock

12.5MHz Clock

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

TI2 clock cycle

8x + 100

4x + 40

–

900

440

–

740

360

–

VCK

TI2 Low clock pulse width

TI2 High clock pulse width

VCKL

VCKH

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TMP90C800/801

4.7 Interrupt Operation

V_CC= 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)

TA = -20 ~ 70°C (1 ~ 12.5MHz)

Variable

10MHz Clock

12.5MHz Clock

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

NMI, INT0 Low level pulse width

–

400

–

320

–

INTAL

INTAH

NMI, INT0 High level pulse width

INT1, INT2 Low level pulse width

–

400

900

–

320

740

–

8x + 100

INTBL

INT1, INT2 High level pulse width

8x + 100

–

900

–

740

–

INTBH

4.8 I/O Interface Mode Timing

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TMP90C800/801

4.9 Timing Chart

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TMP90C800N [ETC]

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