TMPR3907F [ETC]
MICROPROCESSOR|32-BIT|CMOS|QFP|208PIN|PLASTIC ;
| 型号： | TMPR3907F |
| 厂家： | 
ETC |
| 描述： | MICROPROCESSOR|32-BIT|CMOS|QFP|208PIN|PLASTIC |
| 文件： | 总4页 (文件大小：31K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMPR3907F 32-bit MIPSÒ
RISC Microprocessor
TOSHIBA
Peripheral Features
Description
·
DRAM Controller
The TMPR3907F is a 32-bit MIPS RISC
microprocessor of the TX39 family. The
TMPR3907F uses the TX39/H Processor Core as
the CPU, which is a RISC CPU core Toshiba
developed based on the MIPSÒ R3000A
architecture. The TMPR3907F has built-in
peripheral circuits such as a PCI Bus Controller,
DRAM and ROM Memory Controllers, Serial
Communication Ports, and Timer/Counter
implementations.
- Supports 3 channels of DRAM memories
- Each channel supports two banks of memory
- Independent memory size and timing set-up
for each channel
- Support of 32/16-bit static bus sizing
- Supports both fast and hyper page EDO
modes
·
ROM Controller
- Supports 5 channels of ROM controller with a
single chip select per channel
- Supports simple-page-mode and interleaved-
page-mode ROM
The TX39/H core and added PCI Bus Controller
features of this chip allow it to achieve high
performance system interfacing.
- Supports various memory size of
1M/2M/4M/8M/16Mbyte per channel
- Supports 32/16-bit static bus sizing and fast
page read mode
Microprocessor Features
·
Built–in TX39 Processor Core
- Developed based on the R3000A architecture
- Instruction cache 4KB and Data cache 1KB
- Built-in Debug Support Unit (DSU)
- Five-stage pipeline: Fetch, Decode, Execute,
Memory access, and Register write
- Incorporates single cycle DSP function Multiply-
Accumulate (MAC)
- Supports Mask ROM, EPROM, E2PROM,
SRAM, and Flash Memory
- Supports 2-way interleaved ROM attachment
on Channel 0
Timer/Counter
- 3-channel 24-bit up-counter
- Interval and Watchdog timer modes
Serial I/O Ports
- One-channel UART
- Baud rate generator and modem flow control
Interrupt Controller
·
·
·
·
·
·
·
Power Supply: VDD = 3.3V ± 0.3V
Maximum Operating Frequency: 66MHz
Package: 208 pin plastic QFP
R3900 Core
Timer, Debug,
SIO0, and Test
- Priority process of 8 interrupt sources
- Non-maskable Interrupt (NMI)
PCI Controller
Data
cache
Instruction
cache
SIO, Test
and Debug
DSU
WBU
G-Bus Interface
- Full compliance with PCI Local Bus
Specification Rev. 2.1
IM Bus
GBUS
- 32-bit PCI interface at 33MHz
- Supports both target and initiator mode
- Supports zero-wait-state read and write burst
transfer for target and initiator
- FIFO to minimize initial latency requirements
to and from memory controller
- Supports PIO mode transfer between local bus
and PCI Core
Interrupt
Controller
INT [3:1]
5-Channel
ROM/Flash
Controller
RAM Address
Control Signals
3-Channel
DRAM
Controller
Host PCI Bridge
External
Bus
Interface
(EBIF)
Memory Data
Bus
ROM Address, and
Control Signals
PCI Bus
- Supports auto PCI bus to local bus address
space mapping
Figure 1. TMPR3907F Block Diagram
Product Brief
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TMPR3907F 32-bit MIPS RISC Microprocessor
33 MHz
Clock Generator
ROM / Flash Control
ROM / Flash
ROM / Flash Addressing
Test & Reset
Core Observability
32-Bit Page
Mode ROM
32-Bit Page
Mode ROM
2-Way Quick-Switches
Data Bus
TX3907F-66 MHz
208 PQFP
DRAM Control
DRAM Addressing
Base EDO DRAM
EDO DRAM SIMM
Address/Data
Control/Arb.
Control/Arb.
PCI Slot 0
Address/Data
PCI Slot 1
Figure 2. Typical System Block Diagram
Product Brief
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
2
TMPR3907F 32-bit MIPS RISC Microprocessor
Table 1. Pin Assignment
Pin No.
1
Signal
INT[1]
Pin No.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Signal
ROMAD[7]
ROMAD[8]
ROMAD[9]
OE*
Pin No.
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Signal
D[17]
Pin No.
85
Signal
VDD
2
INT[0]
D[25]
86
VSS
3
GNT_N[2]
GNT_N[1]
GNT_N[0]
ROMAD[23]
ROMAD[22]
SCS[1]*/CE[4]*
VDD
D[18]
87
DRAMA[7]
DRAMA[11]
DRAMA[8]
DRAMA[9]
DRAMA[12]
RAS0[0]*
RAS0[1]*
RAS1[0]*
RAS1[1]*
VSS
4
VSS
88
5
SYSCLK
ACK*
VDD
89
6
VSS
90
7
LAST*/RD*
VDD
D[26]
91
8
D[19]
92
9
VSS
D[27]
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
VSS
DRAMA[0]
DRAMA[1]
DRAMA[2]
DRAMA[3]
DRAMA[4]
DRAMA[5]
VSS
94
VSS
ROMAD[10]
ROMAD[11]
ROMAD[12]
ROMAD[13]
VDD
95
SCS[0]*/CE[3]*
CE[2]*
96
97
VDD
CE[1]*
98
RAS2[0]*
RAS2[1]*
CAS[0]*/BE[0]*
CAS[1]*/BE[1]*
CAS[3]*/BE[3]*
CAS[2]*/BE[2]*
WE*
VSS
99
CE[0]*
ROMAD[14]
ROMAD[15]
ROMAD[16]
ROMAD[17]
ROMAD[18]
ROMAD[19]
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
SWE*
VSS
R/W*
VDD
SPADD[0]
SPADD[1]
ROMAD[2]
ROMAD[3]
ROMAD[4]
ROMAD[5]
VDD
DRAMA[6]
DRAMA[10]
D[20]
D[0]
D[28]
D[8]
ROMAD[20]
ROMAD[21]
ENLEAFA*
ENLEAFB*
D[16]
D[21]
PLLOFF*
PLL_VSS
VSS
D[29]
D[22]
VSS
D[30]
XIN
VSS
D[23]
XOUT
ROMAD[6]
D[24]
D[31]
VDD
*Active-low signal
3
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Product Brief
TMPR3907F 32-bit MIPS RISC Microprocessor
Table 1. Pin Assignment (Continued)
Pin No.
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
Signal
PLL_VDD
VDD
Pin No.
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Signal
SDI*
Pin No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Signal
PCIAD[11]
PCIAD[12]
PCIAD[13]
VSS
Pin No.
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal
PCIAD[18]
PCIAD[19]
PCIAD[20]
PCIAD[21]
PCIAD[22]
PCIAD[23]
ID_SEL
DBGE*
PCST[2]
PCST[1]
PCST[0]
VSS
D[1]
D[9]
D[2]
VDD
D[10]
VSS
PCIAD[14]
PCIAD[15]
C_BE[1]
PAR
GDCLK
PCI_CLK
PCIAD[0]
PCIAD[1]
VDD
D[3]
VSS
D[11]
D[4]
C_BE[3]
PCIAD[24]
PCIAD[25]
PCIAD[26]
PCIAD[27]
PCIAD[28]
PCIAD[29]
VSS
SERR_N
PERR_N
STOP_N
VSS
D[12]
D[13]
D[5]
PCIAD[2]
PCIAD[3]
PCIAD[4]
PCIAD[5]
PCIAD[6]
PCIAD[7]
VDD
D[14]
D[6]
DEVSEL_N
TRDY_N
IRDY_N
FRAME_N
C_BE[2]
PCIAD[16]
PCIAD[17]
VDD
D[15]
D[7]
VDD
VSS
VSS
VSS
VSS
PCIAD[30]
PCIAD[31]
REQ_N[2]
REQ_N[1]
REQ_N[0]
INT[2]
RESET*
TEST*
NMI*
VSS
C_BE[0]
PCIAD[8]
PCIAD[9]
PCIAD[10]
VSS
DSA0
DRESET*
VSS
VDD
*Active-low signal
MIPSÒ is a registered trademark R3000A is a trademark of UPS Technologies, Inc
www.toshiba.com/taec
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third parties.
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