TMS320C6202B-250 [ETC]
Fixed-Point Digital Signal Processor ; 定点数字信号处理器\n
| 型号： | TMS320C6202B-250 |
| 厂家： | 
ETC |
| 描述： | Fixed-Point Digital Signal Processor
|
| 文件： | 总100页 (文件大小：1521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
D
D
High-Performance Fixed-Point Digital
Signal Processors (DSPs) – TMS320C62x
– 5-, 4-, 3.33-ns Instruction Cycle Time
– 200-, 250-, 300-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1600, 2000, 2400 MIPS
D
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
D
D
Flexible Phase-Locked-Loop (PLL) Clock
Generator
32-Bit Expansion Bus (XBus)
– Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
C6202 and C6203B GLS Ball Grid Array
(BGA) Packages are Pin-Compatible With
†
the C6204 GLW BGA Package
D
D
C6202B and C6203B GNZ and GNY
Packages are Pin-Compatible
VelociTI Advanced Very-Long-Instruction-
Word (VLIW) C62x DSP Core
– Eight Highly Independent Functional
Units:
D
Three Multichannel Buffered Serial Ports
(McBSPs)
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral Interface (SPI)
Compatible (Motorola )
D
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Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
D
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Two 32-Bit General-Purpose Timers
‡
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
352-Pin BGA Package (GJL) (C6202)
352-Pin BGA Package (GNZ) (C6202B)
384-Pin BGA Package (GLS) (C6202)
384-Pin BGA Package (GNY) (C6202B)
– Normalization
3M-Bit On-Chip SRAM
– 2M-Bit Internal Program/Cache
(64K 32-Bit Instructions)
– 1M-Bit Dual-Access Internal Data
(128K Bytes)
0.18-µm/5-Level Metal Process (C6202)
0.15-µm/5-Level Metal Process (C6202B)
– CMOS Technology
– Organized as Two 64K-Byte Blocks for
Improved Concurrency
D
3.3-V I/Os, 1.8-V Internal (C6202)
3.3-V I/Os, 1.5-V Internal (C6202B)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
– 52M-Byte Addressable External Memory
Space
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
†
‡
For more details, see the GLS BGA package bottom view.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Table of Contents
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GJL, GNZ, GLS, and GNY BGA packages . . . . . . . . . . . . 3
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
C62x device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
functional and CPU (DSP core) block diagram . . . . . . . . . 9
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . 10
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . 13
DMA synchronization events . . . . . . . . . . . . . . . . . . . . . . . 18
interrupt sources and interrupt selector . . . . . . . . . . . . . . 19
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 20
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . 42
parameter measurement information . . . . . . . . . . . . . . . 44
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . 44
timing parameters and board routing analysis . . . . . . 45
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 49
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 53
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 56
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 64
expansion bus synchronous FIFO timing . . . . . . . . . . . . 65
expansion bus asynchronous peripheral timing . . . . . . 67
expansion bus synchronous host-port timing . . . . . . . . 71
expansion bus asynchronous host-port timing . . . . . . . 77
XHOLD/XHOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 79
multichannel buffered serial port timing . . . . . . . . . . . . . 81
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 93
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
absolute maximum ratings over operating case
temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 43
recommended operating conditions . . . . . . . . . . . . . . . . . 43
electrical characteristics over recommended ranges
of supply voltage and operating case temperature 43
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS104F device-specific data
sheet to make it an SPRS104G revision.
SCOPE: Applicable updates to the C62x device family, specifically relating to the C6202/02B devices, have
been incorporated. Added device-specific information for the new extended-temperature device
(C6202BGNZA-250).
Also added and updated device-specific information to support the characterized C6202B devices which are
now at the production data (PD) stage of development. The C6202BGNZA-250 extended-temperature device
reflects the same electrical specifications as the C6202B-250 devices.
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
Table 1, Characteristics of the Pin-Compatible DSPs:
7
Added extended-temperature device-specific information for C6203B and C6202B device columns.
Changed the device product status for the C6202B device from Advance Information (AI) to Production Data (PD)
Deleted footnote description of PRODUCT PREVIEW and ADVANCE INFORMATION
8
C62x Device Compatibility section:
Added “device clock speeds” bullet and paragraph explanation
36
37
Figure 4, TMS320C6000 DSP Platform Device Nomenclature (Including TMS320C6202 and C6202B):
Added additional devices to the “C6000 DSP:” category
Documentation Support section:
Added paragraph referencing the TMS320C6202 Digital Signal Processor Silicon Errata [literature number SPRZ152]
Added paragraph referencing the Using IBIS Models for Timing Analysis application report [literature number SPRA839]
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
43–95
Electricals:
Added the device-specific information on the extended-temperature device (C6202BGNZA-250)
43
Absolute Maximum Ratings Over Operating Case Temperature Ranges section:
Added the extended-temperature device-specific information to the “Operating case temperature ranges, T : (A version)”
C
43
Recommended Operating Conditions table:
Added “:C6202BGNZA-250” to the A version of T
C
45
Timing Parameters and Board Routing Analysis section:
Added reference to the Using IBIS Models for Timing Analysis application report (literature number SPRA839) in first
paragraph.
Changed the title of Table 20 to “Board-Level Timings Example”
Changed the title of Figure 11 to “Board-Level Input/Output Timings”
98
Replaced GNZ (S-PBGA-N352) [C6202B only] mechanical with the latest version
GJL, GNZ, GLS, and GNY BGA packages
GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) [C6202 only]
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
GJL, GNZ, GLS, and GNY BGA packages (continued)
GNZ 352-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) [C6202B only]
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GLS 384-PIN BGA PACKAGE (BOTTOM VIEW) [C6202 only]
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The C6202 and C6203B GLS BGA packages are pin-compatible with the C6204 GLW
package except that the inner row of balls (which are additional power and ground pins)
are removed for the C6204 GLW package.
These balls are NOT applicable for the C6204 devices 340-pin GLW BGA package.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
GJL, GNZ, GLS, and GNY BGA packages (continued)
GNY 384-PIN BGA PACKAGE (BOTTOM VIEW) [C6202B only]
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description
The TMS320C6202 and TMS320C6202B devices are part of the TMS320C62x fixed-point DSP generation
in the TMS320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced
VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these
DSPs an excellent choice for multichannel and multifunction applications.
The TMS320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges.
The TMS320C6202/02B has a performance capability of up to 2400 million instructions per second (MIPS) at
300 MHz. The C6202/02B DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. These processors have 32 general-purpose registers of 32-bit word length and
eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for
a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6202/02B can produce two
multiply-accumulates (MACs) per cycle. This gives a total of 600 million MACs per second (MMACS) for the
C6202/02B device. The C6202/02B DSP also has application-specific hardware logic, on-chip memory, and
additional on-chip peripherals.
The C6202/02B devices program memory consists of two blocks, with a 128K-byte block configured as
memory-mapped program space, and the other 128K-byte block user-configurable as cache or
memory-mapped program space. Data memory for the C6202/02B consists of two 64K-byte blocks of RAM.
TMS320C6000 is a trademark of Texas Instruments.
5
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
description (continued)
The C6202/02B device has a powerful and diverse set of peripherals. The peripheral set includes three
multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XBus) that
offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless
32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous
peripherals.
The C62x devices have a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
device characteristics
Table 1 provides an overview of the TMS320C6202, TMS320C6202B, TMS320C6203B, and the
TMS320C6204 pin-compatible DSPs. The table shows significant features of each device, including the
capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. This
data sheet primarily focuses on the functionality of the TMS320C6202/02B devices although it also identifies
to the user the pin-compatibility of the C6202 and C6203B GLS, and the C6204 GLW BGA packages. This data
sheet also identifies the pin-compatibility of the C6202B and the C6203B GNZ and GNY packages. For the
functionality information on the TMS320C6203B device, see the TMS320C6203B Fixed-Point Digital Signal
Processor data sheet (literature number SPRS086). For the functionality information on the TMS320C6204
device, see the TMS320C6204 Fixed-Point Digital Signal Processor data sheet (literature number SPRS152).
And for more details on the C6000 DSP device part numbers and part numbering, see Table 15 and Figure 4.
C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
6
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
device characteristics (continued)
Table 1. Characteristics of the Pin-Compatible DSPs
HARDWARE FEATURES
C6202
C6202B
C6203B
C6204
EMIF
√
√
√
√
4-Channel With
Throughput
4-Channel With
Throughput
4-Channel With
Throughput
DMA
4-Channel
Enhancements
Enhancements
Enhancements
Peripherals
Expansion Bus
McBSPs
√
3
√
3
√
3
√
2
32-Bit Timers
Size (Bytes)
2
2
2
2
256K
256K
384K
64K
Block 0:
Block 0:
Block 0:
128K-Byte
Mapped Program
Block 1:
128K-Byte
Cache/Mapped
Program
128K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
256K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
Internal
Program
Memory
1 Block:
64K-Byte
Cache/Mapped
Program
Organization
Size (Bytes)
Organization
128K
128K
512K
64K
2 Blocks:
Four 16-Bit Banks
per Block
2 Blocks:
Four 16-Bit Banks
per Block
2 Blocks:
Four 16-Bit Banks
per Block
2 Blocks:
Four 16-Bit Banks
per Block
Internal Data
Memory
50/50 Split
50/50 Split
50/50 Split
50/50 Split
Control Status
Register
(CSR.[31:16])
CPU ID +
CPU Rev ID
0x0002
0x0003
0x0003
0x0003
200
Frequency
Cycle Time
MHz
200, 250
250, 300
250, 300
3.33 ns (6202B-300)
4 ns (6202B-250)
4 ns (02BGNZA-250)
3.33 ns (6203B-300)
4 ns (6203B-250)
4 ns (03BGNZA-250)
4 ns (6202-250)
5 ns (6202-200)
ns
5 ns (6204-200)
1.5
1.7
3.3
Core (V)
I/O (V)
1.8
3.3
1.5
3.3
1.5
3.3
Voltage
All PLL Options
(GNY Pkg)
All PLL Options
(GLS/GNY Pkgs)
CLKIN frequency
multiplier [Bypass
(x1), x4, x6, x7, x8,
x9, x10, and x11]
x1, x4
(Both Pkgs)
x1, x4
(Both Pkgs)
PLL Options
x1, x4, x8, x10
(GNZ Pkg)
x1, x4, x8, x10
(GNZ Pkg)
27 x 27 mm
18 x 18 mm
352-pin GJL
384-pin GLS
352-pin GNZ
352-pin GNZ
384-pin GLS
–
–
340-pin GLW
BGA
Packages
384-pin GNY
(2.x, 3.x only)
18 x 18 mm
16 x 16 mm
µm
–
–
384-pin GNY
–
–
–
288-pin GHK
0.15 µm
Process
Technology
0.18 µm
0.15 µm
0.15 µm
Product Preview (PP)
Advance Information
(AI)
Product
Status
PD
PD
PD
PD
†
Production Data (PD)
†
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
7
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
C62x device compatibility
The TMS320C6202, C6202B, C6203B, and C6204 devices are pin-compatible; thus, making new system
designs easier and providing faster time to market. The following list summarizes the C62x DSP device
characteristic differences:
D
D
D
Core Supply Voltage (1.8 V versus 1.7 V versus 1.5 V)
The C6202 device core supply voltage is 1.8 V while the C6202B, C6203B, C6204 devices have core supply
voltages of 1.5 V. Furthermore, the C6203B-300 speed devices (GNY and GNZ packages) also have a
1.7-V core supply voltage.
Device Clock Speeds
The C6202B and C6203B devices run at –250 and –300 MHz clock speeds (with a C620xBGNZA extended
temperature device that also runs at –250 MHz), while the C6202 device runs at –200 and –250 MHz, and
the C6204 device runs at –200 MHz clock speed.
PLL Options Availability
Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4, etc.] for each of the
C62x DSP devices. For additional details on the PLL clock module and specific options for the C6202/02B
devices, see the Clock PLL section of this data sheet.
For additional details on the PLL clock module and specific options for the C6203B device, see the Clock
PLL section of the TMS320C6203B Fixed-Point Digital Signal Processor data sheet (literature number
SPRS086).
And for additional details on the PLL clock module and specific options for the C6204 device, see the Clock
PLL section of the TMS320C6204 Fixed-Point Digital Signal Processor data sheet (literature number
SPRS152).
D
D
On-Chip Memory Size
The C6202/02B, C6203B, and C6204 devices have different on-chip program memory and data memory
sizes (see Table 1).
McBSPs
The C6202, C6202B, and C6203B devices have three McBSPs while the C6204 device has two McBSPs
on-chip.
For a more detailed discussion on migration concerns, and similarities/differences between the C6202,
C6202B, C6203B, and C6204 devices, see the How to Begin Development Today and Migrate Across the
TMS320C6202/02B/03B/04 DSPs application report (literature number SPRA603).
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
functional and CPU (DSP core) block diagram
C6202/02B Digital Signal Processors
SDRAM or
SBSRAM
Program
Access/Cache
Controller
32
Internal Program Memory
(See Table 1)
SRAM
External Memory
Interface (EMIF)
ROM/FLASH
I/O Devices
C62x CPU (DSP Core)
Timer 0
Timer 1
Instruction Fetch
Control
Registers
Instruction Dispatch
Control
Logic
Instruction Decode
Multichannel
Buffered Serial
Port 0
Data Path A
Data Path B
Test
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
A Register File
B Register File
In-Circuit
Emulation
Multichannel
Buffered Serial
Port 1
Interrupt
Control
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Multichannel
Buffered Serial
Port 2
Interrupt
Selector
Internal Data
Memory
Data
Access
Synchronous
FIFOs
Controller
(See Table 1)
32
Peripheral Control Bus
Expansion
Bus (XBus)
32-Bit
I/O Devices
Direct Memory
Access Controller
(DMA)
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
Power-
Down
Logic
(See Table 1)
PLL
Boot Configuration
960
(x1, x4, x6, x7, x8,
†
x9, x10, x11)
†
For additional details on the PLL clock module and specific options for the C6202/02B devices, see Table 1 and the Clock PLL section of this
data sheet.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram
and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally, each side features a single data bus connected to all the registers on the other side, by
which the two sets of functional units can access data from the register files on the opposite side. While register
access by functional units on the same side of the CPU as the register file can service all the units in a single
clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
10
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
CPU (DSP core) description (continued)
src1
src2
.L1
dst
long dst
long src
8
8
32
ST1
8
long src
long dst
dst
Register
File A
Data Path A
.S1
src1
(A0–A15)
src2
dst
src1
.M1
.D1
src2
LD1
DA1
dst
src1
src2
2X
1X
src2
src1
dst
DA2
LD2
.D2
src2
.M2
.S2
src1
dst
src2
Register
File B
(B0–B15)
Data Path B
src1
dst
long dst
long src
8
32
8
ST2
8
long src
long dst
dst
.L2
src2
src1
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
memory map summary
Table 2 shows the memory map address ranges of the C6202/02B device. The C6202/02B device has the
capability of a MAP 0 or MAP 1 memory block configuration. These memory block configurations are set up at
reset by the boot configuration pins (generically called BOOTMODE[4:0]). For the C6202/02B device, the
BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically XD[4:0] pins). For
more detailed information on the C6202/02B device settings, which include the device boot mode configuration
at reset and other device-specific configurations, see the Boot Configuration section and the Boot Configuration
Summary table of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
Table 2. TMS320C6202/02B Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE
HEX ADDRESS RANGE
(BYTES)
MAP 0
External Memory Interface (EMIF) CE0
EMIF CE0
MAP 1
Internal Program RAM
Reserved
256K
0000_0000 – 0003_FFFF
0004_0000 – 003F_FFFF
0040_0000 – 00FF_FFFF
0100_0000 – 013F_FFFF
0140_0000 – 0143_FFFF
0144_0000 – 017F_FFFF
0180_0000 – 0183_FFFF
0184_0000 – 0187_FFFF
0188_0000 – 018B_FFFF
018C_0000 – 018F_FFFF
0190_0000 – 0193_FFFF
0194_0000 – 0197_FFFF
0198_0000 – 019B_FFFF
019C_0000 – 019C_01FF
019C_0200 – 019F_FFFF
01A0_0000 – 01A3_FFFF
01A4_0000 – 01A7_FFFF
01A8_0000 – 01FF_FFFF
0200_0000 – 02FF_FFFF
0300_0000 – 03FF_FFFF
0400_0000 – 3FFF_FFFF
4000_0000 – 4FFF_FFFF
5000_0000 – 5FFF_FFFF
6000_0000 – 6FFF_FFFF
7000_0000 – 7FFF_FFFF
8000_0000 – 8001_FFFF
8002_0000 – FFFF_FFFF
4M – 256K
12M
EMIF CE0
EMIF CE0
EMIF CE1
EMIF CE0
4M
Internal Program RAM
Reserved
EMIF CE1
256K
EMIF CE1
4M – 256K
256K
EMIF Registers
DMA Controller Registers
256K
Expansion Bus (XBus) Registers
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
Interrupt Selector Registers
Power-Down Registers
Reserved
256K
256K
256K
256K
256K
512
256K – 512
256K
McBSP 2 Registers
Reserved
256K
5.5M
EMIF CE2
16M
EMIF CE3
16M
Reserved
1G – 64M
256M
XBus XCE0
XBus XCE1
256M
XBus XCE2
256M
XBus XCE3
256M
Internal Data RAM
Reserved
128K
2G – 128K
12
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
peripheral register descriptions
Table 3 through Table 12 identify the peripheral registers for the C6202/02B device by their register names,
acronyms, and hex address or hex address range. For more detailed information on the register contents, bit
names, and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number
SPRU190).
Table 3. EMIF Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
EMIF global control
COMMENTS
0180 0000
GBLCTL
External or internal; dependent on MAP0 or
MAP1 configuration (selected by the MAP bit
in the EMIF GBLCTL register)
0180 0004
0180 0008
CECTL1
CECTL0
EMIF CE1 space control
EMIF CE0 space control
External or internal; dependent on MAP0 or
MAP1 configuration (selected by the MAP bit
in the EMIF GBLCTL register)
0180 000C
0180 0010
–
Reserved
Corresponds to EMIF CE2 memory space:
[0200 0000 – 02FF FFFF]
CECTL2
EMIF CE2 space control
Corresponds to EMIF CE3 memory space:
[0300 0000 – 03FF FFFF]
0180 0014
CECTL3
EMIF CE3 space control
0180 0018
0180 001C
SDCTL
EMIF SDRAM control
EMIF SDRAM refresh control
Reserved
SDTIM
0180 0020 – 0180 0054
0180 0058 – 0183 FFFF
–
–
Reserved
13
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
peripheral register descriptions (continued)
Table 4. DMA Registers
HEX ADDRESS RANGE
0184 0000
0184 0004
0184 0008
0184 000C
0184 0010
0184 0014
0184 0018
0184 001C
0184 0020
0184 0024
0184 0028
0184 002C
0184 0030
0184 0034
0184 0038
0184 003C
0184 0040
0184 0044
0184 0048
0184 004C
0184 0050
0184 0054
0184 0058
0184 005C
0184 0060
0184 0064
0184 0068
0184 006C
0184 0070
0184 0074 – 0187 FFFF
ACRONYM
PRICTL0
PRICTL2
SECCTL0
SECCTL2
SRC0
REGISTER NAME
DMA channel 0 primary control
DMA channel 2 primary control
DMA channel 0 secondary control
DMA channel 2 secondary control
DMA channel 0 source address
DMA channel 2 source address
DMA channel 0 destination address
DMA channel 2 destination address
DMA channel 0 transfer counter
DMA channel 2 transfer counter
DMA global count reload register A
DMA global count reload register B
DMA global index register A
SRC2
DST0
DST2
XFRCNT0
XFRCNT2
GBLCNTA
GBLCNTB
GBLIDXA
GBLIDXB
DMA global index register B
GBLADDRA DMA global address register A
GBLADDRB DMA global address register B
PRICTL1
PRICTL3
SECCTL1
SECCTL3
SRC1
DMA channel 1 primary control
DMA channel 3 primary control
DMA channel 1 secondary control
DMA channel 3 secondary control
DMA channel 1 source address
DMA channel 3 source address
DMA channel 1 destination address
DMA channel 3 destination address
DMA channel 1 transfer counter
DMA channel 3 transfer counter
SRC3
DST1
DST3
XFRCNT1
XFRCNT3
GBLADDRC DMA global address register C
GBLADDRD DMA global address register D
AUXCTL
DMA auxiliary control register
Reserved
–
14
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
peripheral register descriptions (continued)
Table 5. Expansion Bus (XBUS) Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0188 0000
XBGC
Expansion bus global control register
Corresponds to XBus XCE0 memory
space: [4000 0000 – 4FFF FFFF]
0188 0004
XCECTL1
XCE1 space control register
Corresponds to XBus XCE1 memory
space: [5000 0000 – 5FFF FFFF]
0188 0008
0188 000C
0188 0010
XCECTL0
XBHC
XCE0 space control register
Expansion bus host port interface control register
XCE2 space control register
DSP read/write access only
Corresponds to XBus XCE2 memory
space: [6000 0000 – 6FFF FFFF]
XCECTL2
Corresponds to XBus XCE3 memory
space: [7000 0000 – 7FFF FFFF]
0188 0014
XCECTL3
XCE3 space control register
0188 0018
–
–
Reserved
0188 001C
Reserved
0188 0020
XBIMA
XBEA
–
Expansion bus internal master address register
Expansion bus external address register
Reserved
DSP read/write access only
DSP read/write access only
0188 0024
0188 0028 – 018B FFFF
–
–
XBISA
XBD
Expansion bus internal slave address
Expansion bus data
Table 6. Interrupt Selector Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Selects which interrupts drive CPU
interrupts 10–15 (INT10–INT15)
019C 0000
MUXH
Interrupt multiplexer high
Selects which interrupts drive CPU
interrupts 4–9 (INT04–INT09)
019C 0004
019C 0008
MUXL
Interrupt multiplexer low
External interrupt polarity
Sets the polarity of the external
interrupts (EXT_INT4–EXT_INT7)
EXTPOL
019C 000C – 019C 01FF
019C 0200
–
PDCTL
–
Reserved
Peripheral power-down control register
Reserved
019C 0204 – 019F FFFF
Table 7. Peripheral Power-Down Control Register
HEX ADDRESS RANGE
ACRONYM
PDCTL
REGISTER NAME
Peripheral power-down control register
019C 0200
15
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
peripheral register descriptions (continued)
Table 8. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and DMA controller can only read
this register; they cannot write to it.
018C 0000
DRR0
McBSP0 data receive register
018C 0004
018C 0008
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCER0
XCER0
PCR0
–
McBSP0 data transmit register
McBSP0 serial port control register
McBSP0 receive control register
McBSP0 transmit control register
McBSP0 sample rate generator register
McBSP0 multichannel control register
McBSP0 receive channel enable register
McBSP0 transmit channel enable register
McBSP0 pin control register
018C 000C
018C 0010
018C 0014
018C 0018
018C 001C
018C 0020
018C 0024
018C 0028 – 018F FFFF
Reserved
Table 9. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and DMA controller can only read
this register; they cannot write to it.
0190 0000
DRR1
Data receive register
0190 0004
0190 0008
DXR1
SPCR1
RCR1
XCR1
SRGR1
MCR1
RCER1
XCER1
PCR1
–
McBSP1 data transmit register
McBSP1 serial port control register
McBSP1 receive control register
McBSP1 transmit control register
McBSP1 sample rate generator register
McBSP1 multichannel control register
McBSP1 receive channel enable register
McBSP1 transmit channel enable register
McBSP1 pin control register
0190 000C
0190 0010
0190 0014
0190 0018
0190 001C
0190 0020
0190 0024
0190 0028 – 0193 FFFF
Reserved
16
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
peripheral register descriptions (continued)
Table 10. McBSP 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and DMA controller can only read
this register; they cannot write to it.
01A4 0000
DRR2
McBSP2 data receive register
01A4 0004
01A4 0008
DXR2
SPCR2
RCR2
XCR2
SRGR2
MCR2
RCER2
XCER2
PCR2
–
McBSP2 data transmit register
McBSP2 serial port control register
McBSP2 receive control register
McBSP2 transmit control register
McBSP2 sample rate generator register
McBSP2 multichannel control register
McBSP2 receive channel enable register
McBSP2 transmit channel enable register
McBSP2 pin control register
01A4 000C
01A4 0010
01A4 0014
01A4 0018
01A4 001C
01A4 0020
01A4 0024
01A4 0028 – 01A7 FFFF
Reserved
Table 11. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer,
monitors the timer status, and controls the
function of the TOUT pin.
0194 0000
CTL0
Timer 0 control register
Contains the number of timer input clock
cycles to count. This number controls the
TSTAT signal frequency.
0194 0004
PRD0
Timer 0 period register
Contains the current value of the
incrementing counter.
0194 0008
CNT0
Timer 0 counter register
Reserved
0194 000C – 0197 FFFF
–
Table 12. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer,
monitors the timer status, and controls the
function of the TOUT pin.
0198 0000
CTL1
Timer 1 control register
Contains the number of timer input clock
cycles to count. This number controls the
TSTAT signal frequency.
0198 0004
PRD1
Timer 1 period register
Contains the current value of the
incrementing counter.
0198 0008
CNT1
Timer 1 counter register
Reserved
0198 000C – 019B FFFF
–
17
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
DMA synchronization events
The C6202/C6202B DMA supports up to four independent programmable DMA channels, plus an auxiliary
channel used for servicing the HPI module. The four main DMA channels can be read/write synchronized based
on the events shown in Table 13. Selection of these events is done via the RSYNC and WSYNC fields in the
Primary Control registers of the specific DMA channel. For more detailed information on the DMA module,
associated channels, and event-synchronization, see the Direct Memory Access (DMA) Controller chapter of
the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
Table 13. TMS320C6202/02B DMA Synchronization Events
DMA EVENT
NUMBER
(BINARY)
EVENT NAME
EVENT DESCRIPTION
00000
00001
00010
00011
Reserved
TINT0
Reserved
Timer 0 interrupt
TINT1
Timer 1 interrupt
SD_INT
EMIF SDRAM timer interrupt
External interrupt pin 4
External interrupt pin 5
External interrupt pin 6
External interrupt pin 7
DMA channel 0 interrupt
DMA channel 1 interrupt
DMA channel 2 interrupt
DMA channel 3 interrupt
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
Host processor-to-DSP interrupt
McBSP2 transmit event
McBSP2 receive event
Reserved. Not used.
00100
00101
00110
EXT_INT4
EXT_INT5
EXT_INT6
EXT_INT7
DMA_INT0
DMA_INT1
DMA_INT2
DMA_INT3
XEVT0
00111
01000
01001
01010
01011
01100
01101
REVT0
01110
XEVT1
01111
REVT1
10000
10001
10010
10011 – 11111
DSP_INT
XEVT2
REVT2
Reserved
18
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
interrupt sources and interrupt selector
The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 14. The highest-priority interrupt
is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00–INT_03) are non-maskable and fixed. The remaining interrupts (INT_04–INT_15) are maskable and
default to the interrupt source specified in Table 14. The interrupt source for interrupts 4–15 can be programmed
by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control
registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 14. C6202/02B DSP Interrupts
INTERRUPT
CPU
INTERRUPT
NUMBER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
SELECTOR
CONTROL
REGISTER
INTERRUPT SOURCE
†
†
†
†
‡
‡
‡
‡
‡
‡
‡
INT_00
INT_01
INT_02
INT_03
INT_04
INT_05
INT_06
INT_07
INT_08
INT_09
INT_10
–
–
–
RESET
NMI
–
–
–
Reserved
Reserved
EXT_INT4
EXT_INT5
EXT_INT6
EXT_INT7
DMA_INT0
DMA_INT1
SD_INT
DMA_INT2
DMA_INT3
DSP_INT
TINT0
Reserved. Do not use.
–
–
Reserved. Do not use.
External interrupt pin 4
External interrupt pin 5
External interrupt pin 6
External interrupt pin 7
DMA channel 0 interrupt
DMA channel 1 interrupt
EMIF SDRAM timer interrupt
DMA channel 2 interrupt
DMA channel 3 interrupt
Host-processor-to-DSP interrupt
Timer 0 interrupt
MUXL[4:0]
00100
00101
00110
00111
01000
01001
00011
01010
01011
00000
00001
00010
01100
01101
01110
01111
10000
10001
10010
10011 – 11111
MUXL[9:5]
MUXL[14:10]
MUXL[20:16]
MUXL[25:21]
MUXL[30:26]
MUXH[4:0]
‡
INT_11
MUXH[9:5]
‡
‡
‡
‡
INT_12
MUXH[14:10]
INT_13
MUXH[20:16]
INT_14
MUXH[25:21]
INT_15
MUXH[30:26]
TINT1
Timer 1 interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XINT0
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
Reserved. Not used.
RINT0
XINT1
RINT1
Reserved
XINT2
McBSP2 transmit interrupt
McBSP2 receive interrupt
Reserved. Do not use.
RINT2
Reserved
†
‡
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control
registers fields. Table 14 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information
on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals
Reference Guide (literature number SPRU190).
19
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
signal groups description
CLKIN
CLKOUT2
CLKOUT1
RESET
NMI
CLKMODE0
†
CLKMODE1
Clock/PLL
†
EXT_INT7
CLKMODE2
EXT_INT6
EXT_INT5
EXT_INT4
IACK
PLLV
PLLG
PLLF
Reset and
Interrupts
INUM3
INUM2
INUM1
INUM0
TMS
TDO
TDI
IEEE Standard
1149.1
(JTAG)
Emulation
TCK
TRST
EMU1
EMU0
DMAC3
DMAC2
DMAC1
DMAC0
DMA Status
RSV4
RSV3
RSV2
RSV1
RSV0
Reserved
Power-Down
Status
PD
Control/Status
†
CLKMODE1 and CLKMODE2 are NOT available on the C6202 device GJL package.
CLKMODE2 is also NOT available on the GNZ package for the C6202B device.
Figure 2. CPU (DSP Core) Signals
20
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
signal groups description (continued)
ARE
Asynchronous
Memory
32
AOE
AWE
ARDY
ED[31:0]
Data
Control
CE3
CE2
CE1
CE0
Memory Map
Space Select
SDA10
Synchronous
Memory
SDRAS/SSOE
SDCAS/SSADS
SDWE/SSWE
Control
20
EA[21:2]
Word Address
Byte Enables
BE3
BE2
BE1
BE0
HOLD
HOLD/
HOLDA
HOLDA
EMIF
(External Memory Interface)
TOUT1
TINP1
TOUT0
TINP0
Timer 1
Timer 0
Timers
McBSP1
Transmit
McBSP0
Transmit
CLKX1
FSX1
DX1
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
CLKR0
FSR0
DR0
Receive
Clock
Receive
Clock
CLKS1
CLKS0
McBSP2
Transmit
CLKX2
FSX2
DX2
CLKR2
FSR2
DR2
Receive
Clock
CLKS2
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
21
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ꢂ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎꢏ
ꢐ
ꢑꢋ
ꢒ
ꢀ
ꢎ
ꢋ
ꢓ
ꢋ
ꢀꢔ
ꢕ
ꢋ
ꢓꢒ
ꢔꢕ
ꢐ
ꢖꢑ
ꢆꢍ
ꢂꢂ
ꢑ
ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
signal groups description (continued)
32
XCLKIN
XFCLK
XD[31:0]
Data
Clocks
XBE3/XA5
XBE2/XA4
XBE1/XA3
XBE0/XA2
Byte-Enable
Control/
Address
XOE
XRE
XWE/XWAIT
XCE3
XCE2
I/O Port
Control
XRDY
Control
XCE1
XCE0
XHOLD
Arbitration
XHOLDA
XCS
XAS
XCNTL
XW/R
XBLAST
XBOFF
Host
Interface
Control
Expansion Bus
Figure 3. Peripheral Signals (Continued)
22
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GLS/
GNY
TYPE
GNZ
CLOCK/PLL
CLKIN
C12
B10
Y18
I
Clock Input
Clock output at full device speed
Clock output at half (1/2) of device speed
Used for synchronous memory interface
Clock mode selects
CLKOUT1
AD20
O
CLKOUT2
AC19
B15
AB19
B12
O
•
CLKMODE0
CLKMODE1
CLKMODE2
I
I
I
•
Selects what multiply factors of the input clock frequency the CPU frequency
equals.
‡
C11
§
A9
For more details on the GJL, GNZ, GLS, and GNY CLKMODE pins and the PLL multiply
factors for the C6202 and C6202B devices, see the Clock PLL section of this data sheet.
§
A14
–
¶
#
A
#
A
#
A
PLLV
D13
D14
C13
C11
C12
A11
PLL analog V connection for the low-pass filter
CC
¶
PLLG
PLL analog GND connection for the low-pass filter
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
¶
PLLF
TMS
TDO
TDI
AD7
AE6
AF5
AE5
AC7
AF6
AC8
Y5
I
JTAG test-port mode select (features an internal pullup)
JTAG test-port data out
AA4
Y4
O/Z
I
I
I
JTAG test-port data in (features an internal pullup)
JTAG test-port clock
TCK
AB2
AA3
AA5
AB4
TRST
EMU1
EMU0
JTAG test-port reset (features an internal pulldown)
||
||
I/O/Z
I/O/Z
Emulation pin 1, pullup with a dedicated 20-kΩ resistor
Emulation pin 0, pullup with a dedicated 20-kΩ resistor
RESET AND INTERRUPTS
RESET
NMI
K2
L2
J3
I
I
Device reset
Nonmaskable interrupt
K2
•
Edge-driven (rising edge)
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
V4
Y2
U2
U3
W1
V2
V1
R3
T1
T2
T3
External interrupts
•
•
Edge-driven
I
Polarity independently selected via the external interrupt polarity register bits
(EXTPOL.[3:0])
AA1
W4
Y1
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
V2
Active interrupt identification number
INUM2
U4
V3
•
•
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
O
INUM1
INUM0
W2
†
‡
§
¶
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
For the C6202 GJL package only, the C11 pin is ground (V ). For all C62x GNZ packages, the C11 pin is CLKMODE1.
SS
For the C6202 GLS package, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.
PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the Clock PLL section for information on how to connect these
pins.
#
||
A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GNZ
GLS/
GNY
TYPE
POWER-DOWN STATUS
Power-down modes 2 or 3 (active if high)
EXPANSION BUS
PD
AB2
Y2
O
XCLKIN
XFCLK
XD31
XD30
XD29
XD28
XD27
XD26
XD25
XD24
XD23
XD22
XD21
XD20
XD19
XD18
XD17
XD16
XD15
XD14
XD13
XD12
XD11
XD10
XD9
A9
C8
I
Expansion bus synchronous host interface clock input
Expansion bus FIFO interface clock output
B9
A8
O
D15
B16
A17
B17
D16
A18
B18
D17
C18
A20
D18
C19
A21
D19
C20
B21
A22
D20
B22
E25
F24
E26
F25
G24
H23
F26
G25
J23
G26
H25
J24
K23
C13
A13
C14
B14
B15
C15
A15
B16
C16
A17
B17
C17
B18
A19
C18
B19
C19
B20
A21
C21
D20
B22
D21
E20
E21
D22
F20
F21
E22
G20
G21
G22
Expansion bus data
•
•
Used for transfer of data, address, and control
Also controls initialization of DSP modes and expansion bus at reset
[Note: For more information on pin control and boot configuration fields, see the Boot Modes
and Configuration chapter of the TMS320C6000 Peripherals Reference Guide (literature
number SPRU190).]
XD[30:16]– XCE[3:0] memory type
I/O/Z
XD13
XD12
XD11
XD10
XD9
–
–
–
–
–
–
–
XBLAST polarity
XW/R polarity
Asynchronous or synchronous host operation
Arbitration mode (internal or external)
FIFO mode
Little endian/big endian
Boot mode
XD8
XD[4:0]
All other expansion bus data pins not listed should be pulled down.
XD8
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GLS/
GNY
TYPE
GNZ
EXPANSION BUS (CONTINUED)
Expansion bus I/O port memory space enables
XCE3
F2
E1
D2
B1
D3
C2
C5
A4
B5
C6
A6
C7
B7
C9
B6
B9
B8
C4
B4
A10
A2
B3
XCE2
•
•
Enabled by bits 28, 29, and 30 of the word address
Only one asserted during any I/O port data access
O/Z
XCE1
F3
XCE0
E2
XBE3/XA5
XBE2/XA4
XBE1/XA3
XBE0/XA2
XOE
C7
D8
A6
Expansion bus multiplexed byte-enable control/address signals
•
•
Act as byte-enable for host-port operation
Act as address for I/O port operation
I/O/Z
C8
A7
O/Z
O/Z
O/Z
I
Expansion bus I/O port output-enable
XRE
C9
D10
A10
D9
B10
D11
A5
Expansion bus I/O port read-enable
XWE/XWAIT
XCS
Expansion bus I/O port write-enable and host-port wait signals
Expansion bus host-port chip-select input
XAS
I/O/Z
I
Expansion bus host-port address strobe
XCNTL
XW/R
Expansion bus host control. XCNTL selects between expansion bus address or data register.
Expansion bus host-port write/read-enable. XW/R polarity is selected at reset.
Expansion bus host-port ready (active low) and I/O port ready (active high)
Expansion bus host-port burst last-polarity selected at reset
Expansion bus back off
I/O/Z
I/O/Z
I/O/Z
I
XRDY
XBLAST
XBOFF
XHOLD
XHOLDA
B6
B11
B5
I/O/Z
I/O/Z
Expansion bus hold request
D7
Expansion bus hold acknowledge
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
CE2
CE1
CE0
BE3
BE2
BE1
BE0
AB25
AA24
AB26
AA25
Y24
Y21
W20
AA22
W21
V20
Memory space enables
•
•
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
O/Z
O/Z
Byte-enable control
W23
AA26
Y25
V21
•
•
•
Decoded from the two lowest bits of the internal address
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
W22
U20
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GNZ
GLS/
GNY
TYPE
EMIF – ADDRESS
EA21
J25
J26
H20
H21
H22
J20
EA20
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
L23
K25
L24
L25
M23
M24
M25
N23
P24
P23
R25
R24
R23
T25
T24
U25
T23
V26
J21
K21
K20
K22
L21
L20
L22
M20
M21
N22
N20
N21
P21
P20
R22
R21
O/Z
External address (word address)
EA8
EA7
EA6
EA5
EA4
EA3
EA2
EMIF – DATA
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
AD8
AC9
Y6
AA6
AB6
Y7
AF7
AD9
AC10
AE9
AA7
AB8
Y8
AF9
AC11
AE10
AD11
AE11
AC12
AD12
AE12
AC13
AD14
AC14
AE15
AA8
AA9
Y9
I/O/Z
External data
AB10
Y10
AA10
AA11
Y11
AB12
Y12
AA12
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
TYPE
DESCRIPTION
GJL/
GLS/
GNY
GNZ
EMIF – DATA (CONTINUED)
ED13
AD15
AC15
AE16
AD16
AE17
AC16
AF18
AE18
AC17
AD18
AF20
AC18
AD19
AF21
AA13
Y13
ED12
ED11
ED10
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
AB13
Y14
AA14
AA15
Y15
I/O/Z
External data
AB15
AA16
Y16
AB17
AA17
Y17
AA18
EMIF – ASYNCHRONOUS MEMORY CONTROL
ARE
V24
V25
U23
W25
T21
R20
T22
T20
O/Z
Asynchronous memory read-enable
Asynchronous memory output-enable
Asynchronous memory write-enable
Asynchronous memory ready input
AOE
AWE
ARDY
O/Z
O/Z
I
EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10
AE21
AE22
AF22
AC20
AA19
AB21
Y19
O/Z
O/Z
O/Z
O/Z
SDRAM address 10 (separate for deactivate command)
SDRAM column-address strobe/SBSRAM address strobe
SDRAM row-address strobe/SBSRAM output-enable
SDRAM write-enable/SBSRAM write-enable
EMIF – BUS ARBITRATION
SDCAS/SSADS
SDRAS/SSOE
SDWE/SSWE
AA20
HOLD
Y26
V23
V22
U21
I
Hold request from the host
HOLDA
O
Hold-request-acknowledge to the host
TIMER 0
TOUT0
TINP0
F1
H4
D1
E2
O
I
Timer 0 or general-purpose output
Timer 0 or general-purpose input
TIMER 1
TOUT1
TINP1
J4
F2
F3
O
I
Timer 1 or general-purpose output
Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
G2
DMAC3
DMAC2
DMAC1
DMAC0
Y3
V3
W2
AA1
W3
AA2
AB1
AA3
O
DMA action complete
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GNZ
GLS/
GNY
TYPE
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
M4
M2
M3
R2
P4
N3
N4
K3
L2
I
External clock source (as opposed to internal)
Receive clock
CLKR0
CLKX0
DR0
I/O/Z
I/O/Z
I
K1
M2
M3
M1
L3
Transmit clock
Receive data
DX0
O/Z
I/O/Z
I/O/Z
Transmit data
FSR0
FSX0
Receive frame sync
Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
CLKR1
CLKX1
DR1
G1
J3
H2
L4
J1
J2
K4
E1
G2
G3
H1
H2
H3
G1
I
External clock source (as opposed to internal)
Receive clock
I/O/Z
I/O/Z
I
Transmit clock
Receive data
DX1
O/Z
I/O/Z
I/O/Z
Transmit data
FSR1
FSX1
Receive frame sync
Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
CLKS2
CLKR2
CLKX2
DR2
R3
T2
R4
V1
T4
U2
T3
N1
N2
N3
R2
R1
P3
P2
I
External clock source (as opposed to internal)
Receive clock
I/O/Z
I/O/Z
I
Transmit clock
Receive data
DX2
O/Z
I/O/Z
I/O/Z
Transmit data
FSR2
FSX2
Receive frame sync
Transmit frame sync
RESERVED FOR TEST
RSV0
RSV1
RSV2
RSV3
RSV4
L3
J2
I
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
G3
E3
A12
C15
D12
B11
B13
C10
I
O
O
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GLS/
GNY
TYPE
GNZ
SUPPLY VOLTAGE PINS
A11
A16
B7
A3
A7
A16
A20
D4
B8
B19
B20
C6
D6
D7
C10
C14
C17
C21
G4
D9
D10
D13
D14
D16
D17
D19
F1
G23
H3
H24
K3
F4
K24
L1
F19
F22
G4
L26
N24
P3
G19
J4
DV
S
3.3-V supply voltage (I/O)
DD
T1
J19
K4
T26
U3
K19
L1
U24
W3
M22
N4
W24
Y4
N19
P4
Y23
AD6
AD10
AD13
AD17
AD21
AE7
AE8
AE19
AE20
AF11
P19
T4
T19
U1
U4
U19
U22
W4
W6
W7
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GNZ
GLS/
GNY
TYPE
SUPPLY VOLTAGE PINS (CONTINUED)
AF16
–
W9
W10
W13
W14
W16
W17
W19
AB5
AB9
AB14
AB18
E7
–
–
–
–
DV
S
3.3-V supply voltage (I/O)
DD
–
–
–
–
–
A1
A2
A3
A24
A25
A26
B1
B2
B3
B24
B25
B26
C1
C2
C3
C4
C23
C24
C25
C26
D3
D4
D5
D22
D23
D24
E4
E23
AB4
E8
E10
E11
E12
E13
E15
E16
F7
F8
F9
F11
F12
F14
F15
F16
G5
1.5-V supply voltage (core) (C6202B only)
1.8-V supply voltage (core) (C6202 only)
CV
S
DD
G6
G17
G18
H5
H6
H17
H18
J6
J17
K5
K18
L5
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GLS/
GNY
TYPE
GNZ
SUPPLY VOLTAGE PINS (CONTINUED)
AB23
AC3
AC4
AC5
AC22
AC23
AC24
AD1
AD2
AD3
AD4
AD23
AD24
AD25
AD26
AE1
AE2
AE3
AE24
AE25
AE26
AF1
AF2
AF3
AF24
AF25
AF26
–
L6
L17
L18
M5
M6
M17
M18
N5
N18
P6
P17
R5
R6
R17
R18
T5
T6
1.5-V supply voltage (core) (C6202B only)
1.8-V supply voltage (core) (C6202 only)
T17
T18
U7
CV
S
DD
U8
U9
U11
U12
U14
U15
U16
V7
–
V8
–
V10
V11
V12
V13
V15
V16
–
–
–
–
–
GROUND PINS
A4
A8
A1
A5
V
SS
GND
Ground pins
A13
A14
A12
A18
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GNZ
GLS/
GNY
TYPE
GROUND PINS (CONTINUED)
A15
A19
A23
B4
A22
B2
B21
C1
B12
B13
B14
B23
C5
C3
C20
C22
D5
D8
‡
C11
D11
D12
D15
D18
E4
C16
C22
D1
D2
D6
E5
D21
D25
D26
E3
E6
E9
E14
E17
E18
E19
F5
V
SS
GND
Ground pins
E24
F4
F23
H1
F6
H26
K1
F10
F13
F17
F18
H4
K26
M1
M26
N1
H19
J1
N2
N25
N26
P1
J5
J18
J22
K6
P2
P25
P26
K17
L4
†
‡
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
For the C6202 GJL package only, the C11 pin is ground (V ). For all C62x GNZ packages, the C11 pin is CLKMODE1.
SS
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
TYPE
DESCRIPTION
GJL/
GLS/
GNY
GNZ
GROUND PINS (CONTINUED)
R1
R26
U1
L19
M4
M19
N6
U26
W1
N17
P1
W26
AA4
AA23
AB3
AB24
AC1
AC2
AC6
AC21
AC25
AC26
AD5
AD22
AE4
AE13
AE14
AE23
AF4
AF8
AF10
AF12
AF13
AF14
AF15
AF17
AF19
AF23
–
P5
P18
P22
R4
R19
U5
U6
U10
U13
U17
U18
V4
V5
V
SS
GND
Ground pins
V6
V9
V14
V17
V18
V19
W5
W8
W11
W12
W15
W18
Y1
Y3
–
Y20
Y22
AA2
AA21
–
–
–
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME
†
DESCRIPTION
GJL/
GNZ
GLS/
GNY
TYPE
GROUND PINS (CONTINUED)
–
–
–
–
–
–
–
AB1
AB3
AB7
AB11
AB16
AB20
AB22
V
SS
GND
Ground pins
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS ), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS ) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GLS), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -250 is 250 MHz).
Table 15 lists the device orderable part numbers (P/Ns) and Figure 4 provides a legend for reading the complete
device name for any member of the TMS320C6000 DSP platform. For more information on the C6202/02B
device orderable P/Ns, visit the Texas Instruments web site on the Worldwide web at http://www.ti.com URL,
or contact the nearest TI field sales office or authorized distributor.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
device and development-support tool nomenclature (continued)
Table 15. TMS320C6202/02B Device Part Numbers (P/Ns) and Ordering Information
OPERATING CASE
TEMPERATURE
RANGE
CV
DV
DD
DD
DEVICE ORDERABLE P/N
DEVICE SPEED
(CORE VOLTAGE)
(I/O VOLTAGE)
C6202
TMS320C6202GJL200
TMS320C6202GJL250
TMS320C6202GJLA200
TMS320C6202GLS200
TMS320C6202GLS250
C6202B
200 MHz/1600 MIPS
250 MHz/2000 MIPS
200 MHz/1600 MIPS
200 MHz/1600 MIPS
250 MHz/2000 MIPS
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0_C to 90_C
0_C to 90_C
–40_C to105_C
0_C to 90_C
0_C to 90_C
TMS320C6202BGNY250
TMS320C6202BGNY300
TMS320C6202BGNZ250
TMS320C6202BGNZ300
TMS32C6202BGNZA250
250 MHz/2000 MIPS
300 MHz/2400 MIPS
250 MHz/2000 MIPS
300 MHz/2400 MIPS
250 MHz/2000 MIPS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0_C to 90_C
0_C to 90_C
0_C to 90_C
0_C to 90_C
–40_C to 105_C
(
)
TMS 320
C
6202 GLS
–250
PREFIX
DEVICE SPEED RANGE
TMX= Experimental device
TMP= Prototype device
100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
500 MHz
600 MHz
TMS= Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
= –40°C to 105°C, extended temperature
DEVICE FAMILY
320 = TMS320t DSP family
†
PACKAGE TYPE
GFN = 256-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GNY = 384-pin plastic BGA
GNZ = 352-pin plastic BGA
GHK = 288-pin plastic MicroStar BGAt
TECHNOLOGY
C
=
CMOS
DEVICE
C6000 DSP:
6201
6205
6211
6211B
6411
6414
6415
6416
6701
6711
6711B
6711C
6712
6712C
6713
6202
6202B
6203B
6204
†
BGA
=
Ball Grid Array
Figure 4. TMS320C6000 DSP Platform Device Nomenclature (Including TMS320C6202 and C6202B)
MicroStar BGA is a trademark of Texas Instruments.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
documentation support
Extensive documentation supports all TMS320 DSP family devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices and tools; technical briefs;
development-support tools; on-line help; and hardware and software applications. The following is a brief,
descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory
interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct
memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XBus), peripheral
component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also
includes information on internal data and program memories.
The How to Begin Development Today and Migrate Across the TMS320C6202/02B/03B/04 DSPs application
report (literature number SPRA603) describes the migration concerns and identifies the similarities and
differences between the C6202, C6202B, C6203B, and C6204 C6000 DSP devices.
The TMS320C6202 Digital Signal Processor Silicon Errata (literature number SPRZ152) describes the known
exceptions to the functional specifications for particular silicon revisions of the TMS320C6202 device . There
are currently no known silicon advisories on the TMS320C6202B device.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio IDE. For a
complete listing of the latest C6000 DSP documentation, visit the Texas Instruments web site on the
Worldwide Web at http://www.ti.com uniform resource locator (URL).
37
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
clock PLL
All of the internal C6202/02B clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
and Table 16 through Table 19 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply
modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6202/02B device and the
external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN
rise and fall times should also be observed. For the input clock timing requirements, see the Input and Output
Clocks electricals section.
3.3V
PLLV
Internal to
PLL
CLKMODE0
CLKMODE1
CLKMODE2
C6202/02B
†
†
PLLMULT
CLKIN
C4
C3
PLLCLK
0.1 mF
10 mF
CLKIN
1
0
CPU
CLOCK
LOOP FILTER
(For the PLL Options
and CLKMODE pins setup,
C2
see Table 16 through Table 19)
C1
R1
† CLKMODE1 and CLKMODE2 pins are not applicable (N/A) to the C6202 GJL package. The CLKMODE2 pin is also N/A on the C6202B GNZ package.
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
.
DD
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
3.3V
PLLV
Internal to
C6202/02B
CLKMODE0
†
PLL
CLKMODE1
CLKMODE2
PLLMULT
CLKIN
†
PLLCLK
CLKIN
1
0
LOOP FILTER
CPU
CLOCK
† CLKMODE1 and CLKMODE2 pins are not applicable (N/A) to the C6202 GJL package. The CLKMODE2 pin is also N/A on the C6202B GNZ package.
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
38
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SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
clock PLL (continued)
†
Table 16. TMS320C6202 GLS and C6202B GNY Packages PLL Multiply and Bypass (x1) Options
GLS PACKAGE – 18 x 18 mm BGA [C6202 only] and
GNY PACKAGE – 18 x 18 mm BGA [C6202B only]
DEVICES AND PLL CLOCK OPTIONS
BIT (PIN NO.)
CLKMODE2 (A14)
CLKMODE1 (A9)
CLKMODE0 (B12)
‡
C6202 (GLS)
Bypass (x1)
x4
C6202B (GNY)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bypass (x1)
x4
x8
Bypass (x1)
x4
x10
x6
Value
Bypass (x1)
x4
x9
Bypass (x1)
x4
x7
x11
†
‡
f(CPU Clock) = f(CLKIN) x (PLL mode)
For the C6202 GLS package, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.
†
Table 17. TMS320C6202 GJL and TMS320C6202B GNZ Packages PLL Multiply and Bypass (x1) Options
GJL PACKAGE 27 x 27 mm BGA [C6202 only] and
GNZ PACKAGE – 27 x 27 mm BGA [C6202B only]
DEVICES AND PLL CLOCK OPTIONS
§
§
BIT (PIN NO.)
CLKMODE2 (N/A)
CLKMODE1 (C11)
CLKMODE0 (B15)
§
§
C6202 (GJL)
Bypass (x1)
x4
C6202B (GNZ)
0
0
1
1
0
1
0
1
Bypass (x1)
x4
x8
Value
N/A
N/A
x10
†
§
f(CPU Clock) = f(CLKIN) x (PLL mode)
CLKMODE2 and CLKMODE1 pins are not available on the C6202 GJL package.
The CLKMODE2 pin is not available (N/A) on the C6202B GNZ package.
39
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
clock PLL (continued)
†
Table 18. TMS320C6202 PLL Component Selection Table
CPU CLOCK
CLKOUT2
CLKIN
RANGE
(MHz)
TYPICAL
LOCK TIME
(µs)
FREQUENCY
CLKMODE
RANGE
(MHz)
R1 [±1%]
60.4 Ω
C1 [±10%]
C2 [±10%]
(CLKOUT1)
RANGE (MHz)
x4
32.5–62.5
130–250
65–125
27 nF
560 pF
75
†
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
†
Table 19. TMS320C6202B PLL Component Selection Table
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
TYPICAL
LOCK TIME
(µs)
‡
CLKMODE
R1 [±1%]
C1 [±10%]
C2 [±10%]
x4
x6
32.5–75
21.7–50
x7
18.6–42.9
16.3–37.5
14.4–33.3
13–30
x8
130–300
65–150
45.3 Ω
47 nF
10 pF
75
x9
x10
x11
11.8–27.3
†
‡
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the C6202B GNY devices. The C6202B GNZ device is restricted to x1, x4, x8, and x10
multiply factors.
40
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SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 7).
I/O Supply
DV
CV
DD
Schottky
Diode
C6000
DSP
Core Supply
DD
V
SS
GND
Figure 7. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
On systems using C62x and C67x DSPs, the core may consume in excess of 2 A per DSP until the I/O supply
powers on. This extra current results from uninitialized logic within the DSP(s). A normal current state returns
once the I/O power supply turns on and the CPU sees a clock pulse. Decreasing the amount of time between
the core supply power-up and the I/O supply power-up reduces the effects of the current draw. If the external
supply to the DSP core cannot supply the excess current, the minimum core voltage may not be achieved until
after normal current returns. This voltage starvation of the core supply during power up will not affect run-time
operation. Voltage starvation can affect power supply systems that gate the I/O supply via the core supply,
causing the I/O supply to never turn on. During the transition from excess to normal current, a voltage spike may
be seen on the core supply. Care must be taken when designing overvoltage protection circuitry on the core
supply to not restart the power sequence due to this spike. Otherwise, the supply may cycle indefinitely.
41
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
IEEE 1149.1 JTAG compatibility statement
For compatibility with IEEE 1149.1 JTAG programmers, the TRST pin may need to be externally pulled up via
a 1-kΩ resistor. For these C62x devices, this pin is internally pulled down, holding the JTAG port in reset by
default. This is typically only a problem in systems where the DSP shares a scan chain with some other device.
Some JTAG programmers for these other devices do not actively drive TRST high, leaving the scan chain
inoperable while the C62x JTAG port is held in reset. TI emulators do drive TRST high, so the external pullup
resistor is not needed in systems where TI emulators are the only devices that control JTAG scan chains on
which the DSP(s) reside. If the system has other devices in the same scan chain as the DSP, and the
programmer for these devices does not drive TRST high, then an external 1-kΩ pullup resistor is required.
With this external 1-kΩ pullup resistor installed, care must be taken to keep the DSP in a usable state under
all circumstances. When TRST is pulled up, the JTAG driver must maintain the TMS signal high for 5 TCLK
cycles, forcing the DSP(s) into the test logic reset (TLR) state. From the TLR state, the DSP’s data scan path
can be put in bypass (scan all 1s into the IR) to scan the other devices. The TLR state also allows normal
operation of the DSP. If operation without anything driving the JTAG port is desired, the pullup resistor should
be jumpered so that it may be engaged for programming the other devices and disconneted for running without
a JTAG programmer or emulator.
42
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
†
absolute maximum ratings over operating case temperature ranges (unless otherwise noted)
Supply voltage range, CV
Supply voltage range, DV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
DD
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Operating case temperature ranges, T :(default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
C
(A version): C6202BGNZA-250 . . . . . . . . . . . . . . . –40_C to105_C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C
stg
Temperature cycle range, (1000-cycle performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 125_C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
MIN NOM
MAX UNIT
CV
CV
DV
Supply voltage, Core
Supply voltage, Core
Supply voltage, I/O
C6202B only
C6202 only
1.43
1.71
3.14
0
1.5
1.8
3.3
0
1.57
1.89
3.46
0
V
V
DD
DD
DD
V
V
V
V
Supply ground
V
SS
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
2
V
IH
IL
0.8
–8
8
V
I
mA
mA
_C
_C
OH
OL
I
Default
0
90
105
T
C
Operating case temperature
A version: C6202BGNZA-250
–40
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
DV
DV
= MIN,
= MIN,
I
I
= MAX
= MAX
2.4
OH
DD
DD
OH
0.6
±10
±10
V
OL
OL
‡
I
I
Input current
V = V
I SS
to DV
DD
uA
uA
mA
mA
mA
mA
mA
mA
pF
I
Off-state output current
V
= DV
or 0 V
= NOM, CPU clock = 200 MHz
= NOM, CPU clock = 200 MHz
= NOM, CPU clock = 200 MHz
OZ
O DD
C6202, CV
DD
520
340
390
235
70
Supply current, CPU + CPU memory
I
I
I
DD2V
§
access
C6202B, CV
DD
C6202, CV
DD
§
Supply current, peripherals
DD2V
DD3V
C6202B, CV
= NOM, CPU clock = 200 MHz
= NOM, CPU clock = 200 MHz
DD
C6202, DV
DD
§
Supply current, I/O pins
C6202B, DV
DD
= NOM, CPU clock = 200 MHz
45
C
C
Input capacitance
Output capacitance
10
10
i
pF
o
‡
§
TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power
Consumption Summary application report (literature number SPRA486).
43
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
comm
†
C
T
I
OH
Where:
I
I
V
=
=
=
=
2 mA
2 mA
1.5 V
OL
OH
comm
T
C
15-pF typical load-circuit capacitance
†
Typical distributed load circuit capacitance
Figure 8. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 9. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, and
IL
IH
V
MAX and V
MIN for output clocks.
OL
OH
V
ref
= V MIN (or V
IH OH
MIN)
V
ref
= V MAX (or V
IL OL
MAX)
Figure 10. Rise and Fall Transition Time Voltage Reference Levels
44
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 20 and Figure 11).
Figure 11 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 20. Board-Level TImings Example (see Figure 11)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
CLKOUT2
(Output from DSP)
1
CLKOUT2
(Input to External Device)
2
3
†
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
‡
Data Signals
(Output from External Device)
9
10
11
‡
Data Signals
(Input to DSP)
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 11. Board-Level Input/Output Timings
45
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
INPUT AND OUTPUT CLOCKS
†‡§
timing requirements for CLKIN (PLL used)
(see Figure 12)
C6202-250
C6202B-250
C6202-200
C6202B-300
NO.
UNIT
MIN
5 * M
0.4C
0.4C
MAX
MIN
4 * M
0.4C
0.4C
MAX
MIN
3.33 * M
0.4C
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
0.4C
5
5
5
†
‡
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL IH
M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11) for C6202 GLS and C6202B GNY only.
M = the PLL multiplier factor (x4, x6, x8, or x10) for C6202B GNZ only.
For more details, see the Clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
§
†¶
timing requirements for CLKIN [PLL bypassed (x1)] (see Figure 12)
C6202-250
C6202B-250
C6202-200
C6202B-300
NO.
UNIT
MIN
5
MAX
MIN
4
MAX
MIN
3.33
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
0.45C
0.45C
0.45C
0.45C
0.45C
0.45C
0.6
0.6
0.6
†
¶
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL IH
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. The maximum CLKIN cycle time is PLL bypass mode
(x1) is 200 MHz.
1
4
2
CLKIN
3
4
Figure 12. CLKIN Timings
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
INPUT AND OUTPUT CLOCKS (CONTINUED)
†
timing requirements for XCLKIN (see Figure 13)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN MAX
4P
1
2
3
t
t
t
Cycle time, XCLKIN
ns
ns
ns
c(XCLKIN)
Pulse duration, XCLKIN high
Pulse duration, XCLKIN low
1.8P
w(XCLKINH)
w(XCLKINL)
1.8P
†
P = 1/CPU clock frequency in nanoseconds (ns).
1
2
XCLKIN
3
Figure 13. XCLKIN Timings
‡§
switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 14)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
t
t
t
Cycle time, CLKOUT2
2P – 0.7
P – 0.7
P – 0.7
2P + 0.7
P + 0.7
P + 0.7
ns
ns
ns
c(CKO2)
Pulse duration, CLKOUT2 high
Pulse duration, CLKOUT2 low
w(CKO2H)
w(CKO2L)
‡
§
P = 1/CPU clock frequency in ns.
The reference points for the rise and fall transitions are measured at V
MAX and V
MIN.
OL
OH
1
2
CLKOUT2
3
Figure 14. CLKOUT2 Timings
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡
switching characteristics over recommended operating conditions for XFCLK (see Figure 15)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
D * P – 0.7
MAX
1
2
3
t
t
t
Cycle time, XFCLK
D * P + 0.7
ns
ns
ns
c(XFCK)
Pulse duration, XFCLK high
Pulse duration, XFCLK low
(D/2) * P – 0.7 (D/2) * P + 0.7
(D/2) * P – 0.7 (D/2) * P + 0.7
w(XFCKH)
w(XFCKL)
†
‡
P = 1/CPU clock frequency in ns.
D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable
1
2
XFCLK
3
Figure 15. XFCLK Timings
48
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
ASYNCHRONOUS MEMORY TIMING
†‡§¶
timing requirements for asynchronous memory cycles
(see Figure 16 – Figure 19)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, EDx valid before
ARE high
3
4
6
7
t
t
t
t
1
1
ns
ns
ns
ns
su(EDV-AREH)
Hold time, EDx valid after
ARE high
3.5
–[(RST – 3) * P – 6]
(RST – 3) * P + 2
4.9
–[(RST – 3) * P – 6]
(RST – 3) * P + 2
h(AREH-EDV)
Setup time, ARDY high before
ARE low
su(ARDYH-AREL)
h(AREL-ARDYH)
Hold time, ARDY high after
ARE low
Setup time, ARDY low before
ARE low
9
t
–[(RST – 3) * P – 6]
–[(RST – 3) * P – 6]
ns
su(ARDYL-AREL)
Hold time, ARDY low after
ARE low
10
11
15
t
t
t
(RST – 3) * P + 2
2P
(RST – 3) * P + 2
2P
ns
ns
ns
h(AREL-ARDYL)
Pulse width, ARDY high
w(ARDYH)
Setup time, ARDY high before
AWE low
–[(WST – 3) * P – 6]
–[(WST – 3) * P – 6]
su(ARDYH-AWEL)
Hold time, ARDY high after
AWE low
16
t
(WST – 3) * P + 2
(WST – 3) * P + 2
ns
h(AWEL-ARDYH)
Setup time, ARDY low before
AWE low
18
19
t
–[(WST – 3) * P – 6]
(WST – 3) * P + 2
–[(WST – 3) * P – 6]
(WST – 3) * P + 2
ns
ns
su(ARDYL-AWEL)
h(AWEL-ARDYL)
Hold time, ARDY low after
AWE low
t
†
‡
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
§
¶
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
switching characteristics over recommended operating conditions for asynchronous memory
†‡§¶
cycles
(see Figure 16 – Figure 19)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Output setup time, select
signals valid to ARE low
1
t
RS * P – 2
RH * P – 2
RS * P – 2
RH * P – 2
ns
osu(SELV-AREL)
Output hold time, ARE high to
select signals invalid
2
5
8
t
t
t
ns
ns
ns
oh(AREH-SELIV)
Pulse width, ARE low
RST * P
RST * P
w(AREL)
Delay time, ARDY high to
ARE high
3P
WS * P – 3
WH * P – 2
4P + 5
3P
WS * P – 2
WH * P – 2
4P + 5
d(ARDYH-AREH)
Output setup time, select
signals valid to AWE low
12
t
ns
osu(SELV-AWEL)
Output hold time, AWE high
to select signals invalid
13
14
t
t
ns
ns
oh(AWEH-SELIV)
Pulse width, AWE low
WST * P
WST * P
w(AWEL)
Delay time, ARDY high to
AWE high
17
t
3P
4P + 5
3P
4P + 5
ns
d(ARDYH-AWEH)
†
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
‡
§
¶
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
50
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CLKOUT1
CEx
1
2
1
1
2
2
BE[3:0]
EA[21:2]
3
4
ED[31:0]
AOE
1
2
5
6
7
ARE
AWE
ARDY
Figure 16. Asynchronous Memory Read Timing (ARDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
CEx
1
1
1
2
2
2
BE[3:0]
EA[21:2]
3
4
ED[31:0]
AOE
1
9
2
8
10
ARE
AWE
11
ARDY
Figure 17. Asynchronous Memory Read Timing (ARDY Used)
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CLKOUT1
CEx
12
12
12
12
13
13
13
13
BE[3:0]
EA[21:2]
ED[31:0]
AOE
15
16
ARE
14
AWE
ARDY
Figure 18. Asynchronous Memory Write Timing (ARDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
12
12
12
12
13
13
13
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
17
18
19
AWE
11
ARDY
Figure 19. Asynchronous Memory Write Timing (ARDY Used)
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles for C6202 devices (see Figure 20)
C6202-200
C6202-250
NO.
UNIT
MIN
2.5
MAX
MIN
2.0
MAX
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
ns
ns
su(EDV-CKO2H)
2.0
2.0
h(CKO2H-EDV)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
†‡
cycles for C6202 devices (see Figure 20 and Figure 21)
C6202-200
C6202-250
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
P – 0.8
P – 4
P – 0.8
P – 3
ns
ns
ns
ns
ns
ns
osu(CEV-CKO2H)
oh(CKO2H-CEV)
osu(BEV-CKO2H)
oh(CKO2H-BEIV)
osu(EAV-CKO2H)
oh(CKO2H-EAIV)
P – 0.8
P – 4
P – 0.8
P – 3
P – 0.8
P – 4
P – 0.8
P – 3
Output setup time, SDCAS/SSADS valid before
CLKOUT2 high
9
t
t
t
t
P – 0.8
P – 4
P – 0.8
P – 3
ns
ns
ns
ns
osu(ADSV-CKO2H)
oh(CKO2H-ADSV)
osu(OEV-CKO2H)
oh(CKO2H-OEV)
Output hold time, SDCAS/SSADS valid after CLKOUT2
high
10
11
12
Output setup time, SDRAS/SSOE valid before
CLKOUT2 high
P – 0.8
P – 4
P – 0.8
P – 3
Output hold time, SDRAS/SSOE valid after CLKOUT2
high
§
13
14
t
t
Output setup time, EDx valid before CLKOUT2 high
P – 1.2
P – 4
P – 1.2
P – 3
ns
ns
osu(EDV-CKO2H)
Output hold time, EDx invalid after CLKOUT2 high
oh(CKO2H-EDIV)
Output setup time, SDWE/SSWE valid before CLKOUT2
high
15
16
t
P – 0.8
P – 4
P – 0.8
P – 3
ns
ns
osu(WEV-CKO2H)
Output hold time, SDWE/SSWE valid after CLKOUT2
high
t
oh(CKO2H-WEV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
53
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles C6202B devices (see Figure 20)
C6202B-250
C6202B-300
NO.
UNIT
MIN
2.9
MAX
MIN
1.6
MAX
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
ns
ns
su(EDV-CKO2H)
2.1
2.3
h(CKO2H-EDV)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
†‡
cycles for C6202B devices (see Figure 20 and Figure 21)
C6202B-250
C6202B-300
MIN MAX
P – 1
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
P – 1.7
P – 3.4
P – 1.7
P – 3.4
P – 1.7
P – 3.4
ns
ns
ns
ns
ns
ns
osu(CEV-CKO2H)
oh(CKO2H-CEV)
osu(BEV-CKO2H)
oh(CKO2H-BEIV)
osu(EAV-CKO2H)
oh(CKO2H-EAIV)
P – 2.7
P – 1
P – 2.7
P – 1
P – 2.7
Output setup time, SDCAS/SSADS valid before
CLKOUT2 high
9
t
t
t
t
P – 1.7
P – 3.4
P – 1.7
P – 3.4
P – 1
P – 2.7
P – 1
ns
ns
ns
ns
osu(ADSV-CKO2H)
oh(CKO2H-ADSV)
osu(OEV-CKO2H)
oh(CKO2H-OEV)
Output hold time, SDCAS/SSADS valid after CLKOUT2
high
10
11
12
Output setup time, SDRAS/SSOE valid before
CLKOUT2 high
Output hold time, SDRAS/SSOE valid after CLKOUT2
high
P – 2.7
§
13
14
t
t
Output setup time, EDx valid before CLKOUT2 high
P – 2.3
P – 3.2
P – 1.6
P – 2.5
ns
ns
osu(EDV-CKO2H)
Output hold time, EDx invalid after CLKOUT2 high
oh(CKO2H-EDIV)
Output setup time, SDWE/SSWE valid before CLKOUT2
high
15
16
t
P – 1.7
P – 3.4
P – 1
ns
ns
osu(WEV-CKO2H)
Output hold time, SDWE/SSWE valid after CLKOUT2
high
t
P – 2.7
oh(CKO2H-WEV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2
1
2
CEx
3
4
6
BE[3:0]
BE1
BE2
A2
BE3
A3
BE4
5
A1
A4
8
EA[21:2]
ED[31:0]
7
Q1
Q2
Q3
10
Q4
9
†
SDCAS/SSADS
11
12
†
†
SDRAS/SSOE
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 20. SBSRAM Read Timing
CLKOUT2
1
2
CEx
BE[3:0]
3
4
6
BE1
BE2
A2
BE3
A3
BE4
A4
5
EA[21:2]
A1
13
14
10
Q1
Q2
Q3
Q4
ED[31:0]
9
†
SDCAS/SSADS
†
SDRAS/SSOE
SDWE/SSWE
15
16
†
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 21. SBSRAM Write Timing
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles for C6202 devices (see Figure 22)
C6202-200
C6202-250
MIN MAX
1.2
NO.
UNIT
MIN MAX
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
1.2
3
ns
ns
su(EDV-CKO2H)
2.7
h(CKO2H-EDV)
switching characteristics over recommended operating conditions for synchronous DRAM cycles
†‡
for C6202 devices (see Figure 22–Figure 27)
C6202-200
MIN MAX
P – 1
C6202-250
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
P – 0.9
P – 2.9
P – 0.9
P – 2.9
P – 0.9
P – 2.9
ns
ns
ns
ns
ns
ns
osu(CEV-CKO2H)
oh(CKO2H-CEV)
osu(BEV-CKO2H)
oh(CKO2H-BEIV)
osu(EAV-CKO2H)
oh(CKO2H-EAIV)
P – 3.5
P – 1
P – 3.5
P – 1
P – 3.5
Output setup time, SDCAS/SSADS valid before
CLKOUT2 high
9
t
t
P – 1
P – 0.9
P – 2.9
ns
ns
osu(CASV-CKO2H)
oh(CKO2H-CASV)
Output hold time, SDCAS/SSADS valid after
CLKOUT2 high
10
P – 3.5
§
11
12
t
t
Output setup time, EDx valid before CLKOUT2 high
P – 1
P – 1.5
P – 2.8
ns
ns
osu(EDV-CKO2H)
Output hold time, EDx invalid after CLKOUT2 high
P – 3.5
oh(CKO2H-EDIV)
Output setup time, SDWE/SSWE valid before
CLKOUT2 high
13
14
t
P – 1
P – 0.9
P – 2.9
ns
ns
osu(WEV-CKO2H)
oh(CKO2H-WEV)
Output hold time, SDWE/SSWE valid after CLKOUT2
high
t
P – 3.5
Output setup time, SDA10 valid before CLKOUT2
high
15
16
17
t
t
t
P – 1
P – 3.5
P – 1
P – 0.9
P – 2.9
P – 0.9
ns
ns
ns
osu(SDA10V-CKO2H)
oh(CKO2H-SDA10IV)
osu(RASV-CKO2H)
Output hold time, SDA10 invalid after CLKOUT2 high
Output setup time, SDRAS/SSOE valid before
CLKOUT2 high
Output hold time, SDRAS/SSOE valid after CLKOUT2
high
18
t
P – 3.5
P – 2.9
ns
oh(CKO2H-RASV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS DRAM TIMING (CONTINUED)
timing requirements for synchronous DRAM cycles for C6202B devices (see Figure 22)
C6202B-250
MIN MAX
1.3
C6202B-300
NO.
UNIT
MIN MAX
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
0
ns
ns
su(EDV-CKO2H)
2.3
2.3
h(CKO2H-EDV)
switching characteristics over recommended operating conditions for synchronous DRAM cycles
†‡
for C6202B devices (see Figure 22–Figure 27)
C6202B-250
C6202B-300
MIN MAX
P – 1
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
P – 1.7
P – 3
ns
ns
ns
ns
ns
ns
osu(CEV-CKO2H)
oh(CKO2H-CEV)
osu(BEV-CKO2H)
oh(CKO2H-BEIV)
osu(EAV-CKO2H)
oh(CKO2H-EAIV)
P – 2.3
P – 1
P – 1.7
P – 3
P – 2.3
P – 1
P – 1.7
P – 3
P – 2.3
Output setup time, SDCAS/SSADS valid before
CLKOUT2 high
9
t
t
P – 1.7
P – 3
P – 1
ns
ns
osu(CASV-CKO2H)
oh(CKO2H-CASV)
Output hold time, SDCAS/SSADS valid after
CLKOUT2 high
10
P – 2.3
§
11
12
t
t
Output setup time, EDx valid before CLKOUT2 high
P – 2.3
P – 2.7
P – 1.6
P – 2
ns
ns
osu(EDV-CKO2H)
Output hold time, EDx invalid after CLKOUT2 high
oh(CKO2H-EDIV)
Output setup time, SDWE/SSWE valid before
CLKOUT2 high
13
14
t
t
P – 1.7
P – 3
P – 1
ns
ns
osu(WEV-CKO2H)
Output hold time, SDWE/SSWE valid after CLKOUT2
high
P – 2.3
oh(CKO2H-WEV)
Output setup time, SDA10 valid before CLKOUT2
high
15
16
17
t
t
t
P – 1.7
P – 3
P – 1
P – 2.3
P – 1
ns
ns
ns
osu(SDA10V-CKO2H)
oh(CKO2H-SDA10IV)
osu(RASV-CKO2H)
Output hold time, SDA10 invalid after CLKOUT2 high
Output setup time, SDRAS/SSOE valid before
CLKOUT2 high
P – 1.7
Output hold time, SDRAS/SSOE valid after CLKOUT2
high
18
t
P – 3
P – 2.3
ns
oh(CKO2H-RASV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
CLKOUT2
CEx
1
5
2
3
4
BE[3:0]
EA[15:2]
BE1
BE2
CA3
BE3
7
6
CA1
CA2
8
D1
D2
D3
ED[31:0]
SDA10
15
9
16
10
†
SDRAS/SSOE
†
†
SDCAS/SSADS
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 22. Three SDRAM READ Commands
WRITE
WRITE
WRITE
CLKOUT2
CEx
1
3
5
2
4
6
BE[3:0]
BE1
CA1
BE2
CA2
D2
BE3
CA3
D3
EA[15:2]
11
12
D1
ED[31:0]
SDA10
15
16
†
SDRAS/SSOE
9
10
14
†
SDCAS/SSADS
13
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 23. Three SDRAM WRT Commands
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
CLKOUT2
1
2
CEx
BE[3:0]
5
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
†
†
†
SDRAS/SSOE
SDCAS/SSADS
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 24. SDRAM ACTV Command
DCAB
CLKOUT2
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
15
16
SDA10
17
18
†
†
SDRAS/SSOE
SDCAS/SSADS
13
14
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 25. SDRAM DCAB Command
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
CLKOUT2
CEx
1
2
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
17
18
†
SDRAS/SSOE
9
10
†
SDCAS/SSADS
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 26. SDRAM REFR Command
MRS
CLKOUT2
1
2
6
CEx
BE[3:0]
5
EA[15:2]
ED[31:0]
SDA10
MRS Value
17
18
10
14
†
SDRAS/SSOE
9
†
†
SDCAS/SSADS
13
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 27. SDRAM MRS Command
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
HOLD/HOLDA TIMING
†
timing requirements for the HOLD/HOLDA cycles (see Figure 28)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN MAX
3
t
Output hold time, HOLD low after HOLDA low
P
ns
oh(HOLDAL-HOLDL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
†‡
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 28)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
3P
0
MAX
§
1
2
4
5
t
t
t
t
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
ns
ns
ns
ns
d(HOLDL-EMHZ)
d(EMHZ-HOLDAL)
d(HOLDH-EMLZ)
d(EMLZ-HOLDAH)
2P
7P
2P
3P
0
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
1
4
†
EMIF Bus
C6202/02B
C6202/02B
†
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 28. HOLD/HOLDA Timing
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
RESET TIMING
†
timing requirements for reset (see Figure 29)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
10P
250
5P
MAX
‡
Width of the RESET pulse (PLL stable)
ns
µs
ns
ns
1
t
w(RST)
§
Width of the RESET pulse (PLL needs to sync up)
¶
Setup time, XD configuration bits valid before RESET high
10
11
t
t
su(XD)
¶
Hold time, XD configuration bits valid after RESET high
5P
h(XD)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 only when CLKIN and PLL are stable for C6202.
This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL are stable for C6202B GNY devices.
This parameter applies to CLKMODE x4, x6, x8, and x10 only when CLKIN and PLL are stable for C6202B GNZ devices.
This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1) for C6202. This parameter applies to CLKMODE x4, x6, x7,
x8, x9, x10, and x11 only (it does not apply to CLKMODE x1) for C6202B GNY devices. This parameter applies to CLKMODE x4, x6, x8, and
x10 only (it does not apply to CLKMODE x1) for C6202B GNZ devices. The RESET signal is not connected internally to the clock PLL circuit.
The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time,
RESET must be asserted to ensure proper device operation. See the Clock PLL section for PLL lock times.
§
¶
XD[31:0] are the boot configuration pins during device reset.
†#
switching characteristics over recommended operating conditions during reset (see Figure 29)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
2
3
4
5
6
7
8
9
t
t
t
t
t
t
t
t
Delay time, RESET low to CLKOUT2 invalid
Delay time, RESET high to CLKOUT2 valid
Delay time, RESET low to high group invalid
Delay time, RESET high to high group valid
Delay time, RESET low to low group invalid
Delay time, RESET high to low group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
P
ns
ns
ns
ns
ns
ns
ns
ns
d(RSTL-CKO2IV)
d(RSTH-CKO2V)
d(RSTL-HIGHIV)
d(RSTH-HIGHV)
d(RSTL-LOWIV)
d(RSTH-LOWV)
d(RSTL-ZHZ)
4P
P
P
P
4P
4P
4P
d(RSTH-ZV)
†
#
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
High group consists of:
Low group consists of:
Z group consists of:
XFCLK, HOLDA
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
RESET TIMING (CONTINUED)
CLKOUT1
1
10
11
RESET
2
4
3
CLKOUT2
5
7
9
†
HIGH GROUP
LOW GROUP
6
†
8
†
Z GROUP
Boot Configuration
‡
XD[31:0]
†
‡
High group consists of:
Low group consists of:
Z group consists of:
XFCLK, HOLDA
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA.
XD[31:0] are the boot configuration pins during device reset.
Figure 29. Reset Timing
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXTERNAL INTERRUPT TIMING
†
timing requirements for interrupt response cycles (see Figure 30)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
2P
MAX
2
3
t
t
Width of the interrupt pulse low
Width of the interrupt pulse high
ns
ns
w(ILOW)
2P
w(IHIGH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
switching characteristics over recommended operating conditions during interrupt response
†
cycles (see Figure 30)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
9P
1
MAX
MIN
9P
MAX
1
4
5
6
t
t
t
t
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
ns
ns
ns
ns
R(EINTH – IACKH)
d(CKO2L-IACKV)
d(CKO2L-INUMV)
d(CKO2L-INUMIV)
10
10
10
–1.5
–2.0
–2.0
10
10
10
0
0
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
1
CLKOUT2
3
2
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
Interrupt Number
INUMx
Figure 30. Interrupt Timing
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS FIFO TIMING
timing requirements for synchronous FIFO interface (see Figure 31, Figure 32, and Figure 33)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
MAX
MIN
MAX
5
6
t
t
Setup time, read XDx valid before XFCLK high
Hold time, read XDx valid after XFCLK high
3
3
ns
ns
su(XDV-XFCKH)
2.5
2.5
h(XFCKH-XDV)
switching characteristics over recommended operating conditions for synchronous FIFO
interface (see Figure 31, Figure 32, and Figure 33)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
1.5
MAX
5.2
5.2
5.2
5.2
5.2
5.2
MIN
1.5
MAX
5.5
5.5
5.5
5.5
5.5
6
1
2
3
4
7
8
9
t
t
t
t
t
t
t
Delay time, XFCLK high to XCEx valid
Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid
Delay time, XFCLK high to XOE valid
Delay time, XFCLK high to XRE valid
ns
ns
ns
ns
ns
ns
ns
d(XFCKH-XCEV)
d(XFCKH-XAV)
d(XFCKH-XOEV)
d(XFCKH-XREV)
d(XFCKH-XWEV)
d(XFCKH-XDV)
d(XFCKH-XDIV)
†
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
‡
Delay time, XFCLK high to XWE/XWAIT valid
Delay time, XFCLK high to XDx valid
Delay time, XFCLK high to XDx invalid
1.5
1.5
†
‡
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
XFCLK
1
1
†
XCE3
2
3
4
2
3
‡
XA1
XA2
XA3
XA4
XBE[3:0]/XA[5:2]
XOE
XRE
4
§
XWE/XWAIT
6
5
XD[31:0]
FIFO read (glueless) mode only available in XCE3.
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
D1
D2
D3
D4
†
‡
§
Figure 31. FIFO Read Timing (Glueless Read Mode)
65
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
XFCLK
XCEx
1
2
1
2
3
†
XA1
XA2
XA3
XA4
XBE[3:0]/XA[5:2]
3
4
XOE
XRE
4
‡
XWE/XWAIT
6
5
XD[31:0]
D1
D2
D3
D4
†
‡
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 32. FIFO Read Timing
XFCLK
1
1
XCEx
2
2
†
XA1
XA2
XA3
XA4
XBE[3:0]/XA[5:2]
XOE
XRE
7
8
7
‡
XWE/XWAIT
9
XD[31:0]
D1
D2
D3
D4
†
‡
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 33. FIFO Write Timing
66
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
†‡§¶
timing requirements for asynchronous peripheral cycles
(see Figure 34–Figure 37)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN MAX
MIN MAX
Setup time, XDx valid before XRE
high
3
4
6
7
t
t
t
t
4.5
1
4.5
2.5
ns
ns
ns
ns
su(XDV-XREH)
Hold time, XDx valid after XRE
high
h(XREH-XDV)
Setup time, XRDY high before
XRE low
–[(RST – 3) * P – 6]
(RST – 3) * P + 2
–[(RST – 3) * P – 6]
(RST – 3) * P + 2
su(XRDYH-XREL)
h(XREL-XRDYH)
Hold time, XRDY high after XRE
low
Setup time, XRDY low before XRE
low
9
t
–[(RST – 3) * P – 6]
–[(RST – 3) * P – 6]
ns
su(XRDYL-XREL)
Hold time, XRDY low after XRE
low
10
11
15
t
t
t
(RST – 3) * P + 2
2P
(RST – 3) * P + 2
2P
ns
ns
ns
h(XREL-XRDYL)
Pulse width, XRDY high
w(XRDYH)
Setup time, XRDY high before
XWE low
–[(WST – 3) * P – 6]
–[(WST – 3) * P – 6]
su(XRDYH-XWEL)
Hold time, XRDY high after XWE
low
16
t
(WST – 3) * P + 2
(WST – 3) * P + 2
ns
h(XWEL-XRDYH)
Setup time, XRDY low before
XWE low
18
19
t
–[(WST – 3) * P – 6]
(WST – 3) * P + 2
–[(WST – 3) * P – 6]
(WST – 3) * P + 2
ns
ns
su(XRDYL-XWEL)
h(XWEL-XRDYL)
Hold time, XRDY low after XWE
low
t
†
‡
To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
§
¶
67
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
switching characteristics over recommended operating conditions for asynchronous peripheral
†‡§¶
cycles
(see Figure 34–Figure 37)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Output setup time, select
signals valid to XRE low
1
t
RS * P – 2
RH * P – 2
RS * P – 2
RH * P – 2
ns
osu(SELV-XREL)
Output hold time, XRE low to
select signals invalid
2
5
8
t
t
t
ns
ns
ns
oh(XREH-SELIV)
Pulse width, XRE low
RST * P
RST * P
w(XREL)
Delay time, XRDY high to XRE
high
3P
WS * P – 2
WH * P – 2
4P + 5
3P
WS * P – 3
WH * P – 2
4P + 5
d(XRDYH-XREH)
Output setup time, select
signals valid to XWE low
12
t
ns
osu(SELV-XWEL)
Output hold time, XWE low to
select signals invalid
13
14
t
t
ns
ns
oh(XWEH-SELIV)
Pulse width, XWE low
WST * P
WST * P
w(XWEL)
Delay time, XRDY high to XWE
high
17
t
3P
4P + 5
3P
4P + 5
ns
d(XRDYH-XWEH)
†
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
‡
§
¶
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an
additional 7P ns following the end of the cycle.
68
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CLKOUT1
1
1
2
2
XCEx
XBE[3:0]/
†
XA[5:2]
3
4
XD[31:0]
XOE
1
2
5
6
7
XRE
‡
XWE/XWAIT
§
XRDY
†
‡
§
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 34. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
1
1
2
2
XCEx
XBE[3:0]/
†
XA[5:2]
3
4
XD[31:0]
XOE
1
9
2
8
10
XRE
‡
XWE/XWAIT
11
§
XRDY
†
‡
§
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 35. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)
69
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ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CLKOUT1
XCEx
12
12
13
13
XBE[3:0]/
†
XA[5:2]
12
13
XD[31:0]
XOE
XRE
15
16
14
‡
§
XWE/XWAIT
XRDY
†
‡
§
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 36. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
12
12
13
13
XCEx
XBE[3:0]/
†
XA[5:2]
12
13
XD[31:0]
XOE
XRE
17
18
19
‡
XWE/XWAIT
11
§
XRDY
†
‡
§
XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 37. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)
70
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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as bus master (see Figure 38 and Figure 39)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
3.5
MAX
MIN MAX
3.5
1
2
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, XCS valid before XCLKIN high
Hold time, XCS valid after XCLKIN high
Setup time, XAS valid before XCLKIN high
Hold time, XAS valid after XCLKIN high
Setup time, XCNTL valid before XCLKIN high
Hold time, XCNTL valid after XCLKIN high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(XCSV-XCKIH)
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
h(XCKIH-XCS)
3
su(XAS-XCKIH)
h(XCKIH-XAS)
4
5
su(XCTL-XCKIH)
h(XCKIH-XCTL)
su(XWR-XCKIH)
h(XCKIH-XWR)
su(XBLTV-XCKIH)
h(XCKIH-XBLTV)
su(XBEV-XCKIH)
h(XCKIH-XBEV)
6
†
Setup time, XW/R valid before XCLKIN high
7
†
8
Hold time, XW/R valid after XCLKIN high
Setup time, XBLAST valid before XCLKIN high
‡
9
‡
10
16
17
Hold time, XBLAST valid after XCLKIN high
Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high
§
§
Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high
18
19
t
Setup time, XDx valid before XCLKIN high
Hold time, XDx valid after XCLKIN high
3.5
2.8
3.5
2.8
ns
ns
su(XD-XCKIH)
h(XCKIH-XD)
t
†
‡
§
XW/R input/output polarity selected at boot.
XBLAST input polarity selected at boot
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as bus
¶
master (see Figure 38 and Figure 39)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
11
12
13
14
15
20
21
t
t
t
t
t
t
t
Delay time, XCLKIN high to XDx low impedance
Delay time, XCLKIN high to XDx valid
0
5
0
3
ns
ns
ns
ns
ns
ns
ns
d(XCKIH-XDLZ)
d(XCKIH-XDV)
d(XCKIH-XDIV)
d(XCKIH-XDHZ)
d(XCKIH-XRY)
d(XCKIH-XRYLZ)
d(XCKIH-XRYHZ)
16.5
4P – 0.5
Delay time, XCLKIN high to XDx invalid
Delay time, XCLKIN high to XDx high impedance
4P
16.5
16.5
4P
4P – 0.5
4P – 0.5
7P + 0.5
#
Delay time, XCLKIN high to XRDY invalid
5
5
3
3
Delay time, XCLKIN high to XRDY low impedance
Delay time, XCLKIN high to XRDY high impedance
#
2P + 5 3P + 16.5 2P + 3
¶
#
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
XRDY operates as active-low ready input/output during host-port accesses.
71
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
2
1
XCS
4
3
XAS
6
5
XCNTL
8
7
†
XW/R
8
7
†
‡
XW/R
XBE[3:0]/XA[5:2]
10
10
9
9
§
XBLAST
XBLAST
§
13
14
12
11
D1
15
D2
D3
D4
XD[31:0]
21
20
15
¶
XRDY
†
‡
§
¶
XW/R input/output polarity selected at boot
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XBLAST input polarity selected at boot
XRDY operates as active-low ready input/output during host-port accesses.
Figure 38. External Host as Bus Master—Read
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
2
1
XCS
4
3
XAS
6
5
XCNTL
8
7
†
†
XW/R
XW/R
8
7
17
16
‡
XBE1
XBE2
XBE3
9
XBE4
XBE[3:0]/XA[5:2]
XBLAST
10
10
§
9
§
XBLAST
19
18
D1
15
D2
D3
D4
XD[31:0]
21
20
15
¶
XRDY
†
‡
§
¶
XW/R input/output polarity selected at boot
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XBLAST input polarity selected at boot
XRDY operates as active-low ready input/output during host-port accesses.
Figure 39. External Host as Bus Master—Write
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
timing requirements with C62x as bus master (see Figure 40, Figure 41, and Figure 42)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
3.5
MAX
MIN
3.5
MAX
9
t
t
t
t
t
t
Setup time, XDx valid before XCLKIN high
Hold time, XDx valid after XCLKIN high
Setup time, XRDY valid before XCLKIN high
ns
ns
ns
ns
ns
ns
su(XDV-XCKIH)
h(XCKIH-XDV)
su(XRY-XCKIH)
h(XCKIH-XRY)
su(XBFF-XCKIH)
h(XCKIH-XBFF)
10
11
12
14
15
2.8
3.5
2.8
3.5
2.8
2.8
3.5
2.8
3.5
2.8
†
†
Hold time, XRDY valid after XCLKIN high
Setup time, XBOFF valid before XCLKIN high
Hold time, XBOFF valid after XCLKIN high
†
XRDY operates as active-low ready input/output during host-port accesses.
switching characteristics over recommended operating conditions with C62x as bus master
(see Figure 40, Figure 41, and Figure 42)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
16.5
16.5
16.5
16.5
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
Delay time, XCLKIN high to XAS valid
Delay time, XCLKIN high to XW/R valid
5
3
4P – 0.5
4P – 0.5
4P – 0.5
4P – 0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(XCKIH-XASV)
d(XCKIH-XWRV)
d(XCKIH-XBLTV)
d(XCKIH-XBEV)
d(XCKIH-XDLZ)
d(XCKIH-XDV)
d(XCKIH-XDIV)
d(XCKIH-XDHZ)
d(XCKIH-XWTV)
‡
5
5
5
0
3
3
3
0
§
Delay time, XCLKIN high to XBLAST valid
3
¶
4
Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid
Delay time, XCLKIN high to XDx low impedance
Delay time, XCLKIN high to XDx valid
5
6
16.5
4P – 0.5
7
Delay time, XCLKIN high to XDx invalid
5
5
3
3
8
Delay time, XCLKIN high to XDx high impedance
4P
4P
#
13
Delay time, XCLKIN high to XWE/XWAIT valid
16.5
4P – 0.5
‡
§
¶
#
XW/R input/output polarity selected at boot.
XBLAST output polarity is always active low.
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XWE/XWAIT operates as XWAIT output signal during host-port accesses.
74
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
1
1
XAS
2
2
3
†
†
XW/R
XW/R
3
‡
§
XBLAST
4
4
XBE[3:0]/XA[5:2]
BE
5
9
7
6
8
10
D2
AD
D1
D3
D4
XD[31:0]
XRDY
11
12
13
13
¶
XWE/XWAIT
†
‡
§
¶
XW/R input/output polarity selected at boot
XBLAST output polarity is always active low.
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 40. C62x as Bus Master—Read
XCLKIN
XAS
1
1
†
XW/R
XW/R
2
2
3
4
7
†
3
‡
XBLAST
4
§
XBE[3:0]/XA[5:2]
6
Addr
5
8
D1
D2
11
D3
D4
XD[31:0]
XRDY
12
13
13
¶
XWE/XWAIT
†
‡
§
¶
XW/R input/output polarity selected at boot
XBLAST output polarity is always active low.
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 41. C62x as Bus Master—Write
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
1
1
XAS
†
XW/R
2
2
†
‡
XW/R
XBLAST
4
4
7
§
XBE[3:0]/XA[5:2]
6
5
8
Addr
D1
11
D2
XD[31:0]
XRDY
12
15
14
XBOFF
¶
¶
#
XHOLD
XHOLDA
XHOLD
#
XHOLDA
†
‡
§
¶
#
||
XW/R input/output polarity selected at boot
XBLAST output polarity is always active low.
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
Internal arbiter enabled
Internal arbiter disabled
This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 45 and Figure 46.
||
Figure 42. C62x as Bus Master—BOFF Operation
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
†
timing requirements with external device as asynchronous bus master (see Figure 43 and
Figure 44)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
4P
MAX
MIN
4P
MAX
1
2
t
t
Pulse duration, XCS low
Pulse duration, XCS high
ns
ns
w(XCSL)
4P
1
4P
1
w(XCSH)
‡
Setup time, expansion bus select signals valid before XCS
low
3
t
ns
su(XSEL-XCSL)
‡
4
t
t
t
t
t
t
Hold time, expansion bus select signals valid after XCS low
3
3.4
ns
ns
ns
ns
ns
ns
h(XCSL-XSEL)
h(XRYL-XCSL)
su(XBEV-XCSH)
h(XCSH-XBEV)
su(XDV-XCSH)
h(XCSH-XDV)
10
11
12
13
14
Hold time, XCS low after XRDY low
P + 1.5
P + 1.5
§
Setup time, XBE[3:0]/XA[5:2] valid before XCS high
1
3
1
3
1
3
1
3
§
Hold time, XBE[3:0]/XA[5:2] valid after XCS high
Setup time, XDx valid before XCS high
Hold time, XDx valid after XCS high
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
Expansion bus select signals include XCNTL and XR/W.
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as
†
asynchronous bus master (see Figure 43 and Figure 44)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
5
6
7
8
9
t
t
t
t
t
Delay time, XCS low to XDx low impedance
Delay time, XCS high to XDx invalid
Delay time, XCS high to XDx high impedance
Delay time, XRDY low to XDx valid
0
0
ns
ns
ns
ns
ns
d(XCSL-XDLZ)
d(XCSH-XDIV)
d(XCSH-XDHZ)
d(XRYL-XDV)
d(XCSH-XRYH)
0
12
0
12
4P
1
4P
1.8
12
–4
–4
–1
Delay time, XCS high to XRDY high
0
12
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED)
1
1
2
10
10
XCS
3
3
4
4
XCNTL
†
XBE[3:0]/XA[5:2]
3
3
3
3
4
4
4
4
‡
XR/W
XR/W
‡
7
6
7
6
5
8
5
8
Word
XD[31:0]
XRDY
9
9
†
‡
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XW/R input/output polarity selected at boot
Figure 43. External Device as Asynchronous Master—Read
10
1
2
10
1
XCS
3
3
4
4
XCNTL
11
11
12
12
†
‡
‡
XBE[3:0]/XA[5:2]
XR/W
3
3
3
3
4
4
4
4
XR/W
13
13
14
9
14
9
Word
XD[31:0]
XRDY
†
‡
XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
XW/R input/output polarity selected at boot
Figure 44. External Device as Asynchronous Master—Write
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
XHOLD/XHOLDA TIMING
†
timing requirements for expansion bus arbitration (internal arbiter enabled) (see Figure 45)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
MAX
3
t
Output hold time, XHOLD high after XHOLDA high
P
ns
oh(XHDAH-XHDH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
switching characteristics over recommended operating conditions for expansion bus arbitration
†‡
(internal arbiter enabled) (see Figure 45)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
3P
MAX
§
1
2
4
5
t
t
t
t
Delay time, XHOLD high to XBus high impedance
Delay time, XBus high impedance to XHOLDA high
Delay time, XHOLD low to XHOLDA low
ns
ns
ns
ns
d(XHDH-XBHZ)
d(XBHZ-XHDAH)
d(XHDL-XHDAL)
d(XHDAL-XBLZ)
0
3P
0
2P
2P
Delay time, XHOLDA low to XBus low impedance
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
All pending XBus transactions are allowed to complete before XHOLDA is asserted.
External Requestor
DSP Owns Bus
Owns Bus
DSP Owns Bus
3
XHOLD (input)
2
4
XHOLDA (output)
1
5
†
C6202/02B
C6202/02B
XBus
†
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 45. Expansion Bus Arbitration—Internal Arbiter Enabled
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
XHOLD/XHOLDA TIMING (CONTINUED)
switching characteristics over recommended operating conditions for expansion bus arbitration
†
(internal arbiter disabled) (see Figure 46)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
2P 2P + 10
2P
MAX
‡
1
2
t
t
Delay time, XHOLDA high to XBus low impedance
ns
ns
d(XHDAH-XBLZ)
‡
Delay time, XBus high impedance to XHOLD low
0
d(XBHZ-XHDL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
2
XHOLD (output)
XHOLDA (input)
1
C6202/02B
†
XBus
†
XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 46. Expansion Bus Arbitration—Internal Arbiter Disabled
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING
†‡
timing requirements for McBSP (see Figure 47)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN MAX
MIN
MAX
§
§
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P
2P
ns
ns
c(CKRX)
¶
P–1
¶
P–1
Pulse duration, CLKR/X high or CLKR/X low
w(CKRX)
9
2
9
2
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
6
6
3
3
8
8
7
0.5
3
0.5
3
8
Hold time, DR valid after CLKR low
4
4.5
9
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
2
2
6
6
3
4
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
The maximum bit rate for the C6202/02B device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 250 MHz
(P = 4 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶
The minimum CLKR/X pulse duration is either (P–1) or 4 ns, whichever is larger. For example, when running parts at 250 MHz (P = 4 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P–1) = 9 ns as the minimum CLKR/X pulse
duration.
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
switching characteristics over recommended operating conditions for McBSP (see Figure 47)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Delay time, CLKS high to CLKR/X high for
internal CLKR/X generated from CLKS
input
1
t
4
16
4
16
ns
d(CKSH-CKRXH)
§¶
§¶
2
3
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
2P
2P
ns
ns
c(CKRX)
Pulse duration, CLKR/X high or CLKR/X
low
#
#
3
#
#
3
C – 1
C + 1
C – 1
C + 1
w(CKRX)
Delay time, CLKR high to internal FSR
valid
4
9
t
t
t
t
CLKR int
–2
–2
ns
ns
ns
ns
d(CKRH-FRV)
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
–2
3
3
9
5
9
4
–2
2
3
9
5
9
3
Delay time, CLKX high to internal FSX
valid
–1
2
–1
2
Disable time, DX high impedance following
last data bit from CLKX high
12
13
–1
2
–0.5
2
Delay time, CLKX high to DX valid
11
5
11
5
Delay time, FSX high to DX valid
ONLY applies when in data delay 0
(XDATDLY = 00b) mode.
FSX int
FSX ext
–1
–1
14
t
ns
d(FXH-DXV)
0
10
0
10
†
‡
§
¶
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
The maximum bit rate for the C6202/02B device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 250 MHz
(P = 4 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
#
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
82
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
8
DR
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
13
(n-2)
14
13
12
DX
Bit 0
Bit(n-1)
(n-3)
Figure 47. McBSP Timings
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 48)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
4
MAX
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
su(FRH-CKSH)
4
h(CKSH-FRH)
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 48. FSR Timing When GSYNC = 1
84
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 49)
C6202-200
C6202-250
C6202B-250
NO.
UNIT
C6202B-300
MASTER SLAVE
MIN
12
4
MAX
MIN
2 – 3P
5 + 6P
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
†‡
slave: CLKSTP = 10b, CLKXP = 0 (see Figure 49)
C6202-200
C6202-250
C6202B-250
NO.
PARAMETER
UNIT
C6202B-300
§
MASTER
MIN MAX
SLAVE
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T – 2 T + 3
L – 2 L + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
–3
4
3P + 4 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L – 2 L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from FSX
high
7
8
t
t
P + 3 3P + 17
2P + 2 4P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
86
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 50)
C6202-200
C6202-250
C6202B-250
NO.
UNIT
C6202B-300
MASTER SLAVE
MIN
12
4
MAX
MIN
2 – 3P
5 + 6P
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
†‡
slave: CLKSTP = 11b, CLKXP = 0 (see Figure 50)
C6202-200
C6202-250
C6202B-250
NO.
PARAMETER
UNIT
C6202B-300
§
MASTER
MIN MAX
SLAVE
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L – 2 L + 3
T – 2 T + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
–2
4
3P + 4 5P + 17
3P + 3 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
–2
4
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
H – 2 H + 4
2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
87
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
DX
1
2
7
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
88
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 51)
C6202-200
C6202-250
C6202B-250
NO.
UNIT
C6202B-300
MASTER SLAVE
MIN
12
4
MAX
MIN
2 – 3P
5 + 6P
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
†‡
slave: CLKSTP = 10b, CLKXP = 1 (see Figure 51)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
§
§
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
MIN MAX
MAX
MIN MAX
MAX
Hold time, FSX low after
CLKX high
1
2
3
t
t
t
T – 2 T + 3
H – 2 H + 3
T – 2 T + 3
H – 2 H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
¶
Delay time, FSX low to
#
CLKX low
Delay time, CLKX low to
DX valid
–2
4
3P + 4 5P + 17
–3
4
3P + 4 5P + 17
Disable time, DX high
impedance following last
data bit from CLKX high
6
t
H – 2 H + 3
H – 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high
impedance following last
data bit from FSX high
7
8
t
t
P + 3 3P + 17
2P + 2 4P + 17
P + 3 3P + 17
2P + 2 4P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to
DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
7
6
8
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 51. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
90
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 52)
C6202-200
C6202-250
C6202B-250
NO.
UNIT
C6202B-300
MASTER SLAVE
MIN
12
4
MAX
MIN
2 – 3P
5 + 6P
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
†‡
slave: CLKSTP = 11b, CLKXP = 1 (see Figure 52)
C6202-200
C6202-250
C6202B-250
NO.
PARAMETER
UNIT
C6202B-300
§
MASTER
MIN MAX
SLAVE
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H – 2 H + 3
T – 2 T + 2
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
–3
4
3P + 4 5P + 17
3P + 3 5P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
–2
4
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
L – 2 L + 5
2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
91
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
DX
1
2
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 52. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
92
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
DMAC, TIMER, POWER-DOWN TIMING
†
switching characteristics over recommended operating conditions for DMAC outputs
(see Figure 53)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Pulse duration, DMAC high
2P–3
ns
w(DMACH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
1
DMAC[3:0]
Figure 53. DMAC Timing
†
timing requirements for timer inputs (see Figure 54)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
2P
MAX
1
2
t
t
Pulse duration, TINP high
Pulse duration, TINP low
ns
ns
w(TINPH)
2P
w(TINPL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
†
switching characteristics over recommended operating conditions for timer outputs
(see Figure 54)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
2P–3
2P–3
MAX
3
4
t
t
Pulse duration, TOUT high
Pulse duration, TOUT low
ns
ns
w(TOUTH)
w(TOUTL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
2
1
TINPx
4
3
TOUTx
Figure 54. Timer Timing
93
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
†
switching characteristics over recommended operating conditions for power-down outputs
(see Figure 55)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Pulse duration, PD high
2P
ns
w(PDH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
1
PD
Figure 55. Power-Down Timing
94
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 56)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
UNIT
MIN
35
11
9
MAX
1
3
4
t
t
t
Cycle time, TCK
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 56)
C6202-200
C6202-250
C6202B-250
C6202B-300
NO.
PARAMETER
UNIT
MIN
MAX
12
MIN
MAX
2
t
Delay time, TCK low to TDO valid
–4.5
–4.5
13.5
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 56. JTAG Test-Port Timing
95
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MECHANICAL DATA
GJL (S-PBGA-N352) [C6202 only]
PLASTIC BALL GRID ARRAY
27,20
SQ
26,80
25,20
SQ
25,00 TYP
24,80
1,00
16,30 NOM
0,50
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
A1 Corner
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
2
4
6
8
10 12 14 16 18 20 22 24 26
Bottom View
Heat Slug
See Note E
3,80 MAX
1,30
0,87
Seating Plane
0,15
0,70
0,10
0,50
M
0,60
0,40
4173516-2/H 02/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL)
D. Flip chip application only
E. Possible protrusion in this area, but within 3,50 max package height specification
F. Falls within JEDEC MO-151/AAL-1
thermal resistance characteristics (S-PBGA package) [C6202 only]
†
NO
°C/W
0.47
14.2
12.3
10.9
9.3
Air Flow m/s
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
0.00
0.50
1.00
2.00
†
m/s = meters per second
96
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
ꢊ
ꢋꢌ
ꢍꢎ
ꢏꢐ
ꢑ
ꢋ
ꢒꢀ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MECHANICAL DATA
GLS (S-PBGA-N384)
PLASTIC BALL GRID ARRAY
18,10
17,90
SQ
16,80 TYP
0,80
0,40
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
A1 Corner
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
2
4
6
8
10 12 14 16 18 20 22
Heat Slug
Bottom View
2,80 MAX
1,00 NOM
Seating Plane
0,12
0,55
0,45
M
0,10
0,45
0,35
4188959-3/E 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL)
D. Flip chip application only
thermal resistance characteristics (S-PBGA package) ) [C6202 only]
†
NO
°C/W
0.85
21.6
18.0
15.5
12.8
Air Flow m/s
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
0.00
0.50
1.00
2.00
†
m/s = meters per second
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢅ ꢄꢈ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅ ꢄꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎꢋ ꢓ ꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍ ꢂꢂꢑ ꢖꢂ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MECHANICAL DATA
GNZ (S–PBGA–N352) [C6202B only]
PLASTIC BALL GRID ARRAY
27,20
SQ
25,00 TYP
26,80
1,00
25,20
SQ
24,80
0,50
AF
AE
AD
AC
AB
AA
Y
W
V
1,00
U
T
A1 Corner
R
P
N
M
L
K
0,50
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
2
4
6
8
Bottom View
2,80 MAX
0,50 NOM
Seating Plane
0,15
0,70
0,50
M
0,10
0,60
0,40
4202595-2/E 12/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only.
D. Substrate color may vary.
thermal resistance characteristics (S-PBGA package) [C6202B only]
†
NO
°C/W
6.35
20.0
17.0
16.3
15.2
Air Flow m/s
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
0.00
0.50
1.00
2.00
†
m/s = meters per second
98
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢅꢄ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢄꢉ
ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ ꢂ
ꢊ
ꢋꢌ
ꢍꢎ
ꢏꢐ
ꢑ
ꢋ
ꢒꢀ
SPRS104G – OCTOBER 1999 – REVISED APRIL 2003
MECHANICAL DATA
GNY (S-PBGA-N384) [C6202B only]
PLASTIC BALL GRID ARRAY
18,10
SQ
16,80 TYP
0,80
17,90
0,40
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
A1 Corner
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
2
4
6
8
10 12 14 16 18 20 22
Bottom View
2,35 MAX
Seating Plane
0,12
0,55
0,45
M
0,10
0,45
0,35
4201137/C 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only
D. Substrate color may vary
thermal resistance characteristics (S-PBGA package) [C6202B only]
†
Air Flow m/s
NO
(°C/W)
6.27
17.6
13.9
13.1
11.9
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
0.0
0.5
1.0
2.0
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
†
m/s = meters per second
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
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