TMS320C6711BGFNA100_技术文档

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

D

Excellent Price/Performance Digital Signal

Processors (DSPs): TMS320C67x

(TMS320C6711 and TMS320C6711B)

– Eight 32-Bit Instructions/Cycle

– C6211, C6211B, C6711, and C6711B are

Pin-Compatible

– 100-, 150-MHz Clock Rates

– 10-, 6.7-ns Instruction Cycle Time

– 600, 900 MFLOPS

D

Device Configuration

– Boot Mode: HPI, 8-, 16-, and 32-Bit ROM

Boot

– Endianness: Little Endian, Big Endian

32-Bit External Memory Interface (EMIF)

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

– Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

– 512M-Byte Total Addressable External

Memory Space

VelociTI Advanced Very Long Instruction

Word (VLIW) C67x DSP Core (C6711/11B)

– Eight Highly Independent Functional

Units:

D

Enhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

– Four ALUs (Floating- and Fixed-Point)

– Two ALUs (Fixed-Point)

– Two Multipliers (Floating- and

Fixed-Point)

16-Bit Host-Port Interface (HPI)

– Access to Entire Memory Map

Two Multichannel Buffered Serial Ports

(McBSPs)

– Direct Interface to T1/E1, MVIP, SCSA

Framers

– ST-Bus-Switching Compatible

– Up to 256 Channels Each

– AC97-Compatible

– Serial-Peripheral-Interface (SPI)

Compatible (Motorola )

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

D

Instruction Set Features

– Hardware Support for IEEE

Single-Precision and Double-Precision

Instructions

– Byte-Addressable (8-, 16-, 32-Bit Data)

– 8-Bit Overflow Protection

– Saturation

– Bit-Field Extract, Set, Clear

– Bit-Counting

– Normalization

D

Two 32-Bit General-Purpose Timers

Flexible Phase-Locked-Loop (PLL) Clock

Generator

†

D

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

256-Pin Ball Grid Array (BGA) Package

(GFN Suffix)

L1/L2 Memory Architecture

– 32K-Bit (4K-Byte) L1P Program Cache

(Direct Mapped)

– 32K-Bit (4K-Byte) L1D Data Cache

(2-Way Set-Associative)

0.18-µm/5-Level Metal Process

– CMOS Technology

3.3-V I/Os, 1.8-V Internal

– 512K-Bit (64K-Byte) L2 Unified Mapped

RAM/Cache

(Flexible Data/Program Allocation)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320C67x, VelociTI, and C67x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

All trademarks are the property of their respective owners.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Table of Contents

GFN BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 2

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

functional block and CPU (DSP core) diagram . . . . . . . . . . . 6

CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 7

memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 10

PWRD bits in CPU CSR register description . . . . . . . . . . . 15

EDMA channel synchronization events . . . . . . . . . . . . . . . . 16

interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 17

signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

recommended operating conditions . . . . . . . . . . . . . . . . 35

electrical characteristics over recommended ranges of

supply voltage and operating case temperature . 35

parameter measurement information . . . . . . . . . . . . . . . 36

signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . 36

timing parameters and board routing analysis . . . . . . 37

input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 42

synchronous-burst memory timing . . . . . . . . . . . . . . . . . 46

synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 49

HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 60

host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 61

multichannel buffered serial port timing . . . . . . . . . . . . . 65

timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

absolute maximum ratings over operating case

temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

GFN BGA package (bottom view)

GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE

(BOTTOM VIEW)

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13

12

15

17

19

2

4

6

8

10

14

16

18

20

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

description

The TMS320C67x DSPs (including the TMS320C6711/C6711B devices) compose the floating-point DSP

family in the TMS320C6000 DSP platform. The TMS320C6711 (C6711) and TMS320C6711B (C6711B)

devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW)

architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and

multifunction applications.

With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of

150 MHz, the C6711/C6711B device also offers cost-effective solutions to high-performance DSP

programming challenges. The C6711/C6711B DSP possesses the operational flexibility of high-speed

controllers and the numerical capability of array processors. This processor has 32 general-purpose registers

of 32-bit word length and eight highly independent functional units. The eight functional units provide four

floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711/C6711B

can produce two MACs per cycle for a total of 300 MMACS. The C6711/C6711B DSP also has

application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6711/C6711B uses a two-level cache-based architecture and has a powerful and diverse set of

peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache

(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory

space that is shared between program and data space. L2 memory can be configured as mapped memory,

cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs),

two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)

capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711/C6711B has a complete set of development tools which includes: a new C compiler, an assembly

optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source

code execution.

TMS320C6000 is a trademark of Texas Instruments.

Windows is a registered trademark of the Microsoft Corporation.

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

device characteristics

Table 1 provides an overview of the C6711/C6711B DSP. The table shows significant features of each device,

including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.

For more details on the C6000 DSP device part numbers and part numbering, see Table 17 and Figure 4.

Table 1. Characteristics of the C6711/C6711B Processors

C6711

(FLOATING-POINT DSP)

C6711B

(FLOATING-POINT DSP)

HARDWARE FEATURES

EMIF

1

(Clock source = ECLKIN)

EDMA

(Internal clock source =

CPU clock frequency)

1

2

1

2

HPI

Peripherals

McBSPs

(Internal clock source =

CPU/2 clock frequency)

32-Bit Timers

(Internal clock source =

CPU/4 clock frequency)

2

Size (Bytes)

72K

On-Chip

Memory

4K-Byte (4KB) L1 Program (L1P) Cache

4KB L1 Data (L1D) Cache

4K-Byte (4KB) L1 Program (L1P) Cache

4KB L1 Data (L1D) Cache

Organization

64KB Unified Mapped RAM/Cache (L2)

CPU ID+

CPU Rev ID

Control Status Register

(CSR.[31:16])

0x0202

Frequency

MHz

150, 100

6.7 ns (C6711B-150)

10 ns (C6711B-100)

10 ns (C6711BGFNA-100)

6.7 ns (C6711-150)

10 ns (C6711-100)

Cycle Time

ns

Core (V)

1.8

3.3

1.8

3.3

Voltage

I/O (V)

PLL Options

CLKIN frequency multiplier

27 x 27 mm

Bypass (x1), x4

256-Pin BGA (GFN)

Bypass (x1), x4

256-Pin BGA (GFN)

BGA Package

Process

Technology

µm

0.18 µm

Product Status

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

PD

C6000 is a trademark of Texas Instruments.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

device compatibility

The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set;

thus, making new system designs easier and providing faster time to market. The following list summarizes the

device characteristic differences among the C6211, C6211B, C6711, and C6711B devices:

D

The C6211 and C6211B devices have a fixed-point C62x CPU, while the C6711 and C6711B devices have

a floating-point C67x CPU.

The C6211/C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended

temperature device that also runs at -150 MHz), while the C6711/C6711B device runs at -150 and -100 MHz

(with a C6711BGFNA extended temperature device that also runs at -100 MHz).

For a more detailed discussion on the similarities/differences between the C6211 and C6711 devices, see the

How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the

TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively).

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

functional block and CPU (DSP core) diagram

C6711/C6711B Digital Signal Processors

SDRAM

External

SBSRAM

32

Memory

Interface

(EMIF)

L1P Cache

Direct Mapped

4K Bytes Total

SRAM

ROM/FLASH

I/O Devices

Timer 0

Timer 1

C6000 CPU (DSP Core)

Instruction Fetch

Instruction Dispatch

Instruction Decode

Control

Registers

L2

Memory

4 Banks

64K Bytes

Total

Enhanced

DMA

Controller

(16 channel)

Control

Logic

Multichannel

Buffered

Serial Port 1

(McBSP1)

Data Path A

A Register File

Data Path B

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

Test

B Register File

In-Circuit

Emulation

Multichannel

Buffered

Serial Port 0

(McBSP0)

Interrupt

Control

†

.L1 .S1 .M1 .D1

.D2 .M2 .S2 .L2

L1D Cache

2-Way Set

Associative

Host Port

Interface

(HPI)

16

4K Bytes Total

Power-Down

Logic

PLL

(x1, x4)

Boot

Configuration

Interrupt

Selector

†

In addition to fixed-point instructions, these functional units execute floating-point instructions.

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

CPU (DSP core) description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture

features controls by which all eight units do not have to be supplied with instructions if they are not ready to

execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute

packet as the previous instruction, or whether it should be executed in the following clock as a part of the next

execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The

variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other

VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

eachcontain1632-bitregistersforatotalof32general-purposeregisters. Thetwosetsoffunctionalunits, along

with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and

Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that

side. Additionally, each side features a single data bus connected to all the registers on the other side, by which

the two sets of functional units can access data from the register files on the opposite side. While register access

by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,

register access using the register file across the CPU supports one read and one write per cycle.

The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight

functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two

functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a

total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of

the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet

can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one

per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

7

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

CPU (DSP core) description (continued)

src1

†

.L1

src2

dst

8

long dst

long src

8

32

LD1 32 MSB

ST1

Register

File A

(A0–A15)

long src

long dst

dst

8

Data Path A

†

.S1

src1

src2

dst

†

.M1

src1

src2

LD1 32 LSB

DA1

dst

src1

src2

.D1

2X

1X

src2

src1

dst

DA2

.D2

.M2

LD2 32 LSB

src2

†

src1

dst

src2

Register

File B

(B0–B15)

src1

dst

†

.S2

Data Path B

8

long dst

long src

8

32

LD2 32 MSB

ST2

long src

long dst

dst

8

†

.L2

src2

src1

Control

Register File

†

In addition to fixed-point instructions, these functional units execute floating-point instructions.

Figure 1. TMS320C67x CPU (DSP Core) Data Paths

8

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

memory map summary

Table 2 shows the memory map address ranges of the C6711/C6711B devices. Internal memory is always

located at address 0 and can be used as both program and data memory. The C6711/C6711B configuration

registers for the common peripherals are located at the same hex address ranges. The external memory

address ranges in the C6711/C6711B devices begin at the address location 0x8000 0000.

Table 2. TMS320C6711/C6711B Memory Map Summary

MEMORY BLOCK DESCRIPTION

Internal RAM (L2)

BLOCK SIZE (BYTES)

HEX ADDRESS RANGE

0000 0000 – 0000 FFFF

0001 0000 – 017F FFFF

0180 0000 – 0183 FFFF

0184 0000 – 0187 FFFF

0188 0000 – 018B FFFF

018C 0000 – 018F FFFF

0190 0000 – 0193 FFFF

0194 0000 – 0197 FFFF

0198 0000 – 019B FFFF

019C 0000 – 019F FFFF

01A0 0000 – 01A3 FFFF

01A4 0000 – 01FF FFFF

0200 0000 – 0200 0033

0200 0034 – 2FFF FFFF

3000 0000 – 3FFF FFFF

4000 0000 – 7FFF FFFF

8000 0000 – 8FFF FFFF

9000 0000 – 9FFF FFFF

A000 0000 – AFFF FFFF

B000 0000 – BFFF FFFF

C000 0000 – FFFF FFFF

64K

24M – 64K

256K

Reserved

External Memory Interface (EMIF) Registers

L2 Registers

256K

HPI Registers

256K

McBSP 0 Registers

McBSP 1 Registers

Timer 0 Registers

256K

Timer 1 Registers

256K

Interrupt Selector Registers

EDMA RAM and EDMA Registers

Reserved

256K

6M – 256K

52

QDMA Registers

Reserved

736M – 52

256M

1G

McBSP 0/1 Data

Reserved

†

EMIF CE0

EMIF CE1

EMIF CE2

EMIF CE3

256M

1G

Reserved

†

The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of

addressable memory, additional general-purpose output pin or external logic is required.

9

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

peripheral register descriptions

Table 3 through Table 13 identify the peripheral registers for the C6711/C6711B device by their register names,

acronyms, and hex address or hex address range. For more detailed information on the register contents, bit

names, and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number

SPRU190).

Table 3. EMIF Registers

HEX ADDRESS RANGE

0180 0000

ACRONYM

GBLCTL

CECTL1

CECTL0

–

REGISTER NAME

EMIF global control

EMIF CE1 space control

EMIF CE0 space control

Reserved

0180 0004

0180 0008

0180 000C

0180 0010

CECTL2

CECTL3

SDCTL

SDTIM

SDEXT

–

EMIF CE2 space control

EMIF CE3 space control

EMIF SDRAM control

EMIF SDRAM refresh control

EMIF SDRAM extension

Reserved

0180 0014

0180 0018

0180 001C

0180 0020

0180 0024 – 0183 FFFF

Table 4. L2 Cache Registers

HEX ADDRESS RANGE

0184 0000

ACRONYM

CCFG

REGISTER NAME

Cache configuration register

0184 4000

L2FBAR

L2FWC

L2CBAR

L2CWC

L1PFBAR

L1PFWC

L1DFBAR

L1DFWC

L2FLUSH

L2CLEAN

MAR0

L2 flush base address register

0184 4004

L2 flush word count register

0184 4010

L2 clean base address register

0184 4014

L2 clean word count register

0184 4020

L1P flush base address register

0184 4024

L1P flush word count register

0184 4030

L1D flush base address register

0184 4034

L1D flush word count register

0184 5000

L2 flush register

0184 5004

L2 clean register

0184 8200

Controls CE0 range 8000 0000 – 80FF FFFF

Controls CE0 range 8100 0000 – 81FF FFFF

Controls CE0 range 8200 0000 – 82FF FFFF

Controls CE0 range 8300 0000 – 83FF FFFF

Controls CE1 range 9000 0000 – 90FF FFFF

Controls CE1 range 9100 0000 – 91FF FFFF

Controls CE1 range 9200 0000 – 92FF FFFF

Controls CE1 range 9300 0000 – 93FF FFFF

Controls CE2 range A000 0000 – A0FF FFFF

Controls CE2 range A100 0000 – A1FF FFFF

Controls CE2 range A200 0000 – A2FF FFFF

Controls CE2 range A300 0000 – A3FF FFFF

Controls CE3 range B000 0000 – B0FF FFFF

Controls CE3 range B100 0000 – B1FF FFFF

Controls CE3 range B200 0000 – B2FF FFFF

Controls CE3 range B300 0000 – B3FF FFFF

Reserved

0184 8204

MAR1

0184 8208

MAR2

0184 820C

0184 8240

MAR3

MAR4

0184 8244

MAR5

0184 8248

MAR6

0184 824C

0184 8280

MAR7

MAR8

0184 8284

MAR9

0184 8288

MAR10

MAR11

MAR12

MAR13

MAR14

MAR15

–

0184 828C

0184 82C0

0184 82C4

0184 82C8

0184 82CC

0184 82D0 – 0187 FFFF

10

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

peripheral register descriptions (continued)

Table 5. EDMA Registers

HEX ADDRESS RANGE

01A0 FF9C – 01A0 FFDC

01A0 FFE0

ACRONYM

–

REGISTER NAME

Reserved

PQSR

CIPR

CIER

CCER

ER

Priority queue status register

Channel interrupt pending register

Channel interrupt enable register

Channel chain enable register

Event register

01A0 FFE4

01A0 FFE8

01A0 FFEC

01A0 FFF0

01A0 FFF4

EER

ECR

ESR

–

Event enable register

Event clear register

01A0 FFF8

01A0 FFFC

Event set register

01A1 0000 – 01A3 FFFF

Reserved

†

Table 6. EDMA Parameter RAM

HEX ADDRESS RANGE

01A0 0000 – 01A0 0017

01A0 0018 – 01A0 002F

01A0 0030 – 01A0 0047

01A0 0048 – 01A0 005F

01A0 0060 – 01A0 0077

01A0 0078 – 01A0 008F

01A0 0090 – 01A0 00A7

01A0 00A8 – 01A0 00BF

01A0 00C0 – 01A0 00D7

01A0 00D8 – 01A0 00EF

01A0 00F0 – 01A0 00107

01A0 0108 – 01A0 011F

01A0 0120 – 01A0 0137

01A0 0138 – 01A0 014F

01A0 0150 – 01A0 0167

01A0 0168 – 01A0 017F

01A0 0180 – 01A0 0197

01A0 0198 – 01A0 01AF

...

ACRONYM

REGISTER NAME

–

Parameters for Event 0 (6 words)

Parameters for Event 1 (6 words)

Parameters for Event 2 (6 words)

Parameters for Event 3 (6 words)

Parameters for Event 4 (6 words)

Parameters for Event 5 (6 words)

Parameters for Event 6 (6 words)

Parameters for Event 7 (6 words)

Parameters for Event 8 (6 words)

Parameters for Event 9 (6 words)

Parameters for Event 10 (6 words)

Parameters for Event 11 (6 words)

Parameters for Event 12 (6 words)

Parameters for Event 13 (6 words)

Parameters for Event 14 (6 words)

Parameters for Event 15 (6 words)

Reload/link parameters for Event M (6 words)

Reload/link parameters for Event N (6 words)

...

01A0 07E0 – 01A0 07F7

01A0 07F8 – 01A0 07FF

–

Reload/link parameters for Event Z (6 words)

Scratch pad area (2 words)

†

The C6711/C6711B device has sixty-nine parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

peripheral register descriptions (continued)

†

Table 7. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE

0200 0000

ACRONYM

QOPT

QSRC

QCNT

QDST

QIDX

REGISTER NAME

QDMA options parameter register

QDMA source address register

QDMA frame count register

QDMA destination address register

QDMA index register

0200 0004

0200 0008

0200 000C

0200 0010

0200 0014 – 0200 001C

0200 0020

–

Reserved

QSOPT

QSSRC

QSCNT

QSDST

QSIDX

QDMA pseudo options register

0200 0024

QDMA pseudo source address register

QDMA pseudo frame count register

QDMA pseudo destination address register

QDMA pseudo index register

0200 0028

0200 002C

0200 0030

†

All the QDMA and Pseudo registers are write-accessible only

Table 8. Interrupt Selector Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Selects which interrupts drive CPU interrupts 10–15

(INT10–INT15)

019C 0000

MUXH

Interrupt multiplexer high

Selects which interrupts drive CPU interrupts 4–9

(INT04–INT09)

019C 0004

MUXL

Interrupt multiplexer low

Sets the polarity of the external interrupts

(EXT_INT4–EXT_INT7)

019C 0008

EXTPOL

External interrupt polarity

Reserved

019C 000C – 019F FFFF

–

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

peripheral register descriptions (continued)

Table 9. McBSP 0 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

The CPU and DMA/EDMA

controller can only read this

register; they cannot write to

it.

018C 0000

DRR0

McBSP0 data receive register via Peripheral Bus

0x3000 0000 – 0x33FF FFFF

018C 0004

DRR0

DXR0

SPCR0

RCR0

XCR0

SRGR0

MCR0

RCER0

XCER0

PCR0

–

McBSP0 data receive register via EDMA Bus

McBSP0 data transmit register via Peripheral Bus

McBSP0 data transmit register via EDMA Bus

McBSP0 serial port control register

McBSP0 receive control register

0x3000 0000 – 0x33FF FFFF

018C 0008

018C 000C

018C 0010

McBSP0 transmit control register

018C 0014

McBSP0 sample rate generator register

McBSP0 multichannel control register

McBSP0 receive channel enable register

McBSP0 transmit channel enable register

McBSP0 pin control register

018C 0018

018C 001C

018C 0020

018C 0024

018C 0028 – 018F FFFF

Reserved

Table 10. McBSP 1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

The CPU and DMA/EDMA

controller can only read this

register; they cannot write to

it.

0190 0000

DRR1

Data receive register via Peripheral Bus

0x3400 0000 – 0x37FF FFFF

0190 0004

DRR1

DXR1

SPCR1

RCR1

XCR1

SRGR1

MCR1

RCER1

XCER1

PCR1

–

McBSP1 data receive register via EDMA Bus

McBSP1 data transmit register via Peripheral Bus

McBSP1 data transmit register via EDMA Bus

McBSP1 serial port control register

McBSP1 receive control register

0x3400 0000 – 0x37FF FFFF

0190 0008

0190 000C

0190 0010

McBSP1 transmit control register

0190 0014

McBSP1 sample rate generator register

McBSP1 multichannel control register

McBSP1 receive channel enable register

McBSP1 transmit channel enable register

McBSP1 pin control register

0190 0018

0190 001C

0190 0020

0190 0024

0190 0028 – 0193 FFFF

Reserved

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

peripheral register descriptions (continued)

Table 11. Timer 0 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Determines the operating mode of the timer,

monitors the timer status, and controls the function

of the TOUT pin.

0194 0000

CTL0

Timer 0 control register

Timer 0 period register

Contains the number of timer input clock cycles to

count. This number controls the TSTAT signal

frequency.

0194 0004

PRD0

Contains the current value of the incrementing

counter.

0194 0008

CNT0

Timer 0 counter register

Reserved

0194 000C – 0197 FFFF

–

Table 12. Timer 1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Determines the operating mode of the timer,

monitors the timer status, and controls the function

of the TOUT pin.

0198 0000

CTL1

Timer 1 control register

Contains the number of timer input clock cycles to

count. This number controls the TSTAT signal

frequency.

0198 0004

PRD1

Timer 1 period register

Contains the current value of the incrementing

counter.

0198 0008

CNT1

Timer 1 counter register

Reserved

0198 000C – 019B FFFF

–

Table 13. HPI Registers

HEX ADDRESS RANGE

ACRONYM

HPID

HPIA

HPIC

–

REGISTER NAME

HPI data register

COMMENTS

Host read/write access only

Both Host/CPU read/write access

–

HPI address register

HPI control register

Reserved

0188 0000

0188 0001 – 018B FFFF

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

PWRD bits in CPU CSR register description

Table 14 identifies the PWRD field (bits 15–10) in the CPU CSR register. These bits control the device

power-down modes. For more detailed information on the PWRD bit field of the CPU CSR register, see the

TMS320C6000 Peripherals Reference Guide (literature number SPRU190).

Table 14. PWRD field bits in the CPU CSR Register

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

The PWRD field (bits 15–10 in the CPU CSR)

controls the device power-down modes.

–

CSR

Control status register

Accessible by writing a value to the CSR register.

15

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

EDMA channel synchronization events

The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8–11) are reserved

for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. Table 15 lists the source

of synchronization events associated with each of the programmable EDMA channels. For the C6711/11B, the

association of an event to a channel is fixed; each of the EDMA channels has one specific event associated

with it. For more detailed information on the EDMA module, associated channels, and event-transfer chaining,

see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number

SPRU190).

Table 15. TMS320C6711/C6711B EDMA Channel Synchronization Events

EDMA

CHANNEL

EVENT NAME

EVENT DESCRIPTION

Host-port interface (HPI)-to-DSP interrupt

0

1

2

3

4

5

6

7

DSP_INT

TINT0

Timer 0 interrupt

TINT1

Timer 1 interrupt

SD_INT

EMIF SDRAM timer interrupt

External interrupt pin 4

EXT_INT4

EXT_INT5

EXT_INT6

EXT_INT7

EDMA_TCC8

EDMA_TCC9

EDMA_TCC10

EDMA_TCC11

XEVT0

External interrupt pin 5

External interrupt pin 6

External interrupt pin 7

†

8

9

EDMA transfer complete code (TCC) 1000b interrupt

EDMA TCC 1001b interrupt

EDMA TCC 1010b interrupt

EDMA TCC 1011b interrupt

McBSP0 transmit event

McBSP0 receive event

†

10

†

11

12

13

14

15

REVT0

XEVT1

McBSP1 transmit event

McBSP1 receive event

REVT1

†

EDMA channels 8 through 11 are used for transfer chaining only. For more detailed information on event-transfer chaining, see the EDMA

Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

interrupt sources and interrupt selector

The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 16. The highest-priority interrupt

is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts

(INT_00–INT_03) are non-maskable and fixed. The remaining interrupts (INT_04–INT_15) are maskable and

default to the interrupt source specified in Table 16. The interrupt source for interrupts 4–15 can be programmed

by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control

registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).

Table 16. C6711/C6711B DSP Interrupts

INTERRUPT

CPU

INTERRUPT

NUMBER

SELECTOR

VALUE

(BINARY)

INTERRUPT

EVENT

SELECTOR

CONTROL

REGISTER

INTERRUPT SOURCE

†

‡

INT_00

INT_01

INT_02

INT_03

INT_04

INT_05

INT_06

INT_07

INT_08

INT_09

INT_10

–

RESET

NMI

–

Reserved

EXT_INT4

EXT_INT5

EXT_INT6

EXT_INT7

EDMA_INT

Reserved

SD_INT

Reserved

DSP_INT

TINT0

Reserved. Do not use.

–

Reserved. Do not use.

MUXL[4:0]

MUXL[9:5]

MUXL[14:10]

MUXL[20:16]

MUXL[25:21]

MUXL[30:26]

MUXH[4:0]

MUXH[9:5]

MUXH[14:10]

MUXH[20:16]

MUXH[25:21]

MUXH[30:26]

–

00100

00101

00110

00111

01000

01001

00011

01010

01011

00000

00001

00010

01100

01101

01110

01111

10000 – 11111

External interrupt pin 4

External interrupt pin 5

External interrupt pin 6

External interrupt pin 7

EDMA channel (0 through 15) interrupt

None, but programmable

EMIF SDRAM timer interrupt

None, but programmable

Host-port interface (HPI)-to-DSP interrupt

Timer 0 interrupt

‡

INT_11

‡

INT_12

INT_13

INT_14

INT_15

TINT1

Timer 1 interrupt

–

XINT0

McBSP0 transmit interrupt

McBSP0 receive interrupt

McBSP1 transmit interrupt

McBSP1 receive interrupt

Reserved. Do not use.

–

RINT0

–

XINT1

–

RINT1

–

Reserved

†

‡

Interrupts INT_00 through INT_03 are non-maskable and fixed.

InterruptsINT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control

registers fields. Table 16 shows the default interrupt sources for interrupts INT_04 through INT_15. For more detailed

information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the

TMS320C6000 Peripherals Reference Guide (literature number SPRU190).

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

signal groups description

CLKIN

CLKOUT2

CLKOUT1

RESET

NMI

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

Reset and

Interrupts

CLKMODE0

Clock/PLL

PLLV

PLLG

PLLF

TMS

TDO

TDI

RSV5

RSV4

RSV3

RSV2

RSV1

RSV0

TCK

IEEE Standard

1149.1

(JTAG)

Emulation

TRST

EMU0

EMU1

EMU2

EMU3

EMU4

EMU5

Reserved

Control/Status

HPI

16

(Host-Port Interface)

HD[15:0]

Data

HAS

HCNTL0

HCNTL1

HR/W

HCS

HDS1

HDS2

HRDY

HINT

Register Select

Control

Half-Word

Select

HHWIL

Figure 2. CPU (DSP Core) and Peripheral Signals

18

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

signal groups description (continued)

32

ED[31:0]

Data

ECLKIN

ECLKOUT

Memory

Control

ARE/SDCAS/SSADS

CE3

CE2

CE1

CE0

AOE/SDRAS/SSOE

AWE/SDWE/SSWE

ARDY

Memory Map

Space Select

20

EA[21:2]

Address

HOLD

HOLDA

Bus

Arbitration

BE3

BE2

BE1

BE0

BUSREQ

Byte Enables

EMIF

(External Memory Interface)

TOUT1

TINP1

TOUT0

TINP0

Timer 1

Timer 0

Timers

McBSP1

Transmit

McBSP0

Transmit

CLKX1

FSX1

DX1

CLKX0

FSX0

DX0

CLKR1

FSR1

DR1

CLKR0

FSR0

DR0

Receive

Clock

Receive

Clock

CLKS1

CLKS0

McBSPs

(Multichannel Buffered Serial Ports)

Figure 3. Peripheral Signals

19

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions

SIGNAL

NAME

IPD/

IPU

†

DESCRIPTION

TYPE

‡

NO.

CLOCK/PLL

CLKIN

A3

D7

I

IPD

Clock Input

CLKOUT1

CLKOUT2

O

Clock output at device speed

Clock output at half of device speed

Clock mode select

Y12

CLKMODE0

C4

I

IPU

•

Selects whether the CPU clock frequency = input clock frequency x4 or x1

§

¶

A

¶

A

¶

A

PLLV

A4

C6

B5

PLL analog V connection for the low-pass filter

CC

§

PLLG

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

PLLF

TMS

TDO

TDI

B7

A8

I

IPU

IPD

IPU

JTAG test-port mode select

O/Z

JTAG test-port data out

A7

I

JTAG test-port data in

TCK

A6

JTAG test-port clock

TRST

EMU5

EMU4

EMU3

EMU2

EMU1

EMU0

B6

JTAG test-port reset

B12

C11

B10

D10

B9

I/O/Z

Emulation pin 5. Reserved for future use, leave unconnected.

Emulation pin 4. Reserved for future use, leave unconnected.

Emulation pin 3. Reserved for future use, leave unconnected.

Emulation pin 2. Reserved for future use, leave unconnected.

#

Emulation pin 1

Emulation pin 0

#

D9

RESETS AND INTERRUPTS

Device reset

Nonmaskable interrupt

Edge-driven (rising edge)

RESET

NMI

A13

C13

I

IPU

IPD

•

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

E3

D2

C1

C2

External interrupts

•

Edge-driven

I

IPU

Polarity independently selected via the External Interrupt Polarity Register bits

(EXTPOL.[3:0])

HOST-PORT INTERFACE (HPI)

HINT

J20

G19

G18

H20

G20

O

I

IPU

Host interrupt (from DSP to host)

HCNTL1

HCNTL0

HHWIL

HR/W

Host control – selects between control, address, or data registers

Host half-word select – first or second half-word (not necessarily high or low order)

Host read or write select

I

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-kΩ resistor should be used.)

PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these

§

pins.

¶

#

A = Analog signal (PLL Filter)

The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external

pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ

resistor.

20

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

IPD/

IPU‡

†

TYPE

DESCRIPTION

HOST-PORT INTERFACE (HPI) (CONTINUED)

NO.

HD15

B14

C14

A15

C15

A16

B16

C16

B17

A18

C17

B18

C19

C20

D18

D20

E20

E18

F20

E19

F18

H19

IPU

IPD

IPU

IPD

HD14

HD13

HD12

HD11

HD10

HD9

Host-port data

•

Used for transfer of data, address, and control

Also controls initialization of DSP modes at reset via pullup/pulldown resistors

– Device Endian mode

HD8: 0 – Big Endian

HD8

I/O/Z

1 – Little Endian

HD7

– Boot mode

HD[4:3]: 00 – HPI boot

01 – 8-bit ROM boot with default timings

HD6

HD5

10 – 16-bit ROM boot with default timings

11 – 32-bit ROM boot with default timings

HD4

HD3

HD2

HD1

HD0

HAS

HCS

HDS1

HDS2

HRDY

I

Host address strobe

Host chip select

I

Host data strobe 1

I

Host data strobe 2

O

Host ready (from DSP to host)

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

CE3

CE2

CE1

CE0

BE3

BE2

BE1

BE0

V6

W6

W18

V17

V5

O/Z

IPU

Memory space enables

IPU

•

Enabled by bits 28 through 31 of the word address

Only one asserted during any external data access

IPU

Byte-enable control

Y4

•

Decoded from the two lowest bits of the internal address

Byte-write enables for most types of memory

Can be directly connected to SDRAM read and write mask signal (SDQM)

U19

V20

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-kΩ resistor should be used.)

21

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FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

IPD/

IPU

†

TYPE

DESCRIPTION

‡

NO.

EMIF – BUS ARBITRATION

Hold-request-acknowledge to the host

Hold request from the host

HOLDA

HOLD

J18

J17

J19

O

I

IPU

BUSREQ

O

Bus request output

EMIF – ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL

ECLKIN

Y11

Y10

I

IPD

EMIF input clock

ECLKOUT

O

EMIF output clock (based on ECLKIN)

ARE/SDCAS/

SSADS

V11

O/Z

IPU

Asynchronousmemoryreadenable/SDRAMcolumn-addressstrobe/SBSRAMaddressstrobe

Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable

Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable

AOE/SDRAS/

SSOE

W10

AWE/SDWE/

SSWE

V12

Y5

O/Z

I

IPU

ARDY

Asynchronous memory ready input

EMIF – ADDRESS

EA21

EA20

EA19

EA18

EA17

EA16

EA15

EA14

EA13

EA12

EA11

EA10

EA9

U18

Y18

W17

Y16

V16

Y15

W15

Y14

W14

V14

W13

V10

Y9

O/Z

IPU

External address (word address)

EA8

V9

EA7

Y8

EA6

W8

V8

EA5

EA4

W7

V7

EA3

EA2

Y6

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-kΩ resistor should be used.)

22

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

IPD/

IPU‡

†

TYPE

DESCRIPTION

NO.

EMIF – DATA

ED31

N3

P3

ED30

ED29

ED28

ED27

ED26

ED25

ED24

ED23

ED22

ED21

ED20

ED19

ED18

ED17

ED16

ED15

ED14

ED13

ED12

ED11

ED10

ED9

P2

P1

R2

R3

T2

T1

U3

U1

U2

V1

V2

Y3

W4

V4

I/O/Z

IPU

External data

T19

T20

T18

R20

R19

P20

P18

N20

N19

N18

M20

M19

L19

L18

K19

K18

ED8

ED7

ED6

ED5

ED4

ED3

ED2

ED1

ED0

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-kΩ resistor should be used.)

23

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

IPD/

IPU‡

†

TYPE

DESCRIPTION

NO.

TIMER 1

Timer 1 or general-purpose output

Timer 1 or general-purpose input

TIMER 0

TOUT1

F1

F2

O

I

IPD

TINP1

TOUT0

TINP0

G1

G2

O

I

IPD

Timer 0 or general-purpose output

Timer 0 or general-purpose input

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

CLKS1

CLKR1

CLKX1

DR1

E1

M1

L3

I

IPD

IPU

IPD

External clock source (as opposed to internal)

Receive clock

I/O/Z

I

Transmit clock

M2

L2

Receive data

DX1

O/Z

I/O/Z

Transmit data

FSR1

FSX1

M3

L1

Receive frame sync

Transmit frame sync

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

CLKS0

CLKR0

CLKX0

DR0

K3

H3

G3

J1

I

IPD

IPU

IPD

External clock source (as opposed to internal)

Receive clock

I/O/Z

I

Transmit clock

Receive data

DX0

H2

J3

O/Z

I/O/Z

Transmit data

FSR0

FSX0

Receive frame sync

H1

Transmit frame sync

RESERVED FOR TEST

RSV0

RSV1

RSV2

RSV3

RSV4

RSV5

C12

D12

A5

O

IPU

Reserved (leave unconnected, do not connect to power or ground)

D3

N2

Y20

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-kΩ resistor should be used.)

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

SUPPLY VOLTAGE PINS

NO.

A17

B3

B8

B13

C5

C10

D1

D16

D19

F3

H18

J2

M18

N1

R1

DV

S

3.3-V supply voltage

DD

R18

T3

U5

U7

U12

U16

V13

V15

V19

W3

W9

W12

Y7

Y17

A9

A10

A12

B2

B19

C3

CV

S

1.8-V supply voltage

DD

C7

C18

D5

D6

D11

D14

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

SUPPLY VOLTAGE PINS (CONTINUED)

NO.

D15

F4

F17

K1

K4

K17

L4

L17

L20

R4

CV

S

1.8-V supply voltage

DD

R17

U6

U10

U11

U14

U15

V3

V18

W2

W19

GROUND PINS

A1

A2

A11

A14

A19

A20

B1

B4

B11

B15

B20

C8

V

SS

GND

Ground pins

C9

D4

D8

D13

D17

E2

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

Terminal Functions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

GROUND PINS (CONTINUED)

NO.

E4

E17

F19

G4

G17

H4

H17

J4

K2

K20

M4

M17

N4

N17

P4

P17

P19

T4

V

SS

GND

Ground pins

T17

U4

U8

U9

U13

U17

U20

W1

W5

W11

W16

W20

Y1

Y2

Y13

Y19

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

development support

TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to

evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules.

The following products support development of C6000 DSP-based applications:

Software Development Tools:

Code Composer Studio Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS ), which provides the basic run-time target software

needed to support any DSP application.

Hardware Development Tools:

Extended Development System (XDS ) Emulator (supports C6000 DSP multiprocessor system debug)

EVM (Evaluation Module)

The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about

development-support products for all TMS320 DSP family member devices, including documentation. See

thisdocumentforfurtherinformationonTMS320 DSPdocumentationoranyTMS320 DSPsupportproducts

from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide

(SPRU052), contains information about TMS320 DSP-related products from other companies in the industry.

To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924.

For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select

“Find Development Tools”. For device-specific tools, under “Semiconductor Products”, select “Digital Signal

Processors”, choose a product family, and select the particular DSP device. For information on pricing and

availability, contact the nearest TI field sales office or authorized distributor.

Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.

28

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

device and development-support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three

prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from

engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical

specifications

Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example,GFN), the temperature range (for example, blank is the default commercial temperature range),

and the device speed range in megahertz (for example, -150 is 150 MHz).

Figure 4 provides a legend for reading the complete device name for any TMS3206000 DSP family member.

29

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

device and development-support tool nomenclature (continued)

Table 17. TMS320C6711/C6711B Device Part Numbers (P/Ns) and Ordering Information

OPERATING CASE

TEMPERATURE

RANGE

CV

DV

DD

DEVICE ORDERABLE P/N

DEVICE SPEED

(CORE VOLTAGE)

(I/O VOLTAGE)

C6711

TMS320C6711GFN150

TMS320C6711GFN100

C6711B

150 MHz/900 MFLOPS

100 MHz/600 MFLOPS

1.8 V

3.3 V

0_C to 90_C

TMS320C6711BGFN150

TMS320C6711BGFN100

TMS320C6711BGFNA100

150 MHz/900 MFLOPS

100 MHz/600 MFLOPS

1.8 V

3.3 V

0_C to 90_C

–40_C to105_C

(

)

TMS 320

C

6711 GFN

150

PREFIX

DEVICE SPEED RANGE

TMX= Experimental device

TMP= Prototype device

100 MHz

120 MHz

150 MHz

167 MHz

200 MHz

233 MHz

250 MHz

300 MHz

TMS= Qualified device

SMJ = MIL-PRF-38535, QML

SM = High Rel (non-38535)

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

Blank = 0°C to 90°C, commercial temperature

A

= –40°C to 105°C, extended temperature

DEVICE FAMILY

320 = TMS320 DSP family

†

PACKAGE TYPE

GFN = 256-pin plastic BGA

GGP = 352-pin plastic BGA

GJC = 352-pin plastic BGA

GJL = 352-pin plastic BGA

GLS = 384-pin plastic BGA

GLW = 340-pin plastic BGA

GHK = 288-pin plastic MicroStar BGAt

TECHNOLOGY

C

= CMOS

DEVICE

C6000 DSP:

6201

6204

6205

6211

6211B

6414

6415

6416

6701

6711

6711B

6712

6202

6202B

6203B

6203C

†

BGA

=

Ball Grid Array

Figure 4. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6711

and TMS320C6711B Devices)

MicroStar BGA is a trademark of Texas Instruments.

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

documentation support

Extensive documentation supports all TMS320

DSP family generations of devices from product

announcement through applications development. The types of documentation available include: data sheets,

such as this document, with design specifications; complete user’s reference guides for all devices and tools;

technical briefs; development-support tools; on-line help; and hardware and software applications. The

following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of

the peripherals available on the C6000 DSP platform of devices, such as the external memory interface

(EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA),

enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop

(PLL); and power-down modes. This guide also includes information on internal data and program memories.

The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the

TMS320C62x /TMS320C67x devices, associated development tools, and third-party support.

The tools support documentation is electronically available within the Code Composer Studio Integrated

Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

See the Worldwide Web URL for the application reports How To Begin Development Today with the

TMS320C6211 DSP (literature number SPRA474) and How To Begin Development with the TMS320C6711

DSP(literaturenumberSPRA522), whichdescribeinmoredetailthesimilarities/differencesbetweentheC6211

and C6711 C6000 DSP devices.

TMS320C62x is a trademark of Texas Instruments.

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

clock PLL

All of the internal C67x clocks are generated from a single source through the CLKIN pin. This source clock

either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or

bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5

shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 6 shows the

external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.

To minimize the clock jitter, a single clean power supply should power both the C67x device and the external

clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise

and fall times should also be observed. For the input clock timing requirements, see the input and output clocks

electricals section.

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source

must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended

ranges of suppy voltage and operating case temperature table and the input and output clocks electricals

section). Table 18 lists some examples of compatible CLKIN external clock sources:

Table 18. Compatible CLKIN External Clock Sources

COMPATIBLE PARTS FOR

EXTERNAL CLOCK SOURCES (CLKIN)

PART NUMBER

MANUFACTURER

JITO-2

STA series, ST4100 series

SG-636

Fox Electronix

SaRonix Corporation

Epson America

Oscillators

342

Corning Frequency Control

Integrated Circuit Systems

PLL

MK1711-S, ICS525-02

3.3V

PLLV

Internal to

PLL

C6711/C6711B

CLKMODE0

PLLMULT

CLKIN

C4

C3

PLLCLK

0.1 mF

10 mF

CLKIN

1

0

CPU

CLOCK

LOOP FILTER

Available Multiply Factors

CPU Clock

Frequency

f(CPUCLOCK)

PLL Multiply

Factors

C2

CLKMODE0

(For C1, C2, and R1 values, see Table 19.)

0

1

x1(BYPASS)

x4

1 x f(CLKIN)

4 x f(CLKIN)

C1

R1

NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,

place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 device as possible. For the best

performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or

components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,

and the EMI filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV

D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.

.

DD

Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

clock PLL (continued)

3.3V

PLLV

Internal to

PLL

C6711/C6711B

CLKMODE0

CLKIN

PLLMULT

CLKIN

PLLCLK

1

0

LOOP FILTER

CPU

CLOCK

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.

B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV

.

DD

Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only

Table 19. C6711/C6711B PLL Component Selection

CPU CLOCK

FREQUENCY

(CLKOUT1)

CLKIN

RANGE

(MHz)

CLKOUT2

RANGE

(MHz)

TYPICAL

R1 [±1%]

(Ω)

C1 [±10%]

C2 [±10%]

CLKMODE

LOCK TIME

(nF)

(pF)

†

(µs)

RANGE (MHz)

x4

16.3–41.6

65–167

32.5–83

60.4

27

560

75

†

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

power-supply sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,

systems should be designed to ensure that neither supply is powered up for extended periods of time if the other

supply is below the proper operating voltage.

system-level design considerations

System-level design considerations, such as bus contention, may require supply sequencing to be

implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered

down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the

output buffers are powered up, thus, preventing bus contention with other chips on the board.

power-supply design considerations

For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess

of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic

within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the

I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the

PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A

normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing

the amount of time between the core supply power up and the I/O supply power up can minimize the effects

of this current draw.

A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx

plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the

TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used

to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the

logic within the DSP.

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize

inductance and resistance in the power delivery path. Additionally, when designing for high-performance

applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for

core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

†

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Supply voltage range, CV

Supply voltage range, DV

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

DD

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Operating case temperature ranges, T :(default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C

C

(A version) [C6711BGFNA only] . . . . . . . . . . . . . . –40_C to105_C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

SS

.

recommended operating conditions

MIN NOM

MAX UNIT

CV

DV

Supply voltage, Core

Supply voltage, I/O

Supply ground

1.71

3.14

0

1.8

3.3

0

1.89

3.46

0

V

DD

V

SS

High-level input voltage

Low-level input voltage

2

V

IH

IL

0.8

–4

–8

4

V

All signals except CLKOUT1, CLKOUT2, and ECLKOUT

CLKOUT1, CLKOUT2, and ECLKOUT

All signals except CLKOUT1, CLKOUT2, and ECLKOUT

CLKOUT1, CLKOUT2, and ECLKOUT

Default

mA

_C

I

High-level output current

Low-level output current

Operating case temperature

OH

OL

8

0

90

105

T

C

A version (C6711BGFNA only)

–40

electrical characteristics over recommended ranges of supply voltage and operating case

temperature (unless otherwise noted)

‡

PARAMETER

High-level output voltage

Low-level output voltage

Input current

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

DV

= MIN,

I

= MAX

2.4

OH

DD

OH

OL

0.4

±150

±10

V

OL

I

V = V

I

to DV

uA

mA

pF

SS

= DV

DD

or 0 V

I

Off-state output current

V

O DD

C6711, CV

OZ

= NOM, CPU clock = 150 MHz

410

220

60

Supply current, CPU + CPU memory

DD

I

DD2V

§

access

C6711B, CV

DD

= NOM, CPU clock = 150 MHz

C6711, CV

DD

§

Supply current, peripherals

DD2V

DD3V

C6711B, CV

= NOM, CPU clock = 150 MHz

DD

C6711, DV

DD

§

Supply current, I/O pins

C6711B, DV

DD

= NOM, CPU clock = 150 MHz

60

C

Input capacitance

Output capacitance

7

i

pF

o

‡

§

For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, refer to the TMS320C6000

Power Consumption Summary application report (literature number SPRA486).

35

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

PARAMETER MEASUREMENT INFORMATION

I

OL

Tester Pin

Electronics

Output

Under

Test

50 Ω

V

comm

C

T

I

OH

Where:

I

V

=

2 mA

0.8 V

OL

OH

comm

T

C

10–15-pF typical load-circuit capacitance

Figure 7. Test Load Circuit for AC Timing Measurements

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

V

ref

= 1.5 V

Figure 8. Input and Output Voltage Reference Levels for ac Timing Measurements

All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, and

IL

IH

V

MAX and V

MIN for output clocks.

OL

OH

V

ref

= V MIN (or V

IH

MIN)

OH

V

ref

= V MAX (or V

IL

MAX)

OL

Figure 9. Rise and Fall Transition Time Voltage Reference Levels

36

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TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

timing parameters and board routing analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good

board design practice, such delays must always be taken into account. Timing values may be adjusted by

increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification

(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers

may be used to compensate any timing differences. For example:

D

In typical boards with the C6711B commercial temperature device, the routing delay improves the external

memory’s ability to meet the DSP’s EMIF data input hold time requirement [t ].

h(EKOH-EDV)

In some boards with the C6711BGFNA extended temperature device, the routing delay improves the

external memory’s ability to meet the DSP’s EMIF data input hold time requirement [t ]. In

h(EKOH-EDV)

addition, it may be necessary to add an extra delay to the input clock of the external memory to robustly

meet the DSP’s data input hold time requirement. If the extra delay approach is used, memory bus

frequency adjustments may be needed to ensure the DPS’s input setup time requirement [t

is still maintained.

]

su(EDV-EKOH)

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and

fromtheexternaldevicetotheDSP. Thisround-tripdelaytendstonegativelyimpacttheinputsetuptimemargin,

but also tends to improve the input hold time margins (see Table 20 and Figure 10).

Figure 10 represents a general transfer between the DSP and an external device. The figure also represents

board route delays and how they are perceived by the DSP and the external device.

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

Table 20. IBIS Timing Parameters Example (see Figure 10)

NO.

1

DESCRIPTION

Clock route delay

2

Minimum DSP hold time

3

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

4

5

6

7

8

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

9

10

11

ECLKOUT

(Output from DSP)

1

ECLKOUT

(Input to External Device)

2

3

†

Control Signals

(Output from DSP)

4

5

6

Control Signals

(Input to External Device)

7

8

‡

Data Signals

(Output from External Device)

9

10

11

‡

Data Signals

(Input to DSP)

† Control signals include data for Writes.

‡ Data signals are generated during Reads from an external device.

Figure 10. IBIS Input/Output Timings

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

INPUT AND OUTPUT CLOCKS

†‡

timing requirements for CLKIN (see Figure 11)

–100

CLKMODE = x4 CLKMODE = x1

–150

CLKMODE = x4 CLKMODE = x1

NO.

UNIT

MIN

40

MAX

MIN

10

MAX

MIN

26.7

0.4C

MAX

MIN

6.7

MAX

1

2

3

4

t

Cycle time, CLKIN

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.4C

0.45C

5

1

5

1

†

‡

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

C = CLKIN cycle time in ns. For example, when CLKIN frequency is 40 MHz, use C = 25 ns.

IL

IH

1

4

2

CLKIN

3

4

Figure 11. CLKIN Timings

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

INPUT AND OUTPUT CLOCKS (CONTINUED)

†‡§

switching characteristics over recommended operating conditions for CLKOUT1

(see Figure 12)

–100

–150

NO.

PARAMETER

UNIT

CLKMODE = x4

CLKMODE = x1

MIN

MAX

P + 0.7

MIN

MAX

1

2

3

4

t

Cycle time, CLKOUT1

P – 0.7

P + 0.7

ns

c(CKO1)

w(CKO1H)

w(CKO1L)

t(CKO1)

Pulse duration, CLKOUT1 high

Pulse duration, CLKOUT1 low

Transition time, CLKOUT1

(P/2) – 0.7 (P/2 ) + 0.7 PH – 0.7 PH + 0.7

(P/2) – 0.7 (P/2 ) + 0.7

PL – 0.7

PL + 0.7

2

†

‡

§

The reference points for the rise and fall transitions are measured at V

P = 1/CPU clock frequency in nanoseconds (ns)

PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

MAX and V

MIN.

OH

OL

1

4

2

CLKOUT1

3

4

Figure 12. CLKOUT1 Timings

†‡

switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 13)

–100

–150

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

4

t

Cycle time, CLKOUT2

2P – 0.7 2P + 0.7

ns

c(CKO2)

w(CKO2H)

w(CKO2L)

t(CKO2)

Pulse duration, CLKOUT2 high

Pulse duration, CLKOUT2 low

Transition time, CLKOUT2

P – 0.7

P + 0.7

2

†

‡

The reference points for the rise and fall transitions are measured at V

P = 1/CPU clock frequency in ns

MAX and V

MIN.

OH

OL

1

4

2

CLKOUT2

3

4

Figure 13. CLKOUT2 Timings

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

INPUT AND OUTPUT CLOCKS (CONTINUED)

†

timing requirements for ECLKIN (see Figure 14)

–100

MIN

–150

MIN

NO.

UNIT

MAX

1

2

3

4

t

Cycle time, ECLKIN

15

6.8

10

4.5

ns

c(EKI)

Pulse duration, ECLKIN high

Pulse duration, ECLKIN low

Transition time, ECLKIN

w(EKIH)

w(EKIL)

t(EKI)

2.2

†

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

IL IH

1

4

2

ECLKIN

3

4

Figure 14. ECLKIN Timings

‡§¶

switching characteristics over recommended operating conditions for ECLKOUT

(see Figure 15)

–100

–150

NO.

PARAMETER

UNIT

MIN

E – 0.7

MAX

1

2

3

4

5

6

t

Cycle time, ECLKOUT

E + 0.7

ns

c(EKO)

Pulse duration, ECLKOUT high

EH – 0.7 EH + 0.7

EL – 0.7 EL + 0.7

2

w(EKOH)

w(EKOL)

t(EKO)

Pulse duration, ECLKOUT low

Transition time, ECLKOUT

t

Delay time, ECLKIN high to ECLKOUT high

Delay time, ECLKIN low to ECLKOUT low

1

7

d(EKIH-EKOH)

t

d(EKIL-EKOL)

‡

§

¶

The reference points for the rise and fall transitions are measured at V

E = ECLKIN period in ns

EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.

MAX and V

MIN.

OH

OL

ECLKIN

6

1

4

2

5

3

ECLKOUT

Figure 15. ECLKOUT Timings

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

ASYNCHRONOUS MEMORY TIMING

†‡§

timing requirements for asynchronous memory cycles

(see Figure 16–Figure 17)

C6711–100

C6711–150

NO.

UNIT

MIN MAX

3

4

6

7

t

Setup time, EDx valid before ARE high

Hold time, EDx valid after ARE high

13

1

9

1

3

1

ns

su(EDV-AREH)

h(AREH-EDV)

t

Setup time, ARDY valid before ECLKOUT high

Hold time, ARDY valid after ECLKOUT high

6

su(ARDY-EKOH)

t

1

h(EKOH-ARDY)

C6711B-100

C6711BGFNA–100

C6711B–150

NO.

UNIT

MIN

13

1

MAX

MIN MAX

3

4

6

7

t

Setup time, EDx valid before ARE high

Hold time, EDx valid after ARE high

9

1

ns

su(EDV-AREH)

t

h(AREH-EDV)

t

Setup time, ARDY valid before ECLKOUT high

Hold time, ARDY valid after ECLKOUT high

6

3

su(ARDY-EKOH)

t

2.5

h(EKOH-ARDY)

†

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in

the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide

enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

‡

§

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

E = ECLKOUT period in ns

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

switching characteristics over recommended operating conditions for asynchronous memory

†‡§

cycles

(see Figure 16–Figure 17)

C6711–100

C6711–150

NO.

1

PARAMETER

UNIT

ns

MIN

MAX

MIN

MAX

t

Output setup time, select signals valid to ARE low

RS * E – 3

osu(SELV-AREL)

Output hold time, ARE high to select signals

invalid

2

t

RH * E – 3

ns

oh(AREH-SELIV)

5

8

t

Delay time, ECLKOUT high to ARE vaild

1.5

WS * E – 3

WH * E – 3

1.5

11

1.5

WS * E – 3

WH * E – 3

1.5

8

ns

d(EKOH-AREV)

t

Output setup time, select signals valid to AWE low

Output hold time, AWE high to select signals invalid

Delay time, ECLKOUT high to AWE vaild

osu(SELV-AWEL)

9

t

oh(AWEH-SELIV)

10

t

d(EKOH-AWEV)

C6711B–100

C6711BGFNA-100

C6711B–150

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

t

Output setup time, select signals valid to ARE low

RS * E – 3

ns

osu(SELV-AREL)

Output hold time, ARE high to select signals

invalid

t

RH * E – 3

oh(AREH-SELIV)

5

8

t

Delay time, ECLKOUT high to ARE vaild

1

WS * E – 3

WH * E – 3

1

11

1

WS * E – 3

WH * E – 3

1

8

ns

d(EKOH-AREV)

t

Output setup time, select signals valid to AWE low

Output hold time, AWE high to select signals invalid

Delay time, ECLKOUT high to AWE vaild

osu(SELV-AWEL)

9

t

oh(AWEH-SELIV)

10

t

d(EKOH-AWEV)

†

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

E = ECLKOUT period in ns

‡

§

Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2

Strobe = 3

Not Ready

Hold = 2

ECLKOUT

CEx

1

2

BE[3:0]

EA[21:2]

BE

Address

3

4

ED[31:0]

1

5

2

5

Read Data

†

AOE/SDRAS/SSOE

†

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

7

6

ARDY

†

AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,

respectively, during asynchronous memory accesses.

Figure 16. Asynchronous Memory Read Timing

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2

Hold = 2

Strobe = 3

Not Ready

ECLKOUT

CEx

8

9

BE[3:0]

BE

EA[21:2]

ED[31:0]

Address

Write Data

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

10

†

AWE/SDWE/SSWE

7

6

ARDY

†

AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,

respectively, during asynchronous memory accesses.

Figure 17. Asynchronous Memory Write Timing

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS-BURST MEMORY TIMING

†

timing requirements for synchronous-burst SRAM cycles (see Figure 18)

C6711-100

C6711-150

NO.

UNIT

MIN

6

MAX

MIN

2.5

1

MAX

6

7

t

Setup time, read EDx valid before ECLKOUT high

Hold time, read EDx valid after ECLKOUT high

ns

su(EDV-EKOH)

t

1

h(EKOH-EDV)

C6711BGFNA-100

C6711B-150

C6711B-100

NO.

UNIT

MIN

6

MAX

MIN

2.5

MAX

6

7

t

Setup time, read EDx valid before ECLKOUT high

Hold time, read EDx valid after ECLKOUT high

ns

su(EDV-EKOH)

t

2.5

h(EKOH-EDV)

†

The C6711 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,

but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

switching characteristics over recommended operating conditions for synchronous-burst SRAM

†‡

cycles (see Figure 18 and Figure 19)

C6711-100

C6711-150

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

t

Delay time, ECLKOUT high to CEx valid

1.5

11

1.5

6.5

ns

d(EKOH-CEV)

t

Delay time, ECLKOUT high to BEx valid

d(EKOH-BEV)

3

t

Delay time, ECLKOUT high to BEx invalid

Delay time, ECLKOUT high to EAx valid

1.5

d(EKOH-BEIV)

4

t

11

6.5

d(EKOH-EAV)

5

t

Delay time, ECLKOUT high to EAx invalid

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

Delay time, ECLKOUT high to EDx valid

1.5

d(EKOH-EAIV)

8

t

11

6.5

7

d(EKOH-ADSV)

9

t

d(EKOH-OEV)

10

11

12

t

d(EKOH-EDV)

t

Delay time, ECLKOUT high to EDx invalid

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

1.5

d(EKOH-EDIV)

t

11

6.5

d(EKOH-WEV)

C6711B-100

C6711BGFNA-100

C6711B-150

NO.

PARAMETER

UNIT

MIN

MAX

11

MIN

MAX

8.5

MIN

MAX

7.5

1

2

3

4

5

t

Delay time, ECLKOUT high to CEx valid

Delay time, ECLKOUT high to BEx valid

Delay time, ECLKOUT high to BEx invalid

Delay time, ECLKOUT high to EAx valid

Delay time, ECLKOUT high to EAx invalid

1

ns

d(EKOH-CEV)

t

11

8.5

7.5

d(EKOH-BEV)

t

1

d(EKOH-BEIV)

t

11

8.5

7.5

d(EKOH-EAV)

t

1

d(EKOH-EAIV)

Delay time, ECLKOUT high to

ARE/SDCAS/SSADS valid

8

9

t

ns

d(EKOH-ADSV)

Delay time, ECLKOUT high to,

AOE/SDRAS/SSOE valid

t

1

11

1

8.5

1

7.5

d(EKOH-OEV)

10

11

t

Delay time, ECLKOUT high to EDx valid

Delay time, ECLKOUT high to EDx invalid

ns

d(EKOH-EDV)

t

1

d(EKOH-EDIV)

Delay time, ECLKOUT high to

AWE/SDWE/SSWE valid

12

t

11

8.5

7.5

ns

d(EKOH-WEV)

†

‡

The C6711 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,

but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

ECLKOUT

1

2

1

CEx

3

BE[3:0]

BE1

BE2

BE3

EA

BE4

7

4

5

EA[21:2]

ED[31:0]

6

Q1

Q2

Q3

Q4

8

†

ARE/SDCAS/SSADS

9

†

AOE/SDRAS/SSOE

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

Figure 18. SBSRAM Read Timing

ECLKOUT

1

2

1

3

CEx

BE[3:0]

BE1

BE2

Q2

BE3

5

BE4

Q4

4

EA[21:2]

ED[31:0]

EA

10

11

12

Q1

Q3

8

†

ARE/SDCAS/SSADS

AOE/SDRAS/SSOE

12

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

Figure 19. SBSRAM Write Timing

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING

†

timing requirements for synchronous DRAM cycles (see Figure 20)

C6711-100

C6711-150

NO.

UNIT

MIN

6

MAX

MIN MAX

6

7

t

Setup time, read EDx valid before ECLKOUT high

Hold time, read EDx valid after ECLKOUT high

2.5

1

ns

su(EDV-EKOH)

1

h(EKOH-EDV)

C6711BGFNA-100

C6711B-150

C6711B-100

NO.

UNIT

MIN

6

MAX

MIN

2.5

MAX

6

7

t

Setup time, read EDx valid before ECLKOUT high

Hold time, read EDx valid after ECLKOUT high

ns

su(EDV-EKOH)

2.5

h(EKOH-EDV)

†

The C6711 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but

random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING (CONTINUED)

switching characteristics over recommended operating conditions for synchronous DRAM

†‡

cycles (see Figure 20–Figure 26)

C6711-100

C6711-150

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

t

Delay time, ECLKOUT high to CEx valid

1.5

11

1.5

6.5

ns

d(EKOH-CEV)

d(EKOH-BEV)

d(EKOH-BEIV)

d(EKOH-EAV)

d(EKOH-EAIV)

Delay time, ECLKOUT high to BEx valid

3

Delay time, ECLKOUT high to BEx invalid

Delay time, ECLKOUT high to EAx valid

1.5

4

11

6.5

5

Delay time, ECLKOUT high to EAx invalid

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

Delay time, ECLKOUT high to EDx valid

1.5

8

t

11

6.5

7

d(EKOH-CASV)

9

t

d(EKOH-EDV)

d(EKOH-EDIV)

d(EKOH-WEV)

d(EKOH-RAS)

10

11

12

t

Delay time, ECLKOUT high to EDx invalid

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

1.5

11

6.5

C6711BGFNA-100

C6711B-150

C6711B-100

NO.

PARAMETER

UNIT

MIN

MAX

11

MIN

MAX

1

2

t

Delay time, ECLKOUT high to CEx valid

1

8

ns

d(EKOH-CEV)

d(EKOH-BEV)

d(EKOH-BEIV)

d(EKOH-EAV)

d(EKOH-EAIV)

Delay time, ECLKOUT high to BEx valid

11

3

Delay time, ECLKOUT high to BEx invalid

Delay time, ECLKOUT high to EAx valid

1

4

11

8

5

Delay time, ECLKOUT high to EAx invalid

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

Delay time, ECLKOUT high to EDx valid

1

8

t

11

8

d(EKOH-CASV)

9

t

d(EKOH-EDV)

d(EKOH-EDIV)

d(EKOH-WEV)

d(EKOH-RAS)

10

11

12

t

Delay time, ECLKOUT high to EDx invalid

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

1

11

8

†

‡

The C6711 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but

random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

ECLKOUT

CEx

1

2

3

BE[3:0]

BE1

BE2

BE3

BE4

4

5

Bank

EA[21:13]

EA[11:2]

4

Column

4

EA12

6

7

D2

ED[31:0]

D1

D3

D4

†

AOE/SDRAS/SSOE

8

†

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 20. SDRAM Read Command (CAS Latency 3)

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING (CONTINUED)

WRITE

ECLKOUT

CEx

1

2

4

9

2

4

5

9

3

BE[3:0]

BE1

BE2

BE3

BE4

Bank

EA[21:13]

Column

EA[11:2]

EA12

10

ED[31:0]

D1

D2

D3

D4

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

8

†

11

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 21. SDRAM Write Command

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING (CONTINUED)

ACTV

ECLKOUT

1

4

1

CEx

BE[3:0]

5

Bank Activate

EA[21:13]

EA[11:2]

4

Row Address

4

Row Address

EA12

ED[31:0]

12

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 22. SDRAM ACTV Command

DCAB

ECLKOUT

1

CEx

BE[3:0]

EA[21:13, 11:2]

4

12

11

5

12

11

EA12

ED[31:0]

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 23. SDRAM DCAB Command

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING (CONTINUED)

DEAC

ECLKOUT

1

CEx

BE[3:0]

4

5

EA[21:13]

EA[11:2]

Bank

4

5

EA12

ED[31:0]

12

11

12

11

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 24. SDRAM DEAC Command

REFR

ECLKOUT

1

CEx

BE[3:0]

EA[21:2]

EA12

ED[31:0]

12

8

12

8

†

AOE/SDRAS/SSOE

†

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 25. SDRAM REFR Command

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

SYNCHRONOUS DRAM TIMING (CONTINUED)

MRS

ECLKOUT

1

4

1

5

CEx

BE[3:0]

EA[21:2]

ED[31:0]

MRS value

12

8

12

8

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

11

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 26. SDRAM MRS Command

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

HOLD/HOLDA TIMING

†

timing requirements for the HOLD/HOLDA cycles (see Figure 27)

–100

–150

NO.

UNIT

MIN MAX

3

t

Output hold time, HOLD low after HOLDA low

E

ns

oh(HOLDAL-HOLDL)

E = ECLKIN period in ns

†

†‡

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles

(see Figure 27)

–100

–150

NO.

PARAMETER

UNIT

MIN

2E

0

MAX

§

1

2

4

5

t

Delay time, HOLD low to EMIF Bus high impedance

Delay time, EMIF Bus high impedance to HOLDA low

Delay time, HOLD high to EMIF Bus low impedance

Delay time, EMIF Bus low impedance to HOLDA high

ns

d(HOLDL-EMHZ)

t

2E

7E

2E

d(EMHZ-HOLDAL)

t

2E

0

d(HOLDH-EMLZ)

t

d(EMLZ-HOLDAH)

†

‡

§

E = ECLKIN period in ns

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay

time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

External Requestor

DSP Owns Bus

Owns Bus

3

HOLD

2

5

HOLDA

1

C6711/C6711B

4

†

EMIF Bus

C6711/C6711B

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

Figure 27. HOLD/HOLDA Timing

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

BUSREQ TIMING

switching characteristics over recommended operating conditions for the BUSREQ cycles

(see Figure 28)

–100

MIN

–150

MIN

1.5

NO.

PARAMETER

UNIT

MAX

1

t

Delay time, ECLKOUT high to BUSREQ valid

2

11

ns

d(EKOH-BUSRV)

ECLKOUT

BUSREQ

1

Figure 28. BUSREQ Timing

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

RESET TIMING

†

timing requirements for reset (see Figure 29)

–100

–150

NO.

UNIT

MIN

MAX

‡

Width of the RESET pulse (PLL stable)

Width of the RESET pulse (PLL needs to sync up)

Setup time, HD boot configuration bits valid before RESET high

10P

250

2P

ns

µs

ns

1

t

w(RST)

§

¶

14

15

t

su(HD)

¶

Hold time, HD boot configuration bits valid after RESET high

2P

h(HD)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable.

This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL

circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During

that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.

HD[4:3] are the boot configuration pins during device reset.

¶

†#||

switching characteristics over recommended operating conditions during reset

(see Figure 29)

–100

–150

NO.

PARAMETER

UNIT

MIN

MAX

3P + 4E

2

3

t

Delay time, RESET low to ECLKIN synchronized internally

Delay time, RESET high to ECLKIN synchronized internally

Delay time, RESET low to EMIF Z group high impedance

Delay time, RESET high to EMIF Z group valid

Delay time, RESET low to EMIF high group invalid

Delay time, RESET high to EMIF high group valid

Delay time, RESET low to EMIF low group invalid

Delay time, RESET high to EMIF low group valid

Delay time, RESET low to high group invalid

2P + 3E

ns

d(RSTL-ECKI)

d(RSTH-ECKI)

4

t

d(RSTL-EMIFZHZ)

5

t

3P + 4E

4P

d(RSTH-EMIFZV)

6

t

2P + 3E

2P

d(RSTL-EMIFHIV)

7

t

d(RSTH-EMIFHV)

8

t

d(RSTL-EMIFLIV)

9

t

d(RSTH-EMIFLV)

10

11

12

13

t

d(RSTL-HIGHIV)

t

Delay time, RESET high to high group valid

d(RSTH-HIGHV)

t

Delay time, RESET low to Z group high impedance

Delay time, RESET high to Z group valid

2P

d(RSTL-ZHZ)

t

d(RSTH-ZV)

†

#

||

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

E = ECLKIN period in ns

EMIF Z group consists of:

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE

EMIF high group consists of: HOLDA

EMIF low group consists of: BUSREQ

High group consists of:

Z group consists of:

HRDY and HINT

HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

RESET TIMING (CONTINUED)

CLKOUT1

CLKOUT2

1

15

14

RESET

2

4

6

3

5

ECLKIN

†

EMIF Z Group

7

†

EMIF High Group

8

9

†

EMIF Low Group

10

12

11

13

†

High Group

Z Group

†

‡

HD[8, 4:3]

†

‡

EMIF Z group consists of:

EMIF high group consists of: HOLDA

EMIF low group consists of: BUSREQ

High group consists of:

Z group consists of:

HD[8, 4:3] are the endianness and boot configuration pins during device reset.

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE

HRDY and HINT

HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.

Figure 29. Reset Timing

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

EXTERNAL INTERRUPT TIMING

†

timing requirements for external interrupts (see Figure 30)

–100

–150

NO.

UNIT

MIN

MAX

1

2

t

Width of the interrupt pulse low

Width of the interrupt pulse high

2P

ns

w(ILOW)

w(IHIGH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

2

1

EXT_INT, NMI

Figure 30. External/NMI Interrupt Timing

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

HOST-PORT INTERFACE TIMING

†‡

timing requirements for host-port interface cycles (see Figure 31, Figure 32, Figure 33, and

Figure 34)

C6711-100

C6711-150

C6711B-100

NO.

UNIT

MIN MAX

§

1

2

t

Setup time, select signals valid before HSTROBE low

5

4

ns

su(SELV-HSTBL)

§

t

Hold time, select signals valid after HSTROBE low

h(HSTBL-SELV)

3

t

Pulse duration, HSTROBE low

4P

5

w(HSTBL)

4

Pulse duration, HSTROBE high between consecutive accesses

w(HSTBH)

§

Setup time, select signals valid before HAS low

10

11

12

13

su(SELV-HASL)

h(HASL-SELV)

§

Hold time, select signals valid after HAS low

3

t

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

5

su(HDV-HSTBH)

t

3

h(HSTBH-HDV)

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until

HRDY is active (low); otherwise, HPI writes will not complete properly.

14

t

2

ns

h(HRDYL-HSTBL)

18

19

t

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

2

ns

su(HASL-HSTBL)

t

h(HSTBL-HASL)

C6711B-150

C6711BGFNA-100

NO.

UNIT

MIN MAX

§

1

2

t

Setup time, select signals valid before HSTROBE low

5

ns

su(SELV-HSTBL)

§

t

Hold time, select signals valid after HSTROBE low

4

4P

5

h(HSTBL-SELV)

3

t

Pulse duration, HSTROBE low

w(HSTBL)

4

t

Pulse duration, HSTROBE high between consecutive accesses

w(HSTBH)

§

Setup time, select signals valid before HAS low

10

11

12

13

su(SELV-HASL)

h(HASL-SELV)

§

Hold time, select signals valid after HAS low

3

t

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

5

su(HDV-HSTBH)

t

3

h(HSTBH-HDV)

Hold time, HSTROBE low after HRDY low. HSTROBE should not be

inactivated until HRDY is active (low); otherwise, HPI writes will not complete

properly.

14

t

2

ns

h(HRDYL-HSTBL)

18

19

t

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

2

ns

su(HASL-HSTBL)

t

h(HSTBL-HASL)

†

‡

§

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

Select signals include: HCNTL[1:0], HR/W, and HHWIL.

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

HOST-PORT INTERFACE TIMING (CONTINUED)

switching characteristics over recommended operating conditions during host-port interface

†‡

cycles (see Figure 31, Figure 32, Figure 33, and Figure 34)

C6711-100

C6711-150

C6711B-100

NO.

PARAMETER

UNIT

MIN MAX

§

5

6

t

Delay time, HCS to HRDY

1

15

ns

d(HCS-HRDY)

¶

Delay time, HSTROBE low to HRDY high

3

d(HSTBL-HRDYH)

d(HSTBL-HDLZ)

d(HDV-HRDYL)

oh(HSTBH-HDV)

d(HSTBH-HDHZ)

7

Delay time, HSTROBE low to HD low impedance for an HPI read

Delay time, HD valid to HRDY low

2

8

2P – 4

2P

15

9

Output hold time, HD valid after HSTROBE high

Delay time, HSTROBE high to HD high impedance

3

15

16

17

20

t

Delay time, HSTROBE low to HD valid

3

15

ns

d(HSTBL-HDV)

#

Delay time, HSTROBE high to HRDY high

d(HSTBH-HRDYH)

d(HASL-HRDYH)

Delay time, HAS low to HRDY high

C6711BGFNA-100

C6711B-150

NO.

PARAMETER

UNIT

MIN

1

MAX

13

MIN

1

MAX

12

§

5

6

t

Delay time, HCS to HRDY

ns

d(HCS-HRDY)

¶

t

Delay time, HSTROBE low to HRDY high

3

13

3

12

d(HSTBL-HRDYH)

Delay time, HSTROBE low to HD low impedance for

an HPI read

7

t

2

ns

d(HSTBL-HDLZ)

8

9

t

Delay time, HD valid to HRDY low

2P – 4

2P

13

2P – 4

2P

12

ns

d(HDV-HRDYL)

t

Output hold time, HD valid after HSTROBE high

Delay time, HSTROBE high to HD high impedance

Delay time, HSTROBE low to HD valid

3

oh(HSTBH-HDV)

15

16

t

d(HSTBH-HDHZ)

t

d(HSTBL-HDV)

#

17

20

t

Delay time, HSTROBE high to HRDY high

3

13

3

12

ns

d(HSTBH-HRDYH)

t

Delay time, HAS low to HRDY high

d(HASL-HRDYH)

†

‡

§

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy

completing a previous HPID write or READ with autoincrement.

This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the

requestto the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads

the requested data into HPID.

This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write

or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

¶

#

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

1

2

1

HHWIL

4

3

†

HSTROBE

HCS

15

9

15

9

7

16

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

5

1st halfword

2nd halfword

5

8

17

6

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 31. HPI Read Timing (HAS Not Used, Tied High)

†

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

10

HHWIL

4

3

‡

HSTROBE

18

HCS

15

7

9

16

9

17

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

1st half-word

2nd half-word

5

8

5

20

†

‡

For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 32. HPI Read Timing (HAS Used)

63

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

1

2

3

1

HHWIL

3

4

14

†

HSTROBE

HCS

HD[15:0] (input)

HRDY

12

13

2nd halfword

13

17

1st halfword

5

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 33. HPI Write Timing (HAS Not Used, Tied High)

†

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

HHWIL

3

4

14

‡

HSTROBE

18

12

18

HCS

HD[15:0] (input)

HRDY

12

13

1st half-word

2nd half-word

5

17

†

‡

For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 34. HPI Write Timing (HAS Used)

64

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

MULTICHANNEL BUFFERED SERIAL PORT TIMING

†‡

timing requirements for McBSP (see Figure 35)

C6711-100

C6711-150

NO.

UNIT

MIN

MAX

§

2

3

t

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

0.5t

c(CKRX)

– 1

20

1

w(CKRX)

5

6

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH-CKRL)

6

t

h(CKRL-FRH)

3

22

3

7

t

su(DRV-CKRL)

3

8

t

Hold time, DR valid after CLKR low

h(CKRL-DRV)

4

23

1

10

11

t

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

su(FXH-CKXL)

6

t

h(CKXL-FXH)

3

C6711B-100

C6711B-150

C6711BGFNA-100

NO.

UNIT

MIN MAX

§

2

3

t

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

0.5t

c(CKRX)

– 1

20

1

w(CKRX)

5

6

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH-CKRL)

6

t

h(CKRL-FRH)

5

22

3

7

t

su(DRV-CKRL)

3

8

t

Hold time, DR valid after CLKR low

h(CKRL-DRV)

5

23

1

10

11

t

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

su(FXH-CKXL)

6

t

h(CKXL-FXH)

3

†

‡

§

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP

and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave.

Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP

communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever

valueislarger. Forexample, whenrunningpartsat150MHz(P=6.7ns), use33nsastheminimumCLKR/Xclockcycle(bysettingtheappropriate

CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock

cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with

CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY =

01b or 10b) and the other device the McBSP communicates to is a slave.

65

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6711, TMS320C6711B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

switching characteristics over recommended operating conditions for McBSP (see Figure 35)

(C6711-100 and C6711-150)

C6711-100

C6711-150

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from

CLKS input

1

t

4

26

ns

d(CKSH-CKRXH)

§¶

2

3

4

t

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

#

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

C – 1

C + 1

w(CKRX)

–11

3

9

4

9

d(CKRH-FRV)

9

t

Delay time, CLKX high to internal FSX valid

ns

d(CKXH-FXV)

–9

3

Disable time, DX high impedance following last data bit from

CLKX high

12

13

t

dis(CKXH-DXHZ)

||

–9+ D1

4 + D2

t

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid

d(CKXH-DXV)

||

3 + D1

19 + D2

FSX int

FSX ext

–1

3

9

14

t

ns

d(FXH-DXV)

ONLY applies when in data

delay 0 (XDATDLY = 00b) mode

3

†

‡

§

¶

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

Minimum delay times also represent minimum output hold times.