TMS320VC5410A-160 [ETC]
Digital Signal Processor ; 数字信号处理器\n
| 型号： | TMS320VC5410A-160 |
| 厂家： | 
ETC |
| 描述： | Digital Signal Processor
|
| 文件： | 总93页 (文件大小：1182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5410A Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS139D
November 2000 – Revised July 2002
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
*
November 2000
Product Preview
Original
Updated electrical characteristic data and removed
references to internal oscillator functionality that is not
currently supported.
A
February 2001
Product Preview
B
C
June 2001
Product Preview
Production Data
Updated electrical characteristic data.
Corrected to reflect production data status. Added description
of internal oscillator functionality.
October 2001
Added references to the silicon errata for additional
information concerning internal oscillator functionality.
D
July 2002
Production Data
iii
Contents
Contents
Section
Page
1
2
TMS320VC5410A Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
2
2
4
5
2.1
2.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
2.2.2
Terminal Assignments for the GGU Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
11
11
12
12
13
14
15
16
17
19
19
19
20
22
25
25
26
29
30
30
31
32
33
33
33
34
34
34
35
35
36
36
36
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
3.1.2
3.1.3
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
3.3
3.4
3.5
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
3.6.2
3.6.3
Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Bank-Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
3.7.2
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
3.9
3.10
3.11
3.12
Multichannel Buffered Serial Ports (McBSPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced External Parallel Interface (XIO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1
3.12.2
3.12.3
3.12.4
3.12.5
3.12.6
3.12.7
3.12.8
3.12.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMPREC Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Source/Destination Address Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA in Autoinitialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Transfer Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Transfer in Doubleword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.10 DMA Channel Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.11 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.12 DMA Controller Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13
3.13.1
3.13.2
McBSP Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Data Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
November 2000 – Revised July 2002
SPRS139D
Contents
Section
Page
3.14
3.15
3.16
3.17
3.18
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
37
39
40
42
4
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
44
44
5.1
5.2
5.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
46
46
47
47
49
50
50
53
55
57
58
61
63
65
66
67
67
70
71
75
75
79
5.4
5.5
5.6
5.7
5.8
Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.1
5.8.2
Divide-By-Two and Divide-By-Four Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1
5.9.2
5.9.3
5.9.4
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
5.11
5.12
5.13
5.14
5.15
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15.1
5.15.2
5.15.3
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16.1
5.16.2
HPI8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
83
84
6.1
6.2
Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
SPRS139D
November 2000 – Revised July 2002
Figures
Page
List of Figures
Figure
2–1
2–2
144-Ball GGU MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Pin PGE Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
4
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
3–9
TMS320VC5410A Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program and Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Mode Status (PMST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . .
Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host-Port Interface — Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
13
13
14
16
17
17
20
21
23
23
24
24
24
27
28
29
30
31
32
33
34
36
36
36
42
3–10 Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Multichannel Control Register 2x (MCR2x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Multichannel Control Register 1x (MCR1x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Receive Channel Enable Registers Bit Layout for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 Transmit Channel Enable Registers Bit Layout for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . .
3–15 Nonconsecutive Memory Read and I/O Read Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Consecutive Memory Read Bus Sequence (n = 3 reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Memory Write and I/O Write Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 DMA Transfer Mode Control Register (DMMCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 DMA Channel Enable Control Register (DMCECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . . . . .
3–21 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . .
3–22 DMPREC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–23 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] . . . . . . . . . . . . . . . . . . . .
3–24 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] . . . . . . . . . . . . . . . . . . . . .
3–25 Device ID Register (CSIDR) [MMR Address 003Eh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–26 IFR and IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1
5–2
5–3
5–4
5–5
5–6
5–7
5–8
5–9
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Divide-by-Two Clock Option With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonconsecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write (MSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
47
48
49
51
52
54
56
57
vii
November 2000 – Revised July 2002
SPRS139D
Figures
Figure
Page
5–10 Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–14 HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–15 Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–16 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–17 MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–18 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . .
5–19 External Flag (XF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–20 TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–21 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–22 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–23 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5–25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5–26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5–27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5–28 HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . .
5–29 HPI-8 Mode Timing, Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–30 HPI-8 Mode, HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–31 GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–32 HPI-16 Mode, Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–33 HPI-16 Mode, Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–34 HPI-16 Mode, HRDY Relative to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
60
60
62
63
64
64
65
66
66
68
69
70
71
72
73
74
77
78
78
78
81
82
82
6–1
6–2
TMS320VC5410A 144-Ball MicroStar BGA Plastic Ball Grid Array Package . . . . . . . . . . . . . . . . . .
TMS320VC5410A 144-Pin Low-Profile Quad Flatpack (PGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
84
viii
SPRS139D
November 2000 – Revised July 2002
Tables
Page
List of Tables
Table
2–1
2–2
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Mode Status (PMST) Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Control Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Holder Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Channel Enable Registers for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Channel Enable Registers for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMD Section of the DMMCRn Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Enable Control Register (DMCECTL) Bit Description . . . . . . . . . . . . . . . . . . . . . . . .
DMA Reload Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
15
16
17
18
19
23
24
25
26
31
31
34
35
35
35
37
38
39
40
42
3–9
3–10
3–11
3–12
3–13
3–14
3–15
3–16
3–17
3–18
3–19
3–20
3–21
5–1
5–2
5–3
5–4
5–5
5–6
5–7
5–8
Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clock Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options . . . . . . . . . . . . . .
Divide-By-2 and Divide-by-4 Clock Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Switching Characteristics for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . .
External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
47
48
48
49
49
50
50
53
55
55
57
58
58
61
61
63
65
66
5–9
5–10
5–11
5–12
5–13
5–14
5–15
5–16
5–17
5–18
5–19
5–20
ix
November 2000 – Revised July 2002
SPRS139D
Tables
Table
Page
5–21
5–22
5–23
5–24
5–25
5–26
5–27
5–28
5–29
5–30
5–31
5–32
5–33
5–34
5–35
5–36
McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)† . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
68
70
70
71
71
72
72
73
73
74
74
75
76
79
80
x
SPRS139D
November 2000 – Revised July 2002
Features
1
TMS320VC5410A Features
D
D
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
D
D
D
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
– On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
Internal Oscillator or External Clock
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
†
Source
– One 16-Bit Timer
– Six-Channel Direct Memory Access
(DMA) Controller
– Three Multichannel Buffered Serial Ports
(McBSPs)
– 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D
D
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
D
D
64K x 16-Bit On-Chip RAM Composed of:
– Eight Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM
‡
IEEE Std 1149.1 (JTAG) Boundary Scan
Logic
D
D
D
D
D
D
D
144-Pin Ball Grid Array (BGA)
(GGU Suffix)
16K × 16-Bit On-Chip ROM Configured for
Program Memory
144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
D
Enhanced External Parallel Interface (XIO2)
D
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
6.25-ns Single-Cycle Fixed-Point
Instruction Execution Time (160 MIPS)
D
D
D
Block-Memory-Move Instructions for Better
Program and Data Management
8.33-ns Single-Cycle Fixed-Point
Instruction Execution Time (120 MIPS)
Instructions With a 32-Bit Long Word
Operand
3.3-V I/O Supply Voltage (160 and 120 MIPS)
1.6-V Core Supply Voltage (160 MIPS)
1.5-V Core Supply Voltage (120 MIPS)
Instructions With Two- or Three-Operand
Reads
†
‡
The on-chip oscillator is not available on all 5410A devices. For applicable devices, see the TMS320VC5410A Digital Signal Processor Silicon
Errata (literature number SPRZ187).
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
1
November 2000 – Revised July 2002
SPRS139D
Introduction
2
Introduction
This section lists the pin assignments and describes the function of each pin. This data manual also provides
a detailed description section, electrical specifications, parameter measurement information, and mechanical
data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional
Overview (literature number SPRU307).
2.1 Description
The TMS320VC5410A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory
bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree
of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In
addition, data can be transferred between data and program spaces. Such parallelism supports a powerful
set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.
The 5410A also includes the control mechanisms to manage interrupts, repeated operations, and function
calls.
2.2 Pin Assignments
Figure 2–1illustratestheballlocationsforthe144-pinballgridarray(BGA)packageandisusedinconjunction
with Table 2–1 to locate signal names and ball grid numbers. Figure 2–2 provides the pin assignments for the
144-pin low-profile quad flatpack (LQFP) package.
2.2.1 Terminal Assignments for the GGU Package
13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Figure 2–1. 144-Ball GGU MicroStar BGA (Bottom View)
Table 2–1 lists each signal name and BGA ball number for the 144-pin TMS320VC5410AGGU package.
Table 2–2 lists each terminal name, terminal function, and operating modes for the TMS320VC5410A.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
2
SPRS139D
November 2000 – Revised July 2002
Introduction
†
Table 2–1. Terminal Assignments
SIGNAL
QUADRANT 1
SIGNAL
QUADRANT 2
SIGNAL
QUADRANT 3
SIGNAL
QUADRANT 4
BGA BALL #
BGA BALL #
BGA BALL #
BGA BALL #
CV
A1
B1
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
BFSX1
N13
M13
L12
L13
K10
K11
K12
K13
J10
J11
CV
N1
N2
M3
N3
K4
A19
A20
A13
A12
B11
A11
D10
C10
B10
A10
D9
C9
B9
SS
SS
A22
BDX1
BCLKR1
HCNTL0
CV
DV
DV
DV
CV
DV
SS
DD
SS
DV
DD
SS
SS
DD
A10
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
D6
HD7
A11
A12
A13
A14
A15
L4
D7
D8
M4
N4
K5
D9
D10
D11
D12
HD4
D13
D14
D15
HD5
TOUT
EMU0
EMU1/OFF
TDO
HCNTL1
BDR2
L5
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
B13
B12
M5
N5
K6
CV
DD
HAS
BCLKX0
BCLKX2
A9
D8
C8
B8
DV
CV
CV
TDI
CV
L6
SS
SS
DD
SS
HINT
CV
TRST
M6
N6
M7
N7
L7
TCK
A8
DD
HCS
HR/W
READY
PS
TMS
BFSX0
BFSX2
HRDY
CV
B7
DD
SS
CV
CV
CV
A7
SS
HDS1
DV
C7
D7
A6
DD
HPIENA
DV
DV
DV
K7
DD
SS
HDS2
DV
DS
N8
M8
L8
SS
SS
IS
CLKOUT
HD3
X1
HD0
B6
DD
A0
R/W
BDX0
BDX2
IACK
HBIL
NMI
C6
D6
A5
MSTRB
IOSTRB
MSC
XF
K8
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
X2/CLKIN
RS
N9
M9
L9
J2
B5
J3
D0
C5
D5
A4
HOLDA
IAQ
J4
D1
INT0
INT1
INT2
INT3
K9
K1
K2
K3
L1
D2
N10
M10
L10
N11
M11
L11
N12
M12
HOLD
BIO
D3
B4
D4
C4
A3
MP/MC
D5
CV
DD
DV
L2
A16
HD1
B3
DD
SS
CV
L3
DV
CV
CV
C3
A2
SS
A17
A18
SS
DD
A21
DV
BDR1
M1
M2
BCLKX1
DV
BFSR1
B2
SS
SS
†
DV
is the power supply for the I/O pins while CV
is the power supply for the core CPU. DV
is the ground for the I/O pins while CV is
SS
DD
the ground for the core CPU. The DV
DD
SS
pins can be connected to a common ground plane in a system.
SS
and CV
SS
3
November 2000 – Revised July 2002
SPRS139D
Introduction
2.2.2 Pin Assignments for the PGE Package
The TMS320VC5410APGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 2–2.
1
108
107
106
105
104
103
102
101
100
99
CV
SS
A18
A17
2
A22
3
CV
DV
SS
DD
SS
4
DV
A16
D5
D4
D3
D2
5
A10
HD7
A11
A12
A13
A14
A15
6
7
8
9
D1
D0
RS
X2/CLKIN
X1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
CV
HAS
DD
96
95
DV
HD3
CLKOUT
SS
SS
DD
94
CV
CV
93
DV
HPIENA
SS
92
HCS
HR/W
READY
PS
91
CV
CV
TMS
DD
SS
90
89
88
DS
IS
R/W
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
87
86
85
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
84
83
82
81
80
79
78
77
76
DV
CV
BDR1
DV
DV
BDX1
DD
SS
SS
DD
75
74
73
BFSR1
BFSX1
NOTE A: DV
CV
is the power supply for the I/O pins while CV
DD
is the power supply for the core CPU. DV
and CV
SS
is the ground for the I/O pins while
DD
SS
SS
pins can be connected to a common ground plane in a system.
is the ground for the core CPU. The DV
SS
Figure 2–2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
4
SPRS139D
November 2000 – Revised July 2002
Introduction
2.3 Signal Descriptions
Table 2–2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2–2. Signal Descriptions
TERMINAL
NAME
†
I/O
DESCRIPTION
DATA SIGNALS
‡§
I/O/Z
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
to A22, address external program space memory. A22–A0 is placed in the high-impedance state in the hold
mode. A22–A0 also goes into the high-impedance state when OFF is low.
A16–A0areinputsinHPI16mode. Thesepinscanbeusedtoaddressinternalmemoryviathehost-portinterface
(HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
a high-impedance state.
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
‡§
I/O/Z
D15 (MSB)
D14
D13
D12
D11
D10
D9
Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 is multiplexed to transfer data between the core CPU
and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15–D0 is
placedinthehigh-impedancestatewhennotoutputtingdataorwhenRSorHOLDisasserted.D15–D0alsogoes
into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs.
Thedata bus has a bus holder feature that eliminates passive components and the power dissipation associated
with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the
high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
5
November 2000 – Revised July 2002
SPRS139D
Introduction
Table 2–2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
I/O
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
IACK
O/Z
I
‡
INT0
INT1
INT2
INT3
‡
External user interrupt inputs. INT0–INT3 are maskable and are prioritized by the interrupt mask register (IMR)
and the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
‡
‡
Nonmaskableinterrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
‡
NMI
I
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to
0FF80h.WhenRSisbroughttoahighlevel, executionbeginsatlocation0FF80hofprogrammemory. RSaffects
various registers and status bits.
‡
RS
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MP/MC
I
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
‡
BIO
I
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurationsor used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.
XF
O/Z
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
state when OFF is low.
DS
PS
IS
O/Z
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
MSTRB
READY
R/W
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
IOSTRB
HOLD
O/Z
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the 5410A, these lines go into the high-impedance state.
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
6
SPRS139D
November 2000 – Revised July 2002
Introduction
Table 2–2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
I/O
MEMORY CONTROL SIGNALS (CONTINUED)
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low.
HOLDA
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
MSC
IAQ
O/Z
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when OFF is low.
TIMER SIGNALS
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKOUT
O/Z
I
Clock mode select signals. CLKMD1–CLKMD3 allow the selection and configuration of different clock modes
such as crystal, external clock, and PLL mode. The external CLKMD1–CLKMD3 pins are sampled to determine
the desired clock generation mode while RS is low. Following reset, the clock generation mode can be
reconfigured by writing to the internal clock mode register in software.
‡
‡
‡
CLKMD1
CLKMD2
CLKMD3
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is
revision depended, see Section 3.10 for additional information.)
‡
X2/CLKIN
X1
I
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision depended, see
Section 3.10 for additional information.)
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT
O/Z
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
‡
‡
‡
BCLKR0
BCLKR1
BCLKR2
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
I/O/Z
I
BDR0
BDR1
BDR2
Serial data receive input
BFSR0
BFSR1
BFSR2
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
I/O/Z
I/O/Z
O/Z
I/O/Z
‡
‡
‡
BCLKX0
BCLKX1
BCLKX2
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
aninputoranoutput, andisconfiguredasaninputfollowingreset. BCLKXentersthehigh-impedancestatewhen
OFF goes low.
BDX0
BDX1
BDX2
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
BFSX2
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
into the high-impedance state when OFF is low.
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
7
November 2000 – Revised July 2002
SPRS139D
Introduction
Table 2–2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
I/O
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the 5410A, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.
‡§
HD0–HD7
I/O/Z
¶
¶
HCNTL0
HCNTL1
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs
have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.
I
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
¶
HBIL
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
‡¶
HCS
I
‡¶
‡¶
HDS1
HDS2
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
I
I
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA
register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
‡¶
HAS
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
¶
HR/W
I
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host
when the HPI is ready for the next transfer.
HRDY
HINT
O/Z
O/Z
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT
goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPI module select. HPIENA must be tied to DV
DD
to have HPI selected. If HPIENA is left open or connected to
ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus
has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled
when RS goes high and is ignored until RS goes low again.
#
HPIENA
I
I
#
HPI16
HPI16 mode selection
SUPPLY PINS
CV
CV
DV
DV
S
S
S
S
Ground. Dedicated ground for the core CPU
SS
+V . Dedicated power supply for the core CPU
DD
DD
SS
DD
Ground. Dedicated ground for I/O pins
+V . Dedicated power supply for I/O pins
DD
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
8
SPRS139D
November 2000 – Revised July 2002
Introduction
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
‡¶
TCK
I
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
¶
TDI
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TDO
TMS
O/Z
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
¶
I
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
#
TRST
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system. It is recommended that an external pullup be put on this pin.
EMU0
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU1/OFF
I/O/Z
EMU0 = high
EMU1/OFF = low
It is recommended that an external pullup be put on this pin.
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
9
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3–1.
P, C, D, E Buses and Control Signals
64K RAM
Dual Access
Program/Data
16K Program
54X cLEAD
ROM
MBus
GPIO
RHEA
Bridge
TI BUS
RHEA Bus
McBSP1
XIO
Enhanced XIO
McBSP2
McBSP3
HPI
HPI
xDMA
logic
RHEAbus
TIMER
APLL
JTAG
Clocks
Figure 3–1. TMS320VC5410A Functional Block Diagram
3.1 Memory
The 5410A device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
3.1.1 Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
•
•
•
•
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
10
SPRS139D
November 2000 – Revised July 2002
Functional Overview
3.1.2 Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When the
cells are mapped into program space, the device automatically accesses them when their addresses are
within bounds. When the program-address generation (PAGEN) logic generates an address outside its
bounds, the device automatically generates an external access. The advantages of operating from on-chip
memory are as follows:
•
•
•
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
3.1.3 Extended Program Memory
The 5410A uses a paged extended memory scheme in program space to allow access of up to 8192K of
program memory. In order to implement this scheme, the 5410A includes several features which are also
present on C548/549/5410:
•
•
•
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC
Six extra instructions for addressing extended program space
Program memory in the 5410A is organized into 128 pages that are each 64K in length.
The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.2 On-Chip ROM With Bootloader
The 5410A features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program
memory space.
Customers can arrange to have the ROM of the 5410A programmed with contents unique to any particular
application.
A bootloader is available in the standard 5410A on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the
device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program.
The standard 5410A devices provide different ways to download the code to accommodate various system
requirements:
•
•
•
•
•
•
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space, 8-bit or 16-bit mode
Serial boot from serial ports, 8-bit or 16-bit mode
Host-port interface boot
Serial EEPROM mode
Warm boot
11
November 2000 – Revised July 2002
SPRS139D
Functional Overview
The standard on-chip ROM layout is shown in Table 3–1.
Table 3–1. Standard On-Chip ROM Layout
†
ADDRESS RANGE
C000h–D4FFh
D500h–F7FFh
F800h–FBFFh
FC00h–FCFFh
FD00h–FDFFh
FE00h–FEFFh
FF00h–FF7Fh
FF80h–FFFFh
DESCRIPTION
ROM tables for the GSM EFR speech codec
Reserved
Bootloader
µ-Law expansion table
A-Law expansion table
Sine look-up table
†
Reserved
Interrupt vector table
†
Inthe5410AROM,128wordsarereservedforfactorydevice-testingpurposes.Applicationcode
to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh
in program space.
3.3 On-Chip RAM
The 5410A device contains 64K-word × 16-bit of on-chip dual-access RAM (DARAM).
The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range
0080h–7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. The
otherfourblocksofDARAMarelocatedintheaddressrange18000h–1FFFFhinprogramspace. TheDARAM
located in the address range 18000h–1FFFFh in program space can be mapped into data space by setting
the DROM bit to one.
3.4 On-Chip Memory Security
The 5410A device has a maskable option to protect the contents of on-chip memories. When the ROM protect
bit is set, no externally originating instruction can access the on-chip memory spaces; HPI writes have no
restriction, but HPI reads are restricted to 4000h – 5FFFh.
12
SPRS139D
November 2000 – Revised July 2002
Functional Overview
3.5 Memory Map
Page 0 Program
Page 0 Program
Data
Hex
Hex
Hex
0000
0000
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
Memory-Mapped
Registers
005F
007F
0080
007F
0080
0060
007F
0080
Scratch-Pad
RAM
On-Chip
DARAM0–3
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0–3
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0–3
(32K x 16-bit)
7FFF
8000
BFFF
C000
7FFF
8000
7FFF
8000
External
External
On-Chip
DARAM4–7
(DROM=1)
or
External
(DROM=0)
On-Chip ROM
(4K x 16-bit)
FF7F
FF80
FEFF
FF00
FF7F
FF80
FFFF
Interrupts
(External)
Reserved
Interrupts
(On-Chip)
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Address ranges for on-chip DARAM in data memory are:
DARAM0: 0080h–1FFFh;
DARAM1: 2000h–3FFFh
DARAM2: 4000h–5FFFh;
DARAM4: 8000h–9FFFh;
DARAM6: C000h–DFFFh;
DARAM3: 6000h–7FFFh
DARAM5: A000h–BFFFh
DARAM7: E000h–FFFFh
Figure 3–2. Program and Data Memory Map
Hex
7F0000
Hex
010000
Program
Program
Hex
020000
Program
On-Chip
DARAM0–3
(OVLY=1)
External
On-Chip
DARAM0–3
(OVLY=1)
External
On-Chip
DARAM0–3
(OVLY=1)
External
(OVLY=0)
(OVLY=0)
(OVLY=0)
7F7FFF
7F8000
017FFF
018000
027FFF
028000
......
On-Chip
DARAM4–7
(MP/MC=0)
External
External
External
(MP/MC=1)
7FFFFF
01FFFF
02FFFF
Page 1
XPC=1
Page 2
XPC=2
Page 127
XPC=7Fh
Address ranges for on-chip DARAM in program memory are:
DARAM4: 018000h–019FFFh;
DARAM6: 01C000h–01DFFFh;
DARAM5: 01A000h–01BFFFh
DARAM7: 01E000h–01FFFFh
Figure 3–3. Extended Program Memory Map
13
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.5.1 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved
at each vector location to accommodate a delayed branch instruction which allows branching to the
appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
15
7
6
5
4
3
2
1
0
CLK
OFF
IPTR
MP/MC
OVLY
AVIS
Reserved
SMUL
SST
R/W-1FF
R/W -
R/W-0 R/W-0
R/W-0 R/W-0 R/W-0
MP/MC
pin
LEGEND: R = Read, W = Write, 0 = Value after reset
Figure 3–4. Processor Mode Status (PMST) Register
14
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Table 3–2. Processor Mode Status (PMST) Register Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these
bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The
RESET instruction does not affect this field.
15–7
IPTR
1FFh
Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
program memory space.
-
-
MP/MC = 0: The on-chip ROM is enabled and addressable.
MP/MC = 1: The on-chip ROM is not available.
MP/MC
pin
6
5
4
MP/MC
OVLY
AVIS
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This
pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can
also be set or cleared by software.
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
-
-
OVLY = 0: The on-chip RAM is addressable in data space but not in program space.
0
0
OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses
0h to 7Fh), however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.
-
-
AVIS = 0: The external address lines do not change with the internal program address. Control and
data lines are not affected and the address bus is driven with the last address on the bus.
AVIS = 1: This mode allows the internal program address to appear at the pins of the 5410A so that
the internal program address can be traced. Also, it allows the interrupt vector to be decoded in
conjunction with IACK when the interrupt vectors reside on on-chip memory.
3
2
Reserved
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.
CLKOFF
SMUL
SST
0
0
0
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.
1
0
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.
3.6 On-Chip Peripherals
The 5410A device has the following peripherals:
•
•
•
•
•
•
•
•
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8/16)
Three multichannel buffered serial ports (McBSPs)
A hardware timer
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
15
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.6.1 Software-Programmable Wait-State Generator
The software wait-state generator of the 5410A can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of
the 5410A.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3–5 and described in Table 3–3.
15
14
12 11
9
8
6
5
3
2
0
XPA
I/O
R/W-111
Data
R/W-111
Data
Program
R/W-111
Program
R/W-111
R/W-0
R/W-111
LEGEND: R=Read, W=Write, 0 = Value after reset
Figure 3–5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
Table 3–3. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
15
XPA
0
I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
14–12
11–9
8–6
I/O
111
Upper data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Data
Data
111
111
Lower data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: xx8000 – xxFFFFh
XPA = 1: 400000h – 7FFFFFh
5–3
2–0
Program
Program
111
111
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: xx0000 – xx7FFFh
XPA = 1: 000000 – 3FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
16
SPRS139D
November 2000 – Revised July 2002
Functional Overview
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3–6 and
described in Table 3–4.
15
1
0
SWSM
Reserved
R/W-0
R/W-0
LEGEND: R = Read, W = Write, 0 = Value after reset
Figure 3–6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3–4. Software Wait-State Control Register (SWCR) Bit Fields
PIN
NAME
RESET
VALUE
FUNCTION
NO.
15–1
Reserved
0
These bits are reserved and are unaffected by writes.
Softwarewait-statemultiplier. UsedtomultiplythenumberofwaitstatesdefinedintheSWWSRbyafactor
of 1 or 2.
0
SWSM
0
-
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.6.2 Programmable Bank-Switching
Programmable bank-switching logic allows the 5410A to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 3–7 and are described in Table 3–5.
15
14
13
DIVFCT
R/W-11
12
11
3
2
1
0
Rsvd
R
CONSEC
R/W-1
IACKOFF
Rsvd
R
HBH
R/W-0
BH
R/W-0
R/W-1
LEGEND: R = Read, W = Write, 0 = Value after reset
Figure 3–7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
17
November 2000 – Revised July 2002
SPRS139D
Functional Overview
Table 3–5. Bank-Switching Control Register (BSCR) Fields
RESET
VALUE
BIT
NAME
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
CONSEC = 0:
CONSEC = 1:
†
15
CONSEC
1
Consecutivebank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock.
DIVFCT = 00: CLKOUT is not divided.
13–14 DIVFCT
11
DIVFCT = 01: CLKOUT is divided by 2 from the DSP clock.
DIVFCT = 10: CLKOUT is divided by 3 from the DSP clock.
DIVFCT = 11: CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
IACKOFF = 0: The IACK signal output off function is disabled.
IACKOFF = 1: The IACK signal output off function is enabled.
Reserved
12
IACKOFF
1
11–3
Rsvd
HBH
–
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
HBH = 0:
The bus holder is disabled except when HPI16=1.
2
0
Thebus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
HBH = 1:
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
BH = 0:
BH = 1:
Reserved
The bus holder is disabled.
1
0
BH
0
Thebusholderisenabled. Whennotdriven, thedatabus, D[15:0]isheldinthepreviouslogic
level.
Rsvd
–
†
For additional information, see Section 3.11 of this document.
The 5410A has an internal register that holds the MSB of the last address used for a read or write operation
in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address
used for the current read does not match that contained in this internal register, the MSTRB (memory strobe)
signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new
address. The contents of the internal register are replaced with the MSB for the read of the current address.
If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts
are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
•
•
•
•
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
18
SPRS139D
November 2000 – Revised July 2002
Functional Overview
3.6.3 Bus Holders
The 5410A has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of
theaddressbus(A[16–0]), databus(D[15–0]), andtheHPIdatabus(HD[7–0]). Buskeeperenabling/disabling
is described in Table 3–5.
Table 3–6. Bus Holder Control Bits
HPI16 PIN
BH
0
HBH
D[15–0]
OFF
OFF
ON
A[16–0]
OFF
OFF
OFF
OFF
OFF
ON
HD[7–0]
OFF
ON
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
OFF
ON
1
ON
0
OFF
OFF
ON
ON
0
ON
1
OFF
ON
ON
1
ON
ON
3.7 Parallel I/O Ports
The 5410A has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5410A can
interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding
circuits.
3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
The 5410A host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit
HPI found on earlier TMS320C54x DSPs (542, 545, 548, and 549). The 5410A HPI can be used to interface
to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external
devices in program/data/IO spaces), the 5410A HPI can be configured as an HPI16 to interface to a 16-bit
host. This configuration can be accomplished by connecting the HPI16 pin to logic “1”.
When the HPI16 pin is connected to a logic “0”, the 5410A HPI is configured as an HPI8. The HPI8 is an 8-bit
parallel port for interprocessor communication. The features of the HPI8 include:
Standard features:
•
•
•
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and C54x interrupt capability
Multiple data strobes and control pins for interface flexibility
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — the HPI address register (HPIA), the HPI data register (HPID),
and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the
HPIC register is accessible by both the host and the 5410A.
Enhanced features:
•
•
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
C54x is a trademark of Texas Instruments.
19
November 2000 – Revised July 2002
SPRS139D
Functional Overview
The HPI16 is an enhanced 16-bit version of the TMS320C54x DSP 8-bit host-port interface (HPI8). The
HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master
of the interface. Some of the features of the HPI16 include:
•
•
•
•
16-bit bidirectional data bus
Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
Only nonmultiplexed address/data modes are supported
17-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal
extended address pages)
•
•
HRDY signal to hold off host accesses due to DMA latency
The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP.
NOTE: Only the nonmultiplexed mode is supported when the 5410A HPI is configured as a
HPI16 (see Figure 3–8).
The 5410A HPI functions as a slave and enables the host processor to access the on-chip memory. A major
enhancement to the 5410A HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host
accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same
location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are always
synchronized to the 5410A clock, an active input clock (CLKIN) is required for HPI accesses during IDLE
states, and host accesses are not allowed while the 5410A reset pin is asserted.
3.7.2 HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)
via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 17-bit HA address bus. The
host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access
with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register
is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate
a DMA read or write access. Figure 3–8 shows a block diagram of the HPI16 in nonmultiplexed mode.
HOST
HPI16
PPD[15:0]
DATA[15:0]
HPID[15:0]
HINT
DMA
Address[16:0]
HCNTL0
V
CC
HCNTL1
HBIL
HAS
R/W
HR/W
54xx
CPU
Data Strobes
HDS1, HDS2, HCS
HRDY
READY
Figure 3–8. Host-Port Interface — Nonmultiplexed Mode
20
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Address (Hex)
000 0000
Reserved
000 005F
000 0060
Scratch-Pad
RAM
000 007F
000 0080
DARAM0 –
DARAM3
000 7FFF
000 8000
Reserved
001 7FFF
001 8000
DARAM4 –
DARAM7
001 FFFF
002 0000
Reserved
07F FFFF
Figure 3–9. HPI Memory Map
21
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.8 Multichannel Buffered Serial Ports (McBSPs)
The 5410A device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x
devices, codecs, and other devices in a system. There are three multichannel buffered serial ports (McBSPs)
on board (three per subsystem).
The McBSP provides:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
•
Direct interface to:
–
–
–
–
–
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant device
AC97-compliant device
Serial peripheral interface (SPI)
•
•
•
•
•
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The 5410A McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator
input clock source. On previous TMS320C5000 DSP platform devices, the McBSP sample rate input clock
can be driven from one of two possible choices: the internal CPU clock , or the external CLKS pin. However,
most C5000 DSP devices have only the internal CPU clock as a possible source because the CLKS pin is
not implemented on most device packages.
To accommodate applications that require an external reference clock for the sample rate generator, the
5410A McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured
as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin
control register (PCR) bit 7 – enhanced sample clock mode (SCLKME), and sample rate generator register
2 (SRGR2) bit 13 – McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR
contained in the McBSPs on previous C5000 devices. The new bit layout of the PCR is shown in Figure 3–10.
For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced
Peripherals (literature number SPRU302).
TMS320C5000 and C5000 are trademarks of Texas Instruments.
22
SPRS139D
November 2000 – Revised July 2002
Functional Overview
15
14
13
12
11
10
9
8
Reserved
R,+0
XIOEN
RW,+0
RIOEN
RW,+0
FSXM
RW,+0
FSRM
RW,+0
CLKXM
RW,+0
CLKRM
RW,+0
7
6
5
4
3
2
1
0
SCLKME
RW,+0
CLKS_STAT
R,+0
DX_STAT
R,+0
DR_STAT
R,+0
FSXP
RW,+0
FSRP
RW,+0
CLKXP
RW,+0
CLKRP
RW,+0
Note: R = Read, W = Write, +0 = Value at reset
Figure 3–10. Pin Control Register (PCR)
Theselectionofthesamplerategenerator(SRG)clockinputsourceismadebythecombinationoftheCLKSM
and SCLKME bit values as shown in Table 3–7.
Table 3–7. Sample Rate Generator Clock Source Selection
SCLKME
CLKSM
SRG Clock Source
0
0
0
1
CLKS (not available as a pin on 5410A)
CPU clock
BCLKR pin
BCLKX pin
1
1
0
1
When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is
automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the
SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by
setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the
BCLKX pin because the BCLKR output is automatically disabled.
The McBSP supports independent selection of multiple channels for the transmitter and receiver. When
multiplechannelsareselected, eachframerepresentsatime-divisionmultiplexed(TDM)datastream. Inusing
time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save
memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for
transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled.
The 5410A McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in
the multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3–11 and Figure 3–12. For
a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals
(literature number SPRU302).
•
In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each
containing 16 channels as shown in Figure 3–11 and Figure 3–12. This is compatible with the McBSPs
used in earlier TMS320C54x devices, where only 32-channel selection is enabled (default).
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
R,+0
XMCME
RW,+0
XPBBLK
RW,+0
XPABLK
RW,+0
XCBLK
R,+0
XMCM
RW,+0
Note: R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2
Figure 3–11. Multichannel Control Register 2x (MCR2x)
23
November 2000 – Revised July 2002
SPRS139D
Functional Overview
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
R,+0
RMCME
RW,+0
RPBBLK
RW,+0
RPABLK
RW,+0
RCBLK
R,+0
RMCM
RW,+0
Note: R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2
Figure 3–12. Multichannel Control Register 1x (MCR1x)
•
In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection
capability. Twelve new registers (RCERCx–RCERHx and XCERCx–XCERHx) are used to enable the 128
channel selection. The subaddresses of the new registers are shown in Table 3–19. These new registers,
functionally equivalent to the RCERA0–RCERB1 and XCERA0–XCERB1 registers in the 5420, are used
to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the
128 channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112
to 127) of MCBSP1 for each DSP subsystem. See Figure 3–13, Table 3–8, Figure 3–14, and Table 3–9
for bit layout and function of the receive and transmit registers .
15
RCERyz15
RW,+0
7
14
RCERyz14
RW,+0
6
13
RCERyz13
RW,+0
5
12
RCERyz12
RW,+0
4
11
RCERyz11
RW,+0
3
10
RCERyz10
RW,+0
2
9
8
RCERyz9
RW,+0
1
RCERyz8
RW,+0
0
RCERyz7
RW,+0
RCERyz6
RW,+0
RCERyz5
RW,+0
RCERy4
RW,+0
RCERyz3
RW,+0
RCERyz2
RW,+0
RCERyz1
RW,+0
RCERyz0
RW,+0
Note: R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 3–13. Receive Channel Enable Registers Bit Layout for Partitions A to H
Table 3–8. Receive Channel Enable Registers for Partitions A to H
Bit
Name
Function
15–0
RCERyz(15:0)
Receive Channel Enable Register
RCERyz n = 0
RCERyz n = 1
Disables reception of nth channel in partition y.
Enables reception of nth channel in partition y.
Note: y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0
15
XCERyz15
RW,+0
7
14
XCERyz14
RW,+0
6
13
XCERyz13
RW,+0
5
12
XCERyz12
RW,+0
4
11
XCERyz11
RW,+0
3
10
XCERyz10
RW,+0
2
9
8
XCERyz9
RW,+0
1
XCERyz8
RW,+0
0
XCERyz7
RW,+0
XCERyz6
RW,+0
XCERyz5
RW,+0
XCERy4
RW,+0
XCERyz3
RW,+0
XCERyz2
RW,+0
XCERyz1
RW,+0
XCERyz0
RW,+0
Note: R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 3–14. Transmit Channel Enable Registers Bit Layout for Partitions A to H
24
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Table 3–9. Transmit Channel Enable Registers for Partitions A to H
Bit
Name
Function
15–0
XCERyz(15:0)
Transmit Channel Enable Register
XCERyz n = 0
XCERyz n = 1
Disables transmit of nth channel in partition y.
Enables transmit of nth channel in partition y.
Note: y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI)
protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP
is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or
as a slave.
TheMcBSPisfullystaticandoperatesatarbitrarilylowclockfrequencies. ThemaximumMcBSPmultichannel
operating frequency on the 5410A is 9 MBps. Nonmultichannel operation is limited to 38 MBps.
3.9 Hardware Timer
The 5410A device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by
one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer
can be stopped, restarted, reset, or disabled by specific status bits.
3.10 Clock Generator
The clock generator provides clocks to the 5410A device, and consists of a phase-locked loop (PLL) circuit.
The clock generator requires a reference clock input, which can be provided from an external clock source.
The reference clock input is then divided by two (DIV mode) to generate clocks for the 5410A device, or the
PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency
by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an
adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
5410A device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5410A to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: The crystal oscillator function is not supported by all die revisions of the 5410A device.
See the TMS320VC5410A Silicon Errata (literature number SPRZ187) to verify which die
revisions support this functionality.
25
November 2000 – Revised July 2002
SPRS139D
Functional Overview
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a
built-in software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note
that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state
of the CLKMD1 – CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference
Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options
are shown in Table 3–10.
Table 3–10. Clock Mode Settings at Reset
CLKMD RESET
†
CLOCK MODE
CLKMD1
CLKMD2
CLKMD3
VALUE
0000h
9007h
4007h
1007h
F007h
0000h
F000h
—
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
1/2 (PLL and Oscillator disabled)
PLL x 10 (Oscillator enabled)
PLL x 5 (Oscillator enabled)
PLL x 2(Oscillator enabled)
PLL x 1 (Oscillator enabled)
1/2 (PLL disabled, Oscillator enabled)
1/4 (PLL disabled, Oscillator enabled)
Reserved (Bypass mode)
†
The external CLKMD1–CLKMD3 pins are sampled to determine the desired clock generation mode
whileRSislow. Followingreset, theclockgenerationmodecanbereconfiguredbywritingtotheinternal
clock mode register in software. However, the oscillator enable/disable selection is performed
independently of the state of RS; therefore, if CLKMD1–CLKMD3 are changed following reset, the
oscillatorenable/disable selection may change, but other aspects of the clock generation mode will not.
3.11 Enhanced External Parallel Interface (XIO2)
The 5410A external interface has been redesigned to include several improvements, including: simplification
of the bus sequence, more immunity to bus contention when transitioning between read and write operations,
the ability for external memory access to the DMA controller, and optimization of the power-down modes.
The bus sequence on the 5410A still maintains all of the same interface signals as on previous 54x devices,
but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a
leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
54x devices is available.
26
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Figure 3–15 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode,
or single memory reads in consecutive mode. The accesses shown in Figure 3–15 always require 3 CLKOUT
cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3–15. Nonconsecutive Memory Read and I/O Read Bus Sequence
27
November 2000 – Revised July 2002
SPRS139D
Functional Overview
Figure 3–16 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown
in Figure 3–16 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads
performed.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
READ
READ
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 3–16. Consecutive Memory Read Bus Sequence (n = 3 reads)
28
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Figure 3–17 shows the bus sequence for all memory writes and I/O writes. The accesses shown in
Figure 3–17 always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
WRITE
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 3–17. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more
information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the TMS320C5000 DSP
platformbyswitchingofftheinternalclockstotheinterfacewhenitisnotbeingused. Thispower-savingfeature
is automatic, requires no software setup, and causes no latency in the operation of the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching
cycles when crossing 32K memory boundaries (see Section 3.6.2), the ability to program up to 14 wait states
through software (see Section 3.6.1), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing
down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral
devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow
down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides
a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled
through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3–5).
3.12 DMA Controller
The 5410A direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA allows movements of data to and from internal program/data memory,
internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
29
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.12.1 Features
The DMA has the following features:
•
•
•
•
•
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
be post-decremented, or be adjusted by a programmable value.
•
•
•
Each read or write internal transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.12.2 DMA External Access
The 5410A DMA supports external accesses to extended program, extended data, and extended I/O memory.
These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be used
for external memory accesses. The DMA external accesses require a minimum of 8 cycles for external writes
and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive mode (CONSEC = 1),
wait state is set to two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the
external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes
precedence over XIO requests.
•
Only two channels are available for external accesses. (One for external reads and one for external
writes.)
•
•
•
•
•
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from the peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external-to-external transfers.
The DMA does not support sychronized external transfers.
To allow the DMA access to extended data pages, the SLAXS and DLAXS bits are added to the DMMCRn
register (see Figure 3–18).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CT
AUTO
INIT
DINM IMOD
SLAXS
SIND
DMS
DLAXS
DIND
DMD
MOD
Figure 3–18. DMA Transfer Mode Control Register (DMMCRn)
These new bit fields were created to allow the user to define the space-select for the DMA (internal/external).
The functions of the DLAXS and SLAXS bits are as follows:
DLAXS(DMMCRn[5]) Destination
SLAXS(DMMCRn[11]) Source
0 = No external access (default internal)
1 = External access
0 = No external access (default internal)
1 = External access
Table 3–11 lists the DMD bit values and their corresponding destination space.
30
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Table 3–11. DMD Section of the DMMCRn Register
DMD
DESTINATION SPACE
00
PS
DS
01
10
I/O
11
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the program
address map. When the cells are mapped into program space, the device automatically accesses them when
their addresses are within bounds. When the address generation logic generates an address outside its
bounds, the device automatically generates an external access.
3.12.3 DMPREC Issue
When updating the DE bits of the DMPREC register while one or more DMA channel transfers are in progress,
it is possible for the write to the DMPREC to cause an additional transfer on one of the active channels.
The problem occurs when an active channel completes a transfer at the same time that the user updates the
DMPREC register. When the transfer completes, the DMA logic attempts to clear the DE bit corresponding
to the complete channel transfer, but the register is instead updated with the CPU write (usually an ORM
instruction) which can set the bit and cause an additional transfer on the channel. See the TMS320VC5410A
Digital Signal Processor Silicon Errata (literature number SPRZ187) for further clarification.
A hardware workaround has been implemented in revision A of the 5410A device. This solution consists of
an additional memory mapped register, DMCECTL (DMA Channel Enable Control), at address 0x003E, with
the following characteristics:
15
14
6
5
4
3
2
1
0
Set/Reset
W–0
Reserved
CH5
W–0
CH4
W–0
CH3
W–0
CH2
W–0
CH1
W–0
CH0
W–0
W–0
Figure 3–19. DMA Channel Enable Control Register (DMCECTL)
Table 3–12. DMA Channel Enable Control Register (DMCECTL) Bit Description
RESET
VALUE
BIT FIELD
DESCRIPTION
CH0–CH5
0
These bits are used in conjunction with the set/reset bit to write to the individual DE bits of the
DMPREC register.
0) Corresponding DE bit in the DMPREC register is unaffected by the Set/Reset bit.
1) Corresponding bit in the DMPREC register is set or cleared depending on the state of
Set/Reset.
Reserved
Set/Reset
0
0
Reserved.
Sets or clears individual DE bits of the DMPREC register according to the values of CH0–CH5.
0) Clears the DE bits of the DMPREC register as specified by CH0–CH5.
1) Sets the DE bits of the DMPREC register as specified by CH0–CH5.
Use this register to enable or disable DMA channels instead of writing to the DMPREC register. For example,
to enable channels zero and five, write a value of 0x8021 to address 0x03E. In this case only DE0 and DE5
of the DMPREC are set to 1. Or for another example, to disable channel one, write a value of 0x02 to address
0x03E. In this case only DE1 is cleared. Note that this is a write-only register
31
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.12.4 DMA Memory Map
The DMA memory map, shown in Figure 3–20, allows the DMA transfer to be unaffected by the status of the
MP/MC, DROM, and OVLY bits.
Program
Program
Program
Reserved
Hex
010000
Hex
xx0000
Hex
0000
005F
0060
On-Chip
DARAM0
8K Words
DLAXS = 0
SLAXS = 0
1FFF
2000
On-Chip
DARAM1
8K Words
3FFF
4000
Reserved
On-Chip
DARAM2
8K Words
5FFF
6000
On-Chip
DARAM3
8K Words
017FFF
018000
7FFF
8000
Reserved
On-Chip
DARAM 4
8K Words
019FFF
01A000
On-Chip
DARAM 5
8K Words
01BFFF
01C000
On-Chip
DARAM 6
8K Words
Reserved
01DFFF
01E000
On-Chip
DARAM 7
8K Words
xxFFFF
01FFFF
FFFF
Page 1
Page 0
Page 2 – 127
Figure 3–20. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
32
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Data Space (0000 – 005F)
Hex
Data Space
I/O Space
Hex
0000
0000
001F
0020
0021
0022
0000
Reserved
Data Space
(See Breakout)
DRR20
DRR10
DXR20
005F
0060
0023
0024
002F
0030
0031
0032
0033
DXR10
Scratch-Pad
RAM
Reserved
DRR22
DRR12
DXR22
DXR12
007F
0080
On-Chip
DARAM0
8K Words
1FFF
2000
On-Chip
DARAM1
8K Words
0034
0035
0036
0037
Reserved
RCERA2
XCERA2
3FFF
4000
On-Chip
DARAM2
8K Words
0038
0039
Reserved
Reserved
5FFF
6000
003A
RECRA0
XECRA0
On-Chip
DARAM3
8K Words
003B
003C
003F
0040
0041
Reserved
DRR21
7FFF
8000
On-Chip
DARAM4
8K Words
DRR11
DXR21
DXR11
0042
0043
9FFF
A000
On-Chip
DARAM5
8K Words
0044
0049
004A
Reserved
RCERA1
BFFF
C000
On-Chip
DARAM6
8K Words
004B
XCERA1
004C
005F
Reserved
DFFF
E000
On-Chip
DARAM7
8K Words
FFFF
FFFF
Figure 3–21. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.5 DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.6 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
3.12.7 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR,
and DMGFR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values for
the next block transfer any time after the current block transfer begins.
•
Repetitiveoperation:TheCPUdoesnotpreloadthereloadregisterwithnewvaluesforeachblocktransfer
but only loads them on the first block transfer.
33
November 2000 – Revised July 2002
SPRS139D
Functional Overview
The 5410A DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has
its own DMA reload register set. For example, the DMA reload register set for channel 0 has DMGSA0,
DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and
DMGFR1, etc.
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown in
Figure 3–22.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FREE AUTOIX
DPRC[5:0]
INTOSEL
DE[5:0]
Figure 3–22. DMPREC Register
Table 3–13. DMA Reload Register Selection
AUTOIX
0 (default)
1
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0
Each DMA channel uses its own set of reload registers
3.12.8 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn=0FFFFh). Inautoinitializationmode, oncethelastframeistransferred, thecounterisreloaded
with the DMA global count reload register (DMGCR).
3.12.9 DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
3.12.10 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA transfer
mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index
DMFRI0andDMFRI1, theDMAallowsdifferentadjustmentamountsdependingonwhetherornottheelement
transfer is the last in the current frame. The normal adjustment value (element index) is contained in the
element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame,
is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
•
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.
34
SPRS139D
November 2000 – Revised July 2002
Functional Overview
3.12.11 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available
modes are shown in Table 3–14.
Table 3–14. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multiframe
DINM
IMOD
INTERRUPT
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
Multiframe
Either
Either
No interrupt generated
3.12.12 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events
and the DSYN values are shown in Table 3–15.
Table 3–15. DMA Synchronization Events
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
McBSP0 receive event – ABIS mode
McBSP0 transmit event – ABIS mode
McBSP2 receive event – ABIS mode
McBSP2 transmit event – ABIS mode
McBSP1 receive event – ABIS mode
McBSP1 transmit event – ABIS mode
Timer interrupt event
1000b
1001b
1010b
1011b
1100b
1101b
1110b
External interrupt 3
1111b
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the 5410A is reset, the interrupts from these three DMA channels are deselected. The INTOSEL bit field in
the DMPREC register can be used to select these interrupts, as shown in Table 3–16.
Table 3–16. DMA Channel Interrupt Selection
INTOSEL Value
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
00b (reset)
01b
BXINT2
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
35
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.13 General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the 5410A has pins that can be configured for general-purpose
I/O. These pins are:
•
•
18 McBSP pins — BCLKX0/1/2, BCLKR0/1/2, BDR0/1/2, BFSX0/1/2, BFSR0/1/2, BDX0/1/2
8 HPI data pins—HD0–HD7
The general-purpose I/O function of these pins is only available when the primary pin function is not required.
3.13.1 McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose
inputs or outputs. For more details on this feature, see Section 3.8.
3.13.2 HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the
HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two memory-mapped
registers are used to control the GPIO function of the HPI data pins—the general-purpose I/O control register
(GPIOCR) and the general-purpose I/O status register (GPIOSR). The GPIOCR is shown in Figure 3–23.
15
8
7
6
5
4
3
2
1
0
DIR2
Reserved
0
DIR7
R/W-0
DIR6
R/W-0
DIR5
R/W-0
DIR4
R/W-0
DIR3
R/W-0
DIR1
R/W-0
DIR0
R/W-0
R/W-0
Figure 3–23. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
The direction bits (DIRx) are used to configure HD0–HD7 as inputs or outputs.
The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in
Figure 3–24.
15
8
7
6
5
4
3
2
1
0
Reserved
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Figure 3–24. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
3.14 Device ID Register
A read-only memory-mapped register has been added to the 5410A to allow user application software to
identify on which device the program is being executed.
15
8
7
4
3
0
Chip Revision
R
Chip ID
R
SUBSYSID
R
Bits 15:8: Chip_ID (hex code of 10)
Bits 7:4: Chip_Revision ID
Bits 3:0: Subsystem_ID (0000b for single core device)
Figure 3–25. Device ID Register (CSIDR) [MMR Address 003Eh]
36
SPRS139D
November 2000 – Revised July 2002
Functional Overview
3.15 Memory-Mapped Registers
The 5410A has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to
1Fh. Each 5410A device also has a set of memory-mapped registers associated with peripherals. Table 3–17
gives a list of CPU memory-mapped registers (MMRs) available on 5410A. Table 3–18 shows additional
peripheral MMRs associated with the 5410A.
Table 3–17. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
—
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2–5
6
2–5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15–0)
AH
9
9
Accumulator A high word (31–16)
Accumulator A guard bits (39–32)
Accumulator B low word (15–0)
Accumulator B high word (31–16)
Accumulator B guard bits (39–32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
REA
PMST
XPC
—
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
37
November 2000 – Revised July 2002
SPRS139D
Functional Overview
Table 3–18. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DESCRIPTION
DEC
HEX
DRR20
DRR10
DXR20
DXR10
TIM
32
20
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
33
21
34
22
35
23
36
24
PRD
37
25
Timer Period Register
TCR
38
26
Timer Control Register
—
39
27
Reserved
SWWSR
BSCR
—
40
28
Software Wait-State Register
Bank-Switching Control Register
Reserved
41
29
42
2A
SWCR
HPIC
43
2B
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
44
2C
—
45–47
48
2D–2F
30
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
49
31
50
32
51
33
†
†
52
34
McBSP 2 Subbank Address Register
†
53
35
McBSP 2 Subbank Data Register
Reserved
54–55
56
36–37
38
SPSA0
SPSD0
—
McBSP 0 Subbank Address Register
†
57
39
McBSP 0 Subbank Data Register
Reserved
58–59
60
3A–3B
3C
GPIOCR
GPIOSR
CSIDR
—
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
61
3D
62
3E
63
3F
Reserved
DRR21
DRR11
DXR21
DXR11
—
64
40
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
65
41
66
42
67
43
68–71
72
44–47
48
†
McBSP 1 Subbank Address Register
SPSA1
SPSD1
—
†
73
49
McBSP 1 Subbank Data Register
Reserved
74–83
84
4A–53
54
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
DMA Priority and Enable Control Register
‡
85
55
DMA Subbank Address Register
‡
86
56
DMA Subbank Data Register with Autoincrement
‡
DMA Subbank Data Register
87
57
88
58
Clock Mode Register (CLKMD)
Reserved
89–95
59–5F
†
‡
See Table 3–19 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3–20 for a detailed description of the DMA subbank addressed registers.
38
SPRS139D
November 2000 – Revised July 2002
Functional Overview
3.16 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. TheMcBSPsubbankaddressregister(SPSA)isusedasapointertoselectaparticularregisterwithin
the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
Table 3–19 shows the McBSP control registers and their corresponding subaddresses.
Table 3–19. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB-
ADDRESS
DESCRIPTION
NAME
ADDRESS
39h
NAME
ADDRESS
49h
NAME
ADDRESS
35h
SPCR10
SPCR20
RCR10
SPCR11
SPCR21
RCR11
SPCR12
SPCR22
RCR12
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
39h
49h
35h
Serial port control register 2
39h
49h
35h
Receive control register 1
RCR20
39h
RCR21
49h
RCR22
35h
Receive control register 2
XCR10
39h
XCR11
49h
XCR12
35h
Transmit control register 1
XCR20
39h
XCR21
49h
XCR22
35h
Transmit control register 2
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
SRGR12
SRGR22
MCR12
MCR22
RCERA2
RCERA2
XCERA2
XCERA2
PCR2
35h
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
39h
49h
35h
39h
49h
35h
39h
49h
35h
Multichannel register 2
39h
49h
35h
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
Additional channel enable register for
128-channel selection
RCERC0
RCERD0
XCERC0
XCERD0
RCERE0
RCERF0
XCERE0
XCERF0
RCERG0
RCERH0
XCERG0
XCERH0
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
RCERC1
RCERD1
XCERC1
XCERD1
RCERE1
RCERF1
XCERE1
XCERF1
RCERG1
RCERH1
XCERG1
XCERH1
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
RCERC2
RCERD2
XCERC2
XCERD2
RCERE2
RCERF2
XCERE2
XCERF2
RCERG2
RCERH2
XCERG2
XCERH2
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
39
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.17 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincrementedsothatasubsequentaccessaffectsthenextregisterwithinthesubbank. Thisautoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 3–20 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
Table 3–20. DMA Subbank Addressed Registers
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
40
SPRS139D
November 2000 – Revised July 2002
Functional Overview
Table 3–20. DMA Subbank Addressed Registers (Continued)
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
DMDSTP
DMIDX0
DMIDX1
DMFRI0
DMFRI1
DMGSA0
DMGDA0
DMGCR0
DMGFR0
–
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMA frame index register 1
DMA global source address reload register, channel 0
DMA global destination address reload register, channel 0
DMA global count reload register, channel 0
DMA global frame count reload register, channel 0
Reserved
–
Reserved
DMGSA1
DMGDA1
DMGCR1
DMGFR1
DMGSA2
DMGDA2
DMGCR2
DMGFR2
DMGSA3
DMGDA3
DMGCR3
DMGFR3
DMGSA4
DMGDA4
DMGCR4
DMGFR4
DMGSA5
DMGDA5
DMGCR5
DMGFR5
DMCECTL
DMA global source address reload register, channel 1
DMA global destination address reload register, channel 1
DMA global count reload register, channel 1
DMA global frame count reload register, channel 1
DMA global source address reload register, channel 2
DMA global destination address reload register, channel 2
DMA global count reload register, channel 2
DMA global frame count reload register, channel 2
DMA global source address reload register, channel 3
DMA global destination address reload register, channel 3
DMA global count reload register, channel 3
DMA global frame count reload register, channel 3
DMA global source address reload register, channel 4
DMA global destination address reload register, channel 4
DMA global count reload register, channel 4
DMA global frame count reload register, channel 4
DMA global source address reload register, channel 5
DMA global destination address reload register, channel 5
DMA global count reload register, channel 5
DMA global frame count reload register, channel 5
DMA channel enable control
41
November 2000 – Revised July 2002
SPRS139D
Functional Overview
3.18 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3–21.
Table 3–21. Interrupt Locations and Priorities
LOCATION
PRIORITY
NAME
FUNCTION
DECIMAL
0
HEX
00
RS, SINTR
NMI, SINT16
SINT17
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
4
04
8
08
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Software interrupt #17
SINT18
12
0C
10
Software interrupt #18
SINT19
16
Software interrupt #19
SINT20
20
14
Software interrupt #20
SINT21
24
18
Software interrupt #21
SINT22
28
1C
20
Software interrupt #22
SINT23
32
Software interrupt #23
SINT24
36
24
Software interrupt #24
SINT25
40
28
Software interrupt #25
SINT26
44
2C
30
Software interrupt #26
SINT27
48
Software interrupt #27
SINT28
52
34
Software interrupt #28
SINT29
56
38
Software interrupt #29
SINT30
60
3C
40
Software interrupt #30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
RINT0, SINT4
XINT0, SINT5
RINT2, SINT6
XINT2, SINT7
INT3, SINT8
HINT, SINT9
64
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer interrupt
68
44
4
72
48
5
76
4C
50
6
80
7
McBSP #0 receive interrupt (default)
McBSP #0 transmit interrupt (default)
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
External user interrupt #3
HPI interrupt
84
54
8
88
58
9
92
5C
60
10
11
12
13
14
15
16
—
96
100
104
108
112
116
120–127
64
RINT1, SINT10
XINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
68
McBSP #1 receive interrupt (default)
McBSP #1 transmit interrupt (default)
DMA channel 4 (default)
DMA channel 5 (default)
Reserved
6C
70
74
78–7F
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3–26.
15–14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Resvd DMAC5 DMAC4 XINT1 RINT1 HINT
INT3
XINT2 RINT2 XINT0 RINT0
TINT
INT2
INT1
INT0
Figure 3–26. IFR and IMR
42
SPRS139D
November 2000 – Revised July 2002
Documentation Support
4
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
•
•
•
•
•
TMS320C54x DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete user’s guides
Development support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 is a trademark of Texas Instruments.
43
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5410A DSP.
5.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to DV . Figure 5–1 provides the test load circuit
SS
values for a 3.3-V device.
Supply voltage I/O range, DV
Supply voltage core range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.0 V
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
5.2 Recommended Operating Conditions
MIN
2.7
NOM
3.3
MAX
3.6
UNIT
V
DV
CV
Device supply voltage, I/O
DD
DD
Device supply voltage, core (VC5410A-160)
1.55
1.6
1.65
V
CV
Device supply voltage, core (VC5410A-120)
Supply voltage, GND
1.42
1.5
0
1.65
V
V
DD
DV
CV
,
SS
SS
RS, INTn, NMI, X2/CLKIN,
CLKMDn, BCLKRn, BCLKXn,
HCS, HDS1, HDS2, HAS,
TRST, TCK, BIO, Dn, An, HDn
2.4
DV
DV
+ 0.3
DD
DD
V
V
High-level input voltage, I/O
Low-level input voltage
V
IH
(DV
= 2.7 V to 3.6 V)
DD
All other inputs
2
+ 0.3
–0.3
0.8
V
IL
†
I
I
High-level output current
–2
2
mA
mA
°C
OH
†
Low-level output current
Operating case temperature
These output current limits are used for the test conditions on V
OL
T
–40
100
C
†
and V
.
OH
OL
44
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
2.2
MAX
UNIT
(DV
= 2.7 V to 3.0 V), I
= MAX
= MAX
DD
DD
OH
OH
‡
V
V
High-level output voltage
V
OH
(DV
= 3.0 V to 3.6 V), I
2.4
‡
Low-level output voltage
I
= MAX
0.4
V
OL
OL
DV
Input current in high
impedance
I
IZ
A[16:0]
= MAX, V = DV
to DV
DD
–275
275
µA
µA
DD
O
SS
X2/CLKIN
–40
–10
40
800
400
10
TRST, HPI16
HPIENA
With internal pulldown
With internal pulldown, RS = 0
With internal pullups
–10
Input current
I
I
§
(V = DV
I SS
to DV
)
DD
TMS, TCK, TDI, HPI
D[15:0], HD[7:0]
–400
–275
–5
µA
Bus holders enabled, DV
DD
= MAXk
275
5
All other input-only pins
¶
¶
#
I
I
Supply current, core CPU
Supply current, pins
CV
DV
= 1.6 V, f = 160 MHz,
T
T
= 25°C
= 25°C
60
mA
DDC
DD
DD
x
C
C
||
40
= 3.0 V, f = 160 MHz,
mA
mA
DDP
x
IDLE2
IDLE3
PLL × 1 mode, 20 MHz input
Divide-by-two mode, CLKIN stopped
2
Supply current,
standby
I
DD
1h
mA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0–INT3, NMI, X2/CLKIN, CLKMD1–CLKMD3, BCLKR0 – BCLKR2, BCLKX0 – BCLKX2, HCS,
HAS, HDS1, HDS2, BIO, TCK, TRST, D0 – D15, HD0 – HD7, A0 – A16 are LVTTL-compatible.
HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
Clock mode: PLL × 1 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
§
¶
#
||
This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
kV
≤ V ≤ V
hMaterial with high I
or V
≤ V ≤ V
IH(MAX)
IL(MIN)
I
IL(MAX)
DD
IH(MIN)
I
has been observed with a typical I
value of 5 to 10 mA during high temperature testing.
DD
5.4 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this data manual.
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
= 20-pF typical load circuit capacitance
T
Figure 5–1. 3.3-V Test Load Circuit
45
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
5.5 Package Thermal Resistance Characteristics
Table 5–1 provides the estimated thermal resistance characteristics for the recommended package types
used on the TMS320VC5410A DSP.
Table 5–1. Thermal Resistance Characteristics
GGU
PACKAGE
PGE
PACKAGE
PARAMETER
UNIT
R
R
38
5
56
5
°C/W
°C/W
ΘJA
ΘJC
5.6 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
5.7 Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent;
see Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by
the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit, consisting
of the crystal and two load capacitors, is shown in Figure 5–2. The load capacitors, C and C , should be
1
2
chosen such that the equation below is satisfied. C (recommended value of 10 pF)in the equation is the load
L
specified for the crystal.
C1C2
CL +
(C1 ) C2)
Table 5–2. Input Clock Frequency Characteristics
MIN
MAX
UNIT
†
10
‡
20
f
x
Input clock frequency
MHz
†
‡
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz
It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
approaching ∞. The device is characterized at frequencies
c(CI)
46
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
X1
X2/CLKIN
Crystal
C1
C2
Figure 5–2. Internal Divide-by-Two Clock Option With External Crystal
5.8 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.8.1 Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5–4.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 5–3 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5–3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
0
1
1
0
0
1
0
1
1
1/2, PLL disabled
1/4, PLL disabled
1/2, PLL disabled
47
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
Table 5–4 and Table 5–5 assume testing over recommended operating conditions and H = 0.5t
Figure 5–3).
(see
c(CO)
Table 5–4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
VC5410A-120
VC5410A-160
UNIT
MIN
MAX
t
t
t
t
t
Cycle time, X2/CLKIN
20
ns
ns
ns
ns
ns
c(CI)
Fall time, X2/CLKIN
4
4
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
w(CIL)
w(CIH)
Table 5–5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
5410A-120
TYP
5410A-160
TYP
PARAMETER
UNIT
MIN
MAX
MIN
MAX
†
‡
†
‡
t
Cycle time, CLKOUT
8.33
6.25
ns
ns
ns
ns
ns
ns
c(CO)
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
4
7
1
11
4
7
1
11
d(CIH-CO)
t
f(CO)
t
t
t
Rise time, CLKOUT
1
1
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H –3
H
H
H + 3
H + 3
H –3
H
H
H + 3
H + 3
w(COL)
w(COH)
H – 3
H – 3
†
‡
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
t
t
r(CI)
w(CIH)
t
t
f(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–3. External Divide-by-Two Clock Timing
48
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.8.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer
to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for
detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 5–6.
Table 5–6 and Table 5–7 assume testing over recommended operating conditions and H = 0.5t
Figure 5–4).
(see
c(CO)
Table 5–6. Multiply-By-N Clock Option Timing Requirements
5410A-120
5410A-160
UNIT
MIN
20
MAX
200
†
Integer PLL multiplier N (N = 1–15)
†
PLL multiplier N = x.5
PLL multiplier N = x.25, x.75
20
100
50
t
Cycle time, X2/CLKIN
ns
c(CI)
†
20
t
t
t
t
Fall time, X2/CLKIN
4
4
ns
ns
ns
ns
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
w(CIL)
w(CIH)
†
N is the multiplication factor.
Table 5–7. Multiply-By-N Clock Option Switching Characteristics
5410A-120
TYP
5410A-160
TYP
PARAMETER
UNIT
MIN
8.33
4
MAX
MIN
6.25
4
MAX
t
Cycle time, CLKOUT
ns
ns
ns
ns
ns
ns
ms
c(CO)
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
7
2
11
7
2
11
d(CI-CO)
t
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
2
2
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
H
H
H
H
30
30
t
t
f(CI)
w(CIH)
t
t
r(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
tp
r(CO)
Unstable
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–4. Multiply-by-One Clock Timing
49
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
5.9 Memory and Parallel I/O Interface Timing
Address delay times are longer for cycles immediatly following a HOLD operation. All timings related to the
address bus have been seperated in to two cases; one showing normal operation and the other showing the
delays related to the HOLD operation.
5.9.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5–8 and Table 5–9 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t
(see Figure 5–5 and Figure 5–6).
c(CO)
Table 5–8. Memory Read Timing Requirements
5410A-120
5410A-160
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
4H–9
ns
ns
Access time, read data access from address
valid, first read access
t
a(A)M1
†
For a read accesses immediately following a
HOLD operation
4H–11
2H–9
†
t
t
t
Access time, read data access from address valid, consecutive read accesses
ns
ns
ns
a(A)M2
su(D)R
h(D)R
Setup time, read data valid before CLKOUT low
7
0
Hold time, read data valid after CLKOUT low
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5–9. Memory Read Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
– 1
4
6
ns
ns
†
t
Delay time, CLKOUT low to address valid
d(CLKL-A)
For a read accesses immediately following a
HOLD operation
– 1
t
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
– 1
– 1
4
4
ns
ns
d(CLKL-MSL)
t
d(CLKL-MSH)
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
50
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
CLKOUT
t
d(CLKL-A)
†
A[22:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(A)M1
D[15:0]
MSTRB
t
su(D)R
t
h(D)R
†
R/W
†
PS/DS
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–5. Nonconsecutive Mode Memory Reads
51
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
d(CLKL-MSL)
t
d(CLKL-MSH)
†
A[22:0]
t
a(A)M1
t
a(A)M2
D[15:0]
MSTRB
t
t
su(D)R
su(D)R
t
t
h(D)R
h(D)R
†
R/W
†
PS/DS
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–6. Consecutive Mode Memory Reads
52
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.9.2 Memory Write
Table 5–10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
Figure 5–7).
(see
c(CO)
Table 5–10. Memory Write Switching Characteristics
PARAMETER
5410A-120
5410A-160
UNIT
MIN
MAX
For accesses not immediately following a
– 1
4
6
ns
HOLD operation
Delay time, CLKOUT low to address
valid
t
d(CLKL-A)
†
For a read accesses immediately following a
HOLD operation
– 1
2H – 3
2H – 5
ns
ns
ns
For accesses not immediately following a
HOLD operation
Setup time, address valid before MSTRB
low
t
su(A)MSL
†
For a read accesses immediately following a
HOLD operation
t
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
– 1
2H – 5
2H – 5
– 1
4
2H + 6
2H + 6
4
ns
ns
ns
ns
ns
ns
d(CLKL-D)W
t
su(D)MSH
t
h(D)MSH
t
d(CLKL-MSL)
t
2H – 2
– 1
w(SL)MS
t
Delay time, CLKOUT low to MSTRB high
4
d(CLKL-MSH)
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
53
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
d(CLKL-D)W
t
su(A)MSL
†
A[22:0]
t
su(D)MSH
t
h(D)MSH
D[15:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
w(SL)MS
MSTRB
†
R/W
†
PS/DS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–7. Memory Write (MSTRB = 0)
54
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.9.3 I/O Read
Table 5–11 and Table 5–12 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t (see Figure 5–8).
c(CO)
Table 5–11. I/O Read Timing Requirements
5410A-120
5410A-160
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
4H – 9
ns
ns
Access time, read data access from
address valid, first read access
t
a(A)M1
†
For a read accesses immediately following a
HOLD operation
4H – 11
t
t
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
7
ns
ns
su(D)R
0
h(D)R
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Table 5–12. I/O Read Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
– 1
MAX
For accesses not immediately following a
HOLD operation
4
6
ns
ns
†
t
Delay time, CLKOUT low to address valid
d(CLKL-A)
For a read accesses immediately following
a HOLD operation
– 1
t
Delay time, CLKOUT low to IOSTRB low
Delay time, CLKOUT low to IOSTRB high
– 1
– 1
4
4
ns
ns
d(CLKL-IOSL)
t
d(CLKL-IOSH)
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
55
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
†
A[22:0]
t
a(A)M1
t
su(D)R
t
h(D)R
D[15:0]
IOSTRB
†
R/W
†
IS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–8. Parallel I/O Port Read (IOSTRB = 0)
56
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.9.4 I/O Write
Table 5–13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
Figure 5–9).
(see
c(CO)
Table 5–13. I/O Write Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
– 1
MAX
For accesses not immediately following a
HOLD operation
4
6
ns
Delay time, CLKOUT low to address
valid
t
d(CLKL-A)
†
For a read accesses immediately following a
HOLD operation
– 1
ns
ns
ns
For accesses not immediately following a
HOLD operation
2H – 3
Setup time, address valid before IOSTRB
t
su(A)IOSL
†
low
For a read accesses immediately following a
HOLD operation
2H – 5
– 1
t
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
4
ns
ns
ns
ns
ns
ns
d(CLKL-D)W
t
2H – 5 2H + 6
2H – 5 2H + 6
su(D)IOSH
t
h(D)IOSH
t
t
t
– 1
2H – 2
– 1
4
d(CLKL-IOSL)
w(SL)IOS
Delay time, CLKOUT low to IOSTRB high
4
d(CLKL-IOSH)
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT
t
d(CLKL-A)
†
A[22:0]
t
d(CLKL-D)W
t
d(CLKL-D)W
t
su(A)IOSL
D[15:0]
t
su(D)IOSH
t
d(CLKL-IOSH)
t
h(D)IOSH
t
d(CLKL-IOSL)
IOSTRB
t
w(SL)IOS
†
R/W
†
IS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–9. Parallel I/O Port Write (IOSTRB = 0)
57
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
5.10 Ready Timing for Externally Generated Wait States
Table 5–14 and Table 5–15 assume testing over recommended operating conditions and H = 0.5t
Figure 5–10, Figure 5–11, Figure 5–12, and Figure 5–13).
(see
c(CO)
†
Table 5–14. Ready Timing Requirements for Externally Generated Wait States
5410A-120
5410A-160
UNIT
MIN
7
MAX
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
ns
ns
ns
ns
ns
ns
su(RDY)
0
h(RDY)
‡
Valid time, READY after MSTRB low
4H – 4
4H – 4
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H
4H
‡
Valid time, READY after IOSTRB low
‡
Hold time, READY after IOSTRB low
†
Thehardwarewaitstatescanbeusedonlyinconjunctionwiththesoftwarewaitstatestoextendthebuscycles.TogeneratewaitstatesbyREADY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
†
Table 5–15. Ready Switching Characteristics for Externally Generated Wait States
5410A-120
5410A-160
PARAMETER
UNIT
MIN
– 1
– 1
MAX
t
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
4
ns
ns
d(MSCL)
t
4
d(MSCH)
†
Thehardwarewaitstatescanbeusedonlyinconjunctionwiththesoftwarewaitstatestoextendthebuscycles.TogeneratewaitstatesbyREADY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
58
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MCSL)
t
d(MCSH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–10. Memory Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
States
Generated
by READY
Wait
States
Generated
Internally
Trailing
Cycle
Figure 5–11. Memory Write With Externally Generated Wait States
59
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–12. I/O Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
States
Generated
Internally
Trailing
Cycle
Wait
States
Generated
by READY
Figure 5–13. I/O Write With Externally Generated Wait States
60
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.11 HOLD and HOLDA Timings
Table 5–16 and Table 5–17 assume testing over recommended operating conditions and H = 0.5t
Figure 5–14).
(see
c(CO)
Table 5–16. HOLD and HOLDA Timing Requirements
5410A-120
5410A-160
UNIT
MIN
4H+8
7
MAX
t
t
Pulse duration, HOLD low duration
ns
ns
w(HOLD)
Setup time, HOLD before CLKOUT low
su(HOLD)
Table 5–17. HOLD and HOLDA Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
t
t
t
t
t
t
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
3
ns
ns
ns
ns
ns
ns
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
3
3
2H+6
2H+3
2H+3
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2
– 1
4
4
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
– 1
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H–3
w(HOLDA)
61
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
CLKOUT
t
t
su(HOLD)
su(HOLD)
t
w(HOLD)
HOLD
t
t
v(HOLDA)
v(HOLDA)
w(HOLDA)
t
HOLDA
t
t
en(CLKL–A)
dis(CLKL–A)
A[22:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
en(CLKL–RW)
dis(CLKL–RW)
dis(CLKL–S)
dis(CLKL–S)
t
en(CLKL–S)
MSTRB
IOSTRB
t
en(CLKL–S)
Figure 5–14. HOLD and HOLDA Timings (HM = 1)
62
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.12 Reset, BIO, Interrupt, and MP/MC Timings
Table 5–18 assumes testing over recommended operating conditions and H = 0.5t
Figure 5–16, and Figure 5–17).
(see Figure 5–15,
c(CO)
Table 5–18. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5410A-120
5410A-160
UNIT
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
2
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(RS)
h(BIO)
†
Hold time, INTn, NMI, after CLKOUT low
1
h(INT)
Hold time, MP/MC after CLKOUT low
4
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+3
2H+3
4H
2H+2
4H
2H+2
4H
7
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶
Setup time, RS before X2/CLKIN low
3
Setup time, BIO before CLKOUT low
7
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
7
su(INT)
5
su(MPMC)
†
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
IfthePLLmodeisselected,thenatpower-onsequence,oratwakeupfromIDLE3,RSmustbeheldlowforatleast50µstoensuresynchronization
and lock-in of the PLL.
‡
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
X2/CLKIN
t
su(RS)
t
w(RSL)
RS, INTn, NMI
CLKOUT
BIO
t
su(INT)
t
h(RS)
t
su(BIO)
t
h(BIO)
t
w(BIO)S
Figure 5–15. Reset and BIO Timings
63
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
CLKOUT
t
t
t
su(INT)
su(INT)
h(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 5–16. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 5–17. MP/MC Timing
64
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.13 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5–19 assumes testing over recommended operating conditions and H = 0.5t
(see Figure 5–18).
c(CO)
Table 5–19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
– 1
MAX
t
Delay time, CLKOUT low to IAQ low
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKL-IAQL)
t
Delay time, CLKOUT low to IAQ high
Delay time, IAQ low to address valid
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, IACK low to address valid
Hold time, address valid after IAQ high
Hold time, address valid after IACK high
Pulse duration, IAQ low
– 1
4
2
4
4
2
d(CLKL-IAQH)
d(A)IAQ
t
t
– 1
– 1
d(CLKL-IACKL)
t
d(CLKL-IACKH)
d(A)IACK
h(A)IAQ
t
t
t
t
t
– 2
– 2
h(A)IACK
w(IAQL)
2H – 2
2H – 2
Pulse duration, IACK low
w(IACKL)
CLKOUT
A[22:0]
IAQ
t
t
d(CLKL–IAQH)
d(CLKL–IAQL)
t
h(A)IAQ
t
d(A)IAQ
t
w(IAQL)
t
t
t
d(CLKL–IACKH)
d(CLKL–IACKL)
h(A)IACK
t
d(A)IACK
t
w(IACKL)
IACK
Figure 5–18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
65
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
5.14 External Flag (XF) and TOUT Timings
Table 5–20 assumes testing over recommended operating conditions and H = 0.5t
Figure 5–20).
(see Figure 5–19 and
c(CO)
Table 5–20. External Flag (XF) and TOUT Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
– 1
MAX
Delay time, CLKOUT low to XF high
4
t
ns
d(XF)
Delay time, CLKOUT low to XF low
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
– 1
– 1
4
4
4
t
t
t
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
– 1
2H – 4
CLKOUT
t
d(XF)
XF
Figure 5–19. External Flag (XF) Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 5–20. TOUT Timing
66
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.15 Multichannel Buffered Serial Port (McBSP) Timing
5.15.1 McBSP Transmit and Receive Timings
Table 5–21 and Table 5–22 assume testing over recommended operating conditions (see Figure 5–21 and
Figure 5–22).
†
Table 5–21. McBSP Transmit and Receive Timing Requirements
5410A-120
5410A-160
UNIT
MIN
MAX
‡
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
4P
ns
ns
c(BCKRX)
‡
Pulse duration, BCLKR/X high or BCLKR/X low
2P–1
w(BCKRX)
8
1
1
2
7
1
2
3
8
1
0
2
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
Hold time, BDR valid after BCLKR low
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
t
t
Rise time, BCKR/X
Fall time, BCKR/X
6
6
ns
ns
r(BCKRX)
f(BCKRX)
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 0.5 * processor clock
67
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
†
Table 5–22. McBSP Transmit and Receive Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
‡
§
§
t
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4P
D – 1
C – 1
ns
ns
c(BCKRX)
§
§
3
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
D + 1
w(BCKRXH)
w(BCKRXL)
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
C + 1
ns
ns
ns
– 3
0
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
d(BCKXH-BFXV)
11
5
– 1
2
t
ns
ns
ns
ns
10
6
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
t
dis(BCKXH-BDXHZ)
10
10
20
7
¶
– 1
#
t
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
d(BCKXH-BDXV)
2
¶
–1
t
d(BFXH-BDXV)
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX ext
2
11
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 0.5 * processor clock
T
= BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
Minimum delay times also represent minimum output hold times.
¶
#
The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5410A.
t
t
t
c(BCKRX)
w(BCKRXH)
w(BCKRXL)
t
r(BCKRX)
BCLKR
BFSR (int)
BFSR (ext)
t
d(BCKRH–BFRV)
t
d(BCKRH–BFRV)
t
r(BCKRX)
tsu(BFRH–BCKRL)
t
h(BCKRL–BFRH)
t
h(BCKRL–BDRV)
(n–2)
t
su(BDRV–BCKRL)
BDR
Bit (n–1)
(n–3)
(n–4)
(n–3)
(RDATDLY=00b)
t
su(BDRV–BCKRL)
t
h(BCKRL–BDRV)
(n–2)
BDR
(RDATDLY=01b)
Bit (n–1)
t
t
su(BDRV–BCKRL)
h(BCKRL–BDRV)
(n–2)
BDR
(RDATDLY=10b)
Bit (n–1)
Figure 5–21. McBSP Receive Timings
68
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
t
t
c(BCKRX)
w(BCKRXH)
t
r(BCKRX)
t
f(BCKRX)
t
w(BCKRXL)
BCLKX
BFSX (int)
BFSX (ext)
t
d(BCKXH–BFXV)
t
d(BCKXH–BFXV)
t
su(BFXH–BCKXL)
t
h(BCKXL–BFXH)
t
d(BDFXH–BDXV)
Bit (n–1)
t
t
d(BCKXH–BDXV)
(n–3)
BDX
Bit 0
Bit 0
(n–2)
(n–4)
(n–3)
(n–2)
(XDATDLY=00b)
d(BCKXH–BDXV)
(n–2)
BDX
(XDATDLY=01b)
Bit (n–1)
t
d(BCKXH–BDXV)
Bit (n–1)
t
dis(BCKXH–BDXHZ)
BDX
(XDATDLY=10b)
Bit 0
Figure 5–22. McBSP Transmit Timings
69
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
5.15.2 McBSP General-Purpose I/O Timing
Table 5–23 and Table 5–24 assume testing over recommended operating conditions (see Figure 5–23).
Table 5–23. McBSP General-Purpose I/O Timing Requirements
5410A-120
5410A-160
UNIT
MIN
7
MAX
†
t
t
Setup time, BGPIOx input mode before CLKOUT high
ns
ns
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 5–24. McBSP General-Purpose I/O Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
‡
t
Delay time, CLKOUT high to BGPIOx output mode
– 2
4
ns
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
t
su(BGPIO-COH)
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
Mode
BGPIOx Output
‡
Mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5–23. McBSP General-Purpose I/O Timings
70
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.15.3 McBSP as SPI Master or Slave Timing
Table 5–25 to Table 5–32 assume testing over recommended operating conditions (see Figure 5–24,
Figure 5–25, Figure 5–26, and Figure 5–27).
†
Table 5–25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
5410A-120
5410A-160
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
‡
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
2 – 6P
ns
ns
su(BDRV-BCKXL)
5 + 12P
h(BCKXL-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5–26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
5410A-120
5410A-160
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
t
Hold time, BFSX low after BCLKX low
T – 3 T + 4
C – 4 C + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
#
t
t
Delay time, BFSX low to BCLKX high
‡
‡
Delay time, BCLKX high to BDX valid
– 4
5
6P + 2
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C – 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
‡
‡
‡
‡
t
t
2P– 4
6P + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
4P+ 2
8P + 17
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
=
BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5–24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
71
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
†
Table 5–27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
5410A-120
5410A-160
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
‡
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
2 – 6P
ns
ns
su(BDRV-BCKXL)
5 + 12P
h(BCKXH-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5–28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
5410A-120
5410A-160
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
t
Hold time, BFSX low after BCLKX low
C –3 C + 4
T – 4 T + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
#
t
t
Delay time, BFSX low to BCLKX high
‡
‡
‡
‡
‡
‡
Delay time, BCLKX low to BDX valid
– 4
5
6P + 2
10P + 17
10P + 17
8P + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
t
– 2
4
6P – 4
ns
ns
dis(BCKXL-BDXHZ)
t
Delay time, BFSX low to BDX valid
D – 2 D + 4 4P + 2
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
=
BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5–25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
72
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
†
Table 5–29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
5410A-120
5410A-160
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
‡
‡
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
2 – 6P
ns
ns
su(BDRV-BCKXH)
5 + 12P
h(BCKXH-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5–30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
5410A-120
5410A-160
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
t
Hold time, BFSX low after BCLKX high
T – 3 T + 4
D – 4 D + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
#
t
t
Delay time, BFSX low to BCLKX low
Delay time, BCLKX low to BDX valid
‡
‡
– 4
5
6P + 2
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
t
D – 2 D + 3
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
‡
‡
‡
‡
t
t
2P – 4
6P + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
4P + 2
8P + 17
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
=
BCLKX period = (1 + CLKGDV) * 2P
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
LSB
MSB
BCLKX
BFSX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
(n-3)
(n-4)
Figure 5–26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
73
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
†
Table 5–31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
5410A-120
5410A-160
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
‡
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
2 – 6P
ns
ns
su(BDRV-BCKXL)
5 + 12P
h(BCKXL-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5–32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
5410A-120
5410A-160
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
t
Hold time, BFSX low after BCLKX high
D – 3 D + 4
T – 4 T + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
#
t
t
Delay time, BFSX low to BCLKX low
‡
‡
‡
‡
‡
‡
Delay time, BCLKX high to BDX valid
– 4
5
6P + 2
10P + 17
10P + 17
8P + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
t
– 2
4
6P – 4
ns
ns
dis(BCKXH-BDXHZ)
t
Delay time, BFSX low to BDX valid
C – 2 C + 4 4P + 2
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
=
BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
d(BFXL-BCKXL)
BFSX
t
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXH-BDXHZ)
d(BFXL-BDXV)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5–27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
74
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.16 Host-Port Interface Timing
5.16.1 HPI8 Mode
Table 5–33 and Table 5–34 assume testing over recommended operating conditions and P = 0.5 * processor
clock (see Figure 5–28 through Figure 5–31). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0,
HCNTL1, and HR/W.
Table 5–33. HPI8 Mode Timing Requirements
5410A-120
5410A-160
UNIT
MIN
6
MAX
Setup time, HBIL valid before DS low (when HAS is not used), or HBIL valid before HAS
low
t
t
ns
ns
su(HBV-DSL)
Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low
3
h(DSL-HBV)
t
t
t
t
t
Setup time, HAS low before DS low
Pulse duration, DS low
8
13
7
ns
ns
ns
ns
ns
su(HSL-DSL)
w(DSL)
Pulse duration, DS high
w(DSH)
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
3
su(HDV-DSH)
h(DSH-HDV)W
2
t
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
3
0
ns
ns
su(GPIO-COH)
h(GPIO-COH)
t
75
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
Table 5–34. HPI8 Mode Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
10
t
Enable time, HD driven from DS low
Case 1a: Memory accesses when DMAC is active
0
ns
en(DSL-HD)
18P+10–t
w(DSH)
w(DSH)
†
in 16-bit mode and t
< I8H
w(DSH)
Case 1b: Memory accesses when DMAC is active
36P+10–t
†
in 32-bit mode and t
≥ I8H
w(DSH)
Case 1c: Memory accesses when DMAC is active
10
10
†
in 16-bit mode and t
≥ I8H
w(DSH)
Delay time, DS low to HD valid
for first byte of an HPI read
Case 1d: Memory accesses when DMAC is active
t
d(DSL-HDV1)
ns
†
in 32-bit mode and t
≥ I8H
w(DSH)
Case 2a: Memory accesses when DMAC is inactive
10P+10–t
w(DSH)
†
< 10H
and t
w(DSH)
Case 2b: Memory accesses when DMAC is inactive
10
†
and t
≥ 10H
w(DSH)
Case 3: Register accesses
10
10
t
d(DSL-HDV2)
Delay time, DS low to HD valid for second byte of an HPI read
Hold time, HD valid after DS high, for a HPI read
Valid time, HD valid after HRDY high
ns
ns
ns
ns
t
0
h(DSH-HDV)R
t
2
8
v(HYH-HDV)
‡
t
Delay time, DS high to HRDY low
d(DSH-HYL)
Case 1a: Memory accesses when DMAC is active
in 16-bit mode
18P+6
36P+6
†
Case 1b: Memory accesses when DMAC is active
Delay time, DS high to HRDY
high
t
ns
†
d(DSH-HYH)
in 32-bit mode
‡
†
Case 2: Memory accesses when DMAC is inactive
10P+6
§
Case 3: Write accesses to HPIC register
6P+6
6
9
6
ns
ns
ns
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
t
d(COH-HYH)
t
d(COH-HTX)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output
t
5
ns
d(COH-GPIO)
†
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times
are affected by DMAC activity.
The HRDY output is always high when the HCS input is high, regardless of DS timings.
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously,
and do not cause HRDY to be deasserted.
‡
§
76
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
†
HAD
Valid
Valid
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
Valid
t
h(DSH-HDV)R
HD READ
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
Valid
t
h(DSH-HDV)W
HD WRITE
Valid
Valid
t
d(COH-HYH)
Processor
CLK
†
‡
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
Figure 5–28. HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low)
77
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 5–29. HPI-8 Mode Timing, Using HCS to Control Accesses
CLKOUT
t
d(COH-HTX)
HINT
Figure 5–30. HPI-8 Mode, HINT Timing
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
†
†
GPIOx Input Mode
t
d(COH-GPIO)
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
Figure 5–31. GPIOx Timings
78
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
5.16.2 HPI16 Mode
Table 5–35 and Table 5–36 assume testing over recommended operating conditions and P = 0.5 * processor
clock (see Figure 5–32 through Figure 5–34). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are
shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals (literature number SPRU302) for addition information.
Table 5–35. HPI16 Mode Timing Requirements
5410A-120
5410A-160
UNIT
MIN
6
MAX
t
t
t
t
t
t
t
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
ns
ns
ns
ns
ns
ns
ns
su(HBV-DSL)
h(DSL-HBV)
su(HAV-DSH)
su(HAV-DSL)
h(DSH-HAV)
w(DSL)
5
5
–(4P – 6)
1
30
Pulse duration, DS high
10
w(DSH)
Reads
Writes
Reads
Writes
Reads
Writes
10P + 30
10P + 10
16P + 30
16P + 10
24P + 30
24P + 10
8
Memory accesses with no DMA activity.
Cycle time, DS rising edge to
next DS rising edge
t
Memoryaccesses with 16-bit DMA activity.
Memoryaccesses with 32-bit DMA activity.
ns
c(DSH-DSH)
t
t
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
ns
ns
su(HDV-DSH)W
2
h(DSH-HDV)W
79
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
Table 5–36. HPI16 Mode Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
t
Delay time, DS low to HD driven
0
10
ns
d(DSL-HDD)
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t was < 18H
32P+20 – t
w(DSH)
w(DSH)
w(DSH)
w(DSH)
Case 1b: Memory accesses not immediately following a write when
DMAC is active in 16-bit mode
16P + 20
Delay time,
DS low to HD
valid for first
word of an
HPI read
Case 1c: Memory accesses initiated immediately following a write
48P+20 – t
when DMAC is active in 32-bit mode and t
w(DSH)
was < 26H
t
ns
d(DSL-HDV1)
Case 1d: Memory access not immediately following a write when
DMAC is active in 32-bit mode
24P + 20
Case 2a: Memory accesses initiated immediately following a write
20P+20 – t
10P + 20
when DMAC is inactive and t
w(DSH)
was < 10H
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
Memory writes when no DMA is active
10P + 5
Delay
time,
Memory writes with one or more 16-bit DMA channels active
Memory writes with one or more 32-bit DMA channels active
16P + 5
t
ns
DS high to
HRDY high
d(DSH-HYH)
24P + 5
7
6
ns
ns
ns
ns
ns
t
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
v(HYH-HDV)
t
1
h(DSH-HDV)R
t
5
d(COH-HYH)
t
12
12
d(DSL-HYL)
t
Delay time, DS high to HRDY low
d(DSH–HYL)
80
SPRS139D
November 2000 – Revised July 2002
Electrical Specifications
HCS
HDS
t
w(DSH)
t
c(DSH–DSH)
t
t
su(HBV–DSL)
w(DSL)
t
su(HBV–DSL)
h(DSL–HBV)
t
t
h(DSL–HBV)
HR/W
t
su(HAV–DSL)
t
h(DSH–HAV)
HA[16:0]
Valid Address
Valid Address
t
h(DSH–HDV)R
t
d(DSL–HDV1)
t
t
h(DSH–HDV)R
d(DSL–HDV1)
Data
HD[15:0]
HRDY
Data
v(HYH–HDV)
t
d(DSL–HDD)
t
d(DSL–HDD)
t
t
v(HYH–HDV)
t
t
d(DSL–HYL)
d(DSL–HYL)
Figure 5–32. HPI-16 Mode, Nonmultiplexed Read Timings
81
November 2000 – Revised July 2002
SPRS139D
Electrical Specifications
HCS
t
w(DSH)
t
c(DSH–DSH)
HDS
t
su(HBV–DSL)
t
su(HBV–DSL)
t
t
h(DSL–HBV)
h(DSL–HBV)
HR/W
t
su(HAV–DSH)
t
w(DSL)
t
h(DSH–HAV)
Valid Address
Valid Address
su(HDV–DSH)W
HA[16:0]
HD[15:0]
HRDY
t
t
su(HDV–DSH)W
t
h(DSH–HDV)W
t
h(DSH–HDV)W
Data Valid
Data Valid
t
d(DSH–HYH)
t
d(DSH–HYL)
Figure 5–33. HPI-16 Mode, Nonmultiplexed Write Timings
HRDY
t
d(COH–HYH)
CLKOUT
Figure 5–34. HPI-16 Mode, HRDY Relative to CLKOUT
82
SPRS139D
November 2000 – Revised July 2002
Mechanical Data
6
Mechanical Data
6.1 Ball Grid Array Mechanical Data
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
12,10
SQ
9,60 TYP
11,90
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
0,08
0,45
0,35
4073221-2/B 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Figure 6–1. TMS320VC5410A 144-Ball MicroStar BGA Plastic Ball Grid Array Package
MicroStar BGA is a trademark of Texas Instruments.
83
November 2000 – Revised July 2002
SPRS139D
Mechanical Data
6.2 Low-Profile Quad Flatpack Mechanical Data
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
M
0,08
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–ā7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
Figure 6–2. TMS320VC5410A 144-Pin Low-Profile Quad Flatpack (PGE)
84
SPRS139D
November 2000 – Revised July 2002
相关型号：
©2020 ICPDF网 联系我们和版权申明