TN80C186EA25_技术文档

Intel^®80C186EA/80C188EA AND

80L186EA/80L188EA

16-Bit High-Integration Embedded Processors

Datasheet

■ Intel^®80C186 Upgrade for Power Critical Applications

■ Fully Static Operation

■ True CMOS Inputs and Outputs

Product Features

■ Integrated Feature Set

■ Speed Versions Available (3V)

—13 MHz (Intel^®80L186EA13/

80L188EA13)

—Static 186 CPU Core

—Power Save, Idle and Powerdown

Modes

■ Direct Addressing Capability to 1 Mbyte

Memory and 64 Kbyte I/O

—Clock Generator

■ Supports Intel^®80C187 Numeric

Coprocessor Interface (Intel^®80C186EA

only)

—2 Independent DMA Channels

—3 Programmable 16-Bit Timers

—Dynamic RAM Refresh Control Unit

■ Available in the Following Packages:

—68-Pin Plastic Leaded Chip Carrier

(PLCC)

—Programmable Memory and Peripheral

Chip Select Logic

■ Available in Extended Temperature Range

—Programmable Wait State Generator

—Local Bus Controller

(-40°C to +85°C)

—System-Level Testing Support (High

Impedance Test Mode)

■ Speed Versions Available (5V):

—25 MHz (Intel^®80C186EA25/80C188EA25)

—20 MHz (Intel^®80C186EA20/80C188EA20)

—13 MHz (Intel^®80C186EA13/80C188EA13)

The Intel^®80C186EA is a CHMOS high integration embedded microprocessor. The Intel^®

80C186EA includes all of the features of an ``Enhanced Mode'' Intel^®80C186 while adding the

additional capabilities of Idle and Powerdown Modes. In Numerics Mode, the Intel^®80C186EA

interfaces directly with an Intel^®80C187 Numerics Coprocessor.

Order Number: 272432-005

April 2002

Information in this document is provided in connection with Intel^®products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel^®80C186EA/80C188EA AND 80L186EA/80L188EA may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

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other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1.0 Introduction....................................................................................................................................7

2.0 Intel® 80C186EA Core Architecture.............................................................................................9

2.1

2.2

Bus Interface Unit .................................................................................................................9

Clock Generator....................................................................................................................9

3.0 Intel® 80C186EA Peripheral Architecture .................................................................................11

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Interrupt Control Unit ..........................................................................................................11

Timer/Counter Unit .............................................................................................................11

DMA Control Unit................................................................................................................14

Chip-Select Unit..................................................................................................................14

Refresh Control Unit ...........................................................................................................14

Power Management............................................................................................................14

80C187 Interface (80C186EA Only) ...................................................................................15

ONCE Test Mode ...............................................................................................................15

4.0 Intel® 80C186XL and Intel® 80C186EA Differences.................................................................16

4.1

4.2

4.3

4.4

4.5

4.6

Pinout Compatibility ............................................................................................................16

Operating Modes ................................................................................................................16

TTL vs. CMOS Inputs .........................................................................................................16

Timing Specifications..........................................................................................................16

Package Information...........................................................................................................17

Pin Descriptions..................................................................................................................17

5.0 Intel® 80C186EA Pinout..............................................................................................................22

6.0 Package Thermal Specifications................................................................................................24

7.0 Electrical Specification ...............................................................................................................25

7.1

7.2

Absolute Maximum Ratings*...............................................................................................25

Recommended Connections ..............................................................................................25

8.0 DC Specifications ........................................................................................................................26

8.1

8.2

ICC Versus Frequency and Voltage ...................................................................................28

PDTMR Pin Delay Calculation............................................................................................29

Datasheet

3

Contents

9.0 AC Specifications........................................................................................................................30

10.0 AC Test Conditions .....................................................................................................................34

11.0 AC Timing Waveforms ................................................................................................................35

12.0 Derating Curves...........................................................................................................................38

13.0 Reset.............................................................................................................................................39

14.0 Bus Cycle Waveforms.................................................................................................................42

15.0 Product Name Execution Timings .............................................................................................49

16.0 Revision History ..........................................................................................................................56

17.0 Errata ............................................................................................................................................56

4

Datasheet

Contents

Figures

1

2

3

4

5

6

7

8

9

Product Name Block Diagram ......................................................................................................8

Clock Configurations...................................................................................................................10

68-Lead PLCC Pinout Diagram ..................................................................................................23

AC Test Load..............................................................................................................................34

Input and Output Clock Waveform..............................................................................................35

Output Delay and Float Waveform .............................................................................................35

Input Setup and Hold ..................................................................................................................36

Relative Signal Waveform ..........................................................................................................37

Typical Output Delay Variations Versus Load Capacitance .......................................................38

10 Typical Rise and Fall Variations Versus Load Capacitance .......................................................38

11 Powerup Reset Waveforms ........................................................................................................40

12 Warm Reset Waveforms.............................................................................................................41

13 Read, Fetch and Refresh Cycle Waveform ................................................................................42

14 Write Cycle Waveform................................................................................................................43

15 Halt Cycle Waveform ..................................................................................................................44

16 INTA Cycle Waveform ................................................................................................................45

17 HOLD/HLDA Waveform..............................................................................................................46

18 DRAM Refresh Cycle During Hold Acknowledge .......................................................................47

19 Ready Waveform........................................................................................................................48

20 Instruction Set Summary ............................................................................................................50

Tables

1

Peripheral Control Block Registers.............................................................................................12

2

3

4

5

6

7

8

9

Intel® 80C186EA Slave Mode Peripheral Control Block Registers............................................13

Prefix Identification .....................................................................................................................17

Pin Description Nomenclature ....................................................................................................18

Pin Descriptions..........................................................................................................................19

PLCC Pin Names with Package Location...................................................................................22

PLCC Package Location with Pin Names...................................................................................22

Thermal Resistance (qCA) at Various Airflows (in °C/Watt) .......................................................24

DC SPECIFICATIONS (80C186EA/80C188EA) ........................................................................26

10 DC SPECIFICATIONS (80L186EA/80L188EA)..........................................................................27

11 CDEV Values..............................................................................................................................28

12 AC Characteristics—80C186EA25/80C186EA20/80C186EA13 ................................................30

13 AC Characteristics—80L186EA13/80C186EA8 .........................................................................32

14 Relative Timings (80C186EA25/20/13, 80L186EA13)................................................................33

Datasheet

5

Contents

Revision History

Date

Revision

Description

June 2002

April 2002

005

004

Discontinued device reference removal and reformatting.

Datasheet updates

6

Datasheet

Introduction

1.0

Introduction

Unless specifically noted, all references to the Intel® 80C186EA apply to the Intel^®80C188EA,

Intel^®80L186EA, and Intel^®80L188EA. References to pins that differ between the Intel^®

80C186EA/80L186EA and the Intel^®80C188EA/ 80L188EA are given in parentheses. The “L” in

the part number denotes low voltage operation. Physically and functionally, the “C” and “L”

devices are identical.

The 80C186EA is the second product in a new generation of low-power, high-integration

microprocessors. It enhances the existing Intel^®80C186XL family by offering new features and

operating modes. The 80C186EA is object code compatible with the 80C186XL embedded

processor.

The 80L186EA is the 3V version of the 80C186EA. The 80L186EA is functionally identical to the

80C186EA embedded processor. Current 80C186EA customers can easily upgrade their designs to

use the 80L186EA and benefit from the reduced power consumption inherent in 3V operation.

The feature set of the 80C186EA/80L186EA meets the needs of low-power, space-critical

applications. Low-power applications benefit from the static design of the CPU core and the

integrated peripherals as well as low voltage operation. Minimum current consumption is achieved

by providing a Powerdown Mode that halts operation of the device, and freezes the clock circuits.

Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space-critical applications benefit from the integration of commonly used system peripherals. Two

flexible DMA channels perform CPU-independent data transfers. A flexible chip select unit

simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to

128 external interrupts and will prioritize these interrupts with those generated from the on-chip

peripherals. Three general purpose timer/counters round out the feature set of the 80C186EA.

Figure 1 shows a block diagram of the 80C186EA/ 80C188EA. The Execution Unit (EU) is an

enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address

calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply

and divide instructions, string move instructions that operate at full bus bandwidth, ten new

instructions, and static operation. The Bus Interface Unit (BIU) is the same as that found on the

original 80C186 family products. An independent internal bus is used to allow communication

between the BIU and internal peripherals.

Product Name Datasheet

7

Introduction

Figure 1.

Product Name Block Diagram

Note:

Pin names in parentheses apply to the 80C186EA / 80L188EA

8

Product Name Datasheet

Intel® 80C186EA Core Architecture

2.0

Intel^®80C186EA Core Architecture

2.1

Bus Interface Unit

The 80C186EA core incorporates a bus controller that generates local bus control signals. In

addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle

status information and data (for write operations) information. It is also responsible for reading

data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend

a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates a control signal (DEN) when interfacing to external

transceiver chips. This capability allows the addition of transceivers for simple buffering of the

multiplexed address/data bus.

2.2

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation.

The clock generator features a crystal oscillator, a divideby- two counter, and two low-power

operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-

overtone mode crystal network. Alternatively, the oscillator circuit may be driven from an external

clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency

due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and

the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to

drive other system components. All AC timings are referenced to CLKOUT.

The following parameters are recommended when choosing a crystal:

Temperature Range:

Application Specific

ESR (Equivalent Series Resistance): 60 Ω max

C0 (Shunt Capacitance of Crystal):

7 pF max

C (Load Capacitance):

20 pF ± 2 pF

2 mW maximum

L

Drive Level:

Product Name Datasheet

9

Intel® 80C186EA Core Architecture

Figure 2.

Clock Configurations

Note:

The L C network is only required when using a third-overtone crystal.

1

10

Product Name Datasheet

Intel® 80C186EA Peripheral Architecture

3.0

Intel^®80C186EA Peripheral Architecture

The 80C186EA has integrated several common system peripherals with a CPU core to create a

compact, yet powerful system. The integrated peripherals are designed to be flexible and provide

logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt

requests from the timer/counters or DMA channels).

The list of integrated peripherals include:

• 4-Input Interrupt Control Unit

• 3-Channel Timer/Counter Unit

• 2-Channel DMA Unit

• 13-Output Chip-Select Unit

• Refresh Control Unit

• Power Management Logic

The registers associated with each integrated peripheral are contained within a 128 x 16 register

file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O

space on any 256 byte address boundary.

Table 1 provides a list of the registers associated with the PCB when the processor's Interrupt

Control Unit is in Master Mode. In Slave Mode, the definitions of some registers change. Table 2

provides register definitions specific to Slave Mode.

3.1

Interrupt Control Unit

The 80C186EA can receive interrupts from a number of sources, both internal and external. The

Interrupt Control Unit (ICU) serves to merge these requests on a priority basis, for individual

service by the CPU. Each interrupt source can be independently masked by the Interrupt Control

Unit or all interrupts can be globally masked by the CPU.

Internal interrupt sources include the Timers and DMA channels. External interrupt sources come

from the four input pins INT3:0. The NMI interrupt pin is not controlled by the ICU and is passed

directly to the CPU. Although the timers only have one request input to the ICU, separate vector

types are generated to service individual interrupts within the Timer Unit.

3.2

Timer/Counter Unit

The 80C186EA Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of

these are highly flexible and are connected to external pins for control or clocking. A third timer is

not connected to any external pins and can only be clocked internally. However, it can be used to

clock the other two timer channels. The TCU can be used to count external events, time external

events, generate non-repetitive waveforms, generate timed interrupts, etc.

Product Name Datasheet

11

Intel® 80C186EA Peripheral Architecture

Table 1.

Peripheral Control Block Registers

PCB

Offset

PCB

Offset

PCB

Offset

PCB

Offset

Function

00H

02H

04H

06H

08H

0AH

OCH

0EH

10H

12H

14H

16H

18H

1AH

1CH

1EH

20H

22H

24H

26H

28H

2AH

2CH

2EH

30H

32H

34H

36H

38H

3AH

3CH

3EH

Reserved

40H

42H

44H

46H

48H

4AH

4CH

4EH

50H

52H

54H

56H

58H

5AH

5CH

5EH

60H

62H

64H

66H

68H

6AH

6CH

6EH

70H

72H

74H

76H

78H

7AH

7CH

7EH

Reserved

80H

82H

84H

86H

88H

8AH

8CH

8EH

90H

92H

94H

96H

98H

9AH

9CH

9EH

A0H

A2H

A4H

A6H

A8H

AAH

ACH

AEH

B0H

B2H

B4H

B6H

B8H

BAH

BCH

BEH

Reserved

UMCS

C0H

C2H

C4H

C6H

C8H

CAH

CCH

CEH

D0H

D2H

D4H

D6H

D8H

DAH

DCH

DEH

E0H

E2H

E4H

E6H

E8H

EAH

ECH

EEH

F0H

F2H

F4H

F6H

F8H

FAH

FCH

FEH

DMA0 Src. Lo

DMA0 Src. Hi

DMA0 Dest. Lo

Reserved

DMA0 Count

DMA0 Control

Reserved

Timer 0 Count

Timer 0 Compare A

Timer 0 Compare B

Timer 0 Control

Timer 1 Count

Timer 1 Compare A

Timer 1 Compare B

Timer 1 Control

Timer 2 Count

Timer 2 Compare

Reserved

DMA1 Src. Lo

DMA1 Src. Hi

DMA1 Dest. Lo

DMA1 Dest. Hi

DMA1 Count

DMA1 Control

Reserved

Refresh Base

Refresh Time

Refresh Control

Reserved

End of Interrupt

Poll

LMCS

PACS

Poll Status

Interrupt Mask

Priority Mask

In-Service

Timer 2 Control

Reserved

MMCS

MPCS

Reserved

Interrupt Request

Interrupt Status

Timer Control

DMA0 Int. Control

INT0 Control

INT1 Control

INT2 Control

INT3 Control

Reserved

Power-Save

Power Control

Reserved

Step ID

Reserved

Relocation

12

Product Name Datasheet

Intel® 80C186EA Peripheral Architecture

Table 2.

Intel^®80C186EA Slave Mode Peripheral Control Block Registers

PCB Offset

Function

20H

22H

24H

26H

28H

2AH

2C

Interrupt Vector

Specific EOI

Reserved

Interrupt Mask

Priority Mask

In-Service

2E

Interrupt Request

Interrupt Status

TMR0 Interrupt Control

DMA0 Interrupt Control

DMA1 Interrupt Control

TMR1 Interrupt Control

TMR2 Interrupt Control

Reserved

30

32

34

36

38

3A

3C

3E

Reserved

Product Name Datasheet

13

Intel® 80C186EA Peripheral Architecture

3.3

DMA Control Unit

The 80C186EA DMA Control Unit provides two independent high-speed DMA channels. Data

transfers can occur between memory and I/O space in any combination: memory to memory,

memory to I/O, I/O to I/O or I/O to memory. Data can be transferred either in bytes or words.

Transfers may proceed to or from either even or odd addresses, but even-aligned word transfers

proceed at a faster rate. Each data transfer consumes two bus cycles (a minimum of eight clocks),

one cycle to fetch data and the other to store data. The chip-select/ready logic may be programmed

to point to the memory or I/O space subject to DMA transfers in order to provide hardware chip

select lines. DMA cycles run at higher priority than general processor execution cycles.

3.4

3.5

Chip-Select Unit

The 80C186EA Chip-Select Unit integrates logic which provides up to 13 programmable chip-

selects to access both memories and peripherals. In addition, each chip-select can be programmed

to automatically terminate a bus cycle independent of the condition of the SRDY and ARDY input

pins. The chip-select lines are available for all memory and I/O bus cycles, whether they are

generated by the CPU, the DMA unit, or the Refresh Control Unit.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to

keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks

between refresh requests.

A 9-bit address generator is maintained by the RCU with the address presented on the A9:1 address

lines during the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh

address block to be located on any 8 Kbyte boundary.

3.6

Power Management

The 80C186EA has three operational modes to control the power consumption of the device. They

are Power Save Mode, Idle Mode, and Powerdown Mode.

Power Save Mode divides the processor clock by a programmable value to take advantage of the

fact that current is linearly proportional to frequency. An unmasked interrupt, NMI, or reset will

cause the 80C186EA to exit Power Save Mode.

Idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit at a logic zero state

while all peripherals operate normally.

Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator.

All internal registers hold their values provided VCC is maintained. Current consumption is

reduced to transistor leakage only.

14

Product Name Datasheet

Intel® 80C186EA Peripheral Architecture

3.7

80C187 Interface (80C186EA Only)

The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to

include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and

TEST/ BUSY pins to the 80C187 enables Numerics Mode operation. In Numerics Mode, three of

the four Mid- Range Chip Select (MCS) pins become handshaking pins for the interface. The

exchange of data and control information proceeds through four dedicated I/O ports.

If an 80C187 is not present, the 80C186EA configures itself for regular operation at reset.

Note: The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA.

3.8

ONCE Test Mode

To facilitate testing and inspection of devices when fixed into a target system, the 80C186EA has a

test mode available which forces all output and input/ output pins to be placed in the high-

impedance state. ONCE stands for “ON Circuit Emulation.” The ONCE mode is selected by

forcing the UCS and LCS pins LOW (0) during a processor reset (these pins are weakly held to a

HIGH (1) level) while RESIN is active.

Product Name Datasheet

15

Intel® 80C186XL and Intel® 80C186EA Differences

4.0

4.1

4.2

Intel^®80C186XL and Intel^®80C186EA Differences

The 80C186EA is intended as a direct functional upgrade for 80C186XL designs. In many cases, it

will be possible to replace an existing 80C186XL with little or no hardware redesign. The

following sections describe differences in pinout, operating modes, and AC and DC specifications

to keep in mind.

Pinout Compatibility

The 80C186EA requires a PDTMR pin to time the processor's exit from Powerdown Mode. The

original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to

use for PDTMR. The arrangement of all the other leads in the 68-lead PLCC is identical between

the 80C186XL and the 80C186EA. Therefore, upgrading a PLCC 80C186XL to PLCC 80C186EA

is straightforward.

Operating Modes

The 80C186XL has two operating modes, Compatible and Enhanced. Compatible Mode is a pin-

to-pin replacement for the NMOS 80186, except for numerics coprocessing. In Enhanced Mode,

the processor has a Refresh Control Unit, the Power-Save feature and an interface to the 80C187

Numerics Coprocessor. The MCS0, MCS1, and MCS3 pins change their functions to constitute

handshaking pins for the 80C187.

The 80C186EA allows all non-80C187 users to use all the MCS pins for chip-selects. In regular

operation, all 80C186EA features (including those of the Enhanced Mode 80C186) are present

except for the interface to the 80C187. Numerics Mode disables the three chip-select pins and

reconfigures them for connection to the 80C187.

4.3

4.4

TTL vs. CMOS Inputs

The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity,

but the 80C186XL inputs are rated for TTL switching levels. In particular, the 80C186EA requires

a minimum V of 3.5V to recognize a logic one while the 80C186XL requires a minimum V of

IH

only 1.9V (assuming 5.0V operation). The solution is to drive the 80C186EA with true CMOS

devices, such as those from the HC and AC logic families, or to use pull-up resistors where the

added current draw is not a problem.

Timing Specifications

80C186EA timing relationships are expressed in a simplified format over the 80C186XL. The AC

performance of an 80C186EA at a specified frequency will be very close to that of an 80C186XL

at the same frequency. Check the timings applicable to your design prior to replacing the

80C186XL.

16

Product Name Datasheet

Intel® 80C186XL and Intel® 80C186EA Differences

4.5

Package Information

This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the

Plastic Leaded Chip Carrier (PLCC) package. For complete package specifications and

information, see the Intel^®Packaging Outlines and Dimensions Guide (Order Number: 231369).

With the extended temperature range operational characteristics are guaranteed over a temperature

range corresponding to -40 °C to +85 °C ambient. Package types are identified by a two-letter

prefix to the part number. The prefixes are listed in Table 3.

Table 3.

Prefix Identification

Prefix

Note

Package Type

Temperature Range

TN

PLCC

Extended

NOTE:

1. The 25 MHz version is only available in commercial temperature range corresponding to 0 °C to +70 °C

ambient.

4.6

Pin Descriptions

Each pin or logical set of pins is described in Table 5. There are three columns for each entry in the

Pin Description Table.

The Pin Name column contains a mnemonic that describes the pin function. Negation of the signal

name (for example, RESIN) denotes a signal that is active low.

The Pin Type column contains two kinds of information. The first symbol indicates whether a pin

is power (P), ground (G), input only (I), output only (O) or input/output (I/O). Some pins have

multiplexed functions (for example, A19/S6). Additional symbols indicate additional

characteristics for each pin. Table 5 lists all the possible symbols for this column.

The Input Type column indicates the type of input (asynchronous or synchronous).

Asynchronous pins require that setup and hold times be met only in order to guarantee recognition

at a particular clock edge. Synchronous pins require that setup and hold times be met to guarantee

proper operation. For example, missing the setup or hold time for the SRDY pin (a synchronous

input) will result in a system failure or lockup. Input pins may also be edge- or level-sensitive. The

possible characteristics for input pins are S(E), S(L), A(E) and A(L).

The Output States column indicates the output state as a function of the device operating mode.

Output states are dependent upon the current activity of the processor. There are four operational

states that are different from regular operation: bus hold, reset, Idle Mode and Powerdown Mode.

Appropriate characteristics for these states are also indicated in this column, with the legend for all

possible characteristics in Table 4.

The Pin Description column contains a text description of each pin.

As an example, consider AD15:0. I/O signifies the pins are bidirectional. S(L) signifies that the

input function is synchronous and level-sensitive. H(Z) signifies that, as outputs, the pins are high-

impedance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X)

signifies that the pins retain their states during Powerdown Mode.

Product Name Datasheet

17

Intel® 80C186XL and Intel® 80C186EA Differences

Table 4.

Pin Description Nomenclature

Symbol

Description

P

G

I

Power Pin (Apply +V_CCVoltage)

Ground (Connect to V_SS

Input Only Pin

)

O

Output Only Pin

I/O

Input/Output Pin

S(E)

S(L)

A(E)

A(L)

Synchronous, Edge Sensitive

Synchronous, Level Sensitive

Asynchronous, Edge Sensitive

Asynchronous, Level Sensitive

H(1)

H(0)

H(Z)

H(Q)

H(X)

Output Driven to V_CCduring Bus Hold

Output Driven to V_SSduring Bus Hold

Output Floats during Bus Hold

Output Remains Active during Bus Hold

Output Retains Current State during Bus Hold

R(WH)

R(1)

R(0)

Output Weakly Held at V_CCduring Reset

Output Driven to V_CCduring Reset

Output Driven to V_SSduring Reset

Output Floats during Reset

R(Z)

R(Q)

R(X)

Output Remains Active during Reset

Output Retains Current State during Reset

I(1)

I(0)

I(Z)

I(Q)

I(X)

Output Driven to V_CCduring Idle Mode

Output Driven to V_SSduring Idle Mode

Output Floats during Idle Mode

Output Remains Active during Idle Mode

Output Retains Current State during Idle Mode

P(1)

P(0)

P(Z)

P(Q)

P(X)

Output Driven to V_CCduring Powerdown Mode

Output Driven to V_SSduring Powerdown Mode

Output Floats during Powerdown Mode

Output Remains Active during Powerdown Mode

Output Retains Current State during Powerdown Mode

18

Product Name Datasheet

Intel® 80C186XL and Intel® 80C186EA Differences

Table 5.

Pin Descriptions (Sheet 1 of 3)

Type

Input Output

Pin Name

V_CC

Description

Type

States

P

G

I

POWER connections consist of six pins which must be shorted

externally to a V_CCboard plane.

V_SS

GROUND connections consist of five pins which must be shorted

externally to a V_SSboard plane.

CLKIN

A(E)

CLocK INput is an input for an external clock. An external oscillator

operating at two times the required processor operating frequency can

be connected to CLKIN. For crystal operation, CLKIN (along with

OSCOUT) are the crystal connections to an internal Pierce oscillator.

OSCOUT

O

H(Q)

R(Q)

P(Q)

OSCillator OUTput is only used when using a crystal to generate the

external clock. OSCOUT (along with CLKIN) are the crystal R(Q)

connections to an internal Pierce oscillator. This pin is not to be P(Q)

used as 2X clock output for non-crystal applications (i.e., this pin is N.C.

for non-crystal applications). OSCOUT does not float in ONCE mode.

CLKOUT

RESIN

O

I

H(Q)

R(Q)

P(Q)

CLocK OUTput provides a timing reference for inputs and outputs of the

processor, and is one-half the input clock (CLKIN) frequency. CLKOUT

has a 50% duty cycle and transitions every falling edge of CLKIN.

A(L)

RESet IN causes the processor to immediately terminate any bus cycle

in progress and assume an initialized state. All pins will be driven to a

known state, and RESOUT will also be driven active. The rising edge

(low-to-high) transition synchronizes CLKOUT with CLKIN before the

processor begins fetching opcodes at memory location 0FFFF0H.

RESOUT

PDTMR

O

H(0)

R(I)

P(O)

RESet OUTput that indicates the processor is currently in the reset

state. RESOUT will remain active as long as RESIN remains active.

When tied to the TEST/BUSY pin, RESOUT forces the 80C186EA into

Numerics Mode.

I/O

A(L)

H(WH) Power-Down TiMeR pin (normally connected to an external capacitor)

R(Z)

P(1)

that determines the amount of time the processor waits after an exit from

power down before resuming normal operation. P(1) The duration of time

required will depend on the startup characteristics of the crystal

oscillator.

NMI

I

A(E)

Non-Maskable Interrupt input causes a Type 2 interrupt to be serviced

by the CPU. NMI is latched internally.

TEST/BUSY

(TEST)

TEST/BUSY is sampled upon reset to determine whether the 80C186EA

is to enter Numerics Mode. In regular operation, the pin is TEST. TEST is

used during the execution of the WAIT instruction to suspend CPU

operation until the pin is sampled active (low). In Numerics Mode, the pin

is BUSY. BUSY notifies the 80C186EA of 80C187 Numerics

Coprocessor activity.

AD15:0

(AD7:0)

I/O

O

S(L)

H(Z)

R(Z)

P(X)

These pins provide a multiplexed Address and Data bus. During the

address phase of the bus cycle, address bits 0 through 15 (0 through 7

on the 8-bit bus versions) are presented on the bus and can be latched

using ALE. 8- or 16-bit data information is transferred during the data

phase of the bus cycle.

A18:16

A19/S6–A16

(A19–A8)

H(Z)

R(Z)

P(X)

These pins provide multiplexed Address during the address phase of

the bus cycle. Address bits 16 through 19 are presented on these pins

and can be latched using ALE. A18:16 are driven to a logic 0 during the

data phase of the bus cycle. On the 8-bit bus versions, A15–A8 provide

valid address information for the entire bus cycle. Also during the data

phase, S6 is driven to a logic 0 to indicate a CPU-initiated bus cycle or

logic 1 to indicate a DMA-initiated bus cycle or a refresh cycle.

Product Name Datasheet

19

Intel® 80C186XL and Intel® 80C186EA Differences

Table 5.

Pin Descriptions (Sheet 2 of 3)

Type

Input Output

Pin Name

S2:0

Description

Type

States

O

H(Z)

R(Z)

P(1)

Bus cycle Status are encoded on these pins to provide bus transaction

information. S2:0 are encoded as follows:

S2

S1

S0

Bus Cycle Initiated

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt Acknowledge

Read I/O

Write I/O

Processor HALT

Queue Instruction Fetch

Read Memory

Write Memory

Passive (no bus activity)

ALE/QS0

O

H(0)

R(0)

P(0)

Address Latch Enable output is used to strobe address information into

a transparent type latch during the address phase of the bus cycle. In

Queue Status Mode, QS0 provides queue status information along with

QS1.

BHE

(RFSH)

H(Z)

R(Z)

P(X)

Byte High Enable output to indicate that the bus cycle in progress is

transferring data over the upper half of the data bus. BHE and A0 have

the following logical encoding:

A0

BHE Encoding (For 80C186EA/80L186EA Only)

0

1

0

1

0

1

Word Transfer

Even Byte Transfer

Odd Byte Transfer

Refresh Operation

On the 80C188EA/80L188EA, RFSH is asserted low to indicate a

Refresh bus cycle.

RD/QSMD

O

H(Z)

ReaD output signals that the accessed memory or I/O device must drive

R(WH) data information onto the data bus. Upon reset, this pin has an alternate

P(1)

function. As QSMD, it enables Queue Status Mode when grounded. In

Queue Status Mode, the ALE/QS0 and WR/QS1 pins provide the

following information about processor/instruction queue interaction:

QS1

QS0 Queue Operation

0

1

0

1

0

No Queue Operation

First Opcode Byte Fetched from the Queue

Subsequent Byte Fetched from the Queue

Empty the Queue

WR/QS1

ARDY

O

I

H(Z)

R(Z)

P(1)

WRite output signals that data available on the data bus are to be written

into the accessed memory or I/O device. In Queue Status Mode, QS1

provides queue status information along with QS0.

A(L)

S(L)

Asynchronous ReaDY is an input to signal for the end of a bus cycle.

ARDY is asynchronous on rising CLKOUT and synchronous on falling

CLKOUT. ARDY or SRDY must be active to terminate any processor bus

cycle, unless they are ignored due to correct programming of the Chip

Select Unit.

SRDY

I

S(L)

Synchronous ReaDY is an input to signal for the end of a bus cycle.

ARDY or SRDY must be active to terminate any processor bus cycle,

unless they are ignored due to correct programming of the Chip Select

Unit.

DEN

O

H(Z)

R(Z)

P(1)

Data ENable output to control the enable of bidirectional transceivers

when buffering a system. DEN is active only when data is to be

transferred on the bus.

LOCK

H(Z)

LOCK output indicates that the bus cycle in progress is not to be

R(WH) interrupted. The processor will not service other bus requests (such as

P(1)

HOLD) while LOCK is active. This pin is configured as a weakly held

high input while RESIN is active and must not be driven low.

20

Product Name Datasheet

Intel® 80C186XL and Intel® 80C186EA Differences

Table 5.

Pin Descriptions (Sheet 3 of 3)

Type

Input Output

Pin Name

HOLD

Description

Type

States

I

A(L)

HOLD request input to signal that an external bus master wishes to gain

control of the local bus. The processor will relinquish control of the local

bus between instruction boundaries not conditioned by a LOCK prefix.

HLDA

UCS

O

H(1)

R(0)

P(0)

HoLD Acknowledge output to indicate that the processor has

relinquished control of the local bus. When HLDA is asserted, the

processor will (or has) floated its data bus and control signals allowing

another bus master to drive the signals directly.

O

H(1)

R(1)

P(1)

Upper Chip Select will go active whenever the address of a memory or

I/O bus cycle is within the address limitations programmed by the user.

After reset, UCS is configured to be active for memory accesses

between 0FFC00H and 0FFFFFH. During a processor reset, UCS and

LCS are used to enable ONCE Mode.

LCS

O

H(1)

R(1)

P(1)

Lower Chip Select will go active whenever the address of a memory

bus cycle is within the address limitations programmed by the user. R(1)

LCS is inactive after a reset. During a processor reset, UCS and LCS are

used to enable ONCE Mode.

MCS0/PEREQ

MCS1/ERROR

MCS2

I/O

A(L)

H(1)

R(1)

P(1)

These pins provide a multiplexed function. If enabled, these pins

normally comprise a block of Mid-Range Chip Select outputs which will

go active whenever the address of a memory bus cycle is within the

address limitations programmed by the user. In Numerics Mode

(80C186EA only), three of the pins become handshaking pins for the

80C187. The CoProcessor REQuest input signals that a data transfer is

pending. ERROR is an input which indicates that the previous numerics

coprocessor operation resulted in an exception condition. An interrupt

Type 16 is generated when ERROR is sampled active at the beginning of

a numerics operation. Numerics Coprocessor Select is an output

signal generated when the processor accesses the 80C187.

MCS3/NCS

PCS4:0

O

H(1)

R(1)

P(1)

Peripheral Chip Selects go active whenever the address of a memory

or I/O bus cycle is within the address limitations programmed by the

user.

PCS5/A1

PCS6/A2

H(1)/

H(X)

R(1)

P(1)

These pins provide a multiplexed function. As additional Peripheral

Chip Selects, they go active whenever the address of a memory or

I/O bus cycle is within the address limitations by the user. They may also

be programmed to provide latched Address A2:1 signals.

T0OUT

T1OUT

O

H(Q)

R(1)

P(Q)

Timer OUTput pins can be programmed to provide a single clock or

continuous waveform generation, depending on the timer mode

selected.

T0IN

I

A(L)

A(E)

Timer INput is used either as clock or control signals, depending on the

timer mode selected. T1IN A(E)

DRQ0

DRQ1

I

A(L)

DMA ReQuest is asserted by an external request when it is prepared for

a DMA transfer.

INT0

INT1/SELECT

A(E,L)

Maskable INTerrupt input will cause a vector to a specific Type interrupt

routine. To allow interrupt expansion, INT0 and/or INT1 can be used with

INTA0 and INTA1 to interface with an external slave controller. INT1

becomes SELECT when the ICU is configured for Slave Mode.

INT2/INTA0

INT3/INTA1/IRQ

I/O

A(E,L)

H(1)

R(Z)

P(1)

These pins provide multiplexed functions. As inputs, they provide a

maskable INTerrupt that will cause the CPU to vector to a specific Type

interrupt routine. As outputs, each is programmatically controlled to

provide an INTerrupt Acknowledge handshake signal to allow interrupt

expansion. INT3/INTA1 becomes IRQ when the ICU is configured for

Slave Mode.

N.C.

No Connect. For compatibility with future products, do not connect to

these pins.

NOTE: Pin names in parentheses apply to the 80C188EA and 80L188EA.

Product Name Datasheet

21

Intel® 80C186EA Pinout

5.0

Intel^®80C186EA Pinout

Table 6 and Table 7 list the 80C186EA pin names with package location for the 68-pin Plastic

Leaded Chip Carrier (PLCC) component. Figure 3 depicts the complete 80C186EA/80L186EA

pinout (PLCC package) as viewed from the top side of the component (i.e., contacts facing down).

Table 6.

PLCC Pin Names with Package Location

Address/Data Bus

Name Location

AD0

AD1

AD2

Bus Control

Processor Control

Name Location

RESIN

RESOUT

CLKIN

OSCOUT

CLKOUT

TEST/BUSY

PDTMR

NMI

INT0

I/O

Name

Location

Name

Location

17

15

13

11

8

ALE/QS0

BHE (RFSH)

S0

61

64

52

53

54

62

63

55

49

39

48

50

51

24

57

59

58

56

47

40

46

45

44

42

41

UCS

LCS

34

33

38

37

36

35

25

27

28

29

30

31

32

22

20

23

21

18

19

MCS0/PEREQ

MCS1/ERROR

MCS2

AD3

AD4

S1

S2

AD5

6

RD/QSMD

WR/QS1

ARDY

SRDY

DEN

MCS3/NCS

PCS0

PCS1

PCS2

PCS3

PCS4

PCS5/A1

PCS6/A2

T0OUT

T0IN

AD6

4

AD7

2

AD8 (A8)

AD9 (A9)

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13 (A13)

AD14 (A14)

AD15 (A15)

A16

16

14

12

10

7

5

3

INT1/SELECT

INT2/INTA0

INT3/INTA1/

IRQ

LOCK

HOLD

HLDA

Power

1

T1OUT

T1IN

DRQ0

DRQ1

68

67

66

65

Name

Location

A17

A18

A19/S6

V_SS

V_CC

26, 60

9, 43

NOTE: Pin names in parentheses apply to the 80C188EA/80L188EA.

Table 7.

PLCC Package Location with Pin Names

Location

Name

Location

Name

Location

Name

Location

Name

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

AD15 (A15)

AD7

AD14 (A14)

AD6

AD13 (A13)

AD5

AD12 (A12)

AD4

V_CC

AD11 (A11)

AD3

AD10 (A10)

AD2

AD9 (A9)

AD1

AD8 (A8)

AD0

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

DRQ0

DRQ1

T0IN

35

36

37

38

39

40

41

MCS3/NCS

MCS2

MCS1/ERROR

MCS0/PEREQ

DEN

PDTMR

INT3/INTA1/

IRQ

INT2/INTA0

VCC

INT1/SELECT

INT0

NMI

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

S0

S1

S2

T1IN

ARDY

T0OUT

T1OUT

RESIN

PCS0

V_SS

PCS1

PCS2

PCS3

PCS4

PCS5/A1

PCS6/A2

LCS

CLKOUT

RESOUT

OSCOUT

CLKIN

42

43

44

45

46

47

48

49

50

51

V_SS

ALE/QS0

RD/QSMD

WR/QS1

BHE RFSH

A19/S6

A18

TEST/BUSY

LOCK

SRDY

HOLD

HLDA

A17

A16

UCS

NOTE: Pin names in parentheses apply to the 80C188EA/80L188EA.

22

Product Name Datasheet

Intel® 80C186EA Pinout

Figure 3.

68-Lead PLCC Pinout Diagram

Notes:

1. The nine character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.

2. Pin names in parentheses apply to the 80C186EA/80L188EA.

Product Name Datasheet

23

Package Thermal Specifications

6.0

Package Thermal Specifications

The 80C186EA/80L186EA is specified for operation when T (the case temperature) is within the

C

range of 0°C to 85°C (PLCC package). T may be measured in any environment to determine

C

whether the processor is within the specified operating range. The case temperature must be

measured at the center of the top surface.

T (the ambient temperature) can be calculated from θ (thermal resistance from the case to

A

CA

ambient) with the following equation:

T = T - P × θ

CA

A

C

Typical values for θ at various airflows are given in Table 8.

CA

P (the maximum power consumption, specified in watts) is calculated by using the maximum ICC

as tabulated in the DC specifications and V of 5.5 V.

CC

Table 8.

Thermal Resistance (θ ) at Various Airflows (in °C/Watt)

CA

Airflow Linear ft./min. (m/sec)

0

200

400

600

800

1000

(0)

(1.01)

(2.03)

(3.04)

(4.06)

(5.07)

θ_CA(PLCC)

29

25

21

19

17

16.5

24

Product Name Datasheet

Electrical Specification

7.0

Electrical Specification

7.1

Absolute Maximum Ratings*

Storage Temperature:

-65 °C to + 150 °C

-0.5 V to + 6.5 V

Case Temperature under Bias:

Supply Voltage with Respect to V

:

SS

Voltage on Other Pins with Respect to V

:

-0.5 V to V + 0.5 V

CC

SS

Note: This data sheet contains preliminary information on new products in production. It is valid for the

devices indicated in the revision history. The specifications are subject to change without notice.

*Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

7.2

Recommended Connections

Power and ground connections must be made to multiple V and V pins. Every 80C186EA

CC

SS

based circuit board should contain separate power (V ) and ground (V ) planes. All V and

CC

SS

CC

V

pins must be connected to the appropriate plane. Pins identified as “N.C.” must not be

SS

connected in the system. Decoupling capacitors should be placed near the processor. The value and

type of decoupling capacitors is application and board layout dependent. The processor can cause

transient power surges when its output buffers transition, particularly when connected to large

capacitive loads.

Always connect any unused input pins to an appropriate signal level. In particular, unused interrupt

pins (NMI, INT3:0) should be connected to V to avoid unwanted interrupts. Leave any unused

SS

output pin or any “N.C.” pin unconnected.

Product Name Datasheet

25

DC Specifications

8.0

DC Specifications

Table 9.

DC SPECIFICATIONS (80C186EA/80C188EA)

Symbol

Parameter

Supply Voltage

Min

Max

Units

V

Conditions

V

4ꢀ5

5ꢀ5

CC

IL

b

Input Low Voltage for All Pins

Input High Voltage for All Pins

Output Low Voltage

0ꢀ5

0ꢀ7 V

0ꢀ3 V

V

CC

a

V

CC

0ꢀ5

V

IH

CC

e

3 m A (m in)

0ꢀ45

V

I

OL

OH

HYR

OL

b

e b

2 m A (m in)

Output High Voltage

V

0ꢀ5

V

CC

OH

Input Hysterisis on RESIN

0ꢀ30

V

s

g

I

Input Leakage Current (except

RD-QSMDꢁ UCSꢁ LCSꢁ MCS0-PEREQꢁ

MCS1-ERRORꢁ LOCK and TEST-BUSY)

10

mA

0V

V

CC

IL1

IN

b

e

V 0ꢀ7 V

IN

(Note 1)

I

Input Leakage Current

(RD-QSMDꢁ UCSꢁ LCSꢁ MCS0-PEREQꢁ

MCS1ꢁ ERRORꢁ LOCK and TEST-BUSY

275

mA

IL2

CC

s

V

I

Output Leakage Current

0ꢀ45

(Note 2)

V

OL

CC

OUT

CC

10

Supply Current Cold (RESET)

80C186EA25-80C188EA25

80C186EA20-80C188EA20

80C186EA13-80C188EA13

105

90

mA (Notes 3ꢁ 5)

mA

65

I

Supply Current In Idle Mode

80C186EA25-80C188EA25

80C186EA20-80C188EA20

80C186EA13-80C188EA13

ID

90

70

46

mA (Note 5)

mA

Supply Current In Powerdown Mode

80C186EA25-80C188EA25

80C186EA20-80C188EA20

80C186EA13-80C188EA13

PD

100

mA

(Note 5)

e

C

Output Pin Capacitance

Input Pin Capacitance

0

15

pF

T

1 MHz (Note 4)

1 MHz

OUT

F

IN

NOTES:

1.RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK and TEST/BUSY have internal pull-ups that

are only activated during RESET. Loading these pins above I_OL= -275 µA will cause the processor to

enter alternate modes of operation.

2.Output pins are floated using HOLD or ONCE Mode.

3.Measured at worst case temperature and V_CCwith all outputs loaded as specified in the AC Test

Conditions, and with the device in RESET (RESIN held low). RESET is worst case for I_CC

4.Output capacitance is the capacitive load of a floating output pin.

.

5.Operating conditions for 25 MHz are 0°C to +70°C, V_CC= 5.0V ±10%.

26

Product Name Datasheet

DC Specifications

Table 10.

DC SPECIFICATIONS (80L186EA/80L188EA)

NOTES:

1.RD/QSMD, UCS, LCS, MCS0, MCS1, LOCK and TEST have internal pull-ups that are only activated during

RESET. Loading these pins above I_OL= -275 µA will cause the processor to enter alternate modes of

operation.

2.Output pins are floated using HOLD or ONCE Mode.

3.Measured at worst case temperature and V_CCwith all outputs loaded as specified in the AC Test

Conditions, and with the device in RESET (RESIN held low).

4.Output capacitance is the capacitive load of a floating output pin.

Product Name Datasheet

27

DC Specifications

8.1

I_CCVersus Frequency and Voltage

The current (I ) consumption of the processor is essentially composed of two components; IPD

CC

and ICCS.

I

is the quiescent current that represents internal device leakage, and is measured with all inputs

PD

or floating outputs at GND or V (no clock applied to the device). I is equal to the Powerdown

CC

PD

current and is typically less than 50 µA.

I

is the switching current used to charge and discharge parasitic device capacitance when

CCS

changing logic levels. Since I

is typically much greater than I , I can often be ignored when

CCS

PD PD

calculating I

.

CC

I

is related to the voltage and frequency at which the device is operating. It is given by the

CCS

formula:

Power = V × I = V²× C

× f

DEV

I = I = I

= V × C

× f

DEV

CC

CCS

Where: V = Device operating voltage (V

)

CC

C

= Device capacitance

DEV

f = Device operating frequency

I

= I = Device current

CC

CCS

Measuring C

on a device like the 80C186EA would be difficult. Instead, C

is calculated

DEV

using the above formula by measuring I at a known V and frequency (see Table 11). Using

CC

this C

value, I can be calculated at any voltage and frequency within the specified operating

DEV

CC

range.

EXAMPLE: Calculate the typical I when operating at 20 MHz, 4.8V.

CC

I

= I

= 4.8 × 0.515 × 20 ≈ 49 mA

CCS

CC

Table 11.

C

Values

DEV

Parameter

Type

Max

Units

Notes

C

_DEV(Device in Reset)

0.515

0.391

0.905

0.635

mA/V*MHz

1,2

C_DEV(Device in Idle)

1. Max C_DEVis calculated at -40 °C, all floating outputs driven to V_CCor GND, and all outputs loaded to 50 pF

(including CLKOUT and OSCOUT).

2. Typical C_DEVis calculated at 25°C with all outputs loaded to 50 pF except CLKOUT and OSCOUT, which

are not loaded.

28

Product Name Datasheet

DC Specifications

8.2

PDTMR Pin Delay Calculation

The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal

clocks when exiting Powerdown. A delay is required only when using the on-chip oscillator to

allow the crystal or resonator circuit time to stabilize.

Note: The PDTMR pin function does not apply when RESIN is asserted (i.e., a device reset during

Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has

stabilized).

To calculate the value of capacitor required to provide a desired delay, use the equation:

440 × t = C (5V, 25 °C)

PD

Where: t = desired delay in seconds

C

= capacitive load on PDTMR in microfarads

PD

Example 1. To get a delay of 300 µs, a capacitor value of C = 440 × (300 × 10^-6) = 0.132 µF is

PD

required. Round up to standard (available) capacitive values.

Note: The above equation applies to delay times greater than 10 µs and will compute the TYPICAL

capacitance needed to achieve the desired delay. A delay variance of +50% or -25% can occur due

to temperature, voltage, and device process extremes. In general, higher V and/or lower

CC

temperature will decrease delay time, while lower V and/or higher temperature will increase

CC

delay time.

Product Name Datasheet

29

AC Specifications

9.0

AC Specifications

Table 12.

AC Characteristics—80C186EA25/80C186EA20/80C186EA13 (Sheet 1 of 2)

Symbol

Parameter

MinMax

MinMaxitsUnNotes

(12)

INPUT CLOCK

25 MHz

20 MHz

13 MHz

T

CLKIN Frequency

CLKIN Period

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

0

20

10

1

50

%

8

0

25

10

1

40

%

8

0

38ꢀ5

12

1

26 MHz

%

1

1ꢁ 2

1ꢁ 3

F

ns

C

%

CH

CL

CR

CF

%

ns

8

ns

1

OUTPUT CLOCK

T

CLKIN to CLKOUT Delay

CLKOUT Period

CLKOUT High Time

CLKOUT Low Time

CLKOUT Rise Time

CLKOUT Fall Time

0

15

2T

0

17

2ꢀT

0

23

2ꢀT

C

ns

1ꢁ 4

1

1ꢁ 5

CD

C

b

(T-2)

5

(T-2)

5

(T-2)

5

PH

PL

PR

PF

1

6

1

6

1

6

OUTPUT DELAYS

T

ALEꢁ S2@0ꢁ DEN

BHEꢁ (RFSH)ꢁ LOCKꢁ A19@16

ꢁ

3

20

25

20

3

22

27

22

3

25

30

25

ns 1ꢁ 4ꢁ 6ꢁ 7

ns 1ꢁ 4ꢁ 6ꢁ 8

CHOV1

CHOV2

CLOV1

MCS3@0ꢁ LCSꢁ UCSꢁ PCS6@0ꢁ

NCSꢁ RDꢁ WR

BHE (RFSH)ꢁ DENꢁ LOCKꢁ

RESOUTꢁ HLDAꢁ

T0OUTꢁ T1OUTꢁ A19@16

ns

1ꢁ 4ꢁ 6

T

RDꢁ WRꢁ MCS3@0ꢁ LCSꢁ

UCSꢁ PCS6@0ꢁ AD15@0

(A15@8ꢁ AD7@0)ꢁ

3

25

3

27

3

30

CLOV2

NCSꢁ INTA1@0ꢁ S2@0

T

RDꢁ WRꢁ BHE (RFSH)ꢁ

LOCKꢁ S2@0ꢁ A19@16

ꢁ

0

25

0

25

0

25

ns

1

CHOF

CLOF

DENꢁ AD15@0 (A15@8ꢁ AD7@0)

30

Product Name Datasheet

AC Specifications

Table 12.

AC Characteristics—80C186EA25/80C186EA20/80C186EA13 (Sheet 2 of 2)

Symbol

Parameter

MinMax

25 MHz

8

MinMax

MinMax itUsn Notes

20 MHz 13 MHz

10

(12)

SYNCHRONOUS INPUTS

T

TESTꢁ NMIꢁ INT3@0ꢁ

T1@0INꢁ ARDY

10

3

ns

1ꢁ 9

CHIS

CHIH

CLIS

CLIH

CLIS

CLIH

TESTꢁ NMIꢁ INT3@0ꢁ

T1@0INꢁ ARDY

3

10

3

10

3

AD15@0 (AD7@0)ꢁ ARDYꢁ

SRDYꢁ DRQ1@0

10

3

1ꢁ 10

1ꢁ 9

AD15@0 (AD7@0)ꢁ ARDYꢁ

SRDYꢁ DRQ1@0

HOLDꢁ PEREQꢁ ERROR

(80C186EA Only)

10

3

10

3

10

3

HOLDꢁ PEREQꢁ ERROR

(80C186EA Only)

1ꢁ 9

T

RESIN (to CLKIN)

10

3

10

3

10

3

ns

1ꢁ 9

CLIS

CLIH

RESIN (fromCLKIN)

NOTES:

1.See AC Timing Waveforms, for waveforms and definition.

2.Measured at V_IHfor high time, V_ILfor low time.

3.Only required to guarantee I_CC. Maximum limits are bounded by T_C, T_CHand T_CL

4.Specified for a 50 pF load, see Figure 9 for capacitive derating information.

5.Specified for a 50 pF load, see Figure 10 for rise and fall times outside 50 pF.

6.See Figure 10 for rise and fall times.

.

7.T_CHOV1applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8.T_CHOV2applies to RD and WR only after a HOLD release.

9.Setup and Hold are required to guarantee recognition.

10.Setup and Hold are required for proper operation.

11.T_CHOVSapplies to BHE (RFSH) and A19:16 only after a HOLD release.

12.Operating conditions for 25 MHz are 0°C to +70°C, V_CC= 5.0V ±10%.

13.Pin names in parentheses apply to the 80C188EA/80L188EA.

Product Name Datasheet

31

AC Specifications

Table 13.

AC Characteristics—80L186EA13/80C186EA8

Symbol

Parameter

Min.

Max.

Units

Notes

INPUT CLOCK

T_F

CLKIN Frequency

0

38.5

12

1

26

∞

8

MHz

ns

1

T_C

CLKIN Period

1

T_CH

T_CL

T_CR

T_CF

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

ns

1,2

1,3

ns

1

8

ns

OUTPUT CLOCK

T_CD

T

CLKIN to CLKOUT Delay

0

45

ns

1,4

1

CLKOUT Period

2*T_C

T_PH

T_PL

T_PR

T_PF

CLKOUT High Time

CLKOUT Low Time

CLKOUT Rise Time

CLKOUT Fall Time

(T/2) – 5

1

(T/2) – 5

1

12

1,5

OUTPUT DELAYS

T_CHOV1

T_CHOV2

T_CHOV3

T_CLOV1

T_CLOV2

T_CLOV3

T_CLOV4

T_CLOV5

T_CHOF

ALE, LOCK

3

0

27

32

30

27

32

30

3

ns

1,4,6,7

1,4,6,8

1

MCS3:0, LCS, UCS, PCS6:0, RD, WR

S2:0, (DEN), BHE, (RFSH), A19:16

LOCK, RESOUT, HLDA, T0OUT, T1OUT

RD, WR, MCS3:0, LCS, UCS, PCS6:0, INTA1:0

BHE, (RFSH), DEN, A19:16

1, 4, 6

1

AD15:0, (A15:8, AD7:0)

S2:0

38

27

RD, WR, BHE, (RFSH), LOCK, S2:0, A19:16

DEN, AD15:0, (A15:8, AD7:0)

T_CLOF

1

SYNCHRONOUS INPUTS

T_CHIS

T_CHIH

T_CLIS

T_CLIH

T_CLIS

T_CLIH

T_CLIS

T_CLIH

NOTES:

TEST, NMI, INT3:0, T1:0IN, ARDY

22

3

ns

1, 9

TEST, NMI, INT3:0, T1:0IN, ARDY

AD15:0, (AD7:0), ARDY, SRDY, DRQ1:0

HOLD

22

3

1, 10

1, 9

22

3

HOLD

1, 9

RESIN (to CLKIN)

22

3

1, 9

RESIN (from CLKIN)

1, 9

1. See AC Timing Waveforms, for waveforms and definition.

2. Measured at V_IHfor high time, V_ILfor low time.

3. Only required to guarantee I_CC. Maximum limits are bounded by T_C, T_CHand T_CL

.

4. Specified for a 50 pF load, see Figure 9 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 10 for rise and fall times outside 50 pF.

6. See Figure 10 for rise and fall times.

7. T_CHOV1applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8. T_CHOV2applies to RD and WR only after a HOLD release.

9. Setup and Hold are required to guarantee recognition.

10.Setup and Hold are required for proper operation.

11. T_CHOVSapplies to BHE (RFSH) and A19:16 only after a HOLD release.

12.Pin names in parentheses apply to the 80C188EA/80L188EA.

32

Product Name Datasheet

AC Specifications

Table 14.

Relative Timings (80C186EA25/20/13, 80L186EA13)

Symbol

Parameter

MinMaxit

UNnotes

RELATIVE TIMINGS

b

T

ALE Rising to ALE Falling

Address Valid to ALE Falling

Chip Selects Valid to ALE Falling

Address Hold fromALE Falling

ALE Falling to WR Falling

ALE Falling to RD Falling

RD Rising to ALE Rising

T

15

ns

LHLL

b

ꢀꢁꢂT

10

15

10

AVLL

b

0

1

PLLL

LLAX

1

LLWL

LLRL

RHLH

WHLH

AFRL

RLRH

WLWH

RHAV

WHDX

WHDEX

WHPH

RHPH

PHPL

WR Rising to ALE Rising

Address Float to RD Falling

RD Falling to RD Rising

b

(2ꢀT)

5

2

b

WR Falling to WR Rising

b

RD Rising to Address Active

Output Data Hold after WR Rising

WR Rising to DEN Rising

WR Rising to Chip Select Rising

RD Rising to Chip Select Rising

CS Inactive to CS Active

T

15

b

ꢀꢁꢂT

10

1

1ꢁ 4

1

Rising

T

3

) Active to RESIN

) to RESIN Rising

T

ONCE (UCSꢁ LCS

OVRH

RHOX

3

NOTES:

1. Assumes equal loading on both pins.

2. Can be extended using wait states.

3. Not tested.

4. Not applicable to latched A2:1. These signals change only on falling T₁.

5. For write cycle followed by read cycle.

6. Operating conditions for 25 MHz are 0°C to +70°C, V_CC= 5.0V ±10%.

Product Name Datasheet

33

AC Test Conditions

10.0

AC Test Conditions

The AC specifications are tested with the 50 pF load shown in Figure 4. See the Derating Curves

section to see how timings vary with load capacitance.

Specifications are measured at the V /2 crossing point, unless otherwise specified. See AC

CC

Timing Waveforms, for AC specification definitions, test pins, and illustrations.

Figure 4.

AC Test Load

Note: C = 50 pF for all signals.

L

34

Product Name Datasheet

AC Timing Waveforms

11.0

AC Timing Waveforms

Figure 5.

Input and Output Clock Waveform

Figure 6.

Output Delay and Float Waveform

k

Float 80% V

CC

Note: 20% V

CC

Product Name Datasheet

35

AC Timing Waveforms

Figure 7.

Input Setup and Hold

Note: RESIN measured to CLKIN, not CLKOUT

36

Product Name Datasheet

AC Timing Waveforms

Figure 8.

Relative Signal Waveform

CLKOUT

T

LHLL

V

CC

50%

ALE

OV

T

AVLL

T

LLAX

50%

WHLH

V

CC

T

RHLH

ADD:15 [AD0:7]

A19:16 [A19:8]

50%

OV

T

AFRL

WHDX

T

LLWL LLRL

T

RHAV

V

CC

T

RLRH

WLWH

T

RD# or WR#

50%

OV

T

PHPL

PLLL

T

RHPH WHPH

V

CC

MCS3:0#, LCS#,

UCS#, PCS6:0#

50%

OV

T

WHDEX

50%

V

CC

DEN#

50%

OV

RESIN#

50%

OV

T

RHOX

OVRH

UCS#, LCS#

50%

Notes: Pin names in parentheses apply to the 80C188EA

Product Name Datasheet

37

Derating Curves

12.0

Derating Curves

Figure 9.

Typical Output Delay Variations Versus Load Capacitance

Figure 10.

Typical Rise and Fall Variations Versus Load Capacitance

38

Product Name Datasheet

Reset

13.0

Reset

The processor performs a reset operation any time the RESIN pin is active. The RESIN pin is

actually synchronized before it is presented internally, which means that the clock must be

operating before a reset can take effect. From a power-on state, RESIN must be held active (low) in

order to guarantee correct initialization of the processor. Failure to provide RESIN while the

device is powering up will result in unspecified operation of the device.

Figure 11 shows the correct reset sequence when first applying power to the processor. An external

clock connected to CLKIN must not exceed the V threshold being applied to the processor. This

CC

is normally not a problem if the clock driver is supplied with the same V that supplies the

CC

processor. When attaching a crystal to the device, RESIN must remain active until both V and

CC

CLKOUT are stable (the length of time is application specific and depends on the startup

characteristics of the crystal circuit). The RESIN pin is designed to operate correctly using an RC

reset circuit, but the designer must ensure that the ramp time for V is not so long that RESIN is

CC

never really sampled at a logic low level when V reaches minimum operating conditions.

CC

Figure 12 shows the timing sequence when RESIN is applied after V is stable and the device has

CC

been operating. Note that a reset will terminate all activity and return the processor to a known

operating state. Any bus operation that is in progress at the time RESIN is asserted will terminate

immediately (note that most control signals will be driven to their inactive state first before

floating).

While RESIN is active, signals RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK,

and TEST/BUSY are configured as inputs and weakly held high by internal pull-up transistors.

Forcing UCS and LCS low selects ONCE Mode. Forcing QSMD low selects Queue Status Mode.

Forcing TEST/ BUSY high at reset and low four clocks later enables Numerics Mode. Forcing

LOCK low is prohibited and results in unspecified operation.

Product Name Datasheet

39

Reset

Figure 11.

Powerup Reset Waveforms

Notes:

1. CLKOUT synchronization occurs approximately 1½ CLKIN periods after RESIN# is sampled low.

2. Pin names in parentheses apply to the 80C188EA.

40

Product Name Datasheet

Reset

Figure 12.

Warm Reset Waveforms

Notes:

1. CLKOUT resynchronization occurs approximately 1½ CLKIN periods after RESIN# is sampled low. If RESIN# is

sampled low while transitioning high, then CLKOUT will remain high for two CLKIN periods. If RESIN# is

sampled low while CLKOUT is transitioning high, the CLKOUT will not be affected.

2. Pin names in parentheses apply to the 80C188EA.

Product Name Datasheet

41

Bus Cycle Waveforms

14.0

Bus Cycle Waveforms

Figure 13 through Figure 19 present the various bus cycles that are generated by the processor.

What is shown in the figure is the relationship of the various bus signals to CLKOUT. These

figures along with the information present in AC Specifications allow the user to determine all the

critical timing analysis needed for a given application.

Figure 13.

Read, Fetch and Refresh Cycle Waveform

Notes:

1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.

2. Pin names in parentheses apply to the 80C188EA.

42

Product Name Datasheet

Bus Cycle Waveforms

Figure 14.

Write Cycle Waveform

Notes:

1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle.

2. Pin names in parentheses apply to the 80C188EA.

Product Name Datasheet

43

Bus Cycle Waveforms

Figure 15.

Halt Cycle Waveform

Notes:

1. The processor drives these pins to 0 during Idle and Powerdown Modes.

2. Pin names in parentheses apply to the 80C188EA.

44

Product Name Datasheet

Bus Cycle Waveforms

Figure 16.

INTA Cycle Waveform

Notes:

1. INTA# occurs one clock later in Slave Mode.

2. Pin names in parentheses apply to the 80C188EA.

Product Name Datasheet

45

Bus Cycle Waveforms

Figure 17.

HOLD/HLDA Waveform

Note: Pin names in parentheses apply to the 80C188EA.

46

Product Name Datasheet

Bus Cycle Waveforms

Figure 18.

DRAM Refresh Cycle During Hold Acknowledge

Note: Pin names in parentheses apply to the 80C188EA.

Product Name Datasheet

47

Bus Cycle Waveforms

Figure 19.

Ready Waveform

Notes:

1. Generalized diagram for READ or WRITE.

2. ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized.

3. SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.

4. Either ARDY or SRDY active high will terminate a bus cycle.

5. Pin names in parentheses apply to the 80C188EA.

48

Product Name Datasheet

Product Name Execution Timings

15.0

Product Name Execution Timings

A determination of program execution timing must consider the bus cycles necessary to prefetch

instructions as well as the number of execution unit cycles necessary to execute instructions. The

following instruction timings represent the minimum execution time in clock cycle for each

instruction. The timings given are based on the following assumptions:

• The opcode, along with any data or displacement required for execution of a particular

instruction, has been prefetched and resides in the queue at the time it is needed.

• No wait states or bus HOLDs occur.

• All word-data is located on even-address boundaries. (80C186EA only)

All jumps and calls include the time required to fetch the opcode of the next instruction at the

destination address.

All instructions which involve memory accesses can require one or two additional clocks above the

minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU)

and execution unit.

With a 16-bit BIU, the 80C186EA has sufficient bus performance to endure that an adequate

number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual

program execution time will not be substantially greater than that derived from adding the

instruction timings shown.

The 80C188EA 8-bit BIU is limited in its performance relative to the execution unit. A sufficient

number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time.

Therefore, actual program execution time will be substantially greater than that derived from

adding the instruction timings shown.

Product Name Datasheet

49

Product Name Execution Timings

Figure 20.

Instruction Set Summary

80C186EA 80C188EA

Function

Format

Comments

Clock

Cycles

DATA TRANSFER

e

MOV

Move%

Register to Register-Memory

Register-memory to register

Im m ediate to register-m em ory

Im m ediate to register

1 0 0 0 1 0 0 w

1 0 0 0 1 0 1 w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

m od reg r-m

2-12

2-9

12–13

3–4

8

2-12ꢀ

2-9

m od reg r-m

m od 000 r-m

data

e

data if w1

data

12–13

3–4

8ꢀ

8-16ꢂbit

e

data if w

1

Memory to accumulator

addrꢂlow

addrꢂhigh

Accumulator to memory

addrꢂlow

9

9ꢀ

Register-memory to segment register

Segment register to register-memory

m od 0 reg r-m

2-9

2-11

2-13

2-15

e

PUSH

Push%

Mem ory

Register

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

0 1 1 0 1 0 s 0

m od 1 1 0 r-m

16

10

9

20

14

Segment register

Im m ediate

13

e

data if s

data

0

10

14

e

PUSHA

Push All

0 1 1 0 0 0 0 0

36

68

e

POP

Pop%

Mem ory

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

m od 0 0 0 r-m

(regⁱ01)

20

10

8

24

14

Register

Segment register

12

e

POPA

Pop All

0 1 1 0 0 0 0 1

51

83

XCHG

Exchange%

Register-memory with register

Register with accumulator

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

m od reg r-m

4-17

3

4-17ꢀ

3

e

IN

Input from%

Fixed port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

port

10

8

10ꢀ

7ꢀ

Variable port

e

OUT

Output to%

Fixed port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

9

7

9ꢀ

7ꢀ

15

6

Variable port

e

XLAT

Translate byte to AL

11

6

e

LEA

LDS

LES

Load EA to register

Load pointer to DS

Load pointer to ES

m od reg r-m

(m oⁱd 11)

18

2

26

2

e

LAHF

SAHF

Load AH with flags

Store AH into flags

e

3

e

PUSHF

Push flags

Pop flags

9

13

12

e

POPF

8

Shaded areas indicate instructions not available in 8086-8088 microsystemsꢀ

NOTE%

ꢀClock cycles shown for byte transfersꢀ For word operationsꢁ add 4 clock cycles for all memory transfersꢀ

50

Product Name Datasheet

Product Name Execution Timings

Figure 20.

Instruction Set Summary (Continued)

80C186EA 80C188EA

Function

Format

Comments

Clock

Cycles

DATA TRANSFER (Continued)

e

SEGMENT

Segment Override%

CS

0 0 1 0 1 1 1 0

0 0 1 1 0 1 1 0

0 0 1 1 1 1 1 0

0 0 1 0 0 1 1 0

2

SS

DS

ES

ARITHMETIC

e

ADD

Add%

ꢀ

Reg-memory with register to either

Im m ediate to register-m em ory

Immediate to accumulator

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

m od reg r-m

m od 0 0 0 r-m

data

3-10

4-16

3-4

3-10

4-16

3-4

e

data if s w01

data

e

data if w

1

8-16ꢂbit

e

ADC

Add with carry%

ꢀ

Reg-memory with register to either

Im m ediate to register-m em ory

Immediate to accumulator

0 0 0 1 0 0 d w

1 0 0 0 0 0 s w

0 0 0 1 0 1 0 w

m od reg r-m

m od 0 1 0 r-m

data

3-10

4-16

3-4

3-10

4-16

3-4

e

data if s w01

data

e

data if w

1

e

INC

Increment%

ꢀ

Register-memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

m od 0 0 0 r-m

3-15

3

3-15

3

e

SUB

Subtract%

ꢀ

Reg-memory and register to either

Im m ediate from register-m em ory

Immediate from accumulator

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

m od reg r-m

m od 1 0 1 r-m

data

3-10

4-16

3-4

3-10

4-16

3-4

e

data if s w01

data

e

data if w

1

8-16ꢂbit

e

SBB

Subtract with borrow%

ꢀ

Reg-memory and register to either

Im m ediate from register-m em ory

Immediate from accumulator

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

m od reg r-m

m od 0 1 1 r-m

data

3-10

4-16

3-4

3-10

4-16

e

data if s w01

data

ꢀ

e

data if w

1

3-4

e

DEC

Decrement

ꢀ

Register-memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

m od 0 0 1 r-m

3-15

3

3-15

3

e

CMP

Compare%

ꢀ

Register-memory with register

Register with register-memory

Im m ediate with register-m em ory

Immediate with accumulator

0 0 1 1 1 0 1 w

0 0 1 1 1 0 0 w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

1 1 1 1 0 1 1 w

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

m od reg r-m

m od 1 1 1 r-m

data

3-10

3-4

3-10

3-4

3-10

8

e

data if s w01

data

e

data if w

1

8-16ꢂbit

ꢀ

e

NEG

AAA

DAA

AAS

DAS

Change sign register-memory

ASCII adjust for add

m od 0 1 1 r-m

3-10

8

4

7

4

Decimal adjust for add

4

ASCII adjust for subtract

Decimal adjust for subtract

7

4

e

MUL

Multiply (unsigned)@

1 1 1 1 0 1 1 w

m od 100 r-m

RegisterꢂByte

RegisterꢂWord

MemoryꢂByte

MemoryꢂWord

26–28

35–37

32–34

41–43

26–28

35–37

32–34

ꢀ

41–48

Shaded areas indicate instructions not available in 8086-8088 microsystemsꢀ

NOTE%

ꢀClock cycles shown for byte transfersꢀ For word operationsꢁ add 4 clock cycles for all memory transfersꢀ

Product Name Datasheet

51

Product Name Execution Timings

Figure 20.

Instruction Set Summary (Continued)

80C186EA 80C188EA

Function

Format

Comments

Clock

Cycles

ARITHMETIC (Continued)

e

IMUL

Integer multiply (signed)@

1 1 1 1 0 1 1 w

m od 1 0 1 r-m

RegisterꢂByte

RegisterꢂWord

MemoryꢂByte

MemoryꢂWord

25–28

34–37

31–34

40–43

25–28

34–37

32–34

40–43ꢀ

e

(signed)

e

0

IMUL

Integer Immediate multiply

0 1 1 0 1 0 s 1

1 1 1 1 0 1 1 w

m od reg r-m

data

data if s

22–25

29–32

22ꢂ25

29–32

e

DIV

Divide (unsigned)@

m od 1 1 0 r-m

RegisterꢂByte

RegisterꢂWord

MemoryꢂByte

MemoryꢂWord

29

38

35

44

29

38

35

ꢀ

44

e

IDIV

Integer divide (signed)@

1 1 1 1 0 1 1 w

m od 1 1 1 r-m

RegisterꢂByte

RegisterꢂWord

MemoryꢂByte

MemoryꢂWord

44–52

53–61

50–58

59–67

44–52

53–61

50–58

59–67ꢀ

e

AAM

AAD

CBW

CWD

ASCII adjust for multiply

ASCII adjust for divide

Convert byte to word

1 1 0 1 0 1 0 0

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 0 0 1 0 1 0

19

15

2

19

15

2

Convert word to double word

4

LOGIC

ShiftꢀRotate Instructions%

Register-Memory by 1

1 1 0 1 0 0 0 w

1 1 0 1 0 0 1 w

1 1 0 0 0 0 0 w

m od TTT r-m

TTT Instruction

2-15

a

Register-Memory by CL

5

n-17

n

5

n-17

n

a

5

a

Register-Memory by Count

count

0 0 0

0 0 1

0 1 0

0 1 1

ROL

ROR

RCL

RCR

1 0 0 SHL-SAL

1 0 1

1 1 1

SHR

SAR

e

AND

And%

Reg-memory and register to either

Immediate to register-memory

Immediate to accumulator

0 0 1 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

m od reg r-m

m od 1 0 0 r-m

data

3-10

4-16

3-4

3-10ꢀ

4-16ꢀ

3-4ꢀ

e

data

data if w

1

e

data if w

1

8-16ꢂbit

e

TEST And function to flagsꢁ no result%

ꢀ

3-10

Register-memory and register

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

m od reg r-m

m od 0 0 0 r-m

data

3-10

4-10

3-4

Immediate data and register-memory

Immediate data and accumulator

data

4-10ꢀ

e

data if w

3-4

e

OR Or%

Reg-memory and register to either

Immediate to register-memory

Immediate to accumulator

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

m od reg r-m

m od 0 0 1 r-m

data

3-10

4-16

3-4

3-10ꢀ

ꢀ

data

4-16

data if w

3-4ꢀ

Shaded areas indicate instructions not available in 8086-8088 microsystemsꢀ

NOTE%

ꢀClock cycles shown for byte transfersꢀ For word operationsꢁ add 4 clock cycles for all memory transfersꢀ

52

Product Name Datasheet

Product Name Execution Timings

Figure 20.

Instruction Set Summary (Continued)

80C186EA 80C188EA

Function

Format

Comments

Clock

Cycles

LOGIC (Continued)

e

XOR

Exclusive or%

Reg-memory and register to either

Immediate to register-memory

Immediate to accumulator

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

1 1 1 1 0 1 1 w

m od reg r-m

m od 1 1 0 r-m

data

3-10

4-16

3-4

3-10ꢀ

4-16ꢀ

3-4

e

1

data

data if w

e

data if w

1

8-16ꢂbit

e

NOT

Invert register-memory

m od 0 1 0 r-m

3-10

3-10ꢀ

STRING MANIPULATION

e

MOVS

CMPS

SCAS

LODS

STOS

Move byte-word

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

0 1 1 0 1 1 0 w

0 1 1 0 1 1 1 w

14

22

15

12

10

14

14ꢀ

22ꢀ

15ꢀ

12ꢀ

10ꢀ

14

Compare byte-word

Scan byte-word

Load byte-wd to AL-AX

Store byte-wd fromAL-AX

e

INS

Input byte-wd fromDX port

e

OUTS

Output byte-wd to DX port

14

Repeated by count in CX (REP-REPE-REPZ-REPNE-REPNZ)

ꢀ

e

a

MOVS

CMPS

SCAS

LODS

STOS

Move string

Compare string

Scan string

Load string

1 1 1 1 0 0 1 0

1 1 1 1 0 0 1 z

1 1 1 1 0 0 1 0

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

0 1 1 0 1 1 0 w

8

8n

8

8n

a

5

6

22n

15n

11n

5

22n

a

5

6

15nꢀ

11nꢀ

a

Store string

6

9n

8n

6

9nꢀ

8nꢀ

e

a

INS

Input string

8

e

OUTS

Output string

1 1 1 1 0 0 1 0

0 1 1 0 1 1 1 w

8n

8nꢀ

CONTROL TRANSFER

e

CALL

Call%

Direct within segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

dispꢂlow

dispꢂhigh

15

19

Register-memory

m od 0 1 0 r-m

13-19

17-27

indirect within segment

Direct intersegment

1 0 0 1 1 0 1 0

1 1 1 1 1 1 1 1

segment offset

segment selector

23

31

i

(m od 11)

Indirect intersegment

m od 0 1 1 r-m

38

54

e

JMP

Unconditional jump%

Short-long

1 1 1 0 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 1 1 1

dispꢂlow

14

Direct within segment

dispꢂhigh

Register-memory

m od 1 0 0 r-m

11-17

11-21

indirect within segment

Direct intersegment

Indirect intersegment

1 1 1 0 1 0 1 0

segment offset

segment selector

14

26

14

34

i

(m od 11)

1 1 1 1 1 1 1 1

m od 1 0 1 r-m

Shaded areas indicate instructions not available in 8086-8088 microsystemsꢀ

NOTE%

ꢀClock cycles shown for byte transfersꢀ For word operationsꢁ add 4 clock cycles for all memory transfersꢀ

Product Name Datasheet

53

Product Name Execution Timings

Figure 20.

Instruction Set Summary (Continued)

80C186EA

Clock

80C188EA

Clock

Function

Format

Comments

Cycles

CONTROL TRANSFER (Continued)

e

RET

Returnfrom CALL%

Within segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

16

20

Within seg adding immed to SP

Intersegment

dataꢂlow

dataꢂhigh

18

22

30

Intersegment adding immediate to SP

dataꢂlow

disp

25

33

e

JEꢀJZ

Jump on equal-zero

4-13

5-15

6-16

4-13

5-15

6-16

JMP not

taken-JMP

taken

e

JLꢀJNGE

JLEꢀJNG

JBꢀJNAE

JBEꢀJNA

Jump on less-not greater or equal

Jump on less or equal-not greater

Jump on below-not above or equal

Jump on below or equal-not above

e

JPꢀJPE

Jump on parity-parity even

Jump on overflow

Jum p on sign

e

JO

JS

e

JNEꢀJNZ

JNLꢀJGE

JNLEꢀJG

JNBꢀJAE

JNBEꢀJA

JNPꢀJPO

Jump on not equal-not zero

Jump on not less-greater or equal

Jump on not less or equal-greater

Jump on not below-above or equal

Jump on not below or equal-above

Jump on not par-par odd

e

JNO

JNS

Jump on not overflow

Jum p on not sign

e

JCXZ

LOOP

Jump on CX zero

Loop CX times

e

LOOP not

taken-LOOP

taken

e

LOOPZꢀLOOPE

LOOPNZꢀLOOPNE

Loop while zero-equal

e

Loop while not zero-equal

e

ENTER

Enter Procedure

1 1 0 0 1 0 0 0

dataꢂlow

dataꢂhigh

L

e

l

L

0

1

15

25

19

29

a

b

a

b

22 16(n 1) 26 20(n 1)

e

LEAVE

Leave Procedure

1 1 0 0 1 0 0 1

8

e

INT

Interrupt%

Type specified

Type 3

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

type

47

45

47

45

if INTꢀ taken-

if INTꢀ not

taken

e

INTO

Interrupt on overflow

48-4

e

IRET

Interrupt return

1 1 0 0 1 1 1 1

0 1 1 0 0 0 1 0

28

e

BOUND

Detect value out of range

m od reg r-m

33–35

Shaded areas indicate instructions not available in 8086-8088 microsystemsꢀ

NOTE%

ꢀClock cycles shown for byte transfersꢀ For word operationsꢁ add 4 clock cycles for all memory transfersꢀ

54

Product Name Datasheet

Product Name Execution Timings

Figure 20.

Instruction Set Summary (Continued)

80C186EA 80C188EA

Function

Format

Comments

Clock

Cycles

PROCESSOR CONTROL

e

CLC

CMC

STC

CLD

STD

Clear carry

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 1 1 0 0 0 0

2

6

2

3

2

6

2

3

Complement carry

Set carry

Clear direction

Set direction

e

CLI

STI

Clear interrupt

Set interrupt

e

HLT

Halt

e

0

WAIT

LOCK

Wait

if TEST

e

Bus lock prefix

e

NOP

No Operation

1 0 0 1 0 0 0 0

(TTT LLL are opcode to processor extension)

Shaded areas indicate instructions not available in 8086-8088 microsystemsꢀ

NOTE%

ꢀClock cycles shown for byte transfersꢀ For word operationsꢁ add 4 clock cycles for all memory transfersꢀ

The Effective Address (EA) of the memory operand

is computed according to the mod and r-m fields@

reg is assigned according to the following@

Segment

e

if mod

11 then r-mis treated as a REG field

e

reg

00

01

10

11

Register

ES

CS

00 then DISP

high are absent

0ꢀꢁ dispꢂlow and dispꢂ

e

tended to 16ꢂbitsꢁ dispꢂhigh is absent

if mod

01 then DISP

dispꢂlow signꢂexꢂ

SS

DS

e

if mod

if r-m

10 then DISP

dispꢂhigh@ dispꢂlow

e

a

000 then EA

001 then EA

010 then EA

011 then EA

100 then EA

101 then EA

110 then EA

111 then EA

(BX)

(SI)

(DI)

(SI)

(DI)

DISP

e

REG is assigned according to the following table@

e

0)

(BX)

(BP)

e

16-Bit (w

1)

8-Bit (w

000 AL

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

a

(SI)

DISP

001 CL

010 DL

011 BL

100 AH

101 CH

110 DH

111 BH

a

(DI)

(BP)

(BX)

DISP

DISPꢀ

DISP

a

DISP follows 2nd byte of instruction (before data if

required)

111 DI

e

110 then EA

ꢀexcept if mod

dispꢂhigh@ dispꢂlowꢀ

00 and r-m

The physical addresses of all operands addressed

by the BP register are computed using the SS segꢂ

ment registerꢀ The physical addresses of the destiꢂ

nation operands of the string primitive operations

(those addressed by the DI register) are computed

using the ES segmentꢁ which may not be overriddenꢀ

EA calculation time is 4 clock cycles for all modesꢁ

and is included in the execution times given whenevꢂ

er appropriateꢀ

Segment Override Prefix

0

1

reg

1

0

Product Name Datasheet

55

Revision History

16.0

Revision History

Intel 80C186EA/80L186EA devices are marked with a 9-character alphanumeric Intel FPO

number underneath the product number. This data sheet update is valid for devices with an “A”,

“B”, “C”, “D”, or “E” as the ninth character in the FPO number, as illustrated in Figure 3 for the

68-lead PLCC package, and as also illustrated in diagrams of the 84-lead QFP (EIAJ) package in

previous revisions of this datasheet. Such devices may also be identified by reading a value of 01H,

02H, 03H from the STEPID register.

This data sheet replaces the following data sheets:

• 272019-002—80C186EA

• 272020-002—80C188EA

• 272021-002—80L186EA

• 272022-002—80L188EA

• 272307-001—SB80C186EA/SB80L186EA

• 272308-001—SB80C188EA/SB80L188EA

17.0

Errata

An 80C186EA/80L186EA with a STEPID value of 01H or 02H has the following known errata. A

device with a STEPID of 01H or 02H can be visually identified by noting the presence of an “A,”

“B”, or “C” alpha character, next to the FPO number. The FPO number location is shown in

Figure 3.

1. An internal condition with the interrupt controller can cause no acknowledge cycle on the

INTA1 line in response to INT1. This errata only occurs when Interrupt 1 is configured in

cascade mode and a higher priority interrupt exists. This errata will not occur consistently, it is

dependent on interrupt timing.

An 80C186EA/80L186EA with a STEPID value of 03H has no known errata. A device with a

STEPID of 03H can be visually identified by noting the presence of a “D” or “E” alpha character

next to the FPO number. The FPO number location is shown in Figure 3.

56

Product Name Datasheet


型号：	TN80C186EA25
厂家：	ETC
描述：	Microprocessor 微处理器\n 外围集成电路微处理器装置动态存储器时钟
文件：	总56页 (文件大小：626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TN80C186EA25 [ETC]

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