TS55001 [ETC]
High Efficiency Li-Ion Battery Charger; 高效率的锂离子电池充电器
| 型号： | TS55001 |
| 厂家： | 
ETC |
| 描述： | High Efficiency Li-Ion Battery Charger |
| 文件： | 总22页 (文件大小：1243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS55001
Version 1.3
High Efficiency Li-Ion Battery Charger
DESCRIPTION
FEATURES
.
.
VBAT reverse current blocking
The TS55001 is a DC/DC synchronous switching Li-
ion Battery Charger with fully integrated power
switches, internal compensation, and full fault
protection. The switching frequency of 1MHz enables
the use of small filter components, resulting in smaller
board space and reduced BOM costs.
Programmable temperature-compensated termination
voltage with +/- 1% tolerance
.
Up to 1.5A of continuous output current in Full
Charge Constant-Current (CC) mode
.
.
.
.
.
.
User programmable charging current
High efficiency – up to 92% at typical load
Current mode PWM control in constant voltage
Supervisor for VBAT reported at the nFLT pin
Input supply under-voltage lockout
The regulation in Full Charge mode is Constant-
Current (CC). Once termination voltage is reached, the
regulator operates in voltage mode. When the regulator
is disabled (EN is low), the device draws 10uA
quiescent current.
Full protection for VBAT over-current, over-temp,
over-voltage, and charging timeout
The TS55001 includes supervisory reporting through
the nFLT (Inverted Fault) open drain output to interface
other components in the system. Device programming
is achieved by an I²C interface through SCL and SDA
pins.
.
.
Charge status indication
I2C program interface with EEPROM registers
SUMMARY SPECIFICATIONS
.
Wide input voltage range: VBAT + 0.3V (3.5V min) to
7.2V
APPLICATIONS
.
Packaged in a 16pin QFN (4x4)
.
.
.
.
Portable battery chargers
Smart Phones
Laptops
Tablets / eReaders
TYPICAL APPLICATION
VIN
VTH_REF
VTHERM
RREF
CIN
GND
VDD
CVdd
RSENSE
LOUT
Battery
SW
COUT
TS55001
RTHM
SCL
SDA
VSENSE
VDD
RPULLUP
(optional)
VBAT
VDD
RPULLUP
(optional)
EN
PG
PGND
Specifications subject to change
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TS55001
Version 1.3
PINOUT
SW
VIN
SCL
VIN
TS55001
QFN16 4x4
Top/Symbolization View
VSENSE
VBAT
VTH_REF
VTHERM
Figure 1b: Package Pinout Diagram
PIN DESCRIPTION
Pin Symbol
Pin #
Function
Description
SW
1
Switching Voltage Node
Connected to 4.7uH (typical) inductor
Input voltage
VIN
2
3
4
Input Voltage
VSENSE
VBAT
Current Sense Positive Input
Battery Input
Positive input for the current loop
Regulator Feedback Input
Primary ground for the majority of the device except
the low-side power FET.
GND
EN
5
6
GND
Above 2.2V the device is enabled. GND the pin to
disable the device. Includes internal pull-up.
Enable Input
nFLT
VDD
7
8
Inverted Fault
Open-drain output.
Internal 3.3V Supply Output
Connected to 100nF capacitor to GND
Battery Temperature Sensor
Minus Node
Minus node for the thermistor which is located in close
proximity to the battery.
VTHERM
VTH_REF
9
Battery Temperature Sensor
Positive Node
Positive node for the thermistor which is located in
close proximity to the battery
10
VIN
11
12
13
14
15
16
Input Voltage
Input voltage
I2C clock input.
I2C data open-drain output.
SCL
Clock Input
SDA
SW
Data Input/Output
Switching Voltage Node
Power GND
Connected to 4.7uH (typical) inductor
GND supply for internal low-side FET/integrated diode
GND supply for internal low-side FET/integrated diode
PGND
PGND
Power GND
Specifications subject to change
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TS55001
Version 1.3
FUNCTIONAL BLOCK DIAGRAM
EN
VIN
nFLT
VIN
VIN
SCL
SDA
I²C
Interface
MONITOR
&
CONTROL
Over Voltage
Protection
VBAT
VBAT
VTH_REF
VTHERM
Oscillator
BATT Thermal
Control
Ramp
Generator
BATT Current
Control
VIN
Vref
Gate
Drive
SW
Gate Drive
Control
LOUT
RSENSE
Comparator
Gate
Drive
Error Amp
PGND
Compensation
Network
VIN
Current
Control
VDD Regulator
VSENSE
VBAT
VDD
GND
CVDD
Figure 2: TS55001 Block Diagram
Specifications subject to change
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TS55001
Version 1.3
ABSOLUTE MAXIMUM RATINGS
Over operating free–air temperature range unless otherwise noted(1,2,3)
Parameter
Range
Unit
V
VIN, EN, nFLT, SCL, SDA, VTHERM, VTH_REF, VBAT, VSENSE
SW
-0.3 to 8
-1 to 8.8
-0.3 to 3.6
-40 to 125
-65 to 150
±2k
V
VDD
V
Operating Junction Temperature Range, TJ
Storage Temperature Range, TSTG
Electrostatic Discharge – Human Body Model
Electrostatic Discharge – Machine Model
Lead Temperature (soldering, 10 seconds)
C
C
V
+/-200
V
260
C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
Unit
JA
Thermal Resistance Junction to Air (Note 1)
50
°C/W
Note 1: Assumes 4x4 QFN-16 in 1 in2 area of 2 oz copper and 25C ambient temperature.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
VBAT + 0.3,
(3.5V min)
VIN
Input Operating Voltage
5.3
7.2
V
RSENSE
LOUT
COUT
COUT-ESR
CIN
Sense Resistor
50
m
uH
uF
Output Filter Inductor Typical Value (Note 1)
Output Filter Capacitor Typical Value (Note 2)
Output Filter Capacitor ESR
4.7
4.7
100
m
uF
Input Supply Bypass Capacitor Value (Note 3)
VDD Supply Bypass Capacitor Value (Note 2)
Operating Free Air Temperature
3.3
70
10
CVDD
TA
100
130
85
nF
-40
-40
C
TJ
Operating Junction Temperature
125
C
Note 1: For best performance, an inductor with a saturation current rating higher than the maximum VBAT load requirement plus the inductor current ripple.
Note 2: For best performance, a low ESR ceramic capacitor should be used.
Note 3: For best performance, a low ESR ceramic capacitor should be used. If CIN is not a low ESR ceramic capacitor, a 0.1uF ceramic capacitor should be
added in parallel to CIN.
Specifications subject to change
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TS55001
Version 1.3
CHARACTERISTICS
Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VIN Supply Voltage
VBAT + 0.3,
(3.5V min)
V IN
Voltage Input
5.3
3
7.2
V
Quiescent current
Normal Mode
Quiescent current
Disable Mode
ICC-NORM
ICC-DISABLE
ILOAD = 0A, no switching
EN = 0V
mA
uA
10
50
VBAT Leakage
IBAT-LEAK
IBAT-BACK
Leakage Current From Batt
Reverse Current
EN = 0V, VBAT = 4.1V
VBAT > VIN, VBAT = 4.1V, Tj < 85C
10
10
uA
uA
VIN Under-Voltage Lockout
Input Supply Under-Voltage
Threshold
Input Supply Under-Voltage
Threshold Hysteresis
VIN-UV
VIN Increasing
3.15
200
V
VIN-UV_HYST
100
0.9
mV
OSC
FOSC
Oscillator Frequency
1
1.1
0.4
0.8
MHz
nFLT Open Drain Output
IOH-nFLT High-Level Output Leakage
VOL-nFLT Low-Level Output Voltage
EN/SCL/SDA Input Voltage Thresholds
VnFLT = 5.3V
InFLT = -1mA
0.1
uA
V
VIH
VIL
VHYST
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
2.2
V
V
200
0.1
-2.0
55
-0.1
0.1
-0.1
mV
uA
uA
uA
uA
uA
uA
V
VEN=VIN
VEN=0V
VSCL=VIN
VSCL=0V
VSDA=VIN
VSDA=0V
ISDA = -1mA
IIN-EN
Input Leakage
Input Leakage
IIN-SCL
IIN-SDA
Input Leakage
VOL-SDA
Low-Level Output Voltage
Thermal Shutdown
0.4
3.1
Thermal Shutdown Junction
Temperature
TSD Hysteresis
TSD
150
2.9
170
10
°C
°C
TSDHYST
Pre-Charge End
VPreChg
VPCHYST
Pre-Charge Voltage Threshold
Pre-Charge Voltage Hysteresis
3.0
70
V
mV
Charge Restart
Voltage below termination for
charging restart
VReStart
100
mV
Specifications subject to change
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TS55001
Version 1.3
CHARGER CHARACTERISTICS
Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Charging Regulator: L=4.7uH and C=4.7uF
Output Current Limit in Full-Charge
Mode
Termination Voltage Tolerance in
Top-Off Mode
IBAT
10%
VBAT
1%
-
IBAT +
10%
IBAT-FC
VBAT-TO
tTO
IBAT = 1.5A
IBAT
A
-
VBAT
1%
+
IBAT = 0.1C, 0C < Tj < 85C
VBAT
V
Top-Off Mode Time Out
Full-Charge Timer
Timer Accuracy
0
120
1400
+10%
min
min
tFC
200
-10%
tacc
High Side Switch On Resistance
Low Side Switch On Resistance
Max Output Current
ISW = -1A, TJ=25C
ISW = 1A, TJ=25C
200
250
1.5
mΩ
mΩ
A
RDSON
IBAT
IOCD
Over-Current Detect
HS switch current
2.5
A
101%
VBAT
102%
VBAT
98
103%
VBAT
VBAT-OV
VBAT Over-Voltage Threshold
Max Duty Cycle
DUTYMAX
%
I2C INTERFACE TIMING REQUIREMENTS
Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted)
Symbol
Parameter
Standard Mode Fast Mode(1)
Unit
Min
0
4
4.7
0
250
0
Max
100
Min
0
0.6
1.3
0
Max
400
fscl
tsch
tscl
tsp
tsds
tsdh
I2C clock frequency
kHz
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
I2C clock high time
I2C clock low time
I2C tolerable spike time
50
50
(2)
I2C serial data setup time
250
0
I2C serial data hold time
(2)
ticr
ticf
I2C input rise time
1000
300
300
300
300
300
(2)
I2C input fall time
(2)
tocf
I2C output fall time; 10 pF to 400 pF bus
I2C bus free time between Stop and Start
I2C Start or repeated Start condition setup time
I2C Start or repeated Start condition hold time
I2C Stop condition setup time
tbuf
tsts
tsth
4.7
4.7
4
1.3
0.6
0.6
0.6
(2)
tsps
4
(1) The I²C interface will operate in either standard or fast mode.
(2) Parameters not tested in production.
Specifications subject to change
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TS55001
Version 1.3
THERMISTOR CHARACTERISTICS
Electrical Characteristics, TJ = -40C to 125C, VIN = 5.3V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VVTH_REF
VTH_REF output voltage
IVT_REF = 2uA-100uA
1.22
V
10KΩ Temperature Thresholds – β=3434K
0°C
0°C Vtherm Threshold (0°C)
Decreasing Temperature
Increasing Temperature
Decreasing Temperature
Increasing Temperature
Increasing Temperature
Decreasing Temperature
Increasing Temperature
Decreasing Temperature
Increasing Temperature
Decreasing Temperature
75.6
66.5
66.2
65.4
34.5
35.3
30.8
31.5
24.9
30.8
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
0°CHYST
10°C
0°C Vtherm Threshold with
Hysteresis (10°C)
10°C Vtherm Threshold (10°C)
10°CHYST
45°C
10°C Vtherm Threshold with
Hysteresis (11°C)
45°C Vtherm Threshold (45°C)
45°CHYST
50°C
45°C Vtherm Threshold with
Hysteresis (44°C)
50°C Vtherm Threshold (50°C)
50°CHYST
60°C
50°C Vtherm Threshold with
Hysteresis (49°C)
60°C Vtherm Threshold (60°C)
%VTH
_REF
%VTH
_REF
60°CHYST
60°C Vtherm Threshold with
Hysteresis (50°C)
100KΩ Temperature Thresholds – β=4311K
0°C
0°C Vtherm Threshold (0°C)
Decreasing Temperature
Increasing Temperature
Decreasing Temperature
Increasing Temperature
Increasing Temperature
Decreasing Temperature
Increasing Temperature
Decreasing Temperature
Increasing Temperature
Decreasing Temperature
80.5
69.8
69.8
68.6
31.3
32.3
27.0
27.8
19.4
27.0
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
%VTH
_REF
0°CHYST
10°C
0°C Vtherm Threshold with
Hysteresis (10°C)
10°C Vtherm Threshold (10°C)
10°CHYST
45°C
10°C Vtherm Threshold with
Hysteresis (11°C)
45°C Vtherm Threshold (45°C)
45°CHYST
50°C
45°C Vtherm Threshold with
Hysteresis (44°C)
50°C Vtherm Threshold (50°C)
50°CHYST
60°C
50°C Vtherm Threshold with
Hysteresis (49°C)
60°C Vtherm Threshold (60°C)
%VTH
_REF
%VTH
_REF
60°CHYST
60°C Vtherm Threshold with
Hysteresis (50°C)
Specifications subject to change
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TS55001
Version 1.3
FUNCTIONAL DESCRIPTION
The TS55001 is a fully-integrated Li-Ion battery charger IC based on a highly-efficient switching topology. It includes
configurability for termination voltage, charge current and a host of other variables to allow optimum charging conditions for a
wide range of Li-Ion batteries. A 1 MHz internal switching frequency facilitates low-cost LC filter combinations.
When the battery voltage is below 3.0 volts, the device will enter a pre-charge state and apply a small, programmable charge
current to safely charge the battery to a level for which full charge current can be applied. Once the full charge mode has been
initiated, the regulation will be constant current (CC).
When the battery voltage has increased enough to go into maintenance mode, the PWM control loop will force a constant
voltage across the battery. Once in constant voltage mode, current is monitored to determine when the battery is fully charged.
This regulation voltage as well as the 1C charging current can be set to change based on battery temperature. There are 4
temperature ranges where these can be set independently, 0-10°C, 10-45°C, 45-50°C and 50-60°C. The 0°C and 60°C thresholds
will stop charging and have 10 degrees of hysteresis. The intermediate points have 1 degree of hysteresis.
INTERNAL PROTECTION DETAILS
Internal Current Limit
The current through the inductor is sensed on a cycle by cycle basis and if current limit is reached, it will abbreviate the cycle.
Current limit is always active when the regulator is enabled.
Thermal Shutdown
If the temperature of the die exceeds 170°C (typical), the SW outputs will tri-state to protect the device from damage. The nFLT
and all other protection circuitry will stay active to inform the system of the failure mode. Once the device cools to 160°C
(typical), the device will attempt to start up again. If the device reaches 170°C, the shutdown/restart sequence will repeat.
VIN Under-Voltage Lockout
The device is held in the off state until VIN reaches 3.15V. There is a 200mV hysteresis on this input, which requires the input
to fall below 2.95V before the device will disable.
Battery Over-Voltage Protection
The TS55001 has a battery protection circuit designed to shutdown the charging profile if the battery voltage is greater than
the termination voltage. The termination voltage can change based on user programming, so the protection threshold is set to
2% above the termination voltage. Shutting down the charging profile puts the TS55001 in a fault condition.
FAULT HANDLING
nFLT Pin Functionality
In the event of a battery over-voltage, the battery temperature being outside of the safe charging range or the full charge timer
expiring, charging will stop, and the nFLT pin will be pulled low. When the fault condition is no longer present, the device will
enter the INITIALIZE state, but the nFLT pin will remain low until register 0 is read. When the register 0 is read, the nFLT pin
will go high until a new fault is detected.
Other Faults
When an open thermistor, thermal shut down, VIN under-voltage, or top off time-out are detected, charging will immediately
stop and the corresponding bit in register 0 will be set. The device will enter the INITIALIZE state until the fault is no longer
detected.
Specifications subject to change
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TS55001
Version 1.3
SERIAL INTERFACE
The TS55001 features an I2C slave interface which offers advanced control and diagnostic features. I2C operation offers
configuration control for termination voltages, charge currents, and charge timeouts. This configurability allows for optimum
charging conditions in a wide range of Li-Ion batteries. I2C operation also offers fault and warning indicators. Whenever a fault
is detected, the associated status bit in the STATUS register is set and the nFLT pin is pulled low. Whenever a warning is
detected, the associated status bit in the STATUS register is set, but the nFLT pin is not pulled low. Reading of the STATUS
register resets the fault and warning status bits, and the nFLT pin is released after all fault status bits have been reset.
I2C SUBADDRESS DEFINITION
Figure 3: Sub-address in I2C Transmission
I2C BUS OPERATION
The TS55001 has a slave I2C interface that supports standard and fast mode data rates, auto-sequencing, and is compliant to I2C
standard version 3.0.
I2C is a two-wire serial interface where the two lines are serial clock (SCL) and serial data (SDA). SDA must be connected to a
positive supply through an external pull-up resistor. The devices communicating on this bus can drive the SDA line low or
release it to high impedance. The device that initiates the I2C transaction becomes the master of the bus. Communication is
initiated by the master sending a Start condition, a high-to-low transition on SDA, while the SCL line is high. After the Start
condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/nW). After
receiving the valid address byte, the device responds with an acknowledge (ACK). An ACK is a low on SDA during the high of
the ACK related clock pulse. On the I2C bus, during each clock pulse only one data bit is transferred. The data on the SDA line
must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as Start or
Stop control commands. A low-to-high transition on SDA while the SCL input is high, indicates a Stop condition and is sent by
the master (see Figure 4).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each
byte of eight bits is followed by one ACK bit. The SDA line must be released by the transmitter before the receiver can send an
ACK bit. The receiver that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after
each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. To
ensure proper operation, setup and hold times must be met. An end of data is signaled by the master receiver to the slave
transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. This is done by the master
receiver by holding the SDA line high. The transmitter must then release the data line to enable the master to generate a Stop
condition.
Specifications subject to change
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TS55001
Version 1.3
Figure 4: I2C Start / Stop Protocol
Figure 5: I2C Data Transmission Timing
Specifications subject to change
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TS55001
Version 1.3
CHARGING STATE DIAGRAM
EN
INITIALIZE
Waiting for Valid
Charging Conditions
NO
No Faults &
Vbat < Restart
YES
PRE CHARGE
Pre Charge
NO
Vbat > PreCharge
Threshold
YES
YES
1C CHARGING
1C Current Limit and Full
Charge Timer
Vbat <
PreCharge
NO
NO
Vbat = Vterm &
Icharge < Ieoc
NO
YES
END OF CHARGE
Vbat regulated to Termination
Voltage with EOC Timer
Vbat = Vterm
YES
NO
Icharge < Top Off
End Current
YES
Specifications subject to change
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TS55001
Version 1.3
REGISTER DESCRIPTION (Device Address = 0x48)
REGISTER ADDRESS (HEX) NAME
DEFAULT
0x00
DESCRIPTION
Status bit register
0
00
STATUS
1
2
3
4
5
6
7-16
17
18
N/A
02
03
04
05
06
N/A
11
N/A
N/A
Register not implemented
Configuration register
Configuration register
Configuration register
Configuration register
Configuration register
Registers not implemented
CONFIG1(1)
CONFIG2(1)
CONFIG3(1)
CONFIG4(1)
CONFIG5(1)
N/A
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
N/A
CONFIG_ENABLE 0x00
EEPROM_CTRL(1) 0x00
Enable configuration register access
EEprom control register
12
(1) CONFIG and EEPROM_CTRL registers are only accessible when CONFIG_ENABLE register is written.
STATUS REGISTER (STATUS)
Address – 0x00h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
READ/WRITE
BATT_OV
R
1C_TO
R
TEMP_0C
R
TEMP_60C TSD
TOP_TO
R
VIN_UV
R
TH_OPEN
R
R
R
FIELD NAME
BATT_OV
1C_TO
BIT DEFINITION(2)
Battery over-voltage
Full charge timer has timed out
TEMP_0C
TEMP_60C
TSD
Thermistor indicates battery temperature < 0°C
Thermistor indicates battery temperature > 60°C
Thermal shutdown
TOP_TO
VIN_UV
Top Off timer has timed out
VIN under-voltage
TH_OPEN
Thermistor Open (battery not present)
(2) Faults are defined as BATT_OV, 1C_TO, TEMP_0C, and TEMP_60C. Warnings are defined as TSD, TOP_TO, VIN_UV, and
TH_OPEN. Faults cause the nFLT pin to be pulled low, Warnings do not cause the nFLT pin to be pulled low. All status bits
are cleared after register read access. nFLT pin will go high impedance (open drain output) after the status register has
been read and all status bits have been reset.
Specifications subject to change
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TS55001
Version 1.3
CONFIGURATION REGISTER (CONFIG1)
Address – 0x02h
DATA BIT
FIELD NAME
READ/WRITE R/W
D7
D6
D5
V_TERM_0_10[2:0]
R/W R/W
D4
D3
D2
V_TERM_10_45[2:0]
R/W R/W
D1
D0
PRE_CHRG[1:0]
R/W
R/W
R/W
FIELD NAME
PRE_CHRG[1:0](1)
BIT DEFINITION
Pre-Charging configuration
00 – 50 mA
01 – 100 mA
10 – 185 mA
11 – 370 mA
Voltage Termination 0-10°C configuration
000 – 3.94 V
V_TERM_0_10[2:0](2)
001 – 4.00 V
010 – 4.05 V
011 – 4.10 V
100 – 4.12 V
101 – 4.15 V
110 – 4.18 V
111 – Invalid Setting
Voltage Termination 10-45°C configuration
000 – 3.94 V
V_TERM_10_45[2:0](2)
001 – 4.00 V
010 – 4.05 V
011 – 4.10 V
100 – 4.12 V
101 – 4.15 V
110 – 4.18 V
111 – Invalid Setting
(1) PRE_CHRG Note: Maximum output current when VBAT < 3.0 V.
(2) V_TERM Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For <0°C and
>60°C, charging is disabled and a fault is set.
Specifications subject to change
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TS55001
Version 1.3
CONFIGURATION REGISTER (CONFIG2)
Address – 0x03h
DATA BIT
FIELD NAME
READ/WRITE R/W
D7
EOC[1:0]
D6
D5
V_TERM_45_50[2:0]
R/W R/W
D4
D3
D2
V_TERM_50_60[2:0]
R/W R/W
D1
D0
R/W
R/W
R/W
FIELD NAME
EOC[1:0](1)
BIT DEFINITION
End of charge configuration
00 – 50 mA
01 – 100 mA
10 – 185 mA
11 – 370 mA
Voltage Termination 45-50°C configuration
000 – 3.94 V
V_TERM_45_50[2:0](2)
001 – 4.00 V
010 – 4.05 V
011 – 4.10 V
100 – 4.12 V
101 – 4.15 V
110 – 4.18 V
111 – Invalid Setting
Voltage Termination 50-60°C configuration
000 – 3.94 V
V_TERM_50_60[2:0](2)
001 – 4.00 V
010 – 4.05 V
011 – 4.10 V
100 – 4.12 V
101 – 4.15 V
110 – 4.18 V
111 – Invalid Setting
(1) EOC Note: Maximum output current when VBAT < 3.0 V.
(2) V_TERM Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For <0°C and
>60°C, charging is disabled and a fault is set.
Specifications subject to change
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TS55001
Version 1.3
CONFIGURATION REGISTER (CONFIG3)
Address – 0x04h
DATA BIT
FIELD NAME
READ/WRITE R/W
D7
D6
D5
R/W
D4
D3
MAX_CHRG_CURR_10_45[3:0]
R/W R/W R/W
D2
D1
D0
MAX_CHRG_CURR_0_10[3:0]
R/W
R/W
R/W
FIELD NAME
MAX_CHRG_CURR_0_10[3:0](1)
BIT DEFINITION
Maximum charge current 0-10°C configuration
0000 – 50 mA
0001 – 100 mA
0010 – 200 mA
0011 – 300 mA
0100 – 400 mA
0101 – 500 mA
0110 – 600 mA
0111 – 700 mA
1000 – 800 mA
1001 – 900 mA
1010 – 1000 mA
1011 – 1100 mA
1100 – 1200 mA
1101 – 1300 mA
1110 – 1400 mA
1111 – 1500 mA
MAX_CHRG_CURR_10_45[3:0](1) Maximum charge current 10-45°C configuration
0000 – 50 mA
0001 – 100 mA
0010 – 200 mA
0011 – 300 mA
0100 – 400 mA
0101 – 500 mA
0110 – 600 mA
0111 – 700 mA
1000 – 800 mA
1001 – 900 mA
1010 – 1000 mA
1011 – 1100 mA
1100 – 1200 mA
1101 – 1300 mA
1110 – 1400 mA
1111 – 1500 mA
(1) MAX_CHRG_CURR Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For
<0°C and >60°C, charging is disabled and a fault is set.
Specifications subject to change
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TS55001
Version 1.3
CONFIGURATION REGISTER (CONFIG4)
Address – 0x05h
DATA BIT
FIELD NAME
READ/WRITE R/W
D7
D6
D5
D4
D3
MAX_CHRG_CURR_50_60[3:0]
R/W R/W R/W
D2
D1
D0
MAX_CHRG_CURR_45_50[3:0]
R/W
R/W
R/W
R/W
FIELD NAME
BIT DEFINITION
MAX_CHRG_CURR_45_50[3:0](1) Maximum charge current 45-50°C configuration
0000 – 50 mA
0001 – 100 mA
0010 – 200 mA
0011 – 300 mA
0100 – 400 mA
0101 – 500 mA
0110 – 600 mA
0111 – 700 mA
1000 – 800 mA
1001 – 900 mA
1010 – 1000 mA
1011 – 1100 mA
1100 – 1200 mA
1101 – 1300 mA
1110 – 1400 mA
1111 – 1500 mA
MAX_CHRG_CURR_50_60[3:0](1) Maximum charge current 50-60°C configuration
0000 – 50 mA
0001 – 100 mA
0010 – 200 mA
0011 – 300 mA
0100 – 400 mA
0101 – 500 mA
0110 – 600 mA
0111 – 700 mA
1000 – 800 mA
1001 – 900 mA
1010 – 1000 mA
1011 – 1100 mA
1100 – 1200 mA
1101 – 1300 mA
1110 – 1400 mA
1111 – 1500 mA
(1) MAX_CHRG_CURR Note: Unique settings available for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C. For
<0°C and >60°C, charging is disabled and a fault is set.
Specifications subject to change
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TS55001
Version 1.3
CONFIGURATION REGISTER (CONFIG5)
Address – 0x06h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
READ/WRITE R/W
TOP_END
TH
R/W
TOP_TO[2:0]
R/W
1C_TO[2:0]
R/W
R/W
R/W
R/W
R/W
FIELD NAME
TOP_END(1)
BIT DEFINITION
Top Off end configuration
0 – 25 mA
1 – 92 mA
Thermistor configuration
0 – 10k Ohms
TH(2)
1 – 100k Ohms
Top Off timer time out configuration
000 – 0 minutes
TOP_TO[2:0](3)
001 – 20 minutes
010 – 40 minutes
011 – 60 minutes
100 – 80 minutes
101 – 100 minutes
110 – 120 minutes
111 – Disable time out timer
Full charge timer time out configuration
000 – Disable full charge timer
001 – 200 minutes
1C_TO[2:0](4)
010 – 400 minutes
011 – 600 minutes
100 – 800 minutes
101 – 1000 minutes
110 – 1200 minutes
111 – 1400 minutes
(1) TOP_END Note: Charging stops when VBAT = Vtermination and IBAT < Top Off end.
(2) TH Note: Setting for nominal thermistor and reference resistor value.
(3) TOP_TO Note: Timer starts when VBAT= Vtermination and IBAT < EOC.
(4) 1C_TO Note: Timer starts when VBAT > 3.0V.
Specifications subject to change
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TS55001
Version 1.3
ENABLE CONFIGURATION REGISTER (CONFIG_ENABLE)
Address – 0x11h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
READ/WRITE
RESET VALUE
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
EN_CFG
R/W
0
FIELD NAME
BIT DEFINITION
EN_CFG
Enable access control bit for configuration registers 2-6
0 – Disable access
1 – Enable access
EEPROM CONTROL REGISTER (EEPROM_CTRL)
Address – 0x12h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
READ/WRITE
RESET VALUE
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
Not used
R
0
EE_PROG
R/W
0
FIELD NAME
EE_PROG(1)
BIT DEFINITION
EEprom program control bit for configuration registers 2-6
0 – Disable EEprom programming
1 – Enable EEprom programming with data from configuration registers 2-6
(1) EE_PROG Note: Inputs VIN and EN must be present for 200 ms.
EXTERNAL COMPONENT SELECTION
The internal compensation is optimized for a 4.7uF output capacitor and a 4.7uH inductor. To keep the output ripple low, a
low ESR (less than 35mOhm) ceramic is recommended.
Specifications subject to change
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TS55001
Version 1.3
PACKAGE MECHANICAL DRAWINGS
Specifications subject to change
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TS55001
Version 1.3
APPLICATION USING A MULTI-LAYER PCB
To maximize the efficiency of this package for application on a single layer or multi-layer PCB, certain guidelines must be
followed when laying out this part on the PCB.
The following are guidelines for mounting the exposed pad IC on a Multi-Layer PCB with ground a plane.
Solder Pad (Land Pattern)
Package Thermal Pad
Thermal Via's
Package Outline
Package and PCB Land Configuration
For a Multi-Layer PCB
JEDEC standard FR4 PCB Cross-section:
Package Solder Pad
(square)
Component Traces
1.5038 - 1.5748 mm
Component Trace
(2oz Cu)
2 Plane
1.0142 - 1.0502 mm
Ground Plane
1.5748mm
Thermal Via
(1oz Cu)
4 Plane
0.5246 - 0.5606 mm
Power Plane
Thermal Isolation
Power plane only
(1oz Cu)
0.0 - 0.071 mm Board Base
& Bottom Pad
Package Solder Pad
(bottom trace)
Multi-Layer Board (Cross-sectional View)
In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to
the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal vias,
thickness of copper, etc.
Specifications subject to change
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TS55001
Version 1.3
Mold compound
Die
Epoxy Die attach
Exposed pad
Solder
5% - 10% Cu coverage
Single Layer, 2oz Cu
Thermal Vias with Cu plating
Ground Layer, 1oz Cu
Signal Layer, 1oz Cu
Bottom Layer, 2oz Cu
90% Cu coverage
20% Cu coverage
Note: NOT to Scale
The above drawing is a representation of how the heat can be conducted away from the die using an exposed pad package. Each
application will have different requirements and limitations and therefore the user should use sufficient copper to dissipate the
power in the system. The output current rating for the linear regulators may have to be de-rated for ambient temperatures
above 85C. The de-rate value will depend on calculated worst case power dissipation and the thermal management
implementation in the application.
APPLICATION USING A SINGLE LAYER PCB
Use as much Copper Area
as possible for heat spread
Package Thermal Pad
Package Outline
Layout recommendations for a Single Layer PCB: utilize as much Copper Area for Power Management. In a single layer board
application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method
(solder paste or thermal conductive epoxy).
In both of the methods mentioned above it is advisable to use as much copper traces as possible to dissipate the heat.
IMPORTANT:
If the attachment method is NOT implemented correctly, the functionality of the product is not guaranteed. Power
dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board.
Specifications subject to change
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Copyright © 2012, Triune Systems, LLC
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TS55001
Version 1.3
Legal Notices
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. “Typical” parameters which may be provided in Triune
Systems data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for your application by your technical experts. TRIUNE SYSTEMS MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE
INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR
PURPOSE. Triune Systems disclaims all liability arising from this information and its use. Triune System products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the Triune Systems product could create a situation where personal injury or death may occur. Should the
Buyer purchase or use Triune Systems products for any such unintended or unauthorized application, the Buyer shall indemnify and hold Triune Systems,
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Triune Systems was negligent regarding the design or manufacture of the part. No licenses are conveyed, implicitly or otherwise, under any
Triune Systems intellectual property rights.
Trademarks
The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A..
All other trademarks mentioned herein are property of their respective companies.
© 2012 Triune Systems, LLC. All Rights Reserved.
Specifications subject to change
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