TS8882VF20_技术文档

Features

• Eight General Purpose Floating-point Data Registers, Each Supporting a Full 80-bit

Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit

Signed Exponent)

• A 67-bit Arithmetic Unit to Allow Very Fast Calculations With Intermediate Are

Precision Greater Than the Extended Precision Format

• A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)

• Special Purpose Hardware for High-speed Conversion Between Single, Double, and

Extended Formats and the Internal Extended Format

• An Independent State Machine to Control Main Processor Communication for

Pipelined Instruction Processing

• Forty-six Instructions, Including 35 Arithmetic Operations

• Full Conformation to the IEEE 754 Standard, Including All Requirements and

Suggestions

• Support of Functions Not Defined by the IEEE Standard, Including a Full Set of

Trigonometric and Transcendental Functions

• Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended

Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers

• Twenty-two Constants Available In The On-chip ROM, Including π, e, and Powers of 10

• Virtual Memory / Machine Operations

CMOS

Enhanced

Floating-point

Coprocessor

• Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling

• Fully Concurrent Instruction Execution with the Main Processor

• Fully Concurrent Instruction Execution of Multiple Floating-point Instructions

• Use with any host processor, on an 8-, 16- or 32-bit Data Bus

• Available in 16.67, 20, 25 and 33 MHz for T_cfrom -55°C to +125°C

• V_CC= 5V ± 10%

TS68882

Description

The TS 68882 enhanced floating-point coprocessor is a full implementation of the

IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON

TS 68000 Family of microprocessors. It is a pin and software compatible upgrade of

the TS 68881 with optimized MPU interface that provides over 1.5 times the perfor-

mance of the TS 68881. It is implemented using VLSI technology to give systems

designers the highest possible functionality in a physically small device.

Intended primarily for use as a coprocessor to the TS 68020/68030 32-bit micropro-

cessor units (MPUs), the TS 68882 provides a logical extension to the main MPU

integer data processing capabilities. It does this by providing a very high performance

floating-point arithmetic unit and a set of floating-point data registers that are utilized

in a manner that is analogous to the use of the integer data registers. The TS 68882

instruction set is a natural extension of all earlier members of the TS 68000 Family,

and supports all of the addressing modes of the host MPU. Due to the flexible bus

interface of the TS 68000 Family, the TS 68882 can be used with any of the MPU

devices of the TS 68000 Family, and it may also be used as a peripheral to non-TS

68000 processors.

Screening/Quality

This product could be manufactured

R suffix

PGA 68

Ceramic Pin Grid Array

F suffix

CQFP 68

Ceramic Quad Flat Pack

in full compliance with either:

•

MIL-STD-883 Class B

DESC 5962-89436

or According to ATMEL-

Grenoble Standards

Rev. 2119A–12/01

1

Introduction

The TS 68882 is a high performance floating-point device designed to interface with the TS

68020 or TS 68030 as a coprocessor. This device fully supports the TS 68000 virtual machine

architecture, and is implemented in HCMOS, Atmel’s low power, small geometry process. This

process allows CMOS and HMOS (high-density NMOS) gates to be combined on the same

device. CMOS structures are used where speed and low power is required, and HMOS struc-

tures are used where minimum silicon area is desired. The HCMOS technology enables the

TS 68882 to be very fast while consuming less power than comparable HMOS, and still have

a reasonably small die size.

With some performance degradation, the TS 68882 can also be used as a peripheral proces-

sor in systems where the TS 68020 or TS 68030 is not the main processor (e.g., TS 68000, TS

68010). The configuration of the TS 68882 as a peripheral processor or coprocessor may be

completely transparent to user software (e.g., the same object code may be executed in either

configuration).

The architecture of the TS 68882 appears to the user as a logical extension of the TS 68000

Family architecture. Coupling of the coprocessor interface allows the TS 68020/TS 68030 pro-

grammer to view the TS 68882 registers as though the registers are resident in the TS

68020/TS 68030. Thus, a TS 68020 or TS 68030/TS 68882 device pair appears to be one pro-

cessor that supports seven floating-point and integer data types, and has eight integer data

registers, eight address registers, and eight floating-point data registers.

As shown in Figure 1, the TS 68882 is internally divided into four processing elements; the bus

interface unit (BIU), the conversion control unit (CCU), the execution control unit (ECU), and

the microcode control unit (MCU). The BIU communicates with the main processor, the CCU

controls the main processor communications dialog and performs some data conversions, and

the ECU and MCU execute most floating-point calculations.

The BIU contains the coprocessor interface registers, and the 32-bit control, and instruction

address registers. In addition to these registers, the register select and DSACK timing control

logic is contained in the BIU. Finally, the status flags used to monitor the status of communica-

tions with the main processor are contained in the BIU.

The CCU contains special purpose hardware that performs conversions between the single,

double, and extended precision memory data formula and the internal data format used by the

ECU. It also contains a state machine that controls communications with the main processor

during coprocessor interface dialogs.

The eight 80-bit floating-point data registers (FP0-FP7) are located in the ECU. In addition to

these registers, the ECU contains a high-speed 67-bit arithmetic unit used for both mantissa

and exponent calculations, a barrel shifter that can shift from 1 bit to 67 bits in one machine

cycle, and ROM constants (for use by the internal algorithms or user programs).

The MCU contains the clock generator, a two-level microcoded sequencer that controls the

ECU, the microcode ROM, and self-test circuitry. The built-in self-test capabilities of the TS

68882 enhance reliability and ease manufacturing requirements; however, these diagnostic

functions are not available to the user.

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TS68882

Figure 1. TS 68882 Simplified Block

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2119A–12/01

Figure 2. PGA Terminal Designation

Assignments

* Reserved for future ATMEL-Grenoble use

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TS68882

Figure 2b. CQFP Terminal Designation

Functional Signal

Descriptions

This section contains a brief description of the input and output signals for the TS 68882 float-

ing-point coprocessor. The signals are functionally organized into groups as shown in Figure

3.

Figure 3. TS 68882 Input/output Signals

Note:

The terms assertion and negation are used extensively. This is done to avoid confusion when

describing “active-low” and “active-high” signals. The term assert or assertion is used to indicate

that a signal is active or true, independent of whether that level is represented by a high or low

voltage. The term negate or negation is used to indicate that a signal is inactive or false.

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Signal Summary

Table 1 provides a summary of all the TS 68882 signals described in this section.

Table 1. Signal Summary

Signal Name

Address Bus

Data Bus

Mnemonic

Input/Output

Input

Active State

High

Three State

A0-A4

D0-D31

Input/Output

Input

High

Yes

Size

SIZE

Low

Address Strobe

Chip Select

AS

Input

Low

CS

Input

Low

Read/Write

R/W

DS

Input

High/Low

Low

Data Strobe

Input

Data Transfer and Size Acknowledge

Reset

DSACK0, DSACK1

RESET

CLK

Output

Input

Low

Yes

No

Low

Clock

Input

Sense Device

Power Input

SENSE

V_CC

Input/Output

Input

Low

Ground

GND

Input

Detailed

Specifications

Scope

This drawing describes the specific requirements for the microprocessor 68882, 16.67, 20

MHz and 25 MHz, in compliance with MIL-STD-883 class B.

Applicable

Documents

MIL-STD-883

1. MIL-STD-883: Test Methods And Procedures For Electronics.

2. MIL-PRF-38535 Appendix A: General Specifications For Microcircuits

3. Desc Drawing 5962 - 89436xxx

Requirements

General

The microcircuits are in accordance with the applicable document and as specified herein.

Design and

Construction

Terminal Connections

Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure

2b

Lead Material and

Finish

Lead material and finish shall be any option of MIL-STD-1835.

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TS68882

Package

The macrocircuits are packaged in hermetically sealed ceramic packages which are conform

to case outlines of MIL-STD-1835 (when defined):

•

68-PIN SQ.PGA UP PAE Outline

68-PIN Ceramic Quad Flat Pack CQFP

The precise case outlines are described on Figure 23 and Figure 24.

Electrical

Characteristics

Table 2. Absolute Maximum Ratings

Symbol

V_CC

Parameter

Test Conditions

Min

-0.3

Max

+7.0

0.75

+125

+85

Unit

V

Supply Voltage

Input Voltage

V_I

V

P_dmax

Max Power Dissipation

T_case= -55°C to +125°C

M Suffix

W

-55

-40

-55

°C

T_case

Operating Temperature

V Suffix

T_stg

Storage Temperature

Lead Temperature

+150

+270

T_leads

Max 5 sec. Soldering

Recommended

Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1.).

Condition of Use

Table 3. DC Electrical Characteristics

_CC= 5.0 V_dc± 10%; GND = 0 V_dc; Tc = -55°C to +125°C

V

Symbol

V_CC

T_case

V_IH

Parameter

Min

4.5

Max

5.5

Unit

V

Supply Voltage

Operating Temperature

-55

+125

V_CC

0.8

°C

V

Input High Voltage

2.0

V_IL

Input Low Voltage

GND - 0.3

V

I_IN

Input Leakage Current @ 5.5V CLK, RESET, R/W, A0-A4, CS, DS, AS, SIZE

HI-Z (Off state) Input Current @ 2.4V/0.4V DSACK0, DSACK1, D0-D31

Output High Voltage (IOH = -400 µA)⁽¹⁾DSACK0, DSACK1, D0-D31

Output Low Voltage (IOL = 5.3 mA)⁽¹⁾DSACK0, DSACK1, D0-D31

Output Low Current (VOL = GND) SENSE

Power Dissipation

10

µA

V

I_TSI

20

V_OH

V_OL

I_OL

2.4

0.5

500

0.75

20

V

µA

W

pF

P_D

C_in

Capacitance (V_IN= 0, T_A= 25°C, f = 1 MHz)⁽²⁾

C_L

Output Load Capacitance

130

Notes: 1. Test load, see Figure 5.

2. Capacitance is periodically sampled rather than 100% tested.

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Thermal

Characteristics

Table 4.

Package

Symbol

θ_JA

Parameter

Value

33

4

Rating

°C/W

Thermal Resistance - Ceramic Junction To Ambient

Thermal Resistance - Ceramic Junction To Case

Thermal Resistance - Ceramic Junction To Ambient

Thermal Resistance - Ceramic Junction To Case

PGA 68

θ_JC

θ_JA

33

3

CQFP

θ_JC

Power

The average chip-junction temperature, T_J,in °C can be obtained from:

Considerations

T_J= T_A+ (P_D+ θ_JA)

(1)

T_A= Ambient Temperature, °C

θ_JA= Package Thermal Resistance, Junction-to-Ambient, °C/W

P_D= P_INT+ P_I/O

P_INT= I_CCx V_CC,Watts - Chip Internal Power

P

_I/O= Power Dissipation on Input and Output Pins - User Determined

For most applications P_I/O< P_INTand can be neglected.

An Approximate relationship between P_Dand T_J(if P_I/Ois neglected) is:

P_D= K: (T_J+ 273)

(2)

Solving equations (1) and (2) for K gives

2

K = P_D. (T_A+ 273) + θ_JA· P_D

(3)

where K is constant pertaining to the particular part K can be determined from the equation (3)

by measuring PD (at equilibrium) for a known T_A. Using this value of K, the values of P_Dand T_J

can be obtained by solving equations (1) and (2) iteratively for any value of T_A.

The total thermal resistance of a package (θ_JA) can be separated into two components, θ_JC

and θ_CA, representing the barrier to heat flow from the semiconductor junction to the package

(case), surface (θ_JC) and from the case to the outside ambient (θ_CA). These terms are related

by the equation:

θ_JA= θ_JC+ θ_CA

(4)

θ

_JAis device related and cannot be influenced by the user. However, θ_CAis user dependent

and can be minimized by such thermal management techniques as heat sinks, ambient air

cooling and thermal convection. Thus, good thermal management on the part of the user can

significantly reduce θ_CAso that θ_JAapproximately equals θ_JC.Substitution of θ_JCfor θ_JAin

equation (1) will result in a lower semiconductor junction temperature.

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TS68882

Mechanical and

Environment

The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-

883 for class B devices.

Marking

The document where are defined the marking are identified in the related reference docu-

ments. Each microcircuit are legible and permanently marked with the following information as

minimum:

•

Atmel-Grenoble Logo

Manufacturer’s Part Number

Class B Identification

Date-code of inspection lot

ESD Identifier if Available

Country of Manufacturing

Quality

Conformance

Inspection

DESC/MIL-STD-883

Is in accordance with MIL-M-38510 and method 5005 of MIL-STD-883. Group A and B inspec-

tions are performed on each production lot. Group C and D inspection are performed on a

periodical basis.

Electrical

Characteristics

General

Requirements

All static and dynamic electrical characteristics specified and the relevant measurement condi-

tions are given below. For inspection purpose, refer to relevant specification:

Static electrical characteristics for all electrical variants.

Dynamic electrical characteristics for 68882-16 (16.67 MHz), 68882-20 (20 MHz), 68882-25

(25 MHz) and 68882-33 (33 MHz).

For static characteristics, test methods refer to clause 5.4.1 hereafter of this specification

(Table 5).

For dynamic characteristics (Tables 6 and 7), test methods refer to IEC 748-2 method number,

where existing.

Table 5. Static Characteristics

_CC= 5.0 V_dc± 10%; GND = 0 V_dc; Tc = -55/+125°C or -40/+85°C

V

Symbol

V_IH

Parameter

Min

2.0

Max

V_CC

0.8

10

Unit

V

Input High Voltage

V_IL

Input Low Voltage

GND - 0.3

V

I_IN

Input Leakage Current @ 5.5V CLK, RESET, R/W, A0-A4, CS, DS, AS, SIZE

HI-Z (off state) Input Current @ 2.4V/0.4V DSACK0, DSACK1, D0-D31

Output High Voltage (I_OH= -400 µA)⁽¹⁾DSACK0, DSACK1, D0-D31

Output Low Voltage (I_OL= 5.3 mA)⁽¹⁾DSACK0, DSACK1, D0-D31

µA

V

I_TSI

20

V_OH

V_OL

2.4

0.5

V

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2119A–12/01

Table 5. Static Characteristics

_CC= 5.0 V_dc± 10%; GND = 0 V_dc; Tc = -55/+125°C or -40/+85°C

V

Symbol

I_OL

Parameter

Min

Max

500

136

20

Unit

µA

Output Low Current (V_OL= GND) SENSE

Maximum Supply Current (V_CC= 5.5V; CLK = f_max; part in Reset)

Capacitance (V_IN= 0, T_A= 25°C, f = 1MHz)⁽²⁾

Output Load Capacitance

I_CC

mA

pF

C_in

C_L

130

pF

Notes: 1. Test load, see Figure 5.

2. Capacitance is periodically sampled rather than 100% tested.

Dynamic

(Switching)

Characteristics

The limits and values given in this section apply over the full case temperature range -55°C to

+125°C and V_CCin the range 4.5V to 5.5V, see § 5.4.2.

The numbers (N°) refer to the timing diagrams. See Figure 4, Figure 6, Figure 7, Figure 8 and

Figure 9..

Table 6. AC Electrical Characteristics - Clock Input

_CC= 5.0 V_dc± 10%; GND = 0 V_dc;Tc = -55°C to +125°C (see Figure 4)

V

16.67 MHz 20 MHz

Min Max

25 MHz

Min

33.33 MHz

N°

Parameter

Min

12.5

50

Max

20

80

54

5

Max

25

80

59

4

Min

Max

33.33

60

Unit

MHz

ns

Frequency of Operation

Clck Time

8

16.67

125

95

12.5

40

16.7

30

1

60

24

2, 3 Clock Pulse Width

4, 5 Rise and Fall Times

20

15

14

66

ns

5

3

ns

Figure 4. Clock Input Timing Diagram

Note:

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage

of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside,

and pass through, the range such that the rise of fall will be linear between 0.8 volts and 2.0

volts.

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TS68882

Table 7. AC Electrical Characteristics - Read and Write Cycles

_CC= 5.0 V_dc± 10%; GND = 0 V_dc;Tc = -55°C/+125°C or Tc = -40°C/+85°C (see Figure 7, Figure 8, Figure 9)

V

16.67 MHz 20 MHz 25 MHz 33.33 MHz

N°

6

Parameter

Min

15

50

10

Max

Min

Max

Min

Max

Min

5

Max

Unit

ns

Address valid to AS asserted⁽⁵⁾

Address valid to DS asserted (read)⁽⁵⁾

Address valid to DS asserted (write)⁽⁵⁾

AS negated to address invalid⁽⁶⁾

DS negated to address invalid⁽⁶⁾

10

50

10

5

6a

6b

7

5

ns

35

5

26

5

ns

7a

5

ns

CS asserted to AS asserted or AS asserted

to CS asserted⁽⁹⁾

8

0

ns

CS asserted to DS asserted or DS asserted

to CS asserted (read)⁽⁹⁾

8a

8b

CS asserted to DS asserted or DS asserted

to CS asserted (write)⁽⁹⁾

30

25

20

15

9

AS negated to CS negated

DS negated to CS negated

R/W high to AS asserted (read)

R/W high to DS asserted (read)

R/W low to DS asserted (write)

10

15

35

10

30

5

ns

9a

10

5

10a

10b

5

25

AS negated to R/W low (read) or

AS negated to R/W high (write)

11

10

5

ns

DS negated to R/W low (read) or

DS negated to R/W high (write)

11a

12

13

DS width asserted (write)

40

30

38

30

25

23

18

ns

DS width negated

13a

14

DS negated to AS asserted⁽⁴⁾

CS, DS asserted to data-out valid (read)⁽²⁾

DS negated to data-out invalid (read)

80

50

45

35

45

35

30

15

0

DS negated to data-out high impedance

(read)

16

ns

17

18

Data-in invalid to DS asserted (write)

DS negated to data-in invalid (write)

15

10

5

ns

START true to DSACK0 and DSACK1

asserted⁽²⁾

19

19a

20

50

15

50

35

10

43

30

25

10

32

40

20

5

ns

DSACK0 asserted to DSACK1 asserted

(skew)⁽⁷⁾

-15

-10

DSACK0 or DSACK1 asserted to data-out

valid

17

30

START false to DSACK0 and DSACK1

negated⁽⁸⁾

21

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Table 7. AC Electrical Characteristics - Read and Write Cycles

_CC= 5.0 V_dc± 10%; GND = 0 V_dc;Tc = -55°C/+125°C or Tc = -40°C/+85°C (see Figure 7, Figure 8, Figure 9)

V

16.67 MHz 20 MHz 25 MHz 33.33 MHz

N°

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

START false to DSACK0 and DSACK1

high impedance⁽⁸⁾

22

70

55

40

ns

START true to clock high (synchronous

read)⁽³⁾⁽⁸⁾

23

24

25

26

27

0

ns

Clock low to data-out valid synchronous

read)⁽³⁾

105

80

60

45

START true to data-out valid (synchronous

read)⁽³⁾⁽⁸⁾

0

1.5

105+

2.5

80 +

2.5

60+

2.5

45-

2.5

ns

Clks

1.5

Clock low to DSACK0 and DSACK1

asserted (synchronous read⁽³⁾

75

55

45

30

ns

START true to DSACK0 and DSACK1

asserted (synchronous read) ⁽³⁾⁽⁸⁾

75+

2.5

55+

2.5

45+

2.5

30-

2.5

ns

Clks

1.5

Notes: 1. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise

noted. The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will

be linear between 0.8 volts and 2.0 volts.

2. These specifications only apply if the TS 68882 has completed all internal operations initiated by the termination of the pre-

vious bus cycle when DS was negated.

3. Synchronous read cycles occur only when the save or response CIR locations are read.

4. This specification only applies to systems in which back-to-back accesses (read-write or write-write) of the operand CIR can

occur. When the TS 68882 is used as a coprocessor to the TS 68020/68030, this can occur when the addressing mode is

immediate.

5. If the SIZE pin is not strapped to either V_CCor GND, it must have the same setup times as do addresses.

6. If the SIZE pin is not strapped to either V_CCor GND, it must have the same hold times as do addresses.

7. This number is reduced to 5 nanoseconds if DSACK0 and DSACK1 have equal loads.

8. START is not an external signal; rather, it is the logical condition that indicates the start of an access. The logical equation

for this condition is START = CS + AS + (R/W · DS).

9. If a subsequent access is not a FPCP access, CS must be negated before the assertion of AS and/or DS on the non-FPCP

access. These specifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transi-

tions in CS must not occur simultaneously with transitions of AS or DS. This is not a requirement of the TS 68882).

Test Conditions

Specific to the

Device

Test Load

The applicable loading network shall be as defined in column “Test conditions” of Table 2,

referring to the loading network number as shown in Figure 5.

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Figure 5. Test Loads

AC Electrical

Specification

Definitions

The AC specifications presented consist of output delays, input setup and hold times, and sig-

nal skew times. All signals are specified relative to an appropriate edge of the clock input and,

possibly, relative to one or more other signals.

The measurement of the AC specifications is defined by the waveforms shown in Figure 6. In

order to test the parameters guaranteed inputs must be driven to the voltage levels specified

in Figure 6. Outputs are specified with minimum and/or maximum limits, as appropriate, and

are measured as shown. Inputs are specified with minimum and, an appropriate maximum

setup and hold times, and are measured as shown. Finally, the measurement for signal-to-sig-

nal specifications are also shown.

Note that the testing levels used to verify conformance to the AC specifications does not affect

the guaranteed DC operation of the device specified in the DC electrical characteristics.

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Figure 6. Drive Levels and Test Points for AC Specifications

Legend

A) Maximum output delay specification.

B) Minimum output hold time.

C) Minimum input setup time specification.

D) Minimum input hold time specification.

E) Signal valid to signal valid specification (maximum or minimum).

F) Signal valid to signal invalid specification (maximum or minimum).

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Notes: 1. This output timing is applicable to all parameters specified relative to the rising edge of the

clock.

2. This output timing is applicable to all parameters specified relative to the falling edge of the

clock.

3. This input timing is applicable to all parameters specified relative to the rising edge of the

clock.

4. This input timing is applicable to all parameters specified relative to the falling edge of the

clock.

5. This timing is applicable to all parameters specified relative to the assertion/negation of

another signal.

Figure 7. Asynchronous Read Cycle Timing Diagram

Note:

START is actually a logical condition, but is shown as an active signal for clarity. The

logical equation for this signal is: START = CS + AS + (R/W · DS).

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Figure 8. Asynchronous Write Cycle Timing Diagram

Note:

START is actually a logical condition, but is shown as an active signal for clarity. The logical equation for this signal is: START =

CS + AS + (R/W · DS).

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TS68882

Figure 9. Synchronous Read Cycle Timing Diagram

Note:

START is actually a logical condition, but is shown as an active signal for clarity. The logical

equation for this signal is: START = CS + AS + (R/W · DS).

Additional

Additional information shall not be for any inspection purposes.

Information

Capacitance (Not for Inspection Purposes)

Symbol Parameter

Test Conditions

Vin = 0 T_amb= 25°C

f = 1 MHz

Min

Max

Unit

C_in

Input Capacitance

20

pF

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2119A–12/01

Functional

Description

The Coprocessor

Concept

The TS 68882 functions as a coprocessor in systems where the TS 68020 or TS 68030 is the

main processor via the TS 68000 coprocessor interface. It functions as a peripheral processor

in systems where the main processor is the TS 68000, TS 68010.

The TS 68882 utilizes the TS 68000 Family coprocessor interface to provide extension of the

TS 68020 /TS 68030 registers and instruction set in a manner which is transparent to the pro-

grammer. The programmer perceives the MPU/FPCP execution model as if both devices are

implemented on one chip.

A fundamental goal of the TS 68000 Family coprocessor interface is to provide the program-

mer with an execution model based upon sequential instruction execution by the TS 68020/TS

68030 and the TS 68882. For optimum performance, however, the coprocessor interface

allows concurrent operations in the TS 68882 with respect to the TS 68020/TS 68030 when-

ever possible. In order to simplify the programmer’s model, the coprocessor interface is

designed to emulate, as closely as possible, non-concurrent operation between the TS

68020/TS 68030 and the TS 68882.

The TS 68882 is s non-DMA type coprocessor which uses a subset of the general purpose

coprocessor interface supported by the TS 68020/TS 68030. Features of the interface imple-

mented in the TS 68882 are as follows:

•

The main processor(s) and TS 68882 communicate via standard TS 68000 bus cycles

The main processor(s) and TS 68882 communications are not dependent upon the

instruction sets or internal details of the individual devices (e.g., instruction pipes or

caches, addressing modes)

•

The main processor(s) and TS 68882 may operate at different clock speeds

TS 68882 instructions utilize all addressing modes provided by the main processor; all

effective addresses are calculated by the main processor at the request of the

coprocessor

•

All data transfers are performed by the main processor at the request of the TS 68882;

thus memory management, bus errors, address errors, and bus arbitration function as if

the TS 68882 instructions are executed by the main processor

•

Overlapped (concurrent) instruction execution enhances throughput while maintaining the

programmer’s model of sequential instruction execution

Coprocessor detection of exceptions which require a trap to be taken are serviced by the

main processor at the request of the TS 68882 thus exception processing functions as if

the TS 68882 instructions were executed by the main processor

•

Support of virtual memory/virtual machine systems is provided via the FSAVE and

FRESTORE instructions

Up to eight coprocessors may reside in a system simultaneously: multiple coprocessors of

the same type are also allowed

Systems may use software emulation of the TS 68882 without reassembling or relinking

user software

The TS 68882 programming model is shown in Figure 10 through 15, and consists of the

following:

Eight 80-bit floating-point data registers (FP0-FP7). These registers are analogous to the

integer data registers (D0-D7) and are completely general purpose (i.e., any instruction

may use any register)

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•

A 32-bit control register that contains enable bits for each class of exceptions trap, and

mode bits to set the user-selectable rounding and precision modes

A 32-bit status register that contains floating-point condition codes, quotient bits, and

exception status information

A 32-bit instruction address register that contains the main processor memory address of

the last floating-point instruction that was executed. This address is used in exception

handling to locate the instruction that caused the exception

The connection between the TS 68020/TS 68030 and the TS 68882 is a simple extension of

the TS 68000 bus interface. The TS 68882 is connected as a coprocessor to the TS 68020/TS

68030, and the selection of the TS 68882 is based upon a chip select (CS), which is decoded

from the TS 68020/TS 68030 function codes and address bus. Figure 16 illustrates the TS

68882/TS 68020 or TS 68030 configuration.

Figure 10. TS 68882 Programming Model

Figure 11. Exception Status/enable Byte

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2119A–12/01

Figure 12. Mode Control Byte

7

6

2

5

4

3

1

0

RND

PREC

ROUNDING MODE:

00 TO NEAREST

01 TOWARD ZERO

10 TOWARD MINUS INFINITY

11 TOWARD PLUS INFINITY

ROUNDING PRECISION:

00 extended

01 SINGLE

10 DOUBLE

11 (UNDEFINED RESERVED)

Figure 13. Condition Code Byte

Figure 14. Quotient Byte

Figure 15. Accrued Exception Byte

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Figure 16. Typical Coprocessor Configuration

Bus Interface Unit

All communications between the TS 68020/TS 68030 and the TS 68882 occur via standard TS

68000 Family bus transfers. The TS 68882 is designed to operate on 8-, 16-, or 32-bit data

buses.

The TS 68882 contains a number of coprocessor interface registers (CIRs) which are

addresses in the same manner as memory by the main processor. The TS 68000 Family

coprocessor interface is implemented via a protocol of reading and writing to these registers

by the main processor. The TS 68020 and TS 68030 implements this general purpose copro-

cessor interface protocol in hardware and microcode.

When the TS 68020/TS 68030 detects a typical TS 68882 instruction, the MPU writes the

instruction to the memory-mapped command CIR, and reads the response CIR. In this

response, the BIU encodes requests for any additional action required of the MPU on behalf of

the TS 68882. For example, the response may request that the MPU fetch an operand from

the evaluated effective address and transfer the operand to the operated CIR. Once the MPU

fulfills the coprocessor request(s), it is free to fetch and execute subsequent instructions.

A key concern in a coprocessor interface that allows concurrent instruction execution is syn-

chronization during main processor and coprocessor communication. If a subsequent

instruction is written to the TS 68882 before the CCU has passed the operands for the previ-

ous instructions to the ECU, the response instructs the TS 68020/TS 68030 to wait. Thus, the

choice of concurrent or nonconcurrent instruction execution is determined on an instruction-

by-instruction basis by the coprocessor.

The only difference between a coprocessor bus transfer and any other bus transfer is that the

TS 68020/TS 68030 issues a function code to indicate the CPU address space during the

cycle (the function codes are generated by the TS 68000 Family processors to identify eight

separate address spaces). Thus, the memory-mapped coprocessor interface registers do not

infringe upon instruction or data address spaces. The TS 68020/TS 68030 places a coproces-

sor ID field from the coprocessor instruction onto three of the upper address lines during

coprocessor accesses. This ID, along with the CPU address space function code, is decoded

to select one of eight coprocessors in the system.

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Since the coprocessor interface protocol is based solely on bus transfers, the protocol is easily

emulated by software when the TS 68882 is used as a peripheral with any processor capable

of memory-mapped I/O over on TS 68000 style bus. When used as a peripheral processor

with the 8-bit TS 68008 or the 16-bit TS 68000, or TS 68010, all TS 68882 instructions are

trapped by the main processor to an exception handler at execution time. Thus, the software

emulation of the processor interface protocol can be totally transparent to the user. The sys-

tem can be quickly upgraded by replacing the main processor with an TS 68020/TS 68030

without changes to the user software.

Since the bus is asynchronous, the TS 68882 need not run at the same clock speed as the

main processor. Total system performance may therefore be customized. For example, a sys-

tem requiring very fast floating-point arithmetic with relatively slow integer arithmetic can be

designed with an inexpensive main processor and a fast TS 68882.

Coprocessor

Interface

The TS 68000 Family coprocessor interface is an integral part of the TS 68882 and TS

68020/TS 68030 designs, with the interface tasks shared between the two. The interface is

fully compatible with all present and future TS 68000 Family products. Tasks are partitioned

such that the TS 68020/TS 68030 does not have to decode coprocessor instructions and, the

TS 68882 does not have to duplicate main processor functions such as effective address

evaluation.

This partitioning provides an orthogonal extension of the instruction set by permitting TS

68882 instructions to utilize all TS 68020/TS 68030 addressing modes and to generate execu-

tion time exception traps. Thus, from the programmer’s view, the CPU and coprocessor

appear to be integrated onto a single chip. While the execution of the majority of TS 68882

instructions may be overlapped with the execution of TS 68020/TS 68030 instructions, concur-

rency is completely transparent to the programmer. The TS 68020/TS 68030 single-step and

program flow (trace) modes are fully supported by the TS 68882 and the TS 68000 Family

coprocessor interface.

While the TS 68000 Family coprocessor interface permits coprocessors to be bus masters,

the TS 68882 is never a bus master. The TS 68882 requests that the TS 68020/TS 68030

fetch all operands and store all results. In this manner, the TS 68020/TS 68030 32-bit data bus

provides high speed transfer of floating-point operands and results while simplifying the design

of the TS 68882.

Since the coprocessor interface is based solely upon bus cycles and the TS 68882 is never a

bus master, the TS 68882 can be placed on either the logical or physical side of the system

memory management unit. This provides a great deal of flexibility in the system design.

The virtual machine architecture of the TS 68000 Family is supported by the coprocessor

interface and the TS 68882 through the FSAVE and FRESTORE instructions. If the TS

68020/TS 68030 detects a page fault and/or task time out, it can force the TS 68882 to stop

whatever operation is in process at any time (even in the middle of the execution of an instruc-

tion) and save the TS 68882 internal state in memory.

The size of the saved internal state of the TS 68882 is dependent upon what the CCU and

ECU are doing at the time that the FSAVE is executed. If the TS 68882 is in the reset state

when the FSAVE instruction is received, only one word of state is transferred to memory,

which may be examined by the operating system to determine that the coprocessor program-

mer’s model is empty. If the coprocessor is idle when the save instruction is received, only a

few words of internal state are transferred to memory. If the TS 68882 is in the middle of per-

forming a calculation, it may be necessary to save the entire internal state of the machine.

Instructions that can complete execution in less time than it would take to save the larger state

in mid-instruction are allowed to complete execution and then save the idle state.

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Thus the size of the saved internal state is kept to a minimum. The ability to utilize several

internal state sizes greatly reduces the average context switching time.

The FRESTORE instruction permits reloading of an internal state that was saved earlier, and

continue any operation that was previously suspended. Restoring of the reset internal state

functions just like a hardware reset to the TS 68882 in that defaults are re-established.

Note:

Though the TS 68882 is instruction set compatible with the TS 68881, the idle and busy state

frames are both 32 bytes larger on the TS 68882 than on the TS 68881. A unique format word is

generated by the TS 68882 so that system software can detect this difference.

Operand Data

Formats

The TS 68882 supports the following data formats:

•

Byte Integer (B)

Word Integer (W)

Long Word Integer (L)

Single Precision Real (S)

Double Precision Real (D)

Extended Precision Real (X)

Packed Decimal String Real (P)

The capital letters contained in parenthesis denote suffixes added to instructions in the

assembly language source to specify the data format to be used.

Integer Data

Formats

The three Integer data formats (byte, word, and long word) are the standard data formats sup-

ported in the TS 68000 Family architecture. Whenever an integer is used in a floating-point

operation, the integer is automatically converted by the TS 68882 to an extended precision

floating-point number before being used. For example, to add an integer constant of five to the

number contained in floating-point data register 3 (FP3), the following instruction can be used:

FADD.W #5.FP3

The ability to effectively use integers in floating-point operations saves user memory since an

integer representation of a number, if representable, is usually smaller than the equivalent

floating-point representation.

Floating-point

Data Formats

The floating-point data formats single precision (32-bits) and double precision (64-bits) are as

defined by the IEEE standard. These are the main floating-point formats and should be used

for most calculations involving real numbers. Table 8 lists the exponent and mantissa size for

single, double, and extended precision. The exponent is biased, and the mantissa is in sign

and magnitude form. Since single and double precision require normalized numbers, the most

significant bit of the mantissa is implied as one and is not included, thus giving one extra bit of

precision.

Table 8. Exponent and Mantissa Sizes

Exponent

Bits

Mantissa

Bits

Data Format

Single

Bias

127

8

23 (+1)

52 (+1)

64

Double

11

15

1023

16383

Extended

The extended precision data format is also in conformance with the IEEE standard, but the

standard does not specify this format to the bit level as it does for single and double precision.

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The memory format on the TS 68882 consists of 96 bits (three long words). Only 80 bits are

actually used, the other 16 bits are for future expandability and for long-word alignment of

floating-point data structures. Extended format has a 15-bit exponent, a 64-bit mantissa, and a

1-bit mantissa sign.

Extended precision numbers are intended for use as temporary variables, intermediate val-

ues, or in places where extra precision is needed. For example, a compiler might select

extended precision arithmetic for evaluation of the right side of an equation with mixed sized

data and then convert the answer to the data type on the left side of the equation. It is antici-

pated that extended precision data will not be stored in large arrays, due to the amount of

memory required by each number.

Packed Decimal

String Real Data

Format

The packed decimal string data format allows packed BCD strings to be input to and output

from the TS 68882. The strings consist of a 3-digit base 10 exponent and a 17-digit base 10

mantissa. Both the exponent and mantissa have a separate sign bit. All digits are packed

BCD, such that an entire string fits in 96 bits (three long words). As is the case with all data for-

mats, when packed BCD strings are input to the TS 68882, the strings are automatically

converted to extended precision real values. This allows packed BCD numbers to be used as

inputs to any operation. For example:

FADD.P # - 6.023E + 24, FP5

BCD numbers can be output from the TS 68882 in a format readily used for printing by a pro-

gram generated by a high-level language compiler. For example:

FMOVE.P FP3.BUFFER (# -5)

instructs the TS 68882 to convert the floating-point data register 3 (FP3) contents into a

packed BCD string with five digits to the right of the decimal point (FORTRAN F format).

Data Format

Summary

All data formats described above are supported orthogonally by all arithmetic and transcen-

dental operations, and by all appropriate TS 68000 Family addressing modes. For example,

all of the following are legal instructions:

FADD.B

FADD.W

FADD.L

FADD.S

FADD.D

FADD.X

FADD.P

# 3.FP0

D2.FP3

BIGINT.FP7

# 3.14159.FP5

(SP) + .FP6

[(TEMP -PTR.A7)].FP3

# 1.23E25.FP0

On-chip calculations are performed to extended precision format, and the eight floating-point

data registers always contain extended precision values. All data used in an operation is con-

verted to extended precision by the TS 68882 before the specific operation is performed, and

all results are in extended precision. This ensures accuracy without sacrificing performance.

Refer to Figure 17 for a summary of the memory formats for the seven data formats supported

by the TS 68882.

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Figure 17. TS 68882 Data Format Summary

Instruction Set

The TS 68882 instruction set is organized into six major classes:

1. Moves Between The TS 68882 and Memory or The MPU (In and Out)

2. Move Multiple Registers (In and Out)

3. Monadic Operations

4. Dyadic Operations

5. Branch, Set, or Trap Conditionally, and

6. Miscellaneous

Moves

All moves from memory (or from an MPU data register) to the TS 68882, cause data conver-

sion from the source data format to the internal extended precision format.

All moves from the TS 68882 to memory (or to an MPU data register), cause data conversion

from the internal extended precision format to the destination data format.

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Note that data movement instructions perform arithmetic operations, since the result is always

rounded to the precision selected in the FPCR mode control byte. The result is rounded using

the selected rounding mode, and is checked for overflow and underflow.

The syntax for the move is:

FMOVE.(fmt)

FMOVE.X

(ea).FPn

FPm.(ea)

FPm.FPn

Move to TS 68882

Move from TS 68882

Move within TS 68882

where:

(ea) is an TS 68000 Family effective address operand and (fmt) is the data format size. FPm

and FPn are floating-point data registers.

Move Multiples

The floating-point move multiple instructions on the TS 68882 are much like the integer coun-

terparts on the TS 68000 Family processors. Any set of the floating-point registers FP0

through FP7 can be moved to or from memory with one instruction. These registers are

always moved as 96-bit extended data with no conversion (hence no possibility of conversion

errors). Some move multiple examples are as follows:

FMOVEM

(ea), FP0-FP3/FP7

FMOVEM

FP2/FP4/FP6,(ea)

Move multiples are useful during context switches and interrupts to save or restore the state of

a program. These moves are also useful at the start and end of a procedure to save and

restore the calling routine’s register set. In order to reduce procedure call overhead, the list of

registers to be saved or restored can be contained in a data register. This allows run-time opti-

mization by allowing a called routine to save as few registers as possible. Note that no

rounding or overflow/underflow checking is performed by these operations.

Monadic

Operations

Monadic operations have one operand. This operand may be in a floating-point data register,

memory, or in an MPU data register. The result is always stored in a floating-point data regis-

ter. For example, the syntax for square root is:

FSQRT.(fmt)

FSQRT.X

(ea), FPN or,

FPm, FPn or,

FPn

FSQRT.X

The TS 68882 monadic operations available are as follows:

FABS

Absolute Value

Arc Cosine

FACOS

FASIN

Arc Sine

FATAN

FATANH

FCOS

Arc Tangent

Hyperbolic Arc Tangent

Cosine

FCOSH

FETOX

FETOXM1

Hyperbolic Cosine

e to the x Power

e to the x Power - 1

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FABS

Absolute Value

Arc Cosine

FACOS

FGETEXP

FGETMAN

FINT

Get Exponent

Get Mantissa

Integer Part

FINTRZ

FLOG10

FLOG2

FLOGN

FLOGNP

FNEG

Integer Part (Truncated)

Log Base 10

Log Base 2

Log Base e

Log Base e of(x + 1)

Negate

FSIN

Sine

FSINCOS

FSINH

Simultaneous Sine and Cosine

Hyperbolic Sine

Square Root

FSQRT

FTAN

Tangent

FTANH

FTENTOX

FTST

Hyperbolic Tangent

10 to the x Power

test

FTWOTOX

2 to the x Power

Dyadic Operations

Dyadic operations have two input operands. The first input operand comes from a floating-

point data register, memory, or MPU data register. The second input operand comes from a

floating-point data register. The destination is the same floating-point data register used for the

second input. For example, the syntax for add is:

FADD.(fmt)

(ea).FPnor,

FADD.X

FPm.FPn

The TS 68882 dyadic operations available are as follows:

FADD

Add

FCMP

Compare

FDIV

Divide

FMOD

FMUL

Modulo Remainder

Multiply

FREM

IEEE Remainder

Scale Exponent

Single Precision Divide

Single Precision Multiply

Subtract

FSCALE

FSGLDIV

FSGLMUL

FSUB

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Branch, Set, and

Trap-on Condition

The floating-point branch, set, and trap-on condition instructions implemented by the TS

68882 are similar to the equivalent integer instructions of the TS 68000 Family processors,

except that more conditions exist due to the special values in IEEE floating-point arithmetic.

When a conditional instruction is executed, the TS 68882 performs the necessary condition

checking and tells the MPU whether the condition is true or false; the MPU then takes the

appropriate action. Since the TS 68882 and TS 68020/TS 68030 are closely coupled, the float-

ing-point branch operations executed by the pair are very fast.

The TS 68882 conditional operations are:

FBcc

FDBcc

FScc

Branch

Decrement and Branch

Set Byte According to Condition

Trap-on Condition (with an Optional

Parameter)

FTRAPcc

where:

cc is one of the 32 floating-point conditional test specifiers as shown in Table 9.

rs

Table 9. Floating-point Conditional Test Specifiers

Mnemonic Definition

Note: The following conditional tests do not set the BSUN bit in the status register exception byte under any circumstances.

F

False

EQ

Equal

OGT

OGE

OLT

OLE

OGL

OR

Ordered Greater Than

Ordered Greater Than or Equal

Ordered Less Than

Ordered Less Than or Equal

Ordered Greater or Less Than

Ordered

UN

Unordered

UEQ

UGT

UGE

ULT

ULE

NE

Unordered or Equal

Unordered or Greater Than

Unordered or Greater or Equal

Unordered or Less Than

Unordered or Less or Equal

Not Equal

T

True

Note: The following conditional tests set the BSUN bit in the status register exception byte if the NAN condition code bit is set when a

conditional instruction is executed.

SF

Signaling False

Signaling Equal

Greater Than

SEQ

GT

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Table 9. Floating-point Conditional Test Specifiers

Mnemonic

GE

Definition

Greater Than or Equal

Less Than

LT

LE

Less Than or Equal

Greater or Less Than

Greater Less or Equal

Not (Greater, Less or Equal)

Not (Greater or Less)

Not (Less or Equal)

Not (Less Than)

GL

GLE

NGLE

NGL

NLE

NLT

NGE

NGT

SNE

ST

Not (Greater or Equal)

Not (Greater Than)

Signaling Not Equal

Signaling True

Miscellaneous

Instructions

Miscellaneous instructions include moves to and from the status, control, and instruction

address registers and a no operation function that can be used to “flush” exceptions. Also

included are the virtual memory/machine FSAVE and FRESTORE instructions that save and

restore the internal state of the TS 68882.

FMOVE

FNOP

(ea),FPcr

Move to Control Register(s)

Move from Control Register(s)

No Operation

FPcr,(ea)

FSAVE

(ea)

Virtual Machine State Save

Virtual Machine State Restore

FRESTORE

Addressing Modes

The TS 68882 does not perform address calculations. This satisfies the criterion that an TS

68000 Family coprocessor must not depend on certain features or capabilities that may or

may not be implemented by a given main processor. Thus, when the TS 68882 instructs the

TS 68020/TS 68030 to transfer an operand via the coprocessor interface, the MPU performs

the addressing mode calculations requested in the instruction. In this case, the instruction is

encoded specifically for the TS 68020/TS 68030, and the execution of the TS 68882 is not

dependent on that encoding, but only on the value of the command word written to the TS

68882 by the main processor.

This interface is quite flexible and allows any addressing mode to be used with floating-point

instructions. For the TS 68000 Family, these addressing modes include immediate, postincre-

ment, predecrement, data or address register direct, and the indexed/indirect addressing

modes of the TS 68020/TS 68030. Some addressing modes are restricted for some instruc-

tions in keeping with the TS 68000 Family architectural definitions (e.g., PC relative

addressing is not allowed for a destination operand).

The orthogonal instruction set of the TS 68882, along with the flexible branches and address-

ing modes, allows a programmer writing assembly language code, or a compiler writer

generating object or source code for the MPU/TS 68882 device pair, to think of the TS 68882

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as though it is part of the MPU. There are no special restrictions imposed by the coprocessor

interface, and floating-point arithmetic is coded exactly like integer arithmetic.

Address Bus (A0

through A4)

These active-high address line inputs are used by the main processor to select the coproces-

sor interface register locations located in the CPU address space. These lines control the

register selection as listed in Table 10.

When the TS 68882 is configured to operate over an 8-bit data bus, the A0 pin is used as an

address signal for byte accesses of the coprocessor interface registers. When the TS 68882 is

configured to operate over a 16- or 32-bit system data bus, both the A0 and SIZE pins are

strapped high and/or low as listed in Table 11.

Table 10. Coprocessor Interface Register Selection

A4-A0

0000x

0001x

0010x

0011x

0100x

0101x

0110x

0111x

100xx

1010x

1011x

110xx

111xx

Offset

S00

S02

S04

S06

S08

S0A

S0C

S0E

S10

S14

S16

S18

S1C

Width

16

Type

Read

Write

Read

R/W

-

Register

Response

Control

16

Save

16

Restore

16

(Reserved)

Command

(Reserved)

Condition

16

Write

-

16

Write

R/W

Read

-

32

Operand

16

Register select

(Reserved)

Instruction Address

Operand Address

16

32

Read

R/W

32

Table 11. System Data Bus Size Configuration

A0

Size

Low

High

Data bus

8-Bit

Low

16-Bit

High

32-Bit

Data Bus (D0

through D31)

This 32-bit, bi-directional, three-state bus serves as the general purpose data path between

the TS 68020/TS 68030 and the TS 68882. Regardless of whether the TS 68882 is operated

as a coprocessor or a peripheral processor, all inter-processor transfers of instruction informa-

tion, operand data, status information, and requests for service occur as standard TS 68000

bus cycles.

The TS 68882 will operate over an 8-, 16-, or 32-bit system data bus. Depending upon the

system data bus configuration, both the A0 and SIZE pins are configured specifically for the

applicable bus configuration. (Refer to ADDRESS BUS (A0 through A4) and SIZE (SIZE for

further details).

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Size (SIZE)

This active-low input signal is used in conjunction with the A0 pin to configure the TS 68882 for

operation over an 8-, 16-, or 32-bit system data bus. When the TS 68882 is configured to oper-

ate over a 16-or 32-bit system data bus, both the SIZE and A0 pins are strapped high and/or

low as listed in Table 11.

Address Strobe

(AS)

This active-low input signal indicates that there is a valid address on the address bus, and

both the chip select (CS) and read/write (R/W signal lines are valid).

Chip Select (CS)

This active-low input signal enables the main processor access to the TS 68882 coprocessor

interface registers. When operating the TS 68882 as a peripheral processor, the chip select

decode is system dependent (i.e., like the chip select on any peripheral). The CS signal must

be valid (either asserted or negated) when AS is asserted. Refer to CHIP SELECT TIMING for

further discussion of timing restrictions for this signal.

Read/Write (R/W)

Data Strobe (DS)

This input signal indicates the direction of a bus transaction (read/write) by the main proces-

sor. A logic high (1) indicates a read from the TS 68882, and a logic low (0) indicates a write to

the TS 68882. The R/W signal must be valid when AS is asserted.

This active-low input signal indicates that there is valid data on the data bus during a write bus

cycle.

Data Transfer and Size

Acknowledge

(DSACK0, DSACK1)

These active-low, three-state output signals indicate the completion of a bus cycle to the main

processor. The TS 68882 asserts both the DSACK0, and DSACK1 signals upon assertion of

CS.

If the bus cycle is a main processor read, the TS 68882 asserts DSACK0 and DSACK1 signals

to indicate that the information on the data bus is valid. (Both DSACK signals may be asserted

in advance of the valid data being placed on the bus). If the bus cycle is a main processor

write to the TS 68882, DSACK0 and DSACK1 are used to acknowledge acceptance of the

data by the TS 68882.

The TS 68882 also uses DSACK0 and DSACK1 signals to dynamically indicate to the TS

68020/TS 68030 the “port” size (system data bus width) on a cycle-by-cycle basis. Depending

upon which of the two DSACK pins are asserted in a given bus cycle, the TS 68020/TS 68030

assumes data has been transferred to/from an 8-, 16-, or 32-bit wide data port. Table 12 lists

the DSACK assertions that are used by the TS 68882 for the various bus cycles over the vari-

ous bus cycles over the various system data bus configurations.

Table 12 indicates that all accesses over a 32-bit bus where A4 equals zero are to 16-bit reg-

isters. The TS 68882 implements all 16-bit coprocessor interface registers on data lines D16-

D13 (to eliminate the need for on-chip multiplexers); however, the TS 68020/TS 68030

expects 16-bit registers that are located in a 32-bit port at odd word addresses (A1 = 1) to be

implemented on data lines D0-D15. For accesses to these registers when configured for 32-bit

bus operation, the TS 68882 generates DSACK signals as listed in Table 12 to inform the TS

68020/TS 68030 of valid data on D16-D31 instead of D0-D15.

An external holding resistor is required to maintain both DSACK0 and DSACK1 high between

bus cycles. In order to reduce the signal rise time, the DSACK0 and DSACK1 lines are actively

pulled up (negated) by the TS 68882 following the rising edge of AS or DS and both DSACK

lines are then three-stated (placed in the high-impedance state) to avoid interference with the

next bus cycle.

31

2119A–12/01

Table 12. DSACK Assertions

Data Bus

32-Bit

16-Bit

8-Bit

A4

1

DSACK1

DSACK2

Comments

L

H

L

Valid data on D31-D0

0

Valid data on D31-D16

x

L

Valid data on D31-D16 or D15-D0

Valid data on D31-D24, D23-D16, D15-D8, D7-D0

Insert Wait States in Current Bus Cycle

x

H

All

x

H

Reset (RESET)

This active-low input signal causes the TS 68882 to initialize the floating-point data registers to

non-signaling not-a-numbers (NANs) and clears the floating-point control, status, and instruc-

tion address registers.

When performing a power-up reset, external circuitry should keep the RESET line asserted to

a minimum of four clock cycles after V_CCis within tolerance. This assures correct initialization

of the TS 68882 when power is applied. For compatibility with all TS 68000 Family devices,

100 milliseconds should be used as the minimum.

When performing a reset of the TS 68882 after V_CChas been within tolerance for more than

the initial power-up time, the RESET line must have an asserted pulse width which is greater

than two clock cycles. For compatibility with all TS 68000 Family devices, 10 clock cycles

should be used as the minimum.

Clock (CLK)

The TS 68882 clock input is a TTL-compatible signal that is internally buffered for develop-

ment of the internal clock signals. The clock input should be a constant frequency square

wave with no stretching or shaping techniques required. The clock should not be gated off at

any time and must conform to minimum and maximum period and pulse width times.

Sense Device (SENSE)

Power (V_CCand GND)

This pin may be used optionally as an additional GND pin, or as an indicator to external hard-

ware that the TS 68882 is present in the system. This signal is internally connected to the

GND of the die, but it is not necessary to connect it to the external ground for correct device

operation. If a pullup resistor (which should be larger than 10 kΩ) is connected to this pin loca-

tion, external hardware may sense the presence of the TS 688882 in a system.

These pins provide the supply voltage and system reference level for the internal circuitry of

the TS 68882. Care should be taken to reduce the noise level on these pins with appropriate

capacitance decoupling.

No Connect (NC)

One pin of the TS 68882 package is designated as a no connect (NC). This pin position is

reserved for future use, and should not be used for signal routing or connected to V_CCor GND.

Interfacing Methods

TS 68882/TS 68020 or TS 68030 interfacing

The following paragraphs describe how to connect the TS 68882 to an TS 68020 or TS 68030

for coprocessor operation via an 8-, 16-, or 32-bit data bus.

32-Bit Data Bus

Coprocessor

Connection

Figure 18 illustrates the coprocessor interface connection of an TS 68882 to an TS 68020/TS

68030 via a 32-bit data bus. The TS 68882 is configured to operate over a 32-bit data bus

when both the A0 and SIZE pins are connected to V_CC

.

32

TS68882

2119A–12/01

TS68882

16-Bit Data Bus

Coprocessor

Connection

Figure 19 illustrates the coprocessor interface connection of an TS 68882 to an TS 68020/TS

68030 via a 16-bit data bus. The TS 68882 is configured to operate over a 16-bit data bus

when the SIZE pin is connected to V_CC, and the A0 pin is connected to GND. The sixteen least

significant data pins (D0-D15) must be connected to the sixteen most significant data pins

(D16-D31) when the TS 68882 is configured to operate over a 16-bit data bus (i.e., connect D0

to D16, D1 to D17,... and D15 to D31). The DSACK pins of the two devices are directly con-

nected, although it is not necessary to connect the DSACK0 pin since the TS 68882 never

asserts it in this configuration.

8-Bit Data Bus

Coprocessor

Connection

Figure 20 illustrates the connection of an TS 68882 to an TS 68020/TS 68030 as a coproces-

sor over an 8-bit data bus. The TS 68882 is configured to operate over a 8-bit data bus when

the SIZE pin is connected to GND. The twenty four least significant data pins (D0-D23) must

be connected to eight most significant data pins (D24-D31) when the TS 68882 is configured

to operate over a 8-bit data bus (i.e., connect D0 to D8, D16 to D24; D1 to D9, D17, and

D15;... and D7 to D15, D23 and D31). The DSACK pins of the two devices are directly con-

nected, although it is not necessary to connect the DSACK1 pin since the TS 68882 never

asserts it in this configuration.

• TS 68882/TS 68000/TS 68008/TS 68010 Interfacing

The following paragraphs describe how to connect the TS 68882 to an TS 68000, TS 68008,

or TS 68010 processor for operation as a peripheral via an 8- or 16-bit data bus.

16-Bit Data Peripheral

Processor Connection

Figure 21 illustrates the connection of an TS 68882 to an TS 68000 or TS 68010 as a periph-

eral processor over an 16-bit data bus. The TS 68882 is configured to operate over an 16-bit

data bus when the SIZE pin is connected to V_CC, and the A0 pin is connected to GND. The six-

teen least significant data pins (D0-D15) must be connected to the sixteen most significant

data pins (D16-D31) when the TS 68882 is configured to operate over an 16-bit data bus (i.e.,

connect D0 to D16, D1 to D17,... and D15 to D31). The DSACK1 pin of the TS 68882, is con-

nected to the DTACK pin of the main processor, and the DSACK0 pin is not used.

When connected as a peripheral processor, the TS 68882 chip select (CS) decode is system

dependent. If the TS 68000 is used as the main processor, the TS 68882 CS must be decoded

in the supervisor or user data spaces. However, if the TS 68010 is used as the main proces-

sor, the MOVES instruction may be used to emulate any CPU space access that the TS

68020/TS 68030 generates for coprocessor communications. Thus, the CS decode logic for

such systems may be the same as in an TS 68020/TS 68030 systems, such that the TS 68882

will not use any part of the data address spaces.

33

2119A–12/01

Figure 18. 32-bit Data Bus Coprocessor Connection

Figure 19. 16-bit Data Bus Coprocessor Connection

34

TS68882

2119A–12/01

TS68882

Figure 20. 8-bit Data Bus Coprocessor Connection

GND

Figure 21. 16-bit Data Bus Peripheral Processor Connection

35

2119A–12/01

Figure 22. 8-bit Data Bus Peripheral Processor Connection

8-Bit Data Bus

Peripheral Processor

Connection

Figure 22 illustrates the connection of an TS 68882 to an TS 68008 as a peripheral processor

over an 8-bit data bus. The TS 68882 is configured to operate over an 8-bit data bus when the

SIZE pin is connected to GND. The eight least significant data pins (D0-D7) must be con-

nected to the twenty four most significant data pins (D8-D31) when the TS 68882 is configured

to operate over an 8 bit data bus (i.e., connect D0 to D8, D16 and D24; D1 to D9, D17, and

D25;... and D7 to D 15, D 23, and D31). The DSACK0 pin of the TS 68882 is connected to the

DTACK pin of the TS 68008, and the DSACK1 pin is not used.

When connected as a peripheral processor, the TS 68882 chip select (CS) decode is system

dependent, and the CS must be decoded in the supervisor or user data spaces.

Preparation For

Delivery

Certificate of

Compliance

ATMEL-Grenoble offers a certificate of compliance with each shipment of parts, affirming the

products are in compliance with MIL-STD-883 and guaranteeing the parameters are tested at

extreme temperatures for the entire temperature range.

Handling

Devices must be handled with certain precautions to avoid damage due to accumulation of

static charge. Input protection devices have been designed in the chip to minimize the effect of

this static buildup. However, the following handling practices are recommended:

a) Device should be handled on benches with conductive and grounded surface.

b) Ground test equipment, tools and operator.

c) Do not handle devices by the leads.

36

TS68882

2119A–12/01

TS68882

d) Store devices in conductive foam or carriers.

e) Avoid use of plastic, rubber, or silk.

f) Maintain relative humidity above 50%, if practical.

Package

Mechanical

Data

Figure 23. 68 pins - Ceramic Pin Grid Array

Notes: 1. Dimensions A and B are datums and T S datum surface.

2. Positional tolerance for leads 168 places:

θ φ0,13(0,005) T, A (5)|B (5)

3. Dimensioning and tolerancing per AN5I Y14 5M 1982.

4. Controlling dimension: INCH.

37

2119A–12/01

Figure 24. 68 pins - Ceramic Quad Flat Pack

Terminal

Connections

68 pins - Ceramic

Pin Grid Array

See Figure 23.

See Figure 24.

68 pins - Ceramic

Quad Flat Pack

38

TS68882

2119A–12/01

TS68882

Ordering

Information

HI-REL Product

Commercial Atmel

Part-Number

Temperature Range

Tc (°C)

Frequency

(MHz)

Norms

MIL-STD-883

DESC

Package

PGA 68

CQFP 68

PGA 68

CQFP 68

Drawing Number

TS 68882MRB/C16

TS 68882MRB/C20

TS 68882MRB/C25

TS 68882MRB/C33

TS 68882MFB/C16

TS 68882MFB/C20

TS 68882MFB/C25

TS 68882DESC01XA

TS 68882DESC02XA

TS 68882DESC03XA

TS 68882DESC04XA

TS 68882DESC01YA

TS 68882DESC02YA

TS 68882DESC03YA

TS 68882DESC04YA

-55 / +125

16.67

20

-

25

-

33

-

16.67

20

-

25

-

16.67

20

5962 8946301XA

5962 8946304YA

DESC

25

DESC

33

DESC

16.67

20

DESC

25

DESC

33

Standard Product

Commercial Atmel

Part-Number

Temperature Range

Tc (°c)

Frequency

MHZ

Norms

Package

Drawing Number

Internal

TS 68882VR16

TS 68882VR20

TS 68882VR25

TS 68882VR33

TS 68882MR16

TS 68882MR20

TS 68882MR25

TS 68882MR33

TS 68882VF16

TS 68882VF20

TS 68882VF25

TS 68882VF33

TS 68882MF16

ATMEL-Grenoble Standard

PGA 68

CQFP 68

-40 / +85

-55 / +125

-40 / +85

-55 / +125

16.67

20

Internal

25

33

16.67

20

25

33

16.67

20

25

Internal

33

Internal

16.67

Internal

39

2119A–12/01

Standard Product

Commercial Atmel

Part-Number

Temperature Range

Tc (°c)

Frequency

MHZ

Norms

Package

CQFP 68

Drawing Number

Internal

TS 68882MF20

TS 68882MF25

TS 68882MF33

ATMEL-Grenoble Standard

-55 / +125

20

25

33

Internal

TS68882

M

R

20

1

B/C

Type

Speed (MHz)

Screening

Temperature range: Tc

M: -55/+125°C

V: -40/+85°C

- = Standard

B/C = MIL STD 883 Class B

Package

R = Pin grid array 68

F = CQFP 68

Hirel lead finish

1: Hot solder dip (883C)

Gold

Note:

For availability of the different versions, contact your ATMEL-Grenoble sales office.

40

TS68882

2119A–12/01

TS68882

41

2119A–12/01

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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

®

™

Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

2119A–12/01/xM


型号：	TS8882VF20
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