TSB14AA1T [ETC]
Telecomm/Datacomm ; 电信/数据通信\n
| 型号： | TSB14AA1T |
| 厂家： | 
ETC |
| 描述： | Telecomm/Datacomm
|
| 文件： | 总39页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Manual
June 2001
MSDS1394
SLLS465B
Data Manual
June 2001
MSDS1394
SLLS465B
IMPORTANT NOTICE
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Copyright 2001, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
1.2
1.3
1.4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Terminal Assignments/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
2
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1
2.2
2.3
Open Collector Transceiver System Block Diagram . . . . . . . . . . . . . . 2–1
3-State Transceiver System Block Diagram . . . . . . . . . . . . . . . . . . . . . 2–1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
Link/PHY Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Arbitration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Data Resync/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Data/Arb Encode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
CFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
3
4
Internal Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1
Absolute Maximum Ratings Over Operating
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2
4.3
4.4
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Switching Characteristics, V
= 3.3 V, T = 25°C . . . . . . . . . . . . . . . 4–2
CC
A
5
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.1
5.2
5.3
5.4
5.5
Transceiver Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Link Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Using the EX_ID and EX_PRI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Testability and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1
PHY/Link Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Read/Write Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6.2
Backplane Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
6.2.1 Backplane PHY Connection . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
iii
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
Definition of Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Backplane Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . 6–8
Backplane Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . 6–8
Backplane Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Gap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
6.3
6.4
Arbitration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
6.3.1
6.3.2
6.3.3
Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Arbitration Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Arbitration Sequence Format . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
6.4.1
6.4.2
6.4.3
6.4.4
Fairness Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Fair Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Urgent Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Immediate Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
6.5
6.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
6.5.1
6.5.2
Backplane PHY Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Live Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
7
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
List of Illustrations
Figure
Title
Page
4–1 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
6–1 Block Diagram of the TSB14AA1/LLC Interface . . . . . . . . . . . . . . . . . . . . . . . 6–1
6–2 LREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
6–3 Status Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
6–4 Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6–5 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6–6 Backplane Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
6–7 Minimum Edge Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
6–8 Backplane Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
6–9 Fairness Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
6–10 Fair Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
6–11 Urgent Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
iv
List of Tables
Table
Title
Page
1–1 Speed Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
3–1 Base Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3–2 Base Register Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
6–1 CTL Encoding When PHY Has Control of the Bus . . . . . . . . . . . . . . . . . . . . . 6–2
6–2 CTL Encoding When LLC Has Control of the Bus . . . . . . . . . . . . . . . . . . . . . 6–2
6–3 Request Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–4 Bus Request for Cable Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–5 Bus Request for Backplane Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6–6 Read Request Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6–7 Write Request Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6–8 Request Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6–9 Status Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
6–10 TSB14AA1 to Backplane Transceiver Timing . . . . . . . . . . . . . . . . . . . . . . . . 6–8
6–11 TSB14AA1 to Backplane Transceiver Timing . . . . . . . . . . . . . . . . . . . . . . . . 6–8
v
vi
1 Introduction
1.1 Description
The TSB14AA1 is the second-generation 1394 backplane physical layer device. It is recommended for use in all new
designs instead of the first generation TSB14C01A. It provides the physical layer functions needed to implement a
single port node in a backplane based 1394 network. The TSB14AA1 provides two pins for transmitting, two for
receiving, and two pins to externally control the transceivers for data and strobe. In addition to supporting
†
open-collector drivers, the TSB14AA1 can also support 3-state (high-impedance) drivers. The TSB14AA1 is not
designed to drive the backplane directly; this function must be provided externally. The TSB14AA1 is designed to
interface with a link-layer controller (LLC), such as the TSB12LV01B, TSB12LV32, TSB12LV21B, etc.
The TSB14AA1 requires an external 98.304-MHz reference oscillator input for S100 asynchronous only operation
or 49.152-MHz for S50 asynchronous only operation. Two clock select pins (CLK_SEL0, CLK_SEL1) select the
speed mode for the TSB14AA1 (see Table 1–1). For S100 operation, the 98.304-MHz reference signal is internally
divided to provide the 49.152-MHz system clock signals used to control transmission of the outbound encoded strobe
and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the
two chips and is used for resynchronization of the received data. For S50 operation, a 49.152-MHz reference signal
is used. This reference signal is internally divided to provide the 24.576-MHz system clock signals for S50 operations.
Table 1–1. Speed Mode Setting
MAXIMUM FREQUENCY
SPEED MODE
CLK_SEL0 PIN
CLK_SEL1 PIN
INPUT TO XI PIN
PHY_SCLK OUTPUT
OF TDATA, TSTRB
100 Mbits/s
50 Mbits/s
Reserved
Reserved
0
1
1
0
0
0
1
1
100MHz
50MHz
—
X1/2 (50 MHz)
X1/2 (25 MHz)
50 MHz
25MHz
—
—
—
During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched
internally in the TSB14AA1 in synchronization with the system clock. These bits are combined serially, encoded, and
transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is
transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB.
During packet reception, the data information is received on RDATA and strobe information is received on RSTRB.
The received data and strobe information is decoded to recover the received clock signal and the serial data bits,
which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent
to the associated LLC. The PHY-Link interface has been made compliant to IEEE 1394a–2000 including timing and
transfer of register 0 to the link-layer automatically after every 1394 bus reset.
The TSB14AA1 is a 3.3 V device that provides LVCMOS level outputs. The TSB14AA1 is an asynchronous only
device.
†
3-State means a driver may drive high, low, or may be placed in a high-impedance state
1–1
1.2 Features
•
Provides a Backplane 1394 Environment That Supports an Asynchronous Transfer Rate of 50 or 100
Mbits/s Across 2 Etches
•
•
•
•
Single 3.3-V Supply Operation With 5-V Tolerance on the Transceiver Receive Interface
Allows Utilization of 3-State Drivers as Well as Open-Collector Drivers
Software Compatible With the TSB14CO1APM
Enhanced Compatibility With the 1394 Cable Link Layer. Compatible With 1394–1995 and 1394a–2000
†
Link Layers; PHY/link Interface is 1394a Compliant
‡§
•
•
Supports Provisions of IEEE 1394–1995
Extensive Testability and Debug Functions Added. Expanded Register Set Including Automatic Saving of
ID and Priority for Last Node Winning Arbitration
•
•
100 MHz or 50 MHz Oscillator Provides Transmit, Receive Data, and Link Layer Controller (LLC) Clocks
Logic Performs System Initialization Arbitration Functions. Encode And Decode Functions Included for
Data-Strobe Bit Level Encoding. Incoming Data Resynchronized to Local Clock.
•
•
Operates Over the Extended Temperature Ranges of –40°C to 85°C (I suffix) and –40°C to 105°C (T suffix)
Packaged in the Very Compact 48-Pin 7 x 7 x 1 mm PFB Package
1.3 Terminal Assignments/Package
PFB PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
EX_ID5
EX_ID4
EX_ID3
EX_ID2
EX_ID1
EX_ID0
GND
PD
EN
T1P8
37
38
39
40
RESERVED
RESERVED 41
VCC
42
XI 43
GND 44
VCC
EX_PR3
EX_PR2
EX_PR1
EX_PR0
XO 45
CLK_SEL0 46
CLK_SEL1 47
RESET 48
1
2
3
4
5
6
7
8
9 10 11 12
†
IEEE Std 1394a–2000, IEEE Standard for a High Performance Serial Bus – Amendment 1
‡ †
IEEE Std 1394–1995, IEEE Standard for a High Performance Serial Bus
Implements technology covered by one or more patents of Apple Computer, Inc. and ST Microelectronics.
§
1–2
1.4 Terminal Descriptions
TERMINAL
TYPE I/O
DESCRIPTION
NAME
NO.
CLK_SEL0
46
CMOS
I
Clock select 0. If this terminal is set to low (0) then the speed is 98.304 Mbps. If this terminal is set to
high (1) the speed is 49.152 Mbps.
To operate at 100 Mbps requires an input clock of 98.304 MHz. To operate at 49.152 Mbps requires
an input clock of 49.152 MHz.
CLK_SEL1
CTL0, CTL1
47
CMOS
I
Clock select 1. CLK_SEL1 must be tied to ground during normal operation.
7, 8
CMOS I/O Control I/O. These are bidirectional signals that communicate between the TSB14AA1 and the link
layer that controls the passage of information between the two devices.
D0, D1
10, 12
CMOS I/O Data I/O. These are bidirectional information signals that communicate the data between the
TSB14AA1 and the link layer controller.
EN
38
19
Supply
CMOS
I
I
Enable on-chip regulator. This active low pin enables the 1.8 V on–chip regulator.
EX_ID0
External ID 0. The state of this pin sets the value of bit 0 of the PHYSICAL_ID field in the NODE ID
Register upon hardware or SWHRST reset. The register bit may be modified by software.
EX_ID1
EX_ID2
EX_ID3
EX_ID4
EX_ID5
EX_PR0
EX_PR1
EX_PR2
EX_PR3
GND
20
21
22
23
24
13
14
15
16
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
I
I
I
I
I
I
I
I
I
External ID 1. The state of this pin sets the value of bit 1 of the PHYSICAL_ID field in the NODE ID
register upon hardware or SWHRST reset. The register bit may be modified by software.
External ID 2. The state of this pin sets the value of bit 2 of the PHYSICAL_ID field in the NODE ID
register upon hardware or SWHRST reset. The register bit may be modified by software.
External ID 3. The state of this pin sets the value of bit 3 of the PHYSICAL_ID field in the NODE ID
register upon hardware or SWHRST reset. The register bit may be modified by software.
External ID 4. The state of this pin sets the value of bit 4 of the PHYSICAL_ID field in the NODE ID
register upon hardware or SWHRST reset. The register bit may be modified by software.
External ID 5. The state of this pin sets the value of bit 5 of the PHYSICAL_ID field in the NODE ID
register upon hardware or SWHRST reset. The register bit may be modified by software.
Externalpriority0. Thestateofthispinsetsthevalueofbit0ofthePRIORITYfieldinthePRIORITY
register upon hardware or SWHRST reset. The register bit may be modified by software.
Externalpriority1. Thestateofthispinsetsthevalueofbit1ofthePRIORITYfieldinthePRIORITY
register upon hardware or SWHRST reset. The register bit may be modified by software.
Externalpriority2. Thestateofthispinsetsthevalueofbit2ofthePRIORITYfieldinthePRIORITY
register upon hardware or SWHRST reset. The register bit may be modified by software.
Externalpriority3. Thestateofthispinsetsthevalueofbit3ofthePRIORITYfieldinthePRIORITY
register upon hardware or SWHRST reset. The register bit may be modified by software.
4, 18, 28, Supply
32, 34, 44
Ground voltage reference
IDS
9
CMOS
I
Invert data strobe. When this pin is set low, the TDATA, TSTRB, RDATA, RSTRB, OCDOE, and
TDOE pins operate normally (i.e., true). When this pin is set high, these six pins are inverted.
LINKON
2
CMOS
O
Link-On output. This pin notifies the LLC to power-up and become active. LINKON is a
square-wave signal with a frequency between 4 and 8 MHz when active. LINKON is otherwise
driven low, except during a hardware reset when it is high impedance.
LINKON is activated if the LPS is inactive (LLC inactive) and when the PHY receives a link-on PHY
packet addressed to this node.
Once activated, LINKON will continue active until the LPS becomes active (LLC active). The PHY
also deasserts (low) LINKON when a bus-reset occurs.
1–3
1.4 Terminal Descriptions (Continued)
TERMINAL
TYPE I/O
DESCRIPTION
NAME
LPS
NO.
1
CMOS
I
Link power status input. This pin monitors the active/power status of the link layer controller and
controlsthe state of the PHY-LLC interface. This pin must be connected to either a pulsed output that
isactivewhentheLLCispowered, ortotheV
supplyingtheLLCthrougha10kΩresistor.TheLPS
DD
input is considered inactive if it is sampled low by the PHY for more than 128 SCLK cycles and is
considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less
than 2.6 µs). The LPS input must be high for at least 21 ns in order to ensure observation as high by
the PHY.
When the TSB14AA1 detects that LPS is inactive, it will place the PHY-LLC interface into a
low–power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and
theLREQinputisignored;however, theSCLKoutputremainsactive. IftheLPSinputremainslowfor
more than 1280 SCLK cycles, the PHY-LLC interface is placed into a low-power disabled state in
which the SCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state
upon hardware reset. The LLC is considered active only if the LPS input is active.
LREQ
3
CMOS
CMOS
I
I
Link request input. The LLC uses this input to initiate a service request to the TSB14AA1.
M-TEST
26
Manufacturing tests. When M-TEST is set high, manufacturing test modes are enabled. For normal
operation, this pin must be set low.
OCDOE
25
CMOS
O
Open collector driver output enable pin. This pin is driven low to enable the open-collector
transceivers for both TDATA and TSTRB. OCDOE is also used to enable the TSTRB transceiver
when used with 3-state transceivers. When IDS is high, the output of this pin is inverted.
PD
37
35
48
33
11
5
CMOS
TTL
I
I
Power-down input. This pin is used for manufacturing tests. It should be tied to ground for normal
operation.
RDATA
RESET
RSTRB
SCAN_EN
SCLK
Receivedatainput. Incomingdatafromtheexternaltransceiverisreceivedatthedataratesetbythe
CLK_SELX pins and input clock frequency. When IDS is high the pin input is inverted.
CMOS
TTL
I
Hardware reset input. When pulsed low for a minimum of (2*SCLK) seconds, a hardware reset is
initiated.
I
Receivestrobeinput. Theincomingstrobesignalfromtheexternaltransceiverisreceivedatthedata
rate set by the CLK_SELX pins and input clock frequency. When IDS is high the pin input is inverted.
CMOS
CMOS
I
Scan enable. When set high this pin enables the manufacturing scan test of the TSB14AA1 device. It
is set low for normal operation.
O
Systemclockoutput. Thispinprovidesaclocksignalsynchronizedwiththedatatransfersandoutput
to the link. It pulses at a rate of 1/2 the data rate. At a data rate of 98.304 Mbps it oscillates at
49.152 MHz, and at a data rate of 49.152 Mbps it oscillates at 24.576 MHz.
T1P8
39
29
31
O
O
O
1.8 V regulator output. This pin is the output of the on-chip 1.8 V voltage regulator. T1P8 must be
decoupled to GND with a 0.1 µF capacitor.
TDATA
TDOE
CMOS
CMOS
Transmit data output. Data to be transmitted is serialized on TDATA and output to the external
transceiver. When IDS is high the pin output is inverted.
3-state (high-impedance) driver output enable. This pin will only be asserted under any of the
following conditions:
1. Data is transmitted after winning arbitration.
2. The arbitration state being driven is 1 (TDATA and TSTRB both = 1).
3. Bus reset is initiated.
It is driven low to enable high impedance transceivers for the TDATA signal. When IDS is high the pin
output is inverted.
TEST_EN
TSTRB
VCC
36
27
CMOS
CMOS
I
O
I
Test enable input. When set high, this pin enables a manufacturing test mode. In normal operation,
this pin must be tied to GND.
Transmit strobe output. TSTRB encodes the transmit of the strobe signal and the output to the
external transceiver. When IDS is high the pin output is inverted.
6, 17, 30, Supply
42
3.3-V supply voltage
Xl
43
Crystal
I
Crystal oscillator input. When used with an oscillator, this pin must be connected to the output of the
oscillator. When operating at 98.304 Mbps this input must be 98.304 MHz. When operating at 49.152
Mbps, this input must be 49.152 MHz.
XO
45
Crystal
O
Oscillator output. When used with an oscillator, this pin must be left unconnected.
1–4
2 Detailed Description
2.1 Open Collector Transceiver System Block Diagram
TSB14AA1
Open Collector Transceiver
D0–D1
OCDOE
CTL0–CTL1
TDATA
BPdata
BPstrb
Host
Interface
1394
LPS
RDATA
TSTRB
1394 Link
Layer
Backplane
Physical-
Layer
LINKON
SCLK
Controller
Controller
RSTRB
LREQ
2.2 3-State Transceiver System Block Diagram
TSB14AA1
3-State Transceiver
D0–D1
TDOE
CTL0–CTL1
TDATA
BPdata
BPstrb
Host
1394
LPS
Interface
RDATA
OCDOE
TSTRB
1394 Link
Layer
Backplane
Physical-
Layer
LINKON
Controller
Controller
LREQ
SCLK
RSTRB
2.3 Functional Block Diagram
TDOE
OCDOE
Data/Arb
Encode
SCLK
D0-1
TDATA
TSTRB
Arbitration
Control
CTL0-1
Link/PHY
Interface
RDATA
RSTRB
Data/
Resync
Decode
LREQ
LPS
LINKON
CFRs
Clock
XI
Generation
XO
EX_ID
EX_PRI
2–1
2.3.1 Link/PHY Interface
Four operations may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data
receive. The LLC issues a link service request to read or write a PHY register, or to request that the PHY gain control
of the serial-bus to transmit a packet. (refer to Section 5).
2.3.2 Arbitration Control
Controls the arbitrating sequence that the TSB14AA1 uses to arbitrate the bus between competing nodes (refer to
Section 6).
2.3.3 Data Resync/Decode
During packet reception, the data information is received on RDATA and strobe information is received on RSTRB.
The received data and strobe information is decoded to recover the received clock signal and the serial data bits,
which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent
to the associated LLC.
2.3.4 Data/Arb Encode
During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched
internally (in the TSB14AA1) in synchronization with the system clock. These bits are combined serially, encoded,
and transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is
transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB.
2.3.5 CFRs
The configuration registers (CFRs) control the operation of the TSB14AA1. The register definitions are specified in
Section 3.
2.3.6 Clock Generation
Provides system clock signals used to control transmission of the outbound encoded strobe and data information,
synchronization of the LLC and PHY, and is used for resynchronization of the received data.
2–2
3 Internal Register Configuration
There are 10 accessible internal registers in the TSB14AA1. The configuration of the registers is shown in Table 3–1,
and corresponding field descriptions given in Table 3–2.
A reserved register or register field (marked as reserved or RSVD in the following register configuration tables) is read
as 0, but is subject to future usage.
Table 3–1. Base Register Configuration
BIT POSITION
Address
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
PHYSICAL_ID
R_F_TEST
TD
IBR
RESERVED
LAST_ARB_WON_PHYSICAL_ID
XFR_SPD
RSVD
E
RDATA
RSTRB
E_REGISTER_COUNT
RESERVED
PRIORITY
PRODUCT IDENTIFIER
RESERVED FOR TEST
LAST_ARB_WON_PRIORITY
EBLREQ
DDLS
IRBR
DSLS
SMRST
ENDLS
SWHRST
RESERVED
TDATA
TSTRB
TDOE
OCDOE
RESERVED FOR TEST
RESERVED FOR TEST
Table 3–2. Base Register Field Description
FIELD
SIZE
TYPE
DESCRIPTION
RESERVED
R/W
All fields marked as reserved or RSVD must be read as 0. Whenever software is
developed that writes to a register that has a reserved field, software must write a 0 to
each reserved bit. In this way a bit can be added later with the default value of 0 that
reverts to previous functionality. Whenever a read is done of a register that has
reserved fields, software must not depend on the reserved fields to hold any particular
value.
RESERVED FOR TEST
PHYSICAL_ID
Reserved All fields marked as reserved for test or R_F_TEST may only be written to as a test to
for Test
allow reading of and writing to the entire 8 bits of a register. For normal operation of the
PHY the bit(s) should be set to 0. Whenever a read is done of a register that has
reserved for test fields, software must not depend on the reserved for test fields to hold
any particular value.
6
R/W
Physical layer ID for this node. Unlike the equivalent field in the cable environment, the
physicalIDinthebackplaneenvironmentiswriteable.Thepower-upstateofthisfieldis
000000b.Thehardware-resetstateofthisfieldisthebinarystateoftheexternalIDpins
onthedevice. Thisfieldisunaffectedbybusreset (IBR, IRBR)andstatemachinereset
(SMRST). It is reinitialized to the external pin values by a hardware reset or reset
initiated by writing to the software initiated hard reset (SWHRST) bit.
TD
1
1
R/W
R/W
Transceiver disable. When set to 1 the PHY sets the output enable signals so that the
bus transceivers are disabled. The TSB14AA1 ignores any link layer service actions
that require a change to this bus output state. The power-up state of this field is 0. The
state of this bit is not affected by bus resets.
IBR
Initiate bus-reset. When set to 1, the PHY initiates a bus request immediately (without
arbitration). This bit causes assertion of the reset signal for approximately 8 µs and is
self-clearing. The IBR bit may be used to initiate bus resets when open collector
transceivers are implemented. In general the IRBR bit must be used to initiate bus
resets instead of IBR. The IBR bit is retained for software compatibility with the
TSB14CO1A when used with open-collector transceivers. When 3-state transceivers
are implemented, the IRBR bit must be used to initiate bus resets. The power-up state
of this field is 0.
3–1
Table 3-2. Base Register Field Description (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
LAST_ARB_WON_PHY_ID
6
R
Last physical layer node ID that won arbitration. This field contains the physical ID of the node
that last won the arbitration phase on the bus. This field is only valid when the E bit is 1. It is
supplied for system debug purposes. The power-up state of this field is 000000b. The state of
these bits is not affected by bus resets.
E
1
1
1
R
R
R
Enhanced register map. This bit is set to 1 to signify that additional extended registers beyond
address 0100b are implemented. When this bit is set to 1, the values in the
LAST_ARB_WON_PHY_ID, LAST_ARB_WON_PRIORITY, RDATA, RSTRB, TDATA,
TSTRB, TDOE, OCDOE fields are valid. When this bit is 0 the values in these fields are not
valid. The power-up state of this field is 1. This bit is always read in a TSB14AA1 as a 1.
RDATA
RSTRB
Received data line state. When the enhanced (E) bit is 1, the sampled and latched line state
readfromthisfieldisvalid.Thisbitreads1foradatabit1(logical1)receivedbytheTSB14AA1
and0foradatabit0(logical0).Thepower-upstateofthisfieldis0.Thisbitisupdatedonabest
effortbasis. Itisnotrequiredtobetoggledwitheverychangeofitsnamesake’s input pin. It can
be expected to be updated at least every 9 SCLKs, the length of the register read LREQ.
Received strobe line state. When the enhanced (E) bit is 1, the sampled and latched line state
read from this field is valid. This bit reads 1 for a strobe line 1 (logical 1)
received by the TSB14AA1 and 0 for a strobe line 0 (logical 0). The power-up state of this field
is 0. This bit is updated on a best effort basis. It is not required to be toggled with every change
ofitsnamesake’sinputpin.Itcanbeexpectedtobeupdatedatleastevery9SCLKs,thelength
of the register read LREQ.
XFR_SPD
2
R
Transfer speed. These bits map exactly to the CLK_SEL0 and CLK_SEL1 pins (CLK_SEL0 is
the left most bit, CLK_SEL1 is the right most bit). This enables software to verify the state of
those pins and therefore the performance level of the bus transfers (100 Mbps or 50 Mbps).
See the definitions for CLK_SEL0 and CLK_SEL1 for decoding. The state of these bits is not
affected by bus resets or state machine resets. Upon power up, hardware reset, or SWHRST
reset these bits are reloaded with the values from the CLK_SEL0 and CLK_SEL1 pins.
E_REGISTER_COUNT
PRIORITY
4
4
R
Enhanced register count. When the E bit is 1, this field is valid. This field is set to 0101b to
signify that there are five register addresses implemented above 0100b. The power-up state
of this field is 0101b.
R/W
Priority setting. These bits contain the priority of the local node. These bits contain the priority
used in the arbitration process and transmitted as the PRI field in the packet header. The
power-up state of this field is 0000b. Bit field 0 maps to priority [0] the most significant bit of the
priority field used during arbitration. The hardware or SWHRST reset state of this field is the
binary state of the external priority pins on the device. The state of these bits is not affected by
bus resets or state machine resets.
WhenthisfieldisnonzeroTSB14AA1usesurgentarbitrationevenwhenafairrequestismade
of the PHY by the link. When this field is zero, the PHY uses fair arbitration unless the link
makes an urgent request using an 11-bit LREQ, if this device is configured to accept 11-bit
LRFQs.
PRODUCT_IDENTIFIER
EBLREQ
4
1
R
Product identifier. This field contains the product identifier for the part. For the TSB14AA1 this
field should be 0000b. Bits 0-3 are used to indicate functional changes to the design. The
power-up state of this field for the TSB14AA1 is 0000b.
R/W
Enable backplane LREQ. When this bit is set to 1, TSB14AA1 interprets all bus request
LREQs from the link as 11 bits long in the backplane format. The power-up state of this field is
0b. When this bit is set to 0, TSB14AA1 interprets the bus request LREQs as being 7 bits long
(standard cable LLC LREQs). The value of this bit must match the value of its corresponding
bit in the attached link layer or the node will not function properly. Bus reset or state machine
reset does not affect the state of this bit. This bit is cleared to 0 upon HW or SWHRST reset.
IRBR
1
R/W
Initiate robust bus reset. The IRBR bit is used when operating with 3-state transceivers to
ensure a bus reset is communicated without bus contention. It works equally well for open
collector transceivers. This bit is self-clearing. The power-up state of this field is 0b. This bit
should be used for all SW initiated bus resets. Care should be taken that when writing to the
IRBR bit, other bits in this same register are not changed. This register should be first read,
then the read value should have bit 1 (the bit to be written to the IRBR field) set to 1 and the
value written into the register.
3–2
Table 3-2. Base Register Field Description (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
SMRST
1
R/W
State machine reset. When this bit is written to, TSB14AA1 first clears, then resets all
state machines in the PHY. This bit is self-clearing. The power-up state of this field is 0b.
SWHRST
1
4
1
R/W
Softwareinitiatehardwarereset. Whenthisbitissetto1, TSB14AA1performsaresetof
the same nature as the reset caused by toggling the RESET pin on the device. This
clears all state machines and register settings to their power-on reset states. This bit is
self-clearing. The power-up state of this field is 0b.
LAST_ARB_WON_PRIORITY
DDLS
R
Priority code of physical layer node that last won arbitration. This field contains the
priority used by the node that last won the arbitration process on the bus. It is only valid
whentheEbitis1. Thisfieldissuppliedforsystemdebugpurposes. Thepower-upstate
of this field is 0b.
R/W
Drive data line state. When the M_TEST pin is asserted (high) and the ENDLS bit is set
to 1, the TSB14AA1 drives the state of the DDLS bit on the TDATA output pin of the
device. This mode of operation is for diagnostic testing only. It is not a valid 1394
operatingmodeandwillnotallowproper1394busoperationifconnectedtoa1394bus.
The power-up state of this bit is 0b. The state of this bit is not affected by bus resets or
state machine resets. This bit is cleared upon HW or SWHRST reset.
DSLS
1
1
R/W
R/W
Drive strobe line state. When the M_TEST pin is asserted (high) and the ENDLS bit is
set to 1, the TSB14AA1 drives the state of the DSLS bit on the TSTRB output pin of the
device. This mode of operation is for diagnostic testing only. It is not a valid 1394
operationmodeandwillnotallowproper1394busoperationifconnectedtoa1394bus.
The power-up state of this bit is 0b. The state of this bit is not affected by bus resets or
state machine resets. This bit is cleared upon hardware or SWHRST reset.
ENDLS
Enable drive line state. When the M_TEST pin is asserted (high) and ENDLS is set to 1,
the TSB14AA1 drives the state of the DDLS bit on the TDATA output pin of the device. It
alsodrivesthestateoftheDSLSbitontheTSTRBoutputpinofthedevice. Thismodeof
operation is for diagnostic testing only. It is not a valid 1394 operation mode and will not
allow proper 1394 bus operation if connected to a 1394 bus. The power-up state of this
bitis0b. Thestateofthisbitisnotaffectedbybusresetsorstatemachineresets. Thisbit
is cleared upon hardware or SWHRST reset.
TDATA
TSTRB
1
1
R
R
Transmitteddata line state. When the E bit is 1, the line state read from this field is valid.
This bit reads 1 for a data line 1 (logical 1) being transmitted by the TSB14AA1 and 0 for
adataline0(logical0). Thepower-upstateofthisfieldis0b. Thisbitisupdatedonabest
effort basis. TDATA is not required to be toggled with every change of the TDATA output
pin. It can be expected to be updated at least every 9 SCLKs, the length of the register
read LREQ.
Transmit strobe line state. When the E bit is 1, the line state read from this field is valid.
This bit reads 1 for a strobe line 1 (logical 1) being transmitted by the TSB14AA1 and 0
forastrobeline0(logical0).Thepower-upstateofthisfieldis0b.Thisbitisupdatedona
best effort basis. TSTRB is not required to be toggled with every change of the TSTRB
output pin. It can be expected to be updated at least every 9 SCLKs, the length of the
register read LREQ.
TDOE
1
1
R
R
3-State output enable. When the E bit is 1, the state read from this field is valid. The
power-up state of this field is 0b. This bit is updated on a best effort basis. TDOE is not
required to be toggled with every change of the TDOE output pin. It can be expected to
be updated at least every 9 SCLKs, the length of the register read LREQ.
OCDOE
Open collector output enable. When the E bit is 1, the state read from this field is valid.
Thepower-upstateofthisfieldis0b. Thisbitisupdatedonabesteffortbasis. OCDOEis
not required to be toggled with every change of the OCDOE output pin. It can be
expected to be updated at least every 9 SCLKs, the length of the register read LREQ.
3–3
3–4
4 Electrical Characteristics
4.1 Absolute Maximum Ratings Over Operating Junction Temperature (Unless
†
Otherwise Noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
DD
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
I
DD
Oscillator input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V
5V tolerant I/O supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
DD_5V
5V tolerant input voltage range, V
I–5V
DD_5V
Output voltage range at any output, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5V
O
DD
Electrostatic discharge (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM: 2 kV, MM: 200 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free air temperature, T (TSB14AA1I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
(TSB14AA1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 105°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.
2. HBM is human body model, MM is machine model.
DISSIPATION RATING TABLE
†
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 105°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
‡
PFB
2.01 W
20.1 mW/°C
1.11 W
402 mW
†
‡
This is the inverse of the traditional junction--to-ambient thermal resistance (R
Standard JEDEC high-K board
).
θJA
4.2 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
V
Supply voltage, VDD
3
3.3
3.6
CMOS input and output
0.7×V
V
DD
2
High-level input voltage, V
IH
TTL inputs
V
CMOS input and output
TTL inputs
0
0
0
0.3×V
V
DD
0.8
Low-level input voltage, V
IL
V
Input voltage V
CMOS/TTL
V
DD
4
V
I
High-level output current, I
CMOS Drivers
CMOS Drivers
mA
mA
V
OH
Low-level output current, I
4
OL
High-level output voltage, V
I
I
= max, V
= min
0.8V
OH
OH
CC
= max
DD
Low-level output voltage, V
Input current
= min, V
CC
0.22V
V
OL
OL
DD
V = V
or 0
±1
µA
µA
I
CC
CC
High-impedance state output current, I
OZ
V = V
I
or 0
±10
4–1
4.3 Thermal Characteristics
PARAMETER
TEST CONDITION
0 fpm
MIN
TYP
MAX
UNIT
°C/W
°C/W
100.978
77.142
76.544
75.550
35.483
150 fpm
R
R
Junction-to-free-air thermal resistance
Junction-to-case thermal resistance
Air flow
θJA
θJC
250 fpm
500 fpm
4.4 Switching Characteristics, V
= 3.3 V, T = 25°C (see Note 3)
A
CC
PARAMETER
MEASURED
50% to 50%
TEST CONDITION
See Figure 4–1
See Figure 4–1
See Figure 4–1
MIN
TYP
MAX
UNIT
ns
t
t
t
D, CTL, LREQ low or high before SCLK high
6
su
D, CTL, LREQ low or high after SCLK high
Delay time, SCLK high to D, CTL high or low
50% to 50%
50% to 50%
0
ns
h
0.5
13.5
ns
d
NOTE 3: These parameters are ensured by design and are not production tested.
SCLK
t
t
h
su
D, CTL, LREQ
D, CTL, LREQ Input Setup and Hold Times Waveforms
SCLK
t
d
D, CTL
D, CTL Output Delay Relative to SCLK Waveforms
Figure 4–1. Parameter Measurement Information
4–2
5 Application Information
5.1 Transceiver Selection
The system designer must select transceivers appropriate for the TSB14AA1 and the link layer selected. The
following are requirements for the transceivers needed:
•
The transceivers used must be appropriate to the backplane technology used.
–
The various backplane technologies require different electrical characteristics in their backplanes. For
example, gunning transceiver logic (GTL) uses an operating voltage on the backplane of 1.2 V and a
characteristic impedance of 50 Ω [1] while low-voltage differential signaling (LVDS) uses an operating
voltage of 2.4 V and a difference impedance of 100 Ω [2]. If a backplane is designed to use GTL
technology, then it would be appropriate to also use that technology for the two lines dedicated to the
1394 serial bus. The drivers selected also must be able to supply the current required for the expected
backplaneloading. Forexample, backplanetransceiverlogic(BTL)operatescorrectlyforaFutureBus+
[3] configuration backplane at 50 Mbits/s or for a limited number of nodes in a custom configuration at
100 Mbits/s.
•
The transceivers used must be able to monitor the bus and drive the bus at the same time.
–
During arbitration, each node that is arbitrating for the bus drives its priority code and then its node
number out onto the bus. During each bit period, each node reads back what has been placed on the
bus. If it reads the same data it was sending, the arbitrating node stays in contention for winning the bus.
Ifitreadssomethingdifferentthanwhatitwasdriving, thearbitratingnodelosesthebusanddropsoutof
contention. As long as each node is still sending 0s onto the bus during arbitration, all nodes are still
contending to win the bus. The node with the highest priority (or if all priorities were 0, then the highest
node number) is the first to drive a 1 onto the bus during arbitration. The node that sends the first 1
(asserting the bus) and reads it back wins the bus. All other nodes read back a 1, which does not match
the 0 (releasing the bus) they are sending, and drop out of contention. This arbitration process requires
the transceiver selected to be able to read from the bus at the same time it is driving the bus.
•
•
The transceivers used must be appropriate for the transfer speed required.
–
The 1394 bus has two data lines that use data-strobe encoding on the bus. This requires that the
transceivers be able to operate at a maximum frequency of one half of the maximum data transfer rate.
When operating at 49.152 Mbits/s, the maximum frequency the drivers are required to operate at is
24.576 MHz. When operating at 98.304 Mbits/s, the maximum frequency the drivers are required to
operate at is 49.152 MHz.
Recommended transceivers:
–
When the designer has a choice of transceiver, the open collector transceiver SN74GTLP1394 [4] is
recommended. This is the device used to verify lab operation at both S50 and S100 data rates.
–
When the designer must choose a differential transceiver, the 3-state transceiver SN65LVDM176 [5] is
recommended. This device was also used to verify lab operation at both S50 and S100 data rates.
[1] GTL/BTL a Low Swing Solution for High-Speed Digital Logic (SCEA003)
(2] Low-Voltage Differential Signaling (LVDS) Design Notes (SLLA014)
[3] IEEE Std 896.1–1991, IEEE Standard for FutureBus+—Logical Protocol Specification
[4] SN74GTLP1394, 2-Bit LVTLL-to-GTLP Adjustable-Edge Rate Bus Transceiver With Selectable Polarity data sheet (SCES286A)
[5] SN65LVDM176, High-Speed Differential Line Transceiver data sheet (SLLS320D)
5–1
–
–
–
When the designer must choose a backplane transceiver logic (BTL) transceiver, the FutureBus+
transceiver SN74FB2041A [6] is recommended.
When the designer must choose a VERSA module Eurocard (VME) bus transceiver, the VME1395 is
recommended (to be released).
When the designer must choose a high speed 5-V transistor-transistor logic (TTL) transceiver, the
SN74BCT756 [7] is recommended.
Refer to application report TSB12LV01B/TSB14AA1 Reference Schematic [8] and application report
TSB14AA1/Transceivers Reference Schematic [9] for more information.
5.2 Link Selection
The system designer must select links appropriate for the TSB14AA1 and the host interface selected. The following
are requirements for the LLCs needed:
•
•
Using the TSB14AA1 at 100 Mbits/s, any 1394 cable link layer can be used.
Using the TSB14AA1 at 50 Mbits/s, it is appropriate to use the TSB12LV01B, TSB12LV32 (GP2Lynx), or
TSB12LV21B (PCILynx), depending on the host-link interface. For example:
–
–
–
TSB12LV01B has a 32-bit data bus and is used most appropriately with a host that has 32 or 64-bit data
bus.
TSB12LV32 is designed for interface with a Motorola-type microprocessor and should be used for an 8
or 16-bit host.
TSB12LV21B is best used if the host is the PCI bus.
It is necessary to verify that the CLK on the PHY-link interface is faster than the CLK on the link-host interface, based
on LPS low time and detecting SCLK.
5.3 Layout Recommendation
A local clock (either 98.304 MHz for S100, or 49.152 MHz for S50) is used for the synchronization of the TSB14AA1
state machine within the PHY logic. The source of this clock must be placed as close as possible to PHY pin XI. The
greater the distance, the more the chance of interference from noise. The local clock reference signal is internally
divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information
and system clock (SCLK) sent to the link layer to synchronize the PHY-link interface.
The PHY-link interface (SCLK, LREQ, CTL[0,1], and D[0,1]) must be short (less than 4 inches if practical). The signals
driven across the PHY-link interface are at 3.3 V, but are at 49.152 MHz and should be treated with due care. These
signals should also be approximately the same length. The short distance is to minimize noise coupling from other
devices and signal loss due to resistance. They should be kept the same length to reduce propagation delay
mismatches across this synchronous interface. Refer to RecommendationsforPHYLayout [10] for more information.
TheTSB14AA1requiresanexternal98.304-MHzreferenceoscillatorinputforS100operationor49.152-MHzforS50
operation. Because of the frequencies involved (up to 49.152 MHz system clock at 100 Mbps) the etches propagating
the DATA and STRB signal in the backplane should be treated as transmission lines.
[6] SN74FB2041A, 7–Bit TTL/BTL Transceiver data sheet (SCBS172J)
(7] SN74BCT756, Octal Buffer/Driver With Open-Collector Inputs (SCBS056B)
[8] TSB12LV01B/TSB14AA1 Reference Schematic (SLLS465)
[9] TSB14AA1/Transceivers Reference Schematic (?????????)
[10] Recommendations for PHY Layout (SLLA020A)
5–2
5.4 Using the EX_ID and EX_PRI Pins
During arbitration, each node that is arbitrating for the bus drives its priority code and then its arbitration number out
onto the bus. The most significant bit (MSB) of the priority field is transmitted first. The least significant bit (LSB) of
the priority field is followed by the MSB of the arbitration number. The lowest priority level (all zeroes) is reserved for
fair arbitration, and the highest priority level (all ones) is reserved for the identification of the cycle start packet. The
node with the highest priority (or if all priorities were zero, the highest node number) is the first to drive a 1 onto the
bus during arbitration. The node that sends the first 1 and reads it back wins the bus. In the TSB14AA1, the priority
code and arbitration number can be set externally through the EX_PR and EX_ID pins. Upon hardware reset or
SWHRST, the 4-bit priority code and 6-bit physical_ID are reinitialized to the external pin values. However, unlike the
equivalent field in the cable environment, the priority and physical_ID in the backplane environment is writeable. The
priority code and physical_ID of each node can be reassigned to different values other than the external pin values
after the hardware reset or SWHRST.
5.5 Testability and Debug
The TSB14AA1 offers an extensive testability and debug function. The TSB14AA1 offers the following testability
enhancements:
•
•
•
Register 0000b may have all eight bits written to and read from for verification of stuck at bits or pins. Note
that bits 6 and 7 must be at a logical low (0) for correct normal operation.
Register 0010b contains the physical ID that last won the bus (sent the last packet). Note that after a robust
bus reset this field becomes all ones.
Register 0011b contains the currently captured values of the received data and received strobe pins on the
device for verification of the recent state of the 1394 bus. It also contains the state of the CLK_SEL0 and
CLK_SEL1 pins to verify correct setup of the TSB14AA1.
•
•
•
•
Register 0101 contains the product identifier for the TSB14AA1. This allows software to verify the revision
of the part that is installed in a system.
Register 0110b contains the priority of the last packet sent on the bus. Note that after a robust bus reset
this field becomes all ones.
Register 0111b may be used to verify the state of the pins TDATA, TSTRB, OCDOE, and TDOE by reading
the bits with the same name.
Register 0111b, in combination with register 0011b and the M-TEST pin, may be used to verify the
connectivity of the 14AA1, the transceiver selected and the 1394 bus. Note that this test will break the 1394
bus by driving DC states on the bus. Normal operation is not possible when this test mode is invoked. The
connectivity test is performed as follows:
1. Set the M_TEST pin to the HIGH state, to hardware enable this testing mode. To enable this, use a
jumper, dip switch, or higher layer GPIO.
2. Set the ENDLS bit to 1 via register write, to software enable the DC driving of the TDATA, TSTRB,
OCDOE, and TDOE pins.
3. With the M_TEST pin and ENDLS register bit set to 1, write 0 to DDLS.
4. Verify the TDATA bit reads 0 and RDATA bit reads 0
5. With the M_TEST pin and ENDLS register bit set to 1, write 1 to DDLS.
6. Verify the TDATA bit reads 1 and RDATA bit reads 1
7. With the M_TEST pin and ENDLS register bit set to 1, write 0 to DSLS.
8. Verify the TSTRB bit reads 0 and RSTRB bit reads 0
9. With the M_TEST pin and ENDLS register bit set to 1, write 1 to DSLS.
10. Verify the TSTRB bit reads 1 and RSTRB bit reads 1
11. To return to normal operation, set the M_TEST pin to 0 and set the ENDLS register bit to 0. The RDATA,
RSTRB, TDATA, TSTRB, TDOE, and OCDOE bits will still be operational since they are read-only bits.
5–3
5–4
6 Principles of Operation
6.1 PHY/Link Interface Operation
The TSB14AA1 is designed to operate with link layer controllers (LLC) such as the Texas Instruments TSB12LV01B,
TSB12LV21B, and TSB12LV32. Details of operation for the Texas Instruments LLC devices are found in the
respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface.
The interface to the LLC consists of the SCLK, CTL0–CTL1, D0–D1, LREQ, LPS, and LINKON terminals on the
TSB14AA1, as shown in Figure 6–1.
TSB14AA1
SCLK
Link Layer
Controller
CTL0 – CTL1
D0 – D1
LREQ
LPS
LINKON
Figure 6–1. Block Diagram of the TSB14AA1/LLC Interface
The SCLK terminal provides either a 49.152-MHz interface clock for S100 data transfers or 24.576-MHz interface
clock for S50 data transfers. All control and data signals are synchronized to, and sampled on, the rising edge of
SCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB14AA1 and the LLC.
The D0 and D1 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB14AA1 supports S50 and S100 data transfers over the D0
and D1 data bus.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to read or write internal PHY registers, or to ask the PHY to initiate a transmit action. The PHY initiates a receive action
whenever a packet is received from the serial bus.
The LPS and LINKON terminals are used for power management of the PHY and LLC. The LPS terminal indicates
the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SCLK. The LINKON
terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC when LPS is inactive.
NotethatnotallLLCscontainaLINKONterminal, thoughanexternalcircuittooperatethewake-upmodemayalways
be implemented at the discretion of the designer.
The TSB14AA1 normally controls the CTL0–CTL1 and D0–D1 bidirectional busses. The LLC is allowed to drive these
buses only after the LCC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a link service request to read or write a PHY register, or to request the
PHY to gain control of the serial-bus in order to transmit a packet.
The PHY may initiate a status transfer either autonomously or in response to a register request from the LLC.
The PHY initiates a data transmit operation after winning control of the serial-bus following a bus-request by the LLC.
The data transmit operation is initiated when the PHY grants control of the interface to the LLC.
The PHY initiates a data receive operation whenever a packet is received from the serial-bus.
The encoding of the CTL0–CTL1 bus is shown in Table 6–1 and Table 6–2.
6–1
Table 6–1. CTL Encoding When PHY Has Control of the Bus
CTL0
CTL1
NAME
Idle
DESCRIPTION
No activity (this is the default mode)
0
0
1
1
0
1
0
1
Status
Receive
Grant
Status information is being sent from the PHY to the LLC.
An incoming packet is being sent from the PHY to the LLC.
The LLC has been given control of the bus to send an outgoing packet.
Table 6–2. CTL Encoding When LLC Has Control of the Bus
DESCRIPTION
CTL0
CTL1
NAME
Idle
Hold
0
0
0
1
The LLC releases the bus (transmission has been completed).
The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to
be transmitted (concatenated) without arbitrating.
1
1
0
1
Transmit
An outgoing packet is being sent from the LLC to the PHY.
Reserved
Reserved
When the link needs to request the bus or access a register that is located in the TSB14AA1 PHY, a serial stream
of information is sent across the LREQ line. The length of the stream varies depending on whether the transfer is a
bus request, a read command, or a write command (see Table 6–3). Regardless of the type of transfer, a start bit of
1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the MSB,
and is transmitted first. The LREQ line is required to idle low (logic level 0).
Table 6–3. Request Bit Length
REQUEST TYPE
Bus request (cable)
NUMBER OF BITS
7
11
9
Bus request (backplane)
Read register request
Write register request
17
For a bus request in the cable environment, the length of the LREQ data stream is 7 bits as shown in Table 6–4.
Table 6–4. Bus Request for Cable Environment
BIT(s)
0
NAME
Start bit
DESCRIPTION
Indicates the beginning of the transfer (always 1)
1–3
4–5
Request type
Indicates the type of bus request (see Table 6–8 for the encoding of this field)
Request speed
Indicates the speed at which the PHY sends the packet for this request. This field has the same encoding as the
speed code from the first symbol of the receive packet. See Table 6–5 for the encoding of this field. This field can be
expanded to support data higher than 400 Mbit/s in the future.
6
Stop bit
Indicates the end of the transfer (always 0).
The 14AA1 will accept an LREQ transfer bus request in the backplane format. This request is 11 bits long and has
the format shown in Table 6–5. This is an optional feature of the backplane environment; it allows the priority of a
packet to be changed on a packet by packet basis. When using normal cable LREQs that are 7 bits long, the packet
will have the priority contained in the priority register of the TSB14AA1. For this case to change the priority requires
software to change the value of the priority register inside the PHY.
6–2
Table 6–5. Bus Request for Backplane Environment
DESCRIPTION
BIT(s)
0
NAME
Start bit
Indicates the beginning of the transfer (always 1)
1–3
4–5
6–9
Request type
Indicates the type of bus request (see Table 6–8 for the encoding of this field)
Ignored (set to 00 for cable S100) for backplane environment
Request speed
Request priority Indicates the priority of urgent requests. It is only used with a FairReq request type. All zeros indicate a fair
request.
All ones are reserved (this priority is implied by a PriReq).
Other values are used to indicate the priority of an urgent request.
10
Stop bit
Indicates the end of the transfer (always 0)
For a Read Register Request the length of the LREQ data stream is 9 bits as shown in Table 6–6 (also see
Table 3–2 for the bit definitions).
Table 6–6. Read Request Format
BIT(s)
0
NAME
Start bit
DESCRIPTION
Indicates the beginning of the transfer (always 1).
1–3
4–7
8
Request type
Address
Always a 100 indicating that this is a read register request.
The address of the PHY register to be read.
Stop bit
Indicates the end of the transfer (always 0).
For a Write Register Request the length of the LREQ data stream is 17 bits as shown in Table 6–7 (see Table 3–1
for the bit field format).
Table 6–7. Write Request Format
BIT(s)
0
NAME
Start bit
DESCRIPTION
Indicates the beginning of the transfer (always 1)
1–3
4–7
Request type
Address
Always 101b indicating that this is a write register request
The address of the PHY register to be written to
The data that is to be written to the specified register address
Indicates the end of the transfer (always 0)
8–15 Data
16 Stop bit
The 3-bit request field is defined in Table 6–8.
Table 6–8. Request Field
LREQ1 LREQ2 LREQ3
NAME
ImmReq
DESCRIPTION
0
0
0
1
0
1
Immediate request. When an idle is detected, the PHY takes control of the bus immediately
(no arbitration).
Fair/Urgent Req
Fair or urgent request. The PHY arbitrates after a subaction gap using fair protocol.
Fair/Urgent Req is used for fair transfers with the request priority field differentiating fair and
urgent transfers for the backplane environment.
1
1
1
1
0
0
1
1
0
1
0
1
RdReq
WrReq
Read register. Returns the specified register contents through a status transfer.
Write register. Writes to the specified register.
Reserved
Reserved
LREQ Timing is shown in Figure 6–2. Each cell represents one clock sample time.
6–3
LReq0 LReq1 LReq2 LReq3
LReqN
Figure 6–2. LREQ Timing
6.1.1 Bus Request
For fair or priority access, the link requests control of the bus at least one clock cycle after the PHY–link interface
becomes idle. When the link senses that the CTL terminals are in a receive state (CTL0 and CTL1 = 10), then it knows
that its request has been lost. This is true anytime during or after a bus request transfer by the link. Additionally, the
PHY ignores any fair requests if it asserts the receive state while the link is requesting the bus. When the link finds
the CTL terminals in a receive state, the link reissues the bus request transfer one clock cycle after the next interface
idle.
To send an acknowledge, the link must issue an ImmReq request during the reception of the packet addressed to
it. This is required because the delay from end-of-packet to acknowledge requests adds directly to the minimum delay
everyPHYmustwaitaftereverypackettoallowanacknowledgetooccur. Afterthepacketends, thePHYimmediately
takes control of the bus and grants the bus to the link. If the header cyclic redundancy check (CRC) of the packet turns
out to be bad, the link releases the bus immediately. The link cannot use this grant to send another type of packet.
To ensure this, the link must wait 160 ns after the end of the received packet to allow the PHY to grant it the bus for
the acknowledgement, and then the link releases the bus and proceeds with another request.
Although improbable, it is conceivable that two separate nodes can believe that an incoming packet is intended for
them. The nodes then issue an ImmReq request before checking the CRC of the packet. Since both PHYs seize
control of the bus at the same time, a temporary, localized collision of the bus occurs. As soon as the two nodes check
the CRC, the mistaken node drops its request and the false line is removed. The only side effect is the loss of the
intended acknowledgement packet (this is handled by the higher-layer protocol).
Once the link issues an immediate, fair, or urgent request for access to the bus it cannot issue another request until
the PHY indicates a lost (incoming packet) or won (transmit) signal. The PHY ignores new requests while a previous
request is pending.
6.1.2 Read/Write Requests
For read requests (see Table 6–6), the PHY returns the contents of the addressed register at the next opportunity
through a status transfer. For write requests, the PHY takes the value in the data field (see Table 6–7) of the transfer
and loads it into the addressed register as soon as the transfer is complete. When the status transfer is interrupted
by an incoming packet, the PHY continues to attempt the transfer of the requested register until it is successful.
6.1.3 Status
When the PHY has status information to transfer to the link, it initiates a status transfer. The PHY waits until the
interface is idle to perform the transfer. The PHY initiates the transfer by asserting status (01) on the CTL terminals,
along with the first two bits of status information on D0 and D1. The PHY maintains CTL status for the duration of the
status transfer. The PHY can temporarily halt a status transfer by asserting something other than status on the CTL
terminals. This is done in the event that a packet arrives before the status transfer completes. There must be at least
one idle cycle between consecutive status transfers.
The PHY normally sends only the first 4 bits of status to the link. These bits are status flags that are needed by link
statemachines. ThePHYsendsanentirestatuspackettothelinkafterarequesttransferthatcontainsareadrequest.
The definition of the bits in the status transfer are shown in Table 6–9 (also see Table 3–1 and Table 6–6). Status
transfer timing is shown in Figure 6–3.
6–4
Table 6–9. Status Bit Description
DESCRIPTION
BIT(s)
NAME
Arbitration
0
IndicatesthatthePHYhasdetectedthatthebushasbeenidleforanarbitrationresetgaptime. Thistimeisdefined
†
Reset Gap
in the 1394–1995 standard . This bit is used by the link in its busy/retry state machine.
1
Subaction Gap
Indicates that the PHY has detected that the bus has been idle for a subaction gap time. This time is defined in the
1394 standard.
2
3
Bus Reset
Reserved
Address
Indicates that the PHY has entered the bus reset state
Reserved
4–7
Holds the address of the PHY register whose contents are transferred to the link
Indicates the data that is to be sent to the link
8–15 Data
†
IEEE Std 1394–1995, IEEE Standard for a High Performance Serial Bus
PHY
00
00
00
01
01
01
00
00
00
00
Ctl[0:1]
PHY
00
S[0,1]
S[2,3]
S[14,15]
D[0:1]
Figure 6–3. Status Transfer Timing
6.1.4 Transmit
When the link requests access to the serial bus through the LREQ terminal, the PHY arbitrates for access to the serial
bus. When the PHY wins the arbitration, it grants the bus to the link by asserting transmit on the CTL terminals for
one SCLK cycle, followed by idle for one cycle. After sampling the transmit state from the PHY, the link takes over
control of the interface by asserting either hold or transmit on the CTL terminals. The link asserts hold to keep
ownership of the bus while preparing data. The PHY asserts the data-on state on the serial bus during this time. When
it is ready to begin transmitting a packet, the link asserts transmit on the CTL terminals along with the first bits of the
packet. After sending the last bits of the packet, the link asserts either idle or hold on the CTL terminals for one cycle,
and then idle for one additional cycle before asserting those terminals to a high-impedance state.
The hold state indicates to the PHY that the link needs to send another packet without releasing the bus. The PHY
responds to this hold state by waiting the required minimum time and then asserting transmit as before. This function
is used after sending an acknowledgement if the link intends to send a unified response, during a single cycle. The
only requirement when sending multiples packet during bus ownership is that all packets must be transmitted at the
same speed, since the speed of the packet transmission is set before the first packet.
As noted above, when the link has finished sending the last packet for the current bus ownership, it releases the bus
by asserting idle on the CTL terminals for two SCLK cycles. The PHY begins asserting idle on the CTL terminals one
clock cycle after sampling the second idle from the link. Whenever the D and CTL links change ownership between
thePHYandthelink, thereisanextraclockperiodallowedsothatbothsidesoftheinterfacecanoperateonregistered
versions of the interface signals, rather than having to respond to a CTL state on the next cycle.
It is not required that the link enter the hold state before sending the first packet when implementation permits the
link to be ready to transmit as soon as bus ownership is granted. The timing of a single packet transmit operation is
shown in Figure 6–4. In the diagram, D0–Dn are the data symbols of the packet, ZZ represents the high-impedance
state.
6–5
Single Packet
PHY Cti [0:1]
00
00
ZZ
11
00
00
00
ZZ
ZZ
01
00
ZZ ZZ
ZZ ZZ
ZZ ZZ
ZZ ZZ
ZZ
ZZ
10
ZZ ZZ
ZZ ZZ
00
00
ZZ
ZZ
PHY D [0:7]
Link Cti [0:1]
Link D [0:7]
ZZ ZZ
01
00
10
10
10
00
00
00
ZZ ZZ ZZ
D0 D1
D2
Dn 00
Continued Packet
PHY Cti [0:1]
ZZ
ZZ ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
00
00
11
00
00
00
ZZ
ZZ
ZZ
ZZ
01
00
ZZ ZZ
ZZ ZZ
ZZ
ZZ
10
D1
PHY D [0:7]
Link Cti [0:1]
Link D [0:7]
ZZ ZZ ZZ
10
10 01
ZZ ZZ
01
00
10
Dn-1 Dn 00
ZZ
ZZ
D0
ZZ = High- Impedance State
D0 = > Dn = Packet Data
Figure 6–4. Transmit Timing
6.1.5 Receive
When data is received by the PHY from the serial bus, it transfers the data to the link for further processing. The PHY
asserts receive (see Table 6–1) on the CTL lines and asserts each D terminal high. The PHY indicates the start of
the packet by placing the speed code on the data bus. The PHY then proceeds with the transmission of the packet
to the link on the D lines while keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the PHY asserts idle on the CTL terminals, which completes the receive operation (see Figure 6–5).
NOTE:The speed code is a PHY-link protocol and is not included in the CRC.
PHY
00
00
10
11
10
00
00
00
00
10
11
10
10
10
Ctl[0:1]
PHY
SPD
D0
D1
Dn
D[0:1]
NOTE A: SPD = Speed Code (for the backplane, this speed is fixed at D0, D1 = 00)
D0 to Dn = Packet data
Figure 6–5. Receive Timing
6–6
6.2 Backplane Environment
6.2.1 Backplane PHY Connection
Typically within a single ended signaling backplane environment, the serial bus is implemented with a pair of signals
(STRB and DATA). The topology is a simple pair of bussed signals as shown in Figure 6–6.
Backplane Chassis
Module
Node
Module
Node
Module
Module
Node
PHY
Node
Node
PHY
Node
PHY
PHY
PHY
PHY
STRB
DATA
Figure 6–6. Backplane Topology
NOTE: On a given bus, there can be as many as 63 nodes. There is no restriction on the
distribution of nodes throughout modules on the bus. When more than one node occupies a
module, they must share the same transceivers.
The backplane environment can be implemented with a number of different interface technologies. These include,
but are not limited to: industry-standard gunning transistor logic plus (GTLP), industry-standard transistor-transistor
logic (TTL), backplane transceiver logic (BTL) as defined by IEEE Std 1194 [10] and emitter-coupled logic (ECL).
In addition to the requirements specified by the application environment, the physical media or the serial bus should
meet the requirements defined for media attachment, media signal interface, and media signal timing. Timing
requirements must be met over the ranges specified in the application environment. These include temperature
ranges, voltage ranges, and manufacturing tolerances.
6.2.2 Definition of Logic States
In the open collector environment, the drivers assert the bus to indicate a 1 logic state, or release the bus to indicate
a 0 logic state. To assert the bus, an open collector driver sinks current. To release the bus, drivers are asserted to
a high-impedance state or turned off, allowing the bus signal to be pulled to the termination voltage of the bus.
NOTE: This typically results in a logical inversion of signals on GTLP, TTL and BTL buses.
Signals on ECL buses typically are not inverted.
All drivers operate in a wired-ORed mode during arbitration. Drivers can operate in a totem pole mode during data
packet and acknowledge transfers. In this mode, a driver can drive the bus into its released state to decrease the rise
time of the bus signal (referred to as a rescinding release with TTL technology).
6.2.3 Bit Rates
Data transmission and reception occurs at 49.152 Mbit/s or 98.304 Mbit/s (±100 ppm). In normal operation,
regardless of the interface technology, arbitration occurs at an arbitration clock rate of 49.152 MHz.
[10] IEEE Std 1194.1–1991, IEEE Standard for Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits
6–7
6.2.4 Backplane Transmit Data Timing
Edge separation is the minimum required time between any two consecutive transitions of the backplane bus signals,
as they appear from the output of the transmitters, whether they are transitions on the same signal or transitions on
the two separate signals. A minimum edge separation is required to ensure proper operation of the data strobe
bit-level encoding mechanism. TDATA and TSTRB have the relationship shown in Figure 6–7 and Table 6–10.
t
t
t
t
(1)
(1)
(1)
(1)
TDATA
TSTRB
t
(2)
t
t
(2)
(2)
t
(2)
Figure 6–7. Minimum Edge Separation
Table 6–10. TSB14AA1 to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t
t
Bit cell period for data
9.44 ns minimum
8.65 ns minimum
19.44 ns minimum
18.65 ns minimum
(1)
†
Transmit (Tx) edge separation
(2)
†
This parameter is based on a maximum total transmit skew of 2 ns.
6.2.5 Backplane Receive Data Timing
The receiver typically uses the transitions on the incoming bus signals RDATA and RSTRB to derive a clock at the
code bit frequency to extract the NRZ signal on RDATA. This clock can be derived by performing an exclusive-OR
(XOR) of RDATA and RSTRB.
The bus signals, as they appear from the backplane transceiver media and into the receiver, should fall within the
timing constraints outlined by Figure 6–8.
t
t
t
t
(1)
(1)
(1)
(1)
RDATA
RSTRB
t
(3)
t
t
(2)
(2)
t
(3)
Figure 6–8. Backplane Receive Data Timing
Table 6–11. TSB14AA1 to Backplane Transceiver Timing
PARAMETER
Bit cell period
98.304 MHz
10.1715 ns nominal
3.4 ns minimum
16.3 ns maximum
49.152 MHz
20.34 nominal
t
t
t
(1)
(2)
(3)
†
3.4 ns minimum
36.6 ns maximum
Receive (Rx) edge separation
†
†
Thisparameterisbasedonamaximumtotaltransmitskewof2nsandamaximumbackplaneskewof0.5 ns.
This assumes total receive skew is less than receive edge separation (i.e., some skew margin exists).
6–8
6.2.6 Backplane Timing Definitions
•
•
•
•
•
•
Logic Skew—The skew between data and strobe within the physical layer itself due to internal skews
between data and strobe logic.
Spatial Skew—The skew between data and strobe due to differences in propagation delays along the
transmission line from the arbiter to the transceiver.
Package Skew—The propagation delay difference through the transceiver between the data and strobe
channels.
Backplane Skew—The skew along the backplane itself due to impedance and/or mismatched data and
strobe line length.
Receive Setup/Hold—The setup and hold time needed to latch the incoming data within the PHY arbiter,
based on the recovered clock from Data_Rx and Strb_Rx.
Total Transmit Skew—The total skew between data and strobe in transmitting data from the PHY out to the
bus. This is given by the following equation:
Total Transmit Skew = Transmit Package Skew + Spatial Skew + Logic Skew
•
Total Receive Skew—The total skew between data and strobe in receiving data from the bus into the PHY.
This is given by the following equation:
Total Receive Skew = Receive Package Skew + Spatial Skew + Receive Setup + Receive Hold
Skew Margin—The bit cell period minus all skews. This is given by the following equation:
Skew Margin = Bit Cell Period – Total Transmit Skew – Backplane Skew – Total Receive Skew
•
•
Transmit Edge Separation—The minimum time required between any two consecutive transitions of the
bus signals to ensure proper operation of data-strobe bit level encoding. Transmit edge separation is
measured from the midpoint of the signal transition to the midpoint of the next signal transition out on the
bus. Minimumtransmitedgeseparationistheminimumbitcellperiodlessthemaximumtotaltransmitskew.
•
Receive Edge Separation—The minimum time required between any two consecutive transitions of the bus
signals to ensure proper operation of data-strobe bit level decoding. Receive edge separation is measured
from the midpoint of the signal transition to the midpoint of the next signal transition out on the bus. This
is the minimum bit cell period reduced by the amount of maximum total transmit skew and maximum
backplane skew.
6.2.7 Gap Timing
A gap is a period of time during which the bus is idle (Data_Rx and Strb_Rx are unasserted). There are three types
of gaps:
•
Acknowledge Gap—Appears between the end of a packet and an acknowledge, as well as between
isochronous transfers. A node should detect the occurrence of an acknowledge gap after the bus has been
in an unasserted state for 4 arbitration clock times (approximately 81.38 ns) but should not assert the bus
until a total of 8 arbitration clock times (approximately 182.76 ns) have occurred. This requirement ensures
that a node is given adequate time to detect the acknowledge gap before the bus is asserted by another
node upon detecting an acknowledge gap. This includes the minimum time required to detect a Bus_Idle
(4 arbitration clock times), as well as the maximum delay between the arbitration state machine within any
two nodes on the bus (another 4 arbitration clock times).
•
Subaction Gap—Appears before asynchronous transfers within a fairness interval. A node should detect
the occurrence of a subaction gap after the bus has been in an unasserted state for at least 16 arbitration
clock times (approximately 325.52 ns), but should not assert the bus until a total of 20 arbitration clock times
(approximately 406.9 ns) have occurred. This requirement ensures that a node is given adequate time to
6–9
detect the subaction gap before the bus is asserted by another node (upon detecting a subaction gap). The
duration of the subaction gap ensures that another node asserting the bus after an acknowledge gap has
been detected by this time.
•
Arbitration Reset Gap—Appears before asynchronous transfers when the fairness interval starts. A node
should detect the occurrence of an arbitration reset gap after the bus has been in an unasserted state for
at least 28 arbitration clock times (approximately 569.66 ns), but should not assert the bus until a total of
32 arbitration clock times (approximately 651.04 ns) have occurred. This requirement ensures that a node
is given adequate time to detect the arbitration reset gap before the bus is asserted by another node (upon
detecting an arbitration reset gap). The duration of the arbitration reset gap ensures that another node
asserting the bus after a subaction gap or an acknowledge gap has been detected by this time.
If a node is waiting for the occurrence of a particular gap and the bus has become idle for the specified time
(e.g., 32 arbitration clock times for an arbitration reset gap), the node detects the gap and asserts the bus.
An asserted signal propagates through the node decision/transceiver circuitry and onto the bus soon
enough to allow arbitration to occur properly.
6.3 Arbitration Sequence
The TSB14AA1 uses a particular arbitration sequence to arbitrate the bus between competing modules. The
sequence used consists of a 4-bit priority field and a 6-bit arbitration number field.
6.3.1 Priority
Within the arbitration sequence, the arbitration number is preceded by four bits that define a priority level. The method
by which priority is assigned is to be determined by the system integrator with two exceptions. The lowest priority (all
zeros) is reserved for fair arbitration and the highest priority (all ones) is reserved for cycle start requests. This allows
14 priority levels to be used for the urgent arbitration process.
The use of an urgent priority class allows nodes to be granted a large portion of the bandwidth on the bus. High priority
nodes are granted the bus before lower priority nodes during urgent allocation of the bus, allowing such nodes to be
granted more bandwidth.
In order to ensure forward progress, the lowest priority level is reserved for fair arbitration. This allows all nodes
arbitrating with this priority level to be allowed one fair access to the bus for each fairness interval. For fair arbitration,
the value of the arbitration number has a minimal impact on the allocation of the bus. Although nodes with higher
arbitration numbers are granted the bus sooner, there is only a small decrease in latency.
6.3.2 Arbitration Number
The arbitration sequence uses a unique arbitration number for each module. This 6-bit number is the same as the
node Physical_ID. When less than 6-bits are provided for the arbitration number, they occupy the MSBs of the
arbitration number. The remaining bits are zero-filled. The MSBs are transmitted first.
NOTE: If the serial bus is contained within a host backplane, it is expected that the arbitration
number (i.e., Physical_ID) is set by the host backplane at power up (e.g., with a built-in slot
identifier or configuration mechanism).
This number is software programmable to facilitate testing and to allow for consistent system operation and
repeatability.
6–10
6.3.3 Arbitration Sequence Format
The following format for the arbitration sequence is used:
PRIORITY
ARBITRATION NUMBER
4-bits
6-bits
•
•
Each module on the backplane has unique 6-bit arbitration number that is equal to the nodes Physical_ID.
The arbitration number is preceded by four bits of priority. The MSB of the priority field is transmitted first.
The LSB of the priority field is followed by the MSB of the arbitration number.
•
•
Dynamic assignment of priority is accommodated.
The lowest priority level (all zeroes) is reserved for fair arbitration, and the highest priority level (all ones)
is reserved for the identification of the cycle start packet.
6.4 Arbitration
Unless a node is using immediate arbitration to access the bus (in which case there is no contention for the bus), it
is possible that more than one node can attempt to access the bus at a given time. Consequently, it is necessary for
a node to arbitrate for the bus in order to gain access to the bus.
NOTE: A node uses immediate arbitration to send an acknowledge. Since there is no
contention for the bus in this case, arbitration is not necessary. A node that is transmitting an
acknowledge does not arbitrate for the bus, but merely waits for an acknowledge gap to be
detected before it begins transmission. If a node is attempting to gain access to the bus without
using immediate access, it must first arbitrate for the bus.
Arbitration occurs in response to a PHY arbitration request from the link. Nodes begin arbitrating once the bus has
become idle for a predetermined amount of time (the appropriate gap indication occurs). Once this happens, nodes
begin a bit-by-bit transmission of their arbitration sequence.
A node can obtain access to the bus in a limited number of ways. Since some arbitration classes allow nodes to begin
arbitration before others, nodes arbitrating with certain arbitration classes can detect that the bus is busy before they
can begin to arbitrate. In this way, certain arbitration classes can be bypassed, e.g., fair and urgent nodes do not get
a chance to arbitrate when another node is sending an acknowledge.
The backplane environment supports the fair, urgent, and immediate arbitration classes.
6.4.1 Fairness Intervals
The fairness protocol is based on the concept of a fairness interval. A fairness interval consists of one or more periods
of bus activity separated by short idle periods called subaction gaps and is followed by a longer idle period known
as an arbitration reset gap. At the end of each gap, bus arbitration is used to determine the next bus owner. This
concept is shown in Figure 6–9.
Fairness
Interval N–1
Fairness
Interval N+1
Fairness Interval N
Owner B
arb data
Owner A
Owner M
arb data
arb
data
arb
arb
Subaction
Arbitration
Reset Gap
Arbitration
Reset Gap
Subaction Gaps
Figure 6–9. Fairness Interval
The implementation of the fair arbitration protocol is defined in terms of these fairness intervals as is discussed in
the following paragraphs.
6–11
6.4.2 Fair Arbitration
When using this arbitration class, an active node can send an asynchronous packet exactly once each fairness
interval. Once a subaction gap is detected, a node can begin arbitration when its Arbitration_Enable signal is set. The
Arbitration_Enable signal is set at the beginning of the fairness interval and is cleared when the node successfully
accesses the bus through fair arbitration. This disables further fair arbitration attempts by that node for the remainder
of the fairness interval. In the absence of urgent nodes, a fairness interval ends once all of the nodes attempting fair
arbitration have successfully accessed the bus. At this time, all of the fair nodes have their Arbitration_Enable signals
reset and cannot arbitrate for the bus. The bus remains idle until an arbitration reset gap occurs. Once this happens,
the next fairness interval begins. All of the nodes set their Arbitration_Enable signal and can begin to arbitrate for the
bus. This process is illustrated in Figure 6–10.
Fairness
Interval N–1
Fairness
Interval N+1
Fairness Interval N
arb
arb
arb
arb
Node A
Node B
Node C
Node A
Node B
Node B
Clear When Node Wins Arbitration
Note: Arbitration Number of A > B > C
Set at Arbitration Reset Gap
Figure 6–10. Fair Arbitration Timing
NOTE: A node sending a concatenated subaction does not reset its Arbitration_Enable bit.
6.4.3 Urgent Arbitration
The backplane environment enhances the fair priority algorithm by splitting access opportunities among nodes based
on two priority classes: fair and urgent. Nodes using an urgent priority can use up to three-fourths of the access
opportunities, with the remaining equally shared among nodes using the fair priority. All nodes are required to
implement the fair priority class, while the urgent priority class is optional. Packets are labeled as urgent when that
priority class is used.
The fair/urgent allocation uses the same fairness interval described in fair arbitration but accompanies the
Arbitration_Enable flag with an Urgent_Count. The fair/urgent method works as follows:
•
When the bus is idle for longer than an arbitration reset gap, a fairness interval begins and all nodes set
their Arbitration_Enable flags, while nodes implementing urgent priority set their Urgent_Count to three.
•
A node that is waiting to send a packet using the fair priority class should begin arbitrating after detecting
a subaction gap as long as its Arbitration _Enable flag is set. When its Arbitration_Enable flag is cleared,
it waits for an arbitration reset gap before it begins arbitrating. When such a node wins an arbitration contest,
it sends a packet without the urgent label and its Arbitration_Enable flag is cleared.
•
A node that is waiting to send a packet with urgent priority begins arbitrating after detecting a subaction gap
if its Urgent_Count is nonzero. When its Urgent_Count is zero, it waits for an arbitration reset gap before
it begins arbitrating. Whenever such a node wins an arbitration contest, it sends a packet with the urgent
label.
6–12
•
•
A node implementing urgent priority sets its Urgent_Count to three whenever an unlabeled (i.e., fair) packet
is transmitted or received. This includes received packets that are addressed to other nodes.
A node decrements its Urgent_Count whenever a packet with the urgent label is transmitted or received.
This includes received packets that are addressed to other nodes. This ensures that there is at most three
urgent packets for every fair packet. This does not ensure that every node using urgent priority obtains the
bus three times for each fairness interval. The node arbitrating with the highest priority always obtains the
bus before other nodes arbitrating with an urgent, but lower, priority.
In the presence of urgent nodes, a fairness interval ends after the final fair node and up to three remaining urgent
nodes have successfully accessed the bus. Since all fair nodes now have their Arbitration_Enable signals reset and
all urgent nodes have their Urgent_Count decremented to zero, none of the nodes can access the bus. The bus
remains idle until an arbitration reset gap has occurred, re-enabling arbitration on all nodes and starting the next
fairness interval. This process is illustrated in Figure 6–11, which illustrates a situation where there are three nodes
arbitrating for the bus with Physical_IDs such that A has the highest priority, B is in the middle priority, and C has the
lowest priority. Nodes A and C are using fair priority and node B is using urgent priority.
A Node Using The Urgent
Fairness
Fairness
Protocol Has a Higher Priority Than Any Fair Node
Interval N+1
Interval N–1
Fairness Interval N
Urgent
Packet
Urgent
Packet
Urgent
Packet
Fair
Urgent
Packet
Urgent
Packet
Urgent
Packet
Fair
Urgent
Packet
Urgent
Packet
Urgent
Packet
Packet
Packet
arb Node B arb Node B arb Node B arb Node A arb Node B arb Node B arb Node B arb Node C arb Node B arb Node B arb Node B
Node A
Arbitration_Enable
Urgent_Count Set
to 3 at Arbitration Reset Gap
Arbitration_Enable Set at
Urgent_Count Incremented
Arbitration Reset Gap
by 3 After a Fair Node (A) Wins
Arbitration and Sends a Packet
Node B
3
2
1
3
2
1
3
2
1
3
Urgent_Count
Node C
Arbitration_Enable
Urgent_Count Incremented
Urgent_Count Decremented
When Urgent Node Sends a Packet
by 3 After a Fair Node (C) Wins
Arbitration and Sends a Packet
Arbitration_Enable Set at
Arbitration Reset Gap
Note: Physical_ID of A > B > C
Figure 6–11. Urgent Arbitration
In the backplane environment, the natural priority is the concatenation of the 4-bit urgent priority level with the
Physical_ID. These results are listed as follows.
•
•
•
A node using the urgent priority always wins an arbitration contest over all nodes using the fair priority.
The node using the highest priority level wins the arbitration level.
When more than one node uses the highest priority level, then the one with the highest Physical_ID wins.
6.4.4 Immediate Arbitration
This arbitration class is used by nodes sending an acknowledge to a received packet. Transmission of the
acknowledge (beginning with a Data_Prefix) occurs as soon as an acknowledge gap is detected. This arbitration
class is referred to as immediate because an arbitration sequence is not transmitted to obtain access to the bus (i.e.,
the node does not actually arbitrate for the bus).
6.5 Reset
6.5.1 Backplane PHY Reset
Upon a power reset event (i.e., power up) registers and control and status registers (CSRs) associated with the
operation of the PHY are initialized to their default values. State machines associated with PHY operations are
initialized. The Bus_Reset signal is not transmitted on the bus by the PHY.
6–13
6.5.2 Bus Reset
Once a PHY control request of Bus_Reset is communicated from the node controller to the PHY the PHY
communicates a Bus_Reset onto the bus.
NOTE:SinceaPHYtransmittingaBus_ResetmustalsoreactaccordinglyoncetheBus_Reset
event is detected, its state machines do have the opportunity to advance beyond those of other
nodes. This ensures that all nodes are in a somewhat similar state after such a Bus_Reset
event.
Once a PHY detects that a Bus_Reset event has occurred on the bus, it communicates a bus reset status to the LLC.
The node controller initializes a bus reset by writing to the PHY control register with the IBR bit or IRBR bit set to 1.
The PHY hardware resets the IBR and IRBR bit to zero on detection of its own bus reset.
6.6 Live Insertion
It is up to the user to design the node or module to safely receive power from the particular backplane they are using
during a live insertion. But in principle, live insertion is supported and does not cause a bus reset event to occur.
6–14
7 Mechanical Information
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
M
0,08
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
7–1
7–2
相关型号：
TSB14C01APMG4
Line Transceiver, 2 Func, 2 Driver, 2 Rcvr, CMOS, PQFP64, PLASTIC, MS-026, TQFP-64
ROCHESTER
TSB14C01APMG4
IEEE 1394-1995, 5V, 1-Port, 50/100Mbps BACKPLANE Physical Layer Controller 64-LQFP 0 to 70
TI
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