TSC21020F-20MBSL2_技术文档

TSC21020F

Radiation Tolerant 32/40–Bit IEEE Floating–Point

DSP Microprocessor

Introduction

Atmel is manufacturing a radiation tolerant version of the The product is pin and code compatible with ADI

Analog Devices ADSP–21020 32/40–Bit Floating–Point product, making system development straight forward

DSP.

and cost effective, using existing development tools and

algorithms.

Features

D Superscalar IEEE Floating-Point-Processor

D Off-Chip Harvard Architecture Maximizes Signal Processing

Performance

D Multiply with Add & Subtract for FFT Butterfly

Computation

D Efficient Program Sequencing with Zero-Overhead

D 50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution

D 60 MFLOPS Peak, 40 MFLOPS Sustained Performance

D 1024-Point Complex FFT Benchmark : 0.975 ms

D Divide (y/x) : 300 ns

Looping : Single-Cycle Loop Setup

D Single-Cycle Register File Context Switch

D 23 ns External RAM Access Time for Zero-Wait-State, 40 ns

Instruction Execution

D Inverse Square Root (1/√x) : 450 ns

D IEEE JTAG Standard 1149.1 Test Access Port and On-Chip

D 32-Bit Single-Precision and 40-Bit Extended-Precision

Emulation Circuitry

IEEE Floating-Point Data Formats

D 223 CPGA package for breadboarding

D 256 Multi layer quad flat pack, flat leads, for flight models

D Full compatible with Analog Devices ADSP-21020

D Latch up immune

D 32-Bit Fixed-Point Formats, Integer and Fractional, with

80-Bit Accumulators

D IEEE Exception Handling with Interrupt on Exception

D Three Independent Computation Units : Multiplier, ALU,

and Barrel Shifter

D Dual Data Address Generators with Indirect, Immediate,

Modulo, and Bit Reverse Addressing Modes

D Two Off-Chip Memory Transfers in Parallel with Instruction

Fetch and Single-Cycle Multiply & ALU Operations

D Total dose better than 100 Krad (Si)

D SEU immunity better than 50 MeV/mg/cm²

D For 25 MHz specification, call factory

– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO

– Product licensed from Analog Devices Inc.

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TSC21020F

Functional Block Diagram

General Description

The TSC21020F is single-chip IEEE floating-point

processor optimized for digital signal processing

applications . Its architecture is similar to that of Analog

Devices’ ADSP-2100 family of fixed-point DSP

processors.

shifter perform single-cycle instructions. The units

are architecturally arranged in parallel, maximizing

computational throughput. A single multifunction

instruction executes parallel ALU and multiplier

operations. These computation units support IEEE

32-bit single-precision floating-point, extended

precision 40-bit floating-point, and 32-bit fixed-point

data formats.

1

Fabricated in a high-speed, low-power and radiation

tolerant CMOS process, the TSC21020F has a 50 ns

instruction cycle time. With a high-performance on-chip

instruction cache, the TSC21020F can execute every

instruction in a single cycle.

D Data Register File

A general-purpose data register file is used for

transferring data between the computation units and

the data buses, and for storing intermediate results.

This 10-port (16-register) register file, combined with

the TSC21020F’s Harvard architecture, allows

The TSC21020F features :

D Independent Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and

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TSC21020F

unconstrained data flow between computation units

and off-chip memory.

The TSC21020F includes a high performance

instruction cache that enables three-bus operation for

fetching an instruction and two data values. The cache

is selective-only the instructions whose fetches

conflict with program memory data accesses are

cached. This allows full-speed execution of core,

looped operations such as digital filter

multiply-accumulates and FFT butterfly processing.

D Single-Cycle Fetch of Instruction and Two

Operands

The TSC21020F uses a modified Harvard architecture

in which data memory stores data and program

memory stores both instructions and data. Because of

its separate program and data memory buses and

on-chip instruction cache, the processor can

simultaneously fetch an operand from data memory,

an operand from program memory, and an instruction

from the cache, all in a single cycle.

D Hardware Circular Buffers

The TSC21020F provides hardware to implement

circular buffers in memory, which are common in

digital filters and Fourier transform implementations.

It handles address pointer wraparound, reducing

overhead (thereby increasing performance) and

simplifying implementation. Circular buffers can

start and end at any location.

D Memory Interface

Addressing of external memory devices by the

TSC21020F is facilitated by on-chip decoding of

high-order address lines to generate memory bank

select signals. Separate control lines are also

generated for simplified addressing of page-mode

DRAM. The TSC21020F provides programmable

memory wait states, and external memory

acknowledge controls allow interfacing to peripheral

devices with variable access times.

D Flexible Instruction Set

The TSC21020F’s 48-bit instruction word

accommodates a variety of parallel operations, for

concise programming. For example, the TSC21020F

can conditionally execute a multiply, an add, a

subtract and a branch in a single instruction.

D Instruction Cache

1. It is fully compatible with Analog Devices ADSP-21020

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TSC21020F

Development System

The TSC21020F is supported with a complete set of

software and hardware development tools from Analog

Devices. The ADSP-21000 Family Development System

from Analog Devices includes development software, an

evaluation board and an in-circuit emulator.

language architectural features and incorporates

optimizing algorithms to speed up the execution of

code. It includes an extensive runtime library with

over 100 standard and DSP-specific functions.

D C Source Level Debugger

D Assembler

A full-featured C source level debugger that works

with the simulator or EZ-ICE emulator to allow

debugging of assembler source, C source, or mixed

assembler and C.

Creates relocatable, COFF (Common Object File

Format) object files from ADSP-21xxx assembly

source code. It accepts standard C preprocessor

directives for conditional assembly and macro

processing. The algebraic syntax of the ADSP-21xxx

assembly language facilitates coding and debugging

of DSP algorithms.

D Numerical C Compiler

Supports ANSI Standard (X3J11.1) Numerical C as

defined by the Numeric C Extensions Group. The

compiler accepts

C

source input containing

D Linker/Librarian

Numerical C extensions for array selection, vector

math operations, complex data types, circular

pointers, and variably dimensioned arrays, and

outputs ADSP-21xxx assembly language source code.

The Linker processes separately assembled object

files and library files to create a single executable

program. It assigns memory locations to code and to

data in accordance with a user-defined architecture

file that describes the memory and I/O configuration

of the target system. The Librarian allows you to

group frequently used object files into a single library

file that can be linked with your main program.

D ADSP- 21020 EZ-LAB Evaluation Board

The EZ-LAB Evaluation Board is a general-purpose,

standalone TSC21020F system that includes 32K

words of program memory and 32K words of data

memory as well as analog I/O. A PC RS-232

download path enables the user to download and run

programs directly on the EZ-LAB. In addition, it may

be used in conjunction with the EZ-ICE Emulator to

provide a powerful software debug environment.

D Simulator

The Simulator performs interactive, instruction-level

simulation of ADSP-21xxx code within the hardware

configuration described by a system architecture file.

It flags illegal operations and supports full symbolic

disassembly. It provides an easy-to-use, window

oriented, graphical user interface that is identical to

the one used by the ADSP- 21020 EZ-ICE Emulator.

Commands are accessed from pull-down menus with

a mouse.

D ADSP- 21020 EZ-ICE Emulator

This in-circuit emulator provides the system designer

with a PC-based development environment that

allows nonintrusive access to the TSC21020F’s

internal registers through the processor’s 5-pin JTAG

Test Access Port. This use of on-chip emulation

circuitry enables reliable, full-speed performance in

any target. The emulator uses the same graphical user

interface as the ADSP- 21020 Simulator, allowing an

easy transition from software to hardware debug. (See

“Target System Requirements for Use of EZ-ICE

Emulator” on page 27.)

D PROM Splitter

Formats an executable file into files that can be used

with an industry-standard PROM programmer.

D C Compiler and Runtime Library

The C Compiler complies with ANSI specifications.

It takes advantage of the TSC21020F’s high-level

REZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc.

Additional Information

This data sheet provides a general overview of system and programming reference information, refer to

TSC21020F functionality. For additional information on the ADSP-21000 Family Development Software Manuals

the architecture and instruction set of the processor, refer and the ADSP-21020 Programmer’s Quick Reference.

to the ADSP-21020 User’s Manual. For development

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TSC21020F

Architecture Overview

Figure 1 shows a block diagram of the TSC21020F. The multiplication as well as fixed-point multiply/add and

processor features:

multiply/subtract operations. Integer products are 64 bits

wide, and the accumulator is 80 bits wide. The ALU

performs 45 standard arithmetic and logic operations,

supporting both fixed-point and floating-point formats.

The shifter performs 19 different operations on 32-bit

operands. These operations include logical and

arithmetic shifts, bit manipulation, field deposit, and

extract and derive exponent operations.

D Three Computation Units (ALU, Multiplier, and

Shifter) with a Shared Data Register File

D Two Data Address Generators (DAG 1, DAG 2)

D Program Sequencer with Instruction Cache

D 32-Bit Timer

D Memory Buses and Interface

D JTAG Test Access Port and On-Chip Emulation Support

The computation units perform single-cycle operations ;

there is no computation pipeline. The three units are

connected in parallel rather than serially, via multiple-bus

connections with the 10-port data register file. The output

of any computation unit may be used as the input of any

unit on the next cycle. In a multifunction computation, the

ALU and multiplier perform independent, simultaneous

operations.

Computation Units

The TSC21020F contains three independent computation

units : an ALU,

a

multiplier with fixed-point

accumulator, and a shifter. In order to meet a wide variety

of processing needs, the computation units process data

in three formats : 32-bit fixed-point, 32-bit floating-point

and 40-bit floating-point. The floating-point operations

are single-precision IEEE-compatible (IEEE Standard

754/854). The 32-bit floating-point format is the standard

IEEE format, whereas the 40-bit IEEE extended-

precision format has eight additional LSBs of mantissa

for greater accuracy.

Data Register File

The TSC21020F’s general-purpose data register file is

used for transferring data between the computation units

and the data buses, and for storing intermediate results.

The register file has two sets (primary and alternate) of

The multiplier performs floating-point and fixed-point sixteen 40-bit registers each, for fast context switching.

Figure 1. TSC21020F Block Diagram

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TSC21020F

With a large number of buses connecting the registers to counter and loop stack. No explicit jump or decrement

the computation units, data flow between computation instructions are required to maintain the loop.

units and from/to off-chip memory is unconstrained and

free from bottlenecks. The 10-port register file and

Harvard architecture of the TSC21020F allow the

The TSC21020F derives its high clock rate from

pipelined fetch, decode and execute cycles.

Approximately 70% of the machine cycle is available for

following nine data transfers to be performed every

memory accesses ; consequently, TSC21020F systems

cycle :

can be built using slower and therefore less expensive

D Off-chip read/write of two operands to or from the

memory chips.

register file

D Two operands supplied to the ALU

Instruction Cache

D Two operands supplied to the multiplier

The program sequencer includes a high performance,

selective instruction cache that enables three-bus

operation for fetching an instruction and two data values.

This two-way, set-associative cache holds 32

instructions. The cache is selective (only the instructions

whose fetches conflict with program memory data

accesses are cached), so the TSC21020F can perform a

program memory data access and can execute the

corresponding instruction in the same cycle. The program

sequencer fetches the instruction from the cache instead

of from program memory, enabling the TSC21020F to

simultaneously access data in both program memory and

data memory.

D Two results received from the ALU and multiplier

(three, if the ALU operation is a combined

addition/subtraction).

The processor’s 48-bit orthogonal instruction word

supports fully parallel data transfer and arithmetic

operations in the same instruction.

Address Generators and Program Sequencer

Two dedicated address generators and a program

sequencer supply addresses for memory accesses.

Because of this, the computation units need never be used

to calculate addresses. Because of its instruction cache,

the TSC21020F can simultaneously fetch an instruction

and data values from both off-chip program memory and

off-chip data memory in a single cycle.

Context Switching

Many of the TSC21020F’s registers have alternate

register sets that can be activated during interrupt

servicing to facilitate a fast context switch. The data

registers in the register file, DAG registers and the

multiplier result register all have alternate sets. Registers

active at reset are called primary registers ; the others are

called alternate registers. Bits in the MODE1 control

register determine which registers are active at any

particular time.

The data address generators (DAGs) provide memory

addresses when external memory data is transferred over

the parallel memory ports to or from internal registers.

Dual data address generators enable the processor to

output two simultaneous addresses for dual operand reads

and writes. DAG 1 supplies 32-bit addresses to data

memory. DAG 2 supplies 24-bit addresses to program

memory for program memory data accesses.

The primary/alternate select bits for each half of the

register file (top eight or bottom eight registers) are

independent. Likewise, the top four and bottom four

register sets in each DAG have independent

primary/alternate select bits. This scheme allows passing

of data between contexts.

Each DAG keeps track of up to eight address pointers,

eight modifiers, eight buffer length values and eight base

values. A pointer used for indirect addressing can be

modified by a value in a specified register, either before

(premodify) or after (post-modify) the access. To

implement automatic modulo addressing for circular

buffers, the TSC21020F provides buffer length registers

that can be associated with each pointer. Base values for

pointers allow circular buffers to be placed at arbitrary

locations. Each DAG register has an alternate register that

can be activated for fast context switching.

Interrupts

The TSC21020F has four external hardware interrupts,

nine internally generated interrupts, and eight software

interrupts. For the external interrupts and the internal

The program sequencer supplies instruction addresses to timer interrupt, the TSC21020F automatically stacks the

program memory. It controls loop iterations and evaluates arithmetic status and mode (MODE1) registers when

conditional instructions. To execute looped code with servicing the interrupt, allowing five nesting levels of fast

zero overhead, the TSC21020F maintains an internal loop service for these interrupts.

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TSC21020F

An interrupt can occur at any time while the TSC21020F program memory data (PMD) and data memory data

is executing a program. Internal events that generate (DMD) buses are used for data associated with the two

interrupts include arithmetic exceptions, which allow for memory spaces. These buses are extended off chip. Four

fast trap handling and recovery.

data memory select (DMS) signals select one of four

user-configurable banks of data memory. Similarly, two

program memory select (PMS) signals select between

two user-configurable banks of program memory. All

banks are independently programmable for 0-7 wait

states.

Timer

The programmable interval timer provides periodic

interrupt generation. When enabled, the timer

decrements a 32-bit count register every cycle. When this

count register reaches zero, the TSC21020F generates an

interrupt and asserts its TIMEXP output. The count

register is automatically reloaded from a 32-bit period

register and the count resumes immediately.

The PX registers permit passing data between program

memory and data memory spaces. They provide a bridge

between the 48-bit PMD bus and the 40-bit DMD bus or

between the 40-bit register file and the PMD bus.

The PMA bus is 24 bits wide allowing direct access of up

to 16M words of mixed instruction code and data. The

PMD is 48 bits wide to accommodate the 48-bit

instruction width. For access of 40-bit data the lower 8

bits are unused. For access of 32-bit data the lower 16 bits

are ignored.

System Interface

Figure 2 shows an TSC21020F basic system configuration.

The external memory interface supports memory-

mapped peripherals and slower memory with a

user-defined combination of programmable wait states

and hardware acknowledge signals. Both the program

memory and data memory interfaces support addressing

of page-mode DRAMs.

The DMA bus is 32 bits wide allowing direct access of up

to 4 Gigawords of data. The DMD bus is 40 bits wide. For

32-bit data, the lower 8 bits are unused. The DMD bus

provides a path for the contents of any register in the

processor to be transferred to any other register or to any

external data memory location in a single cycle. The data

The TSC21020F’s internal functions are supported by memory address comes from one of two sources : an

four internal buses : the program memory address (PMA) absolute value specified in the instruction code (direct

and data memory address (DMA) buses are used for addressing) or the output of a data address generator

addresses associated with program and data memory. The (indirect addressing).

Figure 2. Basic System Configuration.

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TSC21020F

External devices can gain control of the processor’s

memory buses from the TSC21020F by means of the bus

request/grant signals (BR and BG). To grant its buses in

response to a bus request, the TSC21020F halts internal

operations and places its program and data memory

interfaces in a high impedance state. In addition,

three-state controls (DTMS and PMTS) allow an external

device to place either the program or data memory

interface in a high impedance state without affecting the

other interface and without halting the TSC21020F unless

it requires a memory access from the affected interface.

The three-state controls make it easy for an external cache

controller to hold the TSC21020F off the bus while it

updates an external cache memory.

JTAG Test and Emulation Support

The TSC21020F implements the boundary scan testing

provisions specified by IEEE Standard 1149.1 of the Joint

Testing Action Group (JTAG). The TSC21020F’s test

access port and on-chip JTAG circuitry is fully compliant

with the IEEE 1149.1 specification. The test access port

enables boundary scan testing of circuitry connected to

the TSC21020F’s I/O pins.

The TSC21020F also implements on-chip emulation

through the JTAG test access port. The processor’s eight

sets of breakpoint range registers enable program

execution at full speed until reaching a desired breakpoint

address range. The processor can then halt and allow

reading/writing of all the processor’s internal registers

and external memories through the JTAG port.

Pin Descriptions

This section describes the pins of the TSC21020F. When

groups of pins are identified with subscripts, e.g.

Name

Type

Function

PMD , the highest numbered pin is the MSB (in this

47-0

PMACK

I/S

Program Memory Acknowledge. An external

device deasserts this input to add wait states

to a memory access.

case, PMD ). Inputs identified as synchronous (S) must

47

meet timing requirements with respect to CLKIN (or with

respect to TCK for TMS, TDI, and TRST). Those that are

asynchronous (A) can be asserted asynchronously to

CLKIN.

PMPAGE

PMTS

O

Program Memory Page Boundary. The

TSC21020F asserts this pin to signal that a

program memory page boundary has been

crossed. Memory pages must be defined in

the memory control registers.

O = Output ; I = Input ; S = Synchronous ; A = Asynchronous ;

P = Power Supply ; G = Ground.

I/S

Program Memory Three-State Control. PMTS

places the program memory address, data,

selects, and strobes in a high-impedance state.

If PMTS is asserted while a PM access is

occurring, the processor will halt and the

memory access will not be completed.

PMACK must be asserted for at least one

cycle when PMTS is deasserted to allow any

pending memory access to complete properly.

PMTS should only be asserted (low) during

an active memory access cycle.

Name

Type

Function

PMA

O

Program Memory Address. The TSC21020F

outputs an address in program memory on

these pins.

23-0

PMD

I/O

O

Program Memory Data. The TSC21020F

inputs and outputs data and instructions on

these pins. 32-bit fixed-point data and 32-bit

single-precision floating-point data is

47-0

transferred over bits 47-16 of the PMD bus.

DMA

DMD

O

Data Memory Address. The TSC21020F

outputs an address in data memory on these

pins.

31-0

PMS

Program Memory Select lines. These pins are

asserted as chip selects for the corresponding

banks of program memory. Memory banks

must be defined in the memory control

registers. These pins are decoded program

memory address lines and provide an early

indication of a possible bus cycle.

1-0

I/O

Data Memory Data. The TSC21020F inputs

and outputs data on these pins. 32-bit

fixed-point data and 32-bit single-precision

floating-point data is transferred over bits

39-8 of the DMD bus.

39-0

PMRD

PMWR

O

Program Memory Read strobe. This pin is

asserted when the TSC21020F reads from

program memory.

DMS

O

Data Memory Select lines. These pins are

asserted as chip selects for the corresponding

banks of data memory. Memory banks must

be defined in the memory control registers.

These pins are decoded data memory address

lines and provide an early indication of a

possible bus cycle.

3-0

Program Memory Write strobe. This pin is

asserted when the TSC21020F writes to

program memory.

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TSC21020F

Name

Type

Function

Type

Function

DMRD

O

Data Memory Read strobe. This pin is

asserted when the TSC21020F reads from

data memory.

BG

O

Bus Grant. Acknowledges a bus request (BR),

indicating that the external device may take

control of the memory interface. BG is

asserted (held low) until BR is released.

DMWR

DMACK

DMPAGE

O

I/S

O

Data Memory Write strobe. This pin is

asserted when the TSC21020F writes to data

memory.

TIMEXP

RCOMP

EVDD

EGND

IVDD

IGND

TCK

O

Timer Expired. Asserted for four cycles when

the value of TCOUNT is decremented to zero.

Data Memory Acknowledge. An external

device deasserts this input to add wait states

to a memory access.

Not available

Can be set to any voltage level.

P

G

P

Power supply (for output drivers), nominally

+ 5 V dc (10 pins).

Data Memory Page Boundary. The

TSC21020F asserts this pin to signal that a

data memory page boundary has been

crossed. Memory pages must be defined in

the memory control registers.

Power supply return (for output drivers) ; (16

pins).

Power supply (for internal circuitry),

nominally + 5 V dc (4 pins).

DMTS

I/S

Data Memory Three-State Control. DMTS

places the data memory address, data, selects,

and strobes in a high-impedance state. If

DMTS is asserted while à DM access is

occurring, the processor will halt and the

memory access will not be completed.

DMACK must be asserted for at least one

cycle when DMTS is deasserted to allow any

pending memory access to complete properly.

DMTS should only be asserted (low) during

an active memory access cycle.

G

I

Power supply return (for internal circuitry) ;

(7 pins).

Test Clock. Provides an asynchronous clock

for JTAG boundary scan.

TMS

I/S

Test Mode Select. Used to control the test

state machine. TMS has a 20 kΩ internal

pullup resistor.

TDI

I/S

Test Data Input. Provides serial data for the

boundary scan logic. TDI has a 20 kΩ internal

pullup resistor.

CLKIN

RESET

I

External clock input to the TSC21020F. The

instruction cycle rate is equal to CLKIN.

CLKIN may not be halted, changed, or

operated below the specified frequency.

TDO

O

Test Data Output. Serial scan output of the

boundary scan path.

I/A

Sets the TSC21020F to a known state and

begins execution at the program memory

location specified by the hardware reset

vector (address). This input must be asserted

(low) at power-up.

TRST

I/A

Test Reset. Resets the test state machine.

TRST must be asserted (pulsed low) after

power-up or held low for proper operation of

the TSC21020F. TRST has a 20 kΩ internal

pullup resistor.

IRQ

I/A

Interrupt request lines ; may be either

edgeriggered or level-sensitive.

3-0

NC

No Connect. No Connects are reserved pins

that must be left open and unconnected.

FLAG

I/O/A External Flags. Each is configured via control

bits as either an input or output. As an input, it

can be tested as a condition. As an output, it

can be used to signal external peripherals.

3-0

BR

I/A

Bus Request. Used by an external device to

request control of the memory interface.

When BR is asserted, the processor halts

execution after completion of the current

cycle, places all memory data, addresses,

selects, and strobes in a high-impedance state,

and asserts BG. The processor continues

normal operation when BR is released.

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TSC21020F

Instruction Set Summary

Because of the width and orthogonality of the instruction

word, there are many possible instructions. For example,

the ALU supports 21 fixed-point operations and 24

floating-point operations ; each of these operations can be

the compute portion of an instruction.

The TSC21020F instruction set provides a wide variety

of programming capabilities. Every instruction

assembles into a single word and can execute in a single

processor cycle. Multifunction instructions enable

simultaneous multiplier and ALU operations, as well as

computations executed in parallel with data transfers.

The addressing power of the TSC21020F gives flexibility

in moving data both internally and externally. The

TSC21020F assembly language uses an algebraic syntax

for ease of coding and readability.

The following pages provide an overview and summary

of the TSC21020F instruction set. For complete

information, see the ADSP-21020 User’s Manual from

Analog Devices. For additional reference information,

see the ADSP- 21020 Programmer’s Quick Reference

from Analog Devices.

This section also contains several reference tables for

using the instruction set.

The instruction types are grouped into four categories :

Compute and Move or Modify

Program Flow Control

Immediate Move

D Table 1 describes the notation and abbreviations used.

D Table 2 lists all condition and termination code

Miscellaneous

mnemonics.

The instruction types are numbered ; there are 22 types. D Table 3 lists all register mnemonics.

Some instructions have more than one syntactical form ;

D Tables 4 through 7 list the syntax for all compute

for example, Instruction 4 has four distinct forms. The

instruction number itself has no bearing on programming,

but corresponds to the opcode recognized by the

TSC21020F device.

(ALU, multiplier, shifter or multifunction)

operations.

D Table 8 lists interrupts and their vector addresses.

Compute and Move or Modify Instructions

1.

compute,

DM(Ia, Mb) + dreg1

dreg1 + DM(Ia, Mb)

,

Ť Ť

PM(Ic, Md) + dreg2

dreg2 + PM(Ic, Md)

Ť

2.

3a.

IF condition

compute ;

compute,

= ureg ;

DM(Ia, Mb)

PM(Ic, Md)

Ť Ť

DM(Mb, Ia)

3b.

3c.

3d.

4a.

4b.

4c.

4d.

IF condition

compute,

Ť Ť

PM(Md, Ic)

ureg =

;

DM(Ia, Mb)

PM(Ic, Md)

Ť Ť

DM(Mb, Ia)

Ť Ť

PM(Md, Ic)

= dreg ;

DM(Ia, t data6 u)

PM(Ic, t data6 u)

Ť

DM(t data6 u, Ia)

Ť

PM(t data6 u, Ic)

dreg =

;

DM(Ia, t data6 u)

PM(Ic, t data6 u)

Ť

;

DM(t data6 u, Ia)

PM(t data6 u, Ic)

Ť

5.

6a.

IF condition

compute,

shiftimm,

ureg1 = ureg2 ;

= dreg ;

DM(Ia, Mb)

Ť Ť

PM(Ic, Md)

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TSC21020F

6b.

7.

IF condition

shiftimm,

dreg =

;

DM(Ia, Mb)

PM(Ic, Md)

Ť Ť

;

(Ia, Mb)

compute,

MODIFY

Ť Ť

(Ic, Md)

Program Flow Control Instructions

8.

IF condition

LCNTR =

JUMP

Ť Ť

CALL

t addr24 u

Ť_{(PC, t reladdr24 u)}

(

DB ) ;

Ť

LA

Ť Ť

DB, LA

9.

JUMP

Ť Ť

CALL

DB ) , compute

;

(Md, Ic)

Ť_{(PC, t reladdr6 u)}

Ť

LA

Ť Ť

DB, LA

11.

RTS

Ť Ť

RTI

(

DB ) , compute

;

LA

Ť Ť

DB, LA

DO

12.

13.

,

t addr24 u

Ť_{(PC, t reladdr24 u)}

t addr24 u

Ť_{(PC, t reladdr24 u)}

UNTIL LCE ;

t data16 u

Ť

ureg

DO

UNTIL termination ;

(DB) Delayed branch

(LA) Loop abort (pop loop PC stacks on branch)

Immediate Move Instructions

14a.

= ureg ;

DM(t addr32 u)

PM(t addr24 u)

Ť

14b. ureg =

;

DM(t addr32 u)

PM(t addr24 u)

Ť

15a.

= ureg ;

DM(t data32 u, Ia)

PM(t data24 u, Ic)

Ť

15b. ureg =

;

DM(t data32 u, Ia)

PM(t data24 u, Ic)

Ť

16.

= < data32 > ;

DM(Ia, Mb)

Ť Ť

ureg = < data 32 > ;

PM(Ic, Md)

17.

Miscellaneous Instructions

18.

BIT

sreg < data32 > ;

SET

ȧ ȧ

CLR

ȧ ȧ

TGL

ȧ ȧ

ȧ_TSTȧ

XOR

ȧ ȧ

19a. MODIFY

19b. BITREV

;

(Ia, t data32 u

Ic, t data32 u

Ť

(Ia, < data32 >)

20.

PUSH

Ť Ť

POP

LOOP

,

PUSH

POP

STS

;

Ť Ť

21.

22.

NOP ;

IDLE ;

11

Rev. E – Oct. 05, 1998

TSC21020F

Table 1 : Syntax Notation Conventions

Table 3 : Universal Registers

Notation

Meaning

Name

Function

UPPERCASE

Explicit syntax – assembler keyword (notation only ;

assembler is not case-sensitive and lowercase is

the preferred programming convention)

Instruction terminator

Separates parallel operations in an instruction

Optional part of instruction

List of options (choose one)

n-bit immediate data value

n-bit immediate address value

n-bit immediate PC-relative address value

ALU, multiplier, shifter or multifunction

operation (from Tables 4-7)

Shifter immediate operation (from Table 6)

Status condition (from Table 2)

Termination condition (from Table 2)

Universal register (from Table 3)

System register (from Table 3)

R15-R0, F15-F0 ; register file location

I7-I0 ; DAG1 index register

Register file

R15-R0

Program Sequencer

PC*

Register file locations

;

,

Program counter ; address of instruction currently

executing

Top of PC stack

PC stack pointer

Fetch address

Decode address

Loop termination address, code ; top of loop

address stack

Current loop counter ; top of loop count stack

Loop count for next nested counter-controlled loop

italics

PCSTK

between lines

<datan>

<addrn>

compute

PCSTKP

FADDR*

DADDR*

LADDR

CURLCNTR

LCNTR

Data Address Generators

I7-I0

M7-M0

L7-L0

B7-B0

I15-I8

M15-M8

L15-L8

shiftimm

condition

termination

ureg

sreg

dreg

Ia

Mb

Ic

Md

DAG1 index registers

DAG1 modify registers

DAG1 length registers

DAG1 base registers

DAG2 index registers

DAG2 modify registers

DAG2 length registers

DAG2 base registers

M7-M0 ; DAG1 modify register

I15-I8 ; DAG2 index register

M15-M8 ; DAG2 modify register

B15-B8

Bus Exchange

PX1

PX2

Table 2 : Condition and Termination Codes

PMD-DMD bus exchange 1 (16 bits)

PMD-DMD bus exchange 2 (32 bits)

48-bit PX1 and PX2 combination

Name

Description

PX

Timer

eq

ne

ge

lt

le

gt

ac

not ac

av

not av

mv

not mv

ms

not ms

sv

ALU equal to zero

TPERIOD

TCOUNT

Memory Interface

DMWAIT

DMBANK1

DMBANK2

DMBANK3

DMADR*

PMWAIT

Timer period

Timer counter

ALU not equal to zero

ALU greater than or equal to zero

ALU less than zero

ALU less than or equal to zero

ALU greater than zero

ALU carry

Wait state and page size control for data memory

Data memory bank 1 upper boundary

Data memory bank 2 upper boundary

Data memory bank 3 upper boundary

Copy of last data memory address

Wait state and page size control for program

memory

Not ALU carry

ALU overflow

Not ALU overflow

Multiplier overflow

Not multiplier overflow

Multiplier sign

Not multiplier sign

Shifter overflow

Not shifter overflow

Shifter zero

Not shifter zero

Flag 0

Not Flag 0

Flag 1

Not Flag 1

Flag 2

Not Flag 2

Flag 3

Not Flag 3

Bit test flag

Not bit test flag

PMBANK1

PMADR*

System Register

MODE1

Program memory bank 1 upper boundary

Copy of last program memory address

Mode control bits for bit-reverse, alternate

registers, interrupt nesting and enable, ALU

saturation, floating-point rounding mode and

boundary

Mode control bits for interrupt sensitivity, cache

disable and freeze, timer enable, and I/O flag

configuration

not sv

sz

not sz

flag0_in

not flag0_in

flag1_in

not flag1_in

flag2_in

not flag2_in

flag3_in

not flag3_in

tf

not tf

lce

not lce

forever

true

MODE2

IRPTL

Interrupt latch

Interrupt mask

IMASK

IMASKP

ASTAT

Interrupt mask pointer (for nesting)

Arithmetic status flags, bit test, I/O flag values, and

compare accumulator

Sticky arithmetic status flags, circular buffer

overflow flags, stack status flags (not sticky)

User status register 1

STKY

USTAT1

USTAT2

Loop counter expired (DO UNTIL)

Loop counter not expired (IF)

Always False (DO UNTIL)

Always True (IF)

User status register 2

* read-only

Refer to User’s Manual for bit-level definitions of each register.

In a conditional instruction, the execution of the entire instruction is

based on the specified condition.

12

Rev. E – Oct. 05, 1998

TSC21020F

Table 4 : ALU Compute Operations

Fixed-Point

Floating-Point

Rn = Rx + Ry

Rn = Rx – Ry

Fn = Fx + Fy

Fn = Fx – Fy

Rn = Rx + Ry, Rm = Rx – Ry

Rn = Rx + Ry + CI

Rn = Rx – Ry + CI – 1

Rn = (Rx + Ry)/2

COMP(Rx, Ry)

Rn = –Rx

Fn = Fx + Fy, Fm = Fx – Fy

Fn = ABS (Fx + Fy)

Fn = ABS (Fx – Fy)

Fn = (Fx + Fy)/2

COMP(Fx, Fy)

Fn = –Fx

Rn = ABS Rx

Fn = ABS Fx

Rn = PASS Rx

Fn = PASS Fx

Rn = MIN(Rx, Ry)

Rn = MAX(Rx, Ry)

Rn = CLIP Rx BY Ry

Rn = Rx + CI

Fn = MIN(Fx, Fy)

Fn = MAX(Fx, Fy)

Fn = CLIP Fx BY Fy

Fn = RND Fx

Rn = Rx + CI – 1

Rn = Rx + 1

Fn = SCALB Fx BY Ry

Rn = MANT Fx

Rn = Rx – 1

Rn = LOGB Fx

Rn = Rx AND Ry

Rn = Rx OR Ry

Rn = Rx XOR Ry

Rn = NOT Rx

Rn = FIX Fx BY Ry

Rn = FIX Fx

Fn = FLOAT Rx BY Ry

Fn = FLOAT Rx

Fn = RECIPS Fx

Fn = RSQRTS Fx

Fn = Fx COPYSIGN Fy

Rn, Rx, Ry R15-R0 ; register file location, fixed-point

Fn, Fx, Fy F15-F0 ; register file location, floating point

Table 5 : Multiplier Compute Operations

Rn

F

I

FR

= Rx * Ry ( S S

)

Fn

= Fx * Fy

Ť ŤŤ Ť

MRF

U U

Ť Ť Ť Ť

MRB

F

+ Rx * Ry ( S S

)

– Rx * Ry ( S S

Rn + MRF

)

Rn + MRF

Ť ŤŤ Ť

ȧ

Rn + MRB

I

U U

Rn + MRB

MRF + MRF

MRB + MRB

Ť Ť

ȧ

FR

MRF + MRF

MRB + MRB

ȧ

(SF)

Rn + RND MRF

^{+ SAT MRF}ȧ^(SI)ȧ

_{MRF + SAT MRF}ȧ ȧ

ȧ_(SF)

ȧ

ȧ^Rn

ȧ

_{+ RND MRB}Ť_(UF)Ť

ȧ

MRF + RND MRF

Rn

ȧ^Rn

+ SAT MRB

ȧ ȧ

ȧ^(UI)

ȧ

_{MRB + SAT MRB}ȧ ȧ

MRB + RND MRB

ȧ

ȧ_(UF)

ȧ ȧ

= 0

MRF

Ť Ť

MRB

= Rn

Rn

=

MRxF

Ť Ť

MRxB

Rn, Rx, Ry R15-R0 ; register file location, fixed-point

Fn, Fx, Fy F15-F0 ; register file location, floating-point

MRxF

MRxB

MR2F, MR1F, MR0F ; multiplier result accumulators, foreground

MR2B, MR1B, MR0B ; multiplier result accumulators, background

)

⁽Ť^x-inputŤ Ť^y-input

Ť

data format,

Ť _roundingŤ

S

Signed input

U

I

F

Unsigned input

Integer input(s)

Fractional input(s)

FR

(SF)

Fractional inputs, Rounded output

Default format for 1-input operations

(SSF) Default format for 2-input operations

13

Rev. E – Oct. 05, 1998

TSC21020F

Table 6 : Shifter and Shifter Immediate Compute Operations

Shifter

Shifter Immediate

Rn = LSHIFT Rx BY Ry

Rn = Rn OR LSHIFT Rx BY Ry

Rn = ASHIFT Rx BY Ry

Rn = Rn OR ASHIFT Rx BY Ry

Rn = ROT Rx BY RY

Rn = BCLR Rx BY Ry

Rn = BSET Rx BY Ry

Rn = BTGL Rx BY Ry

BTST Rx BY Ry

Rn = LSHIFT Rx BY<data8>

Rn = Rn OR LSHIFT Rx BY<data8>

Rn = ASHIFT Rx BY<data8>

Rn = Rn OR ASHIFT Rx BY<data8>

Rn = ROT Rx BY<data8>

Rn = BCLR Rx BY<data8>

Rn = BSET Rx BY<data8>

Rn = BTGL Rx BY<data8>

BTST Rx BY<data8>

Rn = FDEP Rx BY Ry

Rn = Rn OR FDEP Rx BY Ry

Rn = FDEP Rx BY Ry (SE)

Rn = Rn OR FDEP Rx BY Ry (SE)

Rn = FEXT Rx BY Ry

Rn = FEXT Rx BY Ry (SE)

Rn = EXP Rx

Rn = FDEP Rx BY <bit6> : <len6>

Rn = Rn OR FDEP Rx BY <bit6> : <len6>

Rn = FDEP Rx BY <bit6> : <len6> (SE)

Rn = Rn OR FDEP Rx BY (bit6> : <len6> (SE)

Rn = FEXT Rx BY <bit6> : <len6>

Rn = FEXT Rx BY <bit6> : <len6> (SE)

Rn = EXP Rx (EX)

Rn = LEFTZ Rx

Rn = LEFTO Rx

Rn, Rx, Ry

R15-R0 ; register file location, fixed-point

<bit6> : <len6> 6-bit immediate bit position and length values (for shifter immediate operations)

Table 7 : Multifunction Compute Operations

Fixed-Point

Floating-Point

Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12

Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 – R15-12

Fm = F3-0 * F7-4, Fa = F11-8 + F15-12

Fm = F3-0 * F7-4, Fa = F11-8 – F15-12

Fm = F3-0 * F7-4, Fa = FLOAT R11-8 by R15-12

Fm = F3-0 * F7-4, Fa = FIX R11-8 by R15-12

Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12)/2

Fm = F3-0 * F7-4, Fa = ABS F11-8

Fm = F3-0 * F7-4, Fa = MAX (F11-8, F15-12)

Fm = F3-0 * F7-4, Fa = MIN (F11-8 + F15-12)

Fm = F3-0 * F7-4, Fa = F11-8 + F15-12,

Fs = F11-8 – F15-12

Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12)/2

MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12

MRF = MRF + R3-0 * R7-4 (SSF), RA = R11-8 – R15-12

MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12)/2

Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12

Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 – R15-12

Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12)/2

MRF = MRF – R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12

MRF = MRF – R3-0 * R7-4 (SSF), Ra = R11-8 – R15-12

MRF = MRF – R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12)/2

Rm = MRF – R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12

Rm = MRF – R3-0 * R7-4 (SSFR), Ra = R11-8 – R15-12

Rm = MRF – R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12)/2

Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12,

Rs = R11-8 – R15-12

Ra, Rm

R3-0

Any register file location (fixed-point)

R3, R2, R1, R0

R7-4

R7, R6, R5, R4

R11-8

R15-12

Fa, Fm

F3-0

R11, R10, R9, R8

R15, R14, R13, 12

Any register file location (floating-point)

F3, F2, F1, F0

F7-4

F7, F6, F5, F4

F11-8

F15-12

(SSF)

(SSFR)

F11, F10, F9, F8

F15, F14, F13, F12

X-input signed, Y-input signed, fractional inputs

X-input signed, Y-input signed, fractional inputs,

rounded output

14

Rev. E – Oct. 05, 1998

TSC21020F

Table 8 : Interrupt Vector Addresses and Priorities

Vector

No

Address

(Hex)

Function

0

0x00

0x08

0x10

0x18

Reserved

Reset

1*

2

Reserved

3

Status stack or loop stack overflow or PC

stack full

4

0x20

0x28

0x30

0x38

0x40

0x48

0x50

0x58

0x60

0x68

0x70

0x78

0x80

0x88

0x90

Timer = 0 (high priority option)

IRQ3 asserted

5

6

IRQ2 asserted

7

IRQ1 asserted

8

IRQ0 asserted

9

Reserved

10

11

12

13

14

15

16

17

18

Reserved

DAG 1 circular buffer 7 overflow

DAG 2 circular buffer 15 overflow

Reserved

Timer = 0 (low priority option)

Fixed-point overflow

Floating-point overflow

Floating-point underflow

Floating-point invalid operation

19-23 0x98-0xB8

24-31 0xC0-OxF8

Reserved

User software interrupts

* Nonmaskable

15

Rev. E – Oct. 05, 1998

TSC21020F

TSC21020F – Specifications

Recommended Operating Conditions

Parameter

Mil Range

Unit

Min

4.50

–55

Max

5.50

V

Supply Voltage

V

DD

T

AMB

Ambient Operating Temperature

+125

°C

Electrical Characteristics

Parameter

Test Conditions

Min

Max

Unit

1

V

Hi-Level Input Voltage

V

= max

= min

= min, I = –1.0 mA

= min, I = 4.0 mA

= max, V = V max

= max, V = 0 V

= max, V = V max

2.0

3.0

V

IH

DD

2, 12

1, 12

IHCR

IL

Lo-Level Input Voltage

0.8

0.6

2

ILC

OH

OL

3, 11

Hi-Level Output Voltage

2.4

OH

Lo-Level Output Voltage

0.4

10

350

10

V

OL

4, 5

I

Hi-Level Input Current

Lo-Level Input Current

µA

mA

IH

IN

DD

4

5

IL

IN

ILT

IN

6

Tristate Leakage Current

Supply Current (Internal)

OZH

OZL

DDIN

IN DD

= max, V = 0 V

= 50 ns, V = max, V = 3.0 V,

IN

7

t

430

CK

DD

IHCR

V

= 2.4 V, V = V

= 0.4 V

IH

IL

ILC

8

I

C

Supply Current (Idle)

Input Capacitance

= max, V = 0 V or V max

100

10

mA

pF

DDIDLE

DD

IN

DD

9, 10

f

= 1 MHz, T

= 25°C, V = 2.5 V

CASE IN

IN

NOTES

1. Applies to : PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, IRQ3-0, FLAG3-0, BR, TMS, TDI.

2. Applies to : CLKIN, TCK.

3. Applies to : PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE,

FLAG3-0, TIMEXP, BG.

4. Applies to : PMACK, PMTS, DMACK, DMTS, IRQ3-0, BR, CLKIN, RESET, TCK.

5. Applies to : TMS, TDI, TRST.

6. Applies to : PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE,

FLAG3-0, TDO.

7. Applies to IVDD pins. At t = 50 ns, I

(typical) = 350 mA. See “Power Dissipation” for calculation of external (EVDD) supply current

CK

DDIN

for total supply current.

8. Applies to IVDD pins. Idle refers to TSC21020F state of operation during execution of the IDLE instruction.

9. Guaranteed but not tested.

10. Applies to all signal pins.

11. Although specified for TTL outputs, all TSC21020F outputs are CMOS-compatible and will drive to V and GND assuming no dc loads.

DD

12. Applies to RESET, TRST.

Absolute Maximum Ratings*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V

Output Voltage Swing . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Operating Temperature Range (Ambient) . . . . . . . . -55°C to + 125°C

Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to + 150°C

* Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

16

Rev. E – Oct. 05, 1998

TSC21020F

ESD Sensitivity

The TSC21020F features proprietary input protection avoid functional damage or performance degradation.

circuitry to dissipate high–energy discharges (Human Charges readily accumulate on the human body and test

Body Model). Per method 3015 of MIL–STD–883, the equipment and discharge without detection. Unused

TSC21020F has been classified as a Class 2 devices, with devices must be stored in conductive foam or shunts, and

the ability to withstand up to 2000V ESD.

the foam should be discharged to the destination socket

before devices are removed.

Prosper ESD precautions are strongly recommended to

TIMING PARAMETERS

others. While addition or subtraction would yield

meaningful results for an individual device, the values

General Notes

See Figure 15 on page 25 for voltage reference levels. Use given in this data sheet reflect statistical variations and

the exact timing information given. Do not attempt to worst cases. Consequently, you cannot meaningfully add

derive parameters from the addition or subtraction of parameters to derive other specifications.

Clock Signal

20 MHz

Parameter

Unit

Min

Max

Timing Requirement

T

t

CLKIN Period

CLKIN Width High

CLKIN Width Low

50

10

150

ns

CK

CKH

CKL

Figure 3. Clock

17

Rev. E – Oct. 05, 1998

TSC21020F

Reset

Frequency

Dependency*

20 MHz

Min

Parameter

Unit

Max

Min

Max

Timing Requirement

1

t

RESET Width Low

RESET Setup before CLKIN High

200

29

4t

ns

WRST

CK

2

50

29 + DT/2

30

SRST

NOTES

*

DT = t – 50 ns

CK

1. Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles

while RESET is low, assuming stable V and CLKIN (not including clock oscillator start-up time).

DD

2. Specification only applies in cases where multiple TSC21020F processors are required to execute in program counter lock-step (all

processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual from

Analog Devices for reset sequence information.

Figure 4. Reset

Interrupts

Frequency

Dependency*

Parameter

20 MHz

Min

Unit

Timing Requireent

t

IRQ3-0 Setup before CLKIN High

IRQ3-0 Hold after CLKIN High

IRQ3-0 Pulse Width

38

0

55

38 + 3DT/4

ns

SIR

HIR

IPW

t

+ 5

CK

NOTES

*

DT = t – 50 ns

CK

Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met.

Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020

User’s Manual from Analog Devices for interrupt servicing information.

Figure 5. Interrupts

18

Rev. E – Oct. 05, 1998

TSC21020F

Timer

Frequency

Dependency*

20 MHz

Max

Parameter

Unit

Min

Max

Switching Characteristic :

t

CLKIN High to TIMEXP

24

ns

DTEX

NOTES

DT = t – 50 ns

*

CK

Figure 6. TIMEXP

19

Rev. E – Oct. 05, 1998

TSC21020F

Flags

Frequency

Dependency*

20 MHz

Parameter

Unit

Min

Max

Min

Max

1

Timing Requirement

t

FLAG3-0 Setup before CLKIN High

19

0

19 + 5DT/16

ns

SFI

IN

FLAG3-0 Hold after CLKIN High

12 + 7DT/16

HFI

IN

FLAG3-0 Delay from xRD, xWR Low

12

DWRFI

HFIWR

IN

FLAG3-0 Hold after xRD, xWR

0

IN

Deasserted

Switching Characteristic

t

FLAG3-0

CLKIN High to FLAG3-0

Delay from CLKIN High

24

ns

DFO

OUT

Hold after CLKIN High

5

1

HFO

OUT

(2)

Enable

DFOE

DFOD

OUT

Disable

NOTES

*

DT = t – 50 ns

CK

1. Flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. See the Hardware

Configuration chapter of the ADSP-21020 User’s Manual from Analog Devices for additional flag servicing information.

2. guaranteed by design

Figure 7. Flags

20

Rev. E – Oct. 05, 1998

TSC21020F

Bus Request/Bus Grant

Frequency

Dependency*

20 MHz

Parameter

Unit

Min

Max

Min

Max

Timing Requirement

t

BR Hold after CLKIN High

BR Setup before CLKIN High

0

18

ns

HBR

SBR

18+5DT/16

25 + DT/2

Switching Characteristic

(1)

t

Memory Interface Disable to BG Low

CLKIN High to Memory Interface

Enable

–2

25

ns

DMDBGL

DME

t

CLKIN High to BG Low

CLKIN High to BG High

22

ns

DBGL

DBGH

NOTES

*

DT = t – 50 ns

CK

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.

Buses are not granted until completion of current memory access.

See the Memory Interface chapter of the ADSP-21020 User’s Manual from Analog Devices for BG, BR cycle relationships.

1. guaranteed by design

Figure 8. Bus Request/Bus Grant

21

Rev. E – Oct. 05, 1998

TSC21020F

External Memory Three-State Control

Frequency

Dependency*

20 MHz

Max

Parameter

Unit

Min

Max

Timing Requirement

t

xTS, Setup before CLKIN High

xTS Delay after Address, Select

xTS Delay after XRD, XWR Low

14

50

28

16

14 +DT/4

t

ns

STS

CK

28 + 7DT/8

16 + DT/2

DADTS

DSTS

Switching Characteristic

t

Memory Interface Disable before

CLKIN High

xTS High to Address, Select Enable

0

DT/4

ns

DTSD

t

DTSAE

NOTES

*

DT = t – 50 ns

CK

xTS should only be asserted (low) during an active memory access cycle.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.

Address = PMA23-0, DMA31-0, Select = PMS1-0, DMS3-0.

x = PM or DM.

Figure 9. External Memory Three-State Control

22

Rev. E – Oct. 05, 1998

TSC21020F

Memory Read

Frequency

Dependency*

20 MHz

Parameter

Unit

Min

Max

Min

Max

Timing Requirement

t

Address, Select to Data Valid

xRD Low to Data Valid

37

24

37 + DT

24 + 5DT/8

ns

DAD

DRLD

HDA

Data Hold from Address, Select

Data Hold from xRD High

xACK Delay from Address

xACK Delay from xRD Low

xACK Setup before CLKIN High

xACK Hold after CLKIN High

0

–1

HDRH

DAAK

DRAK

SAK

27

15

27 + 7DT/8

15 + DT/2

14

0

14 + DT/4

8 + 3DT/8

HAK

Switching Characteristic

t

Address, Select to xRD Low

xPAGE Delay from Address, Select

CLKIN High to xRD Low

xRD Pulse Width

8

ns

DARL

DAP

1

26

16

26

17

16 + DT/4

26 + 5DT/8

17 + 3DT/8

26 + DT/4

DCKRL

RW

xRD High to xRD, xWR Low

RWR

NOTES

*

DT = t – 50 ns

CK

x = PM or DM ; Address = PMA23-0, DMA31-0 ; Data = PMD47-0, DMD39-0 ; Select = PMS1-0, DMS3-0.

Figure 10. Memory Read

23

Rev. E – Oct. 05, 1998

TSC21020F

Memory Write

Frequency

Dependency*

20 MHz

Parameter

Unit

Min

Max

Min

Max

Timing Requirement

t

xACK Delay from Address, Select

xACK Delay from xWR Low

xACK Setup before CLKIN High

xACK Hold after CLKIN High

27

15

27 + 7DT/8

15 + DT/2

ns

DAAK

DWAK

SAK

14

0

14 + DT/4

HAK

Switching Characteristic

t

Address, Select to xWR Deasserted

Address, Select to xWR Low

xWR Pulse Width

37

11

26

23

37 + 15DT/16

11 + 3DT/8

26 + 9DT/16

23 + DT/2

ns

DAWH

DAWL

WW

Data Setup before xWR High

Address, Select Hold after xWR

Deasserted

DDWH

DWHA

1

0

1 + DT/16

DT/16

ns

1

t

Data Hold after xWR Deasserted

HDWH

DAP

xPAGE Delay from Address, Select

CLKIN High to xWR Low

xWR High to xWR or xRD Low

Data Disable before xWR or xRD

Low

1

26

16

17

16 + DT/4

17 + 7DT/16

26 + DT/4

DCKWL

WWR

DDWR

13

0

13 + 3DT/8

DT/16

ns

t

xWR Low to Data Enabled

WDE

NOTES

DT = t – 50 ns

*

C

1. See “System Hold Time Calculation” in “Test Conditions” section for calculating hold times given capacitive and DC loads.

x = PM or DM ; Address = PMA23-0, DMA31-0 ; Data = PMD47-0, DMD39-0 ; Select = PMS1-0, DMS3-0; guaranteed by design.

Figure 11. Memory Write

24

Rev. E – Oct. 05, 1998

TSC21020F

IEEE 1149.1 Test Access Port

Frequency

Dependency*

20 MHz

Parameter

Unit

Min

Max

Min

Max

Timing Requirement

t

TCK Period

50

5

6

7

9

t

ns

TCK

CK

TDI, TMS Setup before TCK High

TDI, TMS Hold after TCK High

System Inputs Setup before TCK High

System Inputs Hold after TCK High

TRST Pulse Width

STAP

HTAP

SSYS

HSYS

TRSTW

200

Switching Characteristic

t

TDO Delay from TCK Low

System Outputs Delay from TCK Low

15

26

ns

DTDO

DSYS

NOTES

*

DT = t – 50 ns

CK

System Inputs = PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, CLKIN, IRQ3-0, RESET, FLAG3-0, BR.

System Outputs = PMA23-0, PMS1-0, PMRD, PMWR, PMD47-0, PMPAGE, DMA31-0, DMS3-0, DMRD, DMWR, DMPAGE, FLAG3-0, BG,

TIMEXP.

See the IEEE 1149.1 Test Access Port chapter of the ADSP-21020 User’s Manual from Analog Devices for further detail.

Figure 12. IEEE 1149.1 Test Access Port

25

Rev. E – Oct. 05, 1998

TSC21020F

Figure 13. Output Enable/Disable

Test Conditions

interval from when a reference signal reaches a high or

Output Disable Time

low voltage level to when the output has reached a

specified high or low trip point, as shown in the Output

Enable /Disable diagram. If multiple pins (such as the

data bus) are enabled, the measurement value is that of the

first pin to start driving.

Output pins are considered to be disable when they stop

driving, go into a high-impedance state, and start to decay

from their output high or low voltage. The time for the

voltage on the bus to decay by ∆V is dependent on the

capacitive load, C , and the load current, I . It can be

L

Figure 14. Equivalent Device Loading for AC

Measurements (Includes all Fixtures)

approximated by the following equation :

C_LDV

I_L

t_DECAY

+

The output disable time (t ) is the difference between

DIS

t

and t

as shown in Figure 13. The time

MEASURED

DECAY

is the interval from when the reference signal

MEASURED

switches to when the output voltage decays ∆V from the

measured output high or output low voltage. t is

DECAY

calculated with ∆V equal to 0.5 V, and test loads C and

L

I .

L

Output Enable Time

Output pins are considered to be enabled when they have

made a transition from a high-impedance state to when

they start driving. The output enable time (t

) is the

ENA

26

Rev. E – Oct. 05, 1998

TSC21020F

Figure 17. Typical Output Rise Time vs. Load

Capacitance (at Maximum Case

Temperature)

Example System Hold Time Calculation

To determine the data output hold time in a particular

system, first calculate t

using the above equation.

DECAY

Choose ∆V to be the difference between the

TSC21020F’s output voltage and the input threshold for

the device requiring the hold time. A typical ∆V will be

5

4.8

4

0.4 V. C is the total bus capacitance (per data line), and

L

I is the total leakage or three-state current (per data line).

L

3

The hold time will be t

plus the minimum disable

DECAY

(1)

time (i.e. t

for the write cycle).

HDWD

2

Figure 15. Voltage Reference Levels

for AC Measurements

1

(Except Output Enable/Disable)

1

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

Capacitive Loading

Note:

(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0,

DMS3–0, DMPAGE, TDO, PMRD, PMWR, DMRD, DMWR

Output delays are based on standard capacitive loads :

100 pF on address, select, page and strobe pins, and 50 pF

on all others (see Figure 14). For different loads, these

timing parameters should be derated. See the Hardware

Configuration chapter of the ADSP-21020 User’s Manual

from Analog Devices for further information on derating

of timing specifications.

Figure 18. Typical Output Delay or Hold vs. Load

Capacitance (at Maximum Case

Temperature)

12

10

Figures 16 and 17 show how the output rise time varies

with capacitance. Figures 18 and 19 show how output

delays vary with capacitance. Note that the graphs may

not be linear outside the ranges shown.

8.3

8

6

4

Figure 16. Typical Output Rise Time vs. Load

Capacitance (at Maximum Case

Temperature)

(1)

2

10

9.9

9

0

–1.7

–2

8

7

6

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

Note:

(1)

(1) OUTPUT PINS BG, TIMEXP, FLAG3–0,

PMD47–0, DMD39–0

5

4

3

2

1.6

1

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE –pF

Note:

(1) OUTPUT PINS BG, TIMEXP, PMD47–0,

DMD39–0, FLAG3–0

27

Rev. E – Oct. 05, 1998

TSC21020F

package (Ceramic). The package uses a cavity-up

configuration.

Figure 19. Typical Output Delay or Hold vs. Load

Capacitance (at Maximum Case

Temperature)

Table 9 : Maximum θ for Various Airflow Values

CA

4

Airflow (m/s)

0

0.5

1

1.5

3

MQFPF

31.5°C/W 25°C/W 21.5°C/W 19°C/W

14.5°C/W 11.2°C/W 8.8°C/W 7.8°C/W

2.8

2

CPGA

NOTES

1

θ

is 1°C/W for CPGA.

is 0.3°C/W for MQFPF.

(1)

JC

0

–1

–2

Maximum recommended T is 130°C.

As per method 1012 MIL-STD-883. Ambient temperature : 25°C.

Power : 3.5 W.

J

–2.2

–3

25

Power Dissipation

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

Total power dissipation has two components : one due to

internal circuitry and one due to the switching of external

output drivers. Internal power dissipation is dependent on

the instruction execution sequence and the data values

involved. Internal power dissipation is calculated in the

following way :

Note:

(1) OUTPUT PINS PMA–23, PMS1–0, PMPAGE, DMA31–0,

DMS3–0, DMPAGE, TDO, PMRD, PMWR, DMRD, DMWR

Environmental Conditions

P

= I

× V

DDIN DD

INT

The TSC21020F is available in a Ceramic Pin Grid Array

(CPGA) and in a multilayer quad flat package with flat

leads (MQFPF).

The external component of total power dissipation is

caused by the switching of output pins. Its magnitude

depends on :

The CPGA package uses a cavity-down configuration

which gives it favorable thermal characteristics. The top 1) the number of output pins that switch during each

surface of the package contains a raised copper slug from cycle (O),

which much of the die heat is dissipated. The slug 2) the maximum frequency at which they can switch (f),

provides a surface for mounting a heat sink (if required).

3) their load capacitance (C), and

4) their voltage swing (V ).

DD

The military range TSC21020F is specified for operation

at T

of –55°C to + 125°C. Maximum T

(case

CASE

AMB

It is calculated by :

temperature) can be calculated from the following

equation :

2

P

= O × C × V

× f

EXT

DD

The load capacitance should include the processor’s

T

= T

+ (PD × θ

)

CASE

AMB

CA

package capacitance (C ). The switching frequency

IN

where PD is power dissipation and θ

case-to-ambient thermal resistance. The value of PD

depends on your application ; the method for calculating

PD is shown under “Power Dissipation” below. θ

varies with airflow. Table 9 shows a range of θ values.

is the

CA

includes driving the load high and then back low. Address

and data pins can drive high and low at a maximum rate

of 1/(2t ). The write strobes can switch every cycle at

CK

CA

a frequency of 1/tCK. Select pins switch at 1/(2t ), but

CK

CA

2 DM and 2 PM selects can switch on each cycle. If only

The TSC 21020F is also available in a 256-pin MQFPF one bank is accessed, no select line will switch.

28

Rev. E – Oct. 05, 1998

TSC21020F

Example :

power lines, especially when many output drivers are

simultaneously charging or discharging their load

capacitances. These transient currents can cause

disturbances on the power and ground lines. To minimize

these effects, the TSC21020F provides separate supply

pins for its internal logic (IGND and IVDD) and for its

external drivers (EGND and EVDD).

Estimate P

with the following assumptions :

EXT

D A system with one RAM bank each of PM (48 bits)

and DM (32 bits).

D 32 K × 8 RAM chips are used, each with a load of

10 pF.

D Single-precision mode is enabled so that only 32 data

All GND pins should have a low impedance path to

ground. A ground plane is required in TSC21020F

systems to reduce this impedance, minimizing noise.

pins can switch at once.

D PM and DM writes occur every other cycle, with 50 %

of the pins switching.

The EVDD and IVDD pins should be bypassed to the

ground plane using approximately 14 high-frequency

capacitors (0.1 µF ceramic). Keep each capacitor’s lead

and trace length to the pins as short as possible. This low

inductive path provides the TSC21020F with the peak

currents required when its output drivers switch. The

capacitors’ ground leads should also be short and connect

directly to the ground plane. This provides a low

impedance return path for the load capacitance of the

TSC21020F’s output drivers.

D The instruction cycle rate is 20 MHz (t = 50 ns) and

CK

V

DD

= 5.0 V.

The P

equation is calculated for each class of pins that

EXT

can drive :

Type

#

%

2

×C

×f

×V_DDP_EXT

Pins Switch

PMA

PMS

15

2

50

0

68 pF

5 MHz

25 V 0.064 W

25 V 0.000 W

If

a

V

plane is not used, the following

DD

PMWR

PMD

DMA

DMS

1

–

68 pF 10 MHz 25 V 0.017 W

recommendations apply. Traces from the + 5 V supply to

the 10 EVDD pins should be designed to satisfy the

32

15

2

50

0

18 pF

48 pF

5 MHz

25 V 0.036 W

25 V 0.045 W

25 V 0.000 W

minimum V

specification while carrying average dc

DD

currents of [I

/10 × (number of EVDD pins per

DDEX

DMWR

DMD

1

32

–

50

48 pF 10 MHz 25 V 0.012 W

18 pF 5 MHz 25 V 0.036 W

trace)]. I

is the calculated external supply current. A

DDEX

similar calculation should be made for the four IVDD pins

using the I specification. The traces connecting

P

EXT

= 0.210 W

DDIN

+ 5 V to the IVDD pins should be separate from those

A typical power consumption can now be calculated for connecting to the EVDD pins.

this situation by adding a typical internal power

A low frequency bypass capacitor (20 µF tantalum)

located near the junction of the IVDD and EVDD traces

is also recommended.

dissipation :

P

= P

+ (5 V × I

(typ)) = 0.210 + 1.15

TOTAL

EXT

DDIN

= 1.36 W

Target System Requirements For Use Of

EZ-ICE Emulator

Note that the conditions causing a worst case P

are

EXT

different from those causing a worst case P . Maximum

INT

P

INT

cannot occur while 100 % of the output pins are

The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG

test access port of the TSC21020F to monitor and control

the target board processor during emulation. The EZ-ICE

probe requires that CLKIN, TMS, TCK, TRST, TDI,

TDO, and GND be made accessible on the target system

via a 12-pin connector (pin strip header) such as that

shown in Figure 20. The EZ-ICE probe plugs directly

switching from all ones to all zeros. Also note that it is not

common for a program to have 100 % or even 50 % of the

outputs switching simultaneously.

Power and Ground Guidelines

To achieve its fast cycle time, including instruction fetch, onto this connector for chip-on-board emulation ; you

data access, and execution, the TSC21020F is designed must add this connector to your target board design if you

with high speed drivers on all output pins. Large peak intend to use the ADSP-21020 EZ-ICE. Figure 21 shows

currents may pass through a circuit board’s ground and the dimensions of the EZ-ICE probe ; be sure to allow

29

Rev. E – Oct. 05, 1998

TSC21020F

enough space in your system to fit the probe onto the must be 0.025 inch square and at least 0.20 inch in length.

12-pin connector.

Pin spacing is 0.1 × 0.1 inches.

The tip of the pins must be at least 0.10 inch higher than

the tallest component under the probe to allow clearance

for the bottom of the probe. Pin strip headers are available

from vendors such as 3M, Mc Kenzie, and Samtec.

Figure 20. Target Board Connector for EZ-ICE

Emulator (Jumpers In Place)

The length of the traces between the EZ-ICE probe

connector and the TSC21020F test access port pins

should be less than 1 inch. Note that the EZ-ICE probe

adds two TTL loads to the CLKIN pin of the TSC21020F.

The BMTS, BTCK, BTRST, and BTDI signals are

provided so that the test access port can also be used for

board-level testing. When the connector is not being used

for emulation, place jumpers between the BXXX pins and

the XXX pins as shown in Figure 20. If you are not going

to use the test access port for board test, tie BTRST to

GND and tie or pull up BTCK to VDD. The TRST pin

must be asserted (pulsed low) after power up (through

BTRST on the connector) or held low for proper

operation of the TSC21020F.

Figure 21. EZ-ICE Probe

The 12-pin, 2-row pin strip header is keyed at the Pin 1

location – you must clip Pin 1 off of the header. The pins

30

Rev. E – Oct. 05, 1998

TSC21020F

31

Rev. E – Oct. 05, 1998

TSC21020F

32

Rev. E – Oct. 05, 1998

TSC21020F

PGA

LOCATION

NAME

LOCATION

NAME

LOCATION

NAME

LOCATION

NAME

G16

G17

F18

F17

F16

F15

E18

E17

E16

D18

E15

D17

D16

C18

C17

D15

B18

B17

C16

D14

C15

B16

A16

D13

C14

B15

B14

D12

C13

A14

B13

C12

H3

DMA0

B5

DMD25

K1

L3

L2

PMD9

L16

U12

T11

T14

R12

S13

U16

U14

H18

A3

TIMEXP

DMA1

DMA2

B6

D6

DMD26

DMD27

DMD28

DMD29

DMD30

DMD31

DMD32

DMD33

DMD34

DMD35

DMD36

DMD37

DMD38

DMD39

DMS0

PMD10

PMD11

PMD12

PMD13

PMD14

PMD15

PMD16

PMD17

PMD18

PMD19

PMD20

PMD21

PMD22

PMD23

PMD24

PMD25

PMD26

PMD27

PMD28

PMD29

PMD30

PMD31

PMD32

PMD33

PMD34

PMD35

PMD36

PMD37

PMD38

PMD39

PMD40

PMD41

PMD42

PMD43

PMD44

PMD45

PMD46

PMD47

PMS0

RCOMP

CLKIN

TRST

TD0

DMA3

DMA4

C6

A8

M1

M2

M3

M4

N2

N3

P1

DMA5

DMA6

C7

D7

TDI

TMS

DMA7

DMA8

B7

B8

TCK

EGND

IGND

EVDD

IVDD

NC

DMA9

A10

C8

DMA10

DMA11

DMA12

DMA13

DMA14

DMA15

DMA16

DMA17

DMA18

DMA19

DMA20

DMA21

DMA22

DMA23

DMA24

DMA25

DMA26

DMA27

DMA28

DMA29

DMA30

DMA31

DMD0

P2

A7

D8

B9

N4

S1

A11

A15

E1

C9

P3

R2

B10

D10

C11

A12

B11

T13

S11

B12

S12

T12

L17

M18

M15

M16

M17

N17

N16

N15

P18

P17

R17

S18

P15

P16

S17

R16

R15

U18

S16

T17

U17

R14

S15

T16

F2

G1

P4

R3

L1

L18

R1

R18

T18

U5

DMS1

DMS2

DMS3

S2

T1

DMWR

DMRD

DMPAGE

DMTS

DMACK

PMA0

S3

R4

T2

U1

T3

U7

U11

U15

D11

G4

G15

L4

L15

R7

R11

A5

R5

PMA1

PMA2

S4

U2

S5

PMA3

PMA4

T4

PMA5

PMA6

R6

U3

U4

S6

PMA7

PMA8

A9

H4

E2

DMD1

DMD2

PMA9

T6

S7

A13

J1

PMA10

PMA11

PMA12

PMA13

PMA14

PMA15

PMA16

PMA17

PMA18

PMA19

PMA20

PMA21

PMA22

PMA23

PMD0

G3

D1

DMD3

DMD4

U6

T7

J18

N1

D2

F3

DMD5

DMD6

R8

S8

N18

U9

C1

C2

DMD7

DMD8

R13

T15

U8

S9

U13

K18

D9

PMS1

F4

E3

DMD9

PMWR

PMRD

PMPAGE

PMTS

DMD10

DMD11

DMD12

DMD13

DMD14

DMD15

DMD16

DMD17

DMD18

DMD19

DMD20

DMD21

DMD22

DMD23

DMD24

J4

D3

B1

S14

T8

J15

R9

E4

B2

U10

A17

A18

H16

H15

H17

G18

J17

J16

K16

K15

R10

PMACK

BG

C10

S10

T10

T9

NC

C3

A2

BR

NC

FLAG0

FLAG1

FLAG2

FLAG3

IRQ0

D4

B3

F1

J3

PMD1

PMD2

K17

T5

NC

A4

C4

H2

H1

PMD3

PMD4

G2

NC

B4

D5

J2

K4

PMD5

PMD6

IRQ1

IRQ2

A6

C5

K3

K2

PMD7

PMD8

IRQ3

RESET

33

Rev. E – Oct. 05, 1998

TSC21020F

MQFP_F

LOCATION

NAME

LOCATION

NAME

LOCATION

NAME

LOCATION

NAME

1

IGND

65

IGND

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

IGND

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

IGND

2

3

IVDD

66

67

IVDD

DMD19

DMD18

DMD17

DMD16

EGND

DMD15

DMD14

DMD13

DMD12

EVDD

DMD11

DMD10

DMD9

DMD8

IGND

PMD25

PMD26

PMD27

EVDD

PMD28

PMD29

PMD30

PMD31

EGND

PMD32

PMD33

PMD34

PMD35

EVDD

IGND

PMA19

PMA18

PMA17

PMA16

EGND

PMA15

PMA14

PMA13

PMA12

EVDD

PMA11

PMA10

PMA9

PMA8

IGND

DMA15

EGND

DMA16

DMA17

DMA18

DMA19

EVDD

DMA20

DMA21

DMA22

DMA23

EGND

DMA24

DMA25

IGND

4

5

68

69

6

7

70

71

8

9

72

73

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

74

75

76

77

78

79

80

81

IVDD

82

83

IVDD

EGND

DMD7

DMD6

DMD5

DMD4

EVDD

DMD3

DMD2

DMD1

DMD0

EGND

PMD0

PMD1

PMD2

IGND

PMD36

PMD37

PMD38

PMD39

EGND

PMD40

PMD41

PMD42

PMD43

EVDD

PMD44

PMD45

PMD46

PMD47

IGND

EGND

PMA7

PMA6

PMA5

PMA4

EVDD

PMA3

PMA2

PMA1

PMA0

EGND

TIMEXP

EVDD

EGND

IGND

DMA26

DMA27

EVDD

DMA28

DMA29

DMA30

DMA31

EGND

DMPAGE

BR

84

85

86

87

88

89

90

91

92

93

BG

94

95

DMS0

DMS1

96

97

EVDD

IGND

IVDD

98

99

IVDD

EGND

PMTS

IVDD

IRQ3

IVDD

DMS2

PMD3

EVDD

PMD4

PMD5

PMD6

PMD7

EGND

PMD8

PMD9

PMD10

PMD11

EVDD

PMD12

PMD13

IGND

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

IRQ2

IRQ1

DMS3

PMWR

PMACK

PMRD

RCMP

EVDD

RESET

CLKIN

DMRD

DMACK

DMWR

EVDD

DMTS

IGND

DMD39

DMD38

EGND

DMD37

DMD36

DMD35

DMD34

EVDD

DMD33

DMD32

DMD31

DMD30

IGND

IRQ0

EVDD

FLAG0

FLAG1

FLAG2

FLAG3

EGND

DMA0

DMA1

DMA2

DMA3

IGND

IVDD

TCK

IVDD

PMD14

PMD15

EGND

PMD16

PMD17

PMD18

PMD19

EVDD

PMD20

PMD21

PMD22

PMD23

EGND

PMD24

EVDD

DMA4

DMA5

DMA6

DMA7

EGND

DMA8

DMA9

DMA10

DMA11

EVDD

DMA12

DMA13

DMA14

EGND

DMD29

DMD28

DMD27

DMD26

EVDD

DMD25

DMD24

DMD23

EGND

DMD22

DMD21

DMD20

EVDD

TMS

TDI

TDO

TRST

PMPAGE

PMS0

PMS1

EGND

PMA23

PMA22

PMA21

PMA20

EVDD

34

Rev. E – Oct. 05, 1998

TSC21020F

223-pin Ceramic Pin Grid Array

Bottom View

MM

INCHES

MAX

.130

SYMBOL

MIN

MAX

MIN

A

C

D

E

H

L

2.54

3.30

.100

2.54 BSC

.100 BSC

46.74

0.41

47.75

0.51

1.840

0.16

1.880

0.20

3.05

3.56

.120

.140

Q

1.14

1.40

0.45

.055

35

Rev. E – Oct. 05, 1998

TSC21020F

256-pin MQFP-F Package

TOP VIEW

MILS

MM

SYMBOL

MIN

MAX

0.125

0.008

2.195

1.470

2.195

1.470

MIN

2.41

MAX

3.18

A

C

D

0.095

0.004

2.095

1.450

2.095

1.450

0.10

0.20

53.23

36.83

53.23

36.83

55.74

37.34

55.74

37.34

D

1

E

1

e

f

0.020 BSC

0.508 BSC

0.006

0.081

0.002

0.323

0.010

0.101

0.014

0.362

0.15

2.06

0.05

8.20

0.25

2.56

0.36

9.20

A

1

2

A

L

N

1

N

2

64

36

Rev. E – Oct. 05, 1998

TSC21020F

Ordering information

TSC

21020F

– 20

M

A

/883

Packaging

A: 223P PGA

B: 256L MQFP–F

C: Die Form

Temperature Range

ꢀ

M: Military –55 C to 125 C

ꢀ

S: Spatial –55 C to 125 C

–E: Engineering Sample

– 20: 20 MHz version

Blank: Standard Military

/883: MIL 883 Compliant B or S

P883: MIL 883 Compliant B+ PIND Test

SB: SCC9000 Level B

SC: SCC9000 Level C

SL3: LAT3

Part number

From ADSP–21020

(Analog Devices)

SL2: LAT2

SL1: LAT1

F: Radiation Tolerant

Hxxx: Customer Code

37

Rev. E – Oct. 05, 1998


型号：	TSC21020F-20MBSL2
厂家：	ETC
描述：	DSP\|32-BIT\|CMOS\| RAD HARD\|QFL\|256PIN\|CERAMIC DSP \| 32位\| CMOS \|抗辐射\| QFL \| 256PIN \|陶瓷\n 外围集成电路异步传输模式 ATM 时钟
文件：	总37页 (文件大小：484K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSC21020F-20MBSL2 [ETC]

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