TTS3816B4E-6E [ETC]
2M x 16Bit x 4 Banks synchronous DRAM; 2米x 16Bit的×4银行同步DRAM型号: | TTS3816B4E-6E |
厂家: | ETC |
描述: | 2M x 16Bit x 4 Banks synchronous DRAM |
文件: | 总8页 (文件大小:275K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M
.tec
TTS3816B4E
2M x 16Bit x 4 Banks synchronous DRAM
GENERAL DESCRIPTION
The TTS3816B4E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 8 x 1,048,576 words by 16 bits,
fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four-banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
ORDERING INFORMATION
Part No.
Max Freq.
Interface
LVTTL
Package
TTS3816B4E-7
TTS3816B4E-6
TTS3816B4E-6A
TTS3816B4E-6B
TTS3816B4E-6C
TTS3816B4E-6D
TTS3816B4E-6E
100MHz 2-2-2
133MHz 3-3-3
100MHz 2-3-3
133MHz 2-3-2
133MHz 2-2-2
150MHz 3-3-3
166MHz 3-3-3
54
TSOP(II)
Revision_1.1
1 TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
PIN CONFIGURATION (Top View)
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
2
Revision_1.1
TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
PIN FUNCTION DESCRIPTION
Pin Name
A0~ A11
Function
Description
Address
Bank
Multiplexed pins for row and column address Row address: A0 ~ A11.
Column address: A0 ~ A8.
BS0, BS1
DQ0 ~DQ15
/CS
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Data Input / Output
Chip Select
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
/RAS
Row Address Strobe
Column Address Strobe
Write Enable
Command input. When sampled at the rising edge of the clock, /RAS,
/CAS and /WE define the operation to be executed.
/CAS
Referred to /RAS
/WE
Referred to /RAS
UDQM/LDQM
Input /output mask
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
CLK
CKE
Vcc
Vss
Vcc
Vss
NC
Clock Input
Clock Enable
Power (+3.3 V)
Ground
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Q Power (+ 3.3 V) for I/O Separated power from VCC , used for output buffers to improve noise.
buffer
Q Ground for I/O buffer
Separated ground from VSS , used for output buffers to improve noise.
No Connection
No connection
Revision_1.1
3
TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
BLOCK DIAGRAM
Bank Select
Data Input
2MX16
2MX16
2MX16
2MX16
Row Decoder
&
Refresh Counter
Address
Buffer
ADD
Output Buffer
DQ
Column Decoder
Column Buffer
/CS
Latency &
Burst Length
Commend
Decoder
/ RAS
/ CAS
/ WE
CLK
&
Clock
Buffer
Programming
Register
CKE
4
Revision_1.1
TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
ABSOLUTE MAXIMUM RATING
Parameter
Voltage on any pin relative to V
Symbol
Value
-1.0 ~ 4.6
Unit
V
SS
IN
OUT
V , V
SS
Q
Voltage on VCC supply relative to V
Storage temperature
VCC, VCC
-1.0 ~ 4.6
V
℃
STG
T
-55 ~ +150
D
P
Power dissipation
1
W
OS
Short circuit current
I
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to the recommended operating conditions.
Exposure to higher voltage than recommended for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
SS
A
Recommended operating conditions (Voltage referenced to V = 0V, T = 0 to 70°C)
Parameter
Supply voltage
Symbol
VCC, VCC
Min
3.0
Typ
3.3
Max
3.6
Unit
V
Note
Q
IH
Q
Input logic high voltage
V
2.0
-0.3
2.4
-
3.0
VCC +0.3
V
V
1
2
IL
V
Input logic low voltage
0
-
0.8
-
OH
OH
Output logic high voltage
Output logic low voltage
Input leakage current (Input)
Input leakage current (I/O pins)
V
V
I
V
I
=-2mA
OL
IL
OL
-
0.4
1
V
I
=2mA
-1
-
uA
uA
3
IL
I
-1.5
-
1.5
3,4
Notes:
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≦ 3ns.
IL
≦
2. V (min) = -2.0V AC. The undershoot voltage duration is
3ns.
IN ≦
Q,
VCC
3. Any input 0V ≦ V
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
out
≦
out ≦
V
Q
VCC
4. D is disabled, 0V
Revision_1.1
5 TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
DC CHARACTERISTICS
A
(Recommended operating condition unless otherwise noted, T = 0 to 70°C)
Parameter
Symbol
Test Condition
TTS3816B4E
Unit Note
Burst length = 1
Operating current
(One bank active)
RC≧ RC
t
t
(min)
100
2
CC1
I
mA
mA
1
IOL = 0mA
IL
CC
CKE≦V (max), t = 15 ns
CC2
I
P
Pre-charge standby current
in power- down mode
IL
CC
∞
CKE&CLK≦V (max), t
=
CC2
I
PS
2
IH
≧
IH
CKE≧V (min), /CS V (min) ,
CC2
I
N
30
10
5
CC
t
= 15ns
Input signals are stable
Pre-charge standby current
in non power-down mode
mA
mA
IH
IL
CKE≧V (min), CLK≦V (Max) ,
CC2
CC
I
I
NS
t
= ∞
Input signals are stable
IL
CC
CKE≦V (max), t = 15 ns
CC3
I
P
Active standby current in
power-down mode
IL
CC
∞
CKE&CLK≦V (max), t
=
CC3
PS
5
IH
≧
IH
CKE≧V (min), /CS V (min) ,
CC3
I
N
40
20
CC
t
= 15ns
Active standby current in
non power-down mode
(One bank active)
Input signals are stable
mA
mA
IH
≦
IL
CKE≧V (min), CLK V (Max) ,
CC3
I
NS
CC
t
= ∞
Input signals are stable
OL
I
=0 mA
150
140
CL = 3
CL = 2
Operating current
(Burst mode)
Page burst
CC4
I
1
2
2Banks activated
CCD
S
t
= 2CLK
RC RC
t
≧t (min)
160
CC5
Refresh current
I
I
mA
mA
CKE≦0.2V
CC6
Self refresh current
1
Note: 1.Measured with outputs open.
2.Refresh period is 64 ms.
Revision_1.1
6 TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
AC CHARACTERISTICS AND OPERATING
(Vcc=3.3V±0.3V, Ta=0° to 70°C)
-7
-6
-6A
-6B
-6C
-6D
-6E
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
RRD
Row active to row active delay
/RAS to /RAS delay
t
t
t
t
t
t
20
15
20
20
30
30
48
70
1
14
20
15
45
63
1
14
15
15
45
63
1
14
20
20
45
63
1
12
18
18
42
60
1
ns
RCD
RP
20
ns
Row pre-charge time
Row active time
20
20
ns
100K
100K
100K
100K
100K
100K
100K
RAS
RC
48
45
ns
67.5
Row cycle time
70
ns
CCD
Col. Address to col. Address delay
Write Recovery Time
1
20
1
CLK
ns
WR
t
15
20
10
8
14
7.5
7.5
2.5
2.5
14
7.5
7.5
2.5
2.5
13
-
12
-
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
CL=2 10
10
CK
CLK Cycle Time
t
ns
1000
1000
CL=3
8
3
3
7.5
2.5
2.5
6.5
2
6
CH
CL
CLK High Level width
CLK Low Level width
t
t
3
2
ns
ns
3
2
2
CL=2
CL=3
6
6
6
8
6
5.4
5.4
5.4
5.4
-
-
AC
Access Time from CLK
t
ns
5.4
5.4
5
OH
Output Data Hold Time
Data-in Set-up Time
Data-in Hold Time
t
t
t
t
t
t
t
t
t
t
t
3
2
1
2
1
2
1
2
1
2.7
1.5
1
3
2
1
2
1
2
1
2
1
2.7
1.5
1
2.7
1.5
1
2.5
1.5
1
2
1.5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS
DH
AS
Address Set-up Time
Address Hold Time
CKE Set-up Time
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
AH
CKS
CKH
CMS
CMH
REF
RSC
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
64
64
64
64
64
64
64 ms
ns
Mode register Set Cycle Time
20
15
20
14
14
12
12
Revision_1.1
7 TwinMOS Technologies Inc. Sep. 2000
M
.tec
TTS3816B4E
54PIN PLASTIC TSOP(II) (400mil)
54
28
detail of lead end
F
P
E
1
2
7
A
H
I
J
G
L
C
N
K
D
M
M
B
NOTE
ITEM MILLIMETERS
INCHES
0.891 MAX.
0.036 MAX.
0.031 (T.P.)
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
22.62 MAX.
0.91 MAX.
0.80 (T.P.)
+0.08
0.32
D
0.013±0.003
–0.07
E
F
G
H
I
0.10±0.05
1.20 MAX.
1.00
0.004±0.002
0.048 MAX.
0.039
11.76±0.20
10.16±0.10
0.463±0.008
0.400±0.004
+0.009
0.031
J
K
L
0.80±0.20
–0.008
+0.025
0.145
0.006±0.001
–0.015
+0.004
0.020
0.50±0.10
–0.005
M
N
0.13
0.10
0.005
0.004
+7°
3°
+7°
3°
P
–3°
–3°
Revision_1.1
8
TwinMOS Technologies Inc. Sep. 2000
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