TU24C64CS2_技术文档

Turbo IC, Inc.

24C64

CMOS I²C 2-WIRE BUS

64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM

8K X 8 BIT EEPROM

FEATURES :

DESCRIPTION:

• Extended Power Supply Voltage

The Turbo IC 24C64 is a serial 64K EEPROM fabricated

with Turbo’s proprietary, high reliability, high performance

CMOS technology.It’s 64K of memory is organized as 8,192

x 8 bits.The memory is configured as 256 pages with each

page containing 32 bytes.This device offers significant ad-

vantages in low power and low voltage applications.

Single Vcc for Read and Programming

(Vcc = 2.7 V to 5.5 V)

• Low Power (Isb = 2µa @ 5.5 V)

• Extended I²C Bus, 2-Wire Serial Interface

• Support Byte Write and Page Write (32 Bytes)

• Automatic Page write Operation (maximum 10 ms)

Internal Control Timer

TheTurbo IC 24C64 uses the extended I²C addressing pro-

tocol and 2-wire serial interface which includes a bidirec-

tional serial data bus synchronized by a clock. It offers a

flexible byte write and a faster 32-byte page write.The data

in the upper quadrant of memory can be protected by a

write protect pin.

Internal Data Latches for 32 Bytes

• Hardware Data Protection by Write Protect Pin

• High Reliability CMOSTechnology with EEPROM Cell

Endurance : 1,000,000 Cycles

Data Retention : 100Years

The Turbo IC 24C64 is assembled in either a 8-pin PDIP or

8-pin SOIC package. Pin #1 (A0), #2 (A1), and #3 (A2) are

device address input pins which are hardwired by the user.

Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA)

pin used for bidirectional transfer of data.Pin #6 is the serial

clock (SCL) input pin. Pin #7 is the write protect (WP) input

pin, and Pin #8 is the power supply (Vcc) pin.

PIN DESCRIPTION

All data is serially transmitted in bytes (8 bits) on the SDA

bus. To access the Turbo IC 24C64 (slave) for a read or

write operation, the controller (master) issues a start condi-

tion by pulling SDA from high to low while SCL is high.The

master then issues the device address byte which consists

of 1010 (A2) (A1) (A0) (R/W). The 4 most significant bits

(1010) are a device type code signifying an EEPROM de-

vice. The A[2:0] bits represent the input levels on the 3 de-

vice address input pins. The read/write bit determines

whether to do a read or write operation. After each byte is

transmitted, the receiver has to provide an acknowledge by

pulling the SDA bus low on the ninth clock cycle. The ac-

knowledge is a handshake signal to the transmitter indicat-

ing a successful data transmission.

A0

A1

VCC

WP

A0

A1

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

VCC

WP

A2

SCL

SDA

A2

SCL

SDA

GND

8 pin SOIC

8 pin PDIP

PIN DESCRIPTION

DEVICE ADDRESSES (A2-A0)

WRITE PROTECT (WP)

drain output.A pullup resistor must be connected

The address inputs are used to define the 3 least

significant bits of the 7-bit device address code -

1010 (A2) (A1) (A0). These pins can be con-

nected either high or low. A maximum of eight

Turbo IC 24C64 can be connected in parallel,

each with a unique device address. When these

pins are left unconnected, the device addresses

are interpreted as zero.

When the write protect input is connected to Vcc,

the upper quadrant of memory (1800-1FFFH) is

protected against write operations. For normal

write operation, the write protect pin should be

grounded.When this pin is left unconnected, WP

is interpreted as zero.

from SDA to Vcc.

SERIAL CLOCK (SCL)

The SCL input synchronizes the data on the SDA

bus. It is used in conjunction with SDA to define

the start and stop conditions. It is also used in

conjunction with SDA to transfer data to and from

the Turbo IC 24C64.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data

in and out of the Turbo IC 24C64. The pin is an

open-

1

Turbo IC, Inc.

24C64

DESCRIPTION (Continued)

For a write operation, the master issues a start condition,

device address byte, 2 memory address bytes, and then up

to 32 data bytes. The Turbo IC 24C64 acknowledges after

each byte transmission. To terminate the transmission, the

master issues a stop condition by pulling SDA from low to

high while SCL is high.

For a read operation, the master issues a start condition and

a device address byte. The Turbo IC 24C64 acknowledges,

and then transmits a data byte, which is accessed from the

EEPROM memory.The master acknowledges, indicating that

it requires more data bytes. The Turbo IC 24C64 transmits

more data bytes, with the memory address counter auto-

matically incrementing for each data byte, until the master

does not acknowledge, indicating that it is terminating the

transmission.The master then issues a stop condition.

DEVICE OPERATION:

BIDIRECTIONAL BUS PROTOCOL:

ACKNOWLEDGE:

The Turbo IC 24C64 follows the extended I²C bus protocol.

The protocol defines any device that sends data onto the

SDA bus as a transmitter, and the receiving device as a re-

ceiver. The device controlling the transfer is the master and

the device being controlled is the slave. The master always

initiates the data transfers, and provides the clock for both

transmit and receive operations.TheTurbo IC 24C64 acts as

a slave device in all applications. Either the master or the

slave can take control of the SDA bus, depending on the

requirement of the protocol.

All data is serially transmitted in bytes (8 bits) on the SDA

bus.The acknowledge protocol is used as a handshake sig-

nal to indicate successful transmission of a byte of data.The

bus transmitter, either the master or the slave (Turbo IC

24C64), releases the bus after sending a byte of data on the

SDA bus.The receiver pulls the SDA bus low during the ninth

clock cycle to acknowledge the successful transmission of a

byte of data. If the SDA is not pulled low during the ninth

clock cycle, the Turbo IC 24C64 terminates the data trans-

mission and goes into standby mode.

START/STOP CONDITION AND DATA TRANSITIONS:

While SCL clock is high, a high to low transition on the SDA

bus is recognized as a START condition which precedes any

read or write operation. While SCL clock is high, a low to

high transition on the SDA bus is recognized as a STOP con-

dition which terminates the communication and places the

Turbo IC 24C64 into standby mode.All other data transitions

on the SDA bus must occur while SCL clock is low to ensure

proper operation.

For the write operation, the Turbo IC 24C64 acknowledges

after the device address byte, acknowledges after each

memory address byte, and acknowledges after each subse-

quent data byte.

For the read operation, the Turbo IC 24C64 acknowledges

after the device address byte.Then theTurbo IC 24C64 trans-

mits each subsequent data byte, and the master acknowl-

edges after each data byte transfer, indicating that it requires

more data bytes.The Turbo IC 24C64 monitors the SDA bus

for the acknowledge.To terminate the transmission, the mas-

ter does not acknowledge, and then sends a stop condition.

Write Cycle Timing

SCL

8th BIT

WORD n

ACK

SDA

t

WC

STOP

CONDITION

START

CONDITION

Note: The write cycle time t_WCis the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.

2

Turbo IC, Inc.

24C64

DataValid

SDA

SCL

DATA STABLE

DATA

CHANGE

Start and Stop Definition

SDA

SCL

START

STOP

Output Acknowledge

SCL

1

8

9

DATA IN

DATA OUT

START

ACKNOWLEDGE

3

Turbo IC, Inc.

24C64

address counter is automatically incremented by one. The

DEVICE ADDRESSING:

stop condition starts the internal EEPROM write cycle only if

the stop condition occurs in the clock cycle immediately fol-

lowing the acknowledge (10th clock cycle).All inputs are dis-

abled until the completion of the write cycle. If the WP pin is

high (1) and the memory address is within the upper quad-

rant (1800-1FFFH) of memory, then the stop condition does

not start the internal write cycle, and the Turbo IC 24C64 is

immediately ready for the next command.

Following the start condition, the master will issue a device

address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac-

cess the selected Turbo IC 24C64 for a read or write opera-

tion. The A[2:0] bits must match with the address input pins

of the selected Turbo IC 24C64. If there is a match, the se-

lected Turbo IC 24C64 acknowledges during the ninth clock

cycle by pulling the SDA bus low. If there is no match, the

Turbo IC 24C64 does not acknowledge during the ninth clock

cycle and goes into standby mode.The (R/W) bit is a high (1)

for read and low (0) for write.

POLLING ACKNOWLEDGE:

During the internal write cycle of a write operation in theTurbo

IC 24C64, the completion of the write cycle can be detected

by polling acknowledge.The master starts acknowledge poll-

ing by issuing a start condition, then followed by the device

address byte 1010 (A2) (A1) (A0) 0.If the internal write cycle

is finished, the Turbo IC 24C64 acknowledges by pulling the

SDA bus low. If the internal write cycle is still ongoing, the

Turbo IC 24C64 does not acknowledge because it’s inputs

are disabled. Therefore, the device will not respond to any

command. By using polling acknowledge, the system delay

for write operations can be reduced. Otherwise, the system

needs to wait for the maximum internal write cycle time, tWC,

given in the spec.

DATA INPUT DURING WRITE OPERATION:

During the write operation, the Turbo IC 24C64 latches the

SDA bus signal on the rising edge of the SCL clock.

DATA OUTPUT DURING READ OPERATION:

During the read operation, theTurbo IC 24C64 serially shifts

the data onto the SDA bus on the falling edge of the SCL

clock.

MEMORY ADDRESSING:

The memory address is sent by the master in the form of 2

memory address bytes.The memory address bytes can only

be sent as part of a write operation. The most significant

address byte XXX (B12) (B11) (B10) (B9) (B8) is sent first,

where X represents “don’t care”. Then the least significant

address byte (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) is sent

last.

POWER ON RESET:

The Turbo IC 24C64 has a Power On Reset circuit (POR) to

prevent data corruption and accidental write operations dur-

ing power up. On power up, the internal reset signal is on

and the Turbo IC 24C64 will not respond to any command

until theVCC voltage has reached the POR threshold value.

BYTE WRITE OPERATION:

The master initiates the byte write operation by issuing a

start condition, followed by the device address byte 1010

(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-

lowed by one data byte, followed by an acknowledge, then a

stop condition. After each byte transfer, the Turbo IC 24C64

acknowledges the successful data transmission by pulling

the SDA bus low. The stop condition starts the internal

EEPROM write cycle, and all inputs are disabled until the

completion of the write cycle. If theWP pin is high (1) and the

memory address is within the upper quadrant (1800-1FFFH)

of memory, then the stop condition does not start the inter-

nal write cycle and the Turbo IC 24C64 is immediately ready

for the next command.

PAGE WRITE OPERATION:

The master initiates the page write operation by issuing a

start condition, followed by the device address byte 1010

(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-

lowed by up to 32 data bytes, followed by an acknowledge,

then a stop condition. After each byte transfer, the Turbo

IC24C64 acknowledges the successful data transmission by

pulling SDA low. After each data byte transfer, the memory

4

Turbo IC, Inc.

24C64

Device Address

1

0

1

0

A₂

A₁

A₀R/W

LSB

MSB

Byte Write

S

T

A

R

T

W

R

I

S

T

O

P

T

E

DEVICE

ADDRESS

FIRST

SECOND

WORD ADDRESS WORD ADDRESS

DATA

SDA LINE

* * *

M

S

B

L R A

S / C

B W K

M

S

B

A

C

K

L A

S C

B K

A

C

K

PageWrite

S

T

A

R

T

W

R

I

S

T

O

P

T

E

DEVICE

ADDRESS

FIRST

WORD ADDRESS (n)

SECOND

WORD ADDRESS (n)

DATA (n)

DATA (n + x)

//

SDA LINE

* * *

A

C

K

M

S

B

L R A

S / C

B W K

M

S

B

A

C

K

L A

S C

B K

A

C

K

* = Don't care bits

5

Turbo IC, Inc.

24C64

CURRENT ADDRESS READ:

an acknowledge by pulling the SDA bus low, and then seri-

ally shifts out the data byte accessed from memory at the

location corresponding to the memory address counter.The

master does not acknowledge, then sends a stop condition

to terminate the read operation. It is noted that the memory

address counter is incremented by one after the data byte is

shifted out.

The internal memory address counter of theTurbo IC 24C64

contains the last memory address accessed during the pre-

vious read or write operation, incremented by one. To start

the current address read operation, the master issues a start

condition, followed by the device address byte 1010 (A2) (A1)

(A0) 1. The Turbo IC 24C64 responds with an acknowledge

by pulling the SDA bus low, and then serially shifts out the

data byte accessed from memory at the location correspond-

ing to the memory address counter. The master does not

acknowledge, then sends a stop condition to terminate the

read operation. It is noted that the memory address counter

is incremented by one after the data byte is shifted out.

SEQUENTIAL READ:

The sequential read is initiated by either a current address

read or random address read.After theTurbo IC 24C64 seri-

ally shifts out the first data byte, the master acknowledges

by pulling the SDA bus low, indicating that it requires addi-

tional data bytes. After the data byte is shifted out, the Turbo

IC 24C64 increments the memory address counter by one.

Then the Turbo IC 24C64 shifts out the next data byte. The

sequential reads continues for as long as the master keeps

acknowledging.When the memory address counter is at the

last memory location, the counter will ‘roll-over’ when

incremented by one to the first location in memory (address

zero). The master terminates the sequential read operation

by not acknowledging, then sends a stop condition.

RANDOM ADDRESS READ:

The master starts with a dummy write operation (one with no

data bytes) to load the internal memory address counter by

first issuing a start condition, followed by the device address

byte 1010 (A2) (A1) (A0) 0, followed by the 2 memory ad-

dress bytes. Following the acknowledge from the Turbo IC

24C64, the master starts the current read operation by issu-

ing a start condition, followed by the device address byte

1010 (A2) (A1) (A0) 1. The Turbo IC 24C64 responds with

Current Address Read

S

T

A

R

S

T

O

P

E

A

D

R

DEVICE

ADDRESS

T

DATA

SDA LINE

M

S

B

L R A

S / C

B W K

M

S

B

N

O

A

C

K

Random Read

S

T

A

R

T

W

R

I

T

E

S

T

O

P

R

E

A

D

WORD

DEVICE

ADDRESS

DEVICE

ADDRESS

ADDRESS N

DATA n

//

SDA LINE

//

A

C

K

N

O

M

S

B

L R A

S / C

B W K

A

C

K

A

C

K

DUMMY WRITE

6

Turbo IC, Inc.

24C64

Sequential Read

S

T

A

R

T

S

T

O

P

R

E

A

D

DEVICE

ADDRESS

DATA n

DATA n + 2

DATA n + 3

DATA n +1

SDA LINE

N

O

M

S

B

L R A

S / C

B W K

A

C

K

A

C

K

A

C

K

A

C

K

ABSOLUTE MAXIMUM RATINGS

TEMPERATURE

RECOMMENDED OPERATING CONDITIONS

Temperature Range:

Vcc Supply Voltage:

Commercial:

0° C to 70° C

Storage:

-65° C to 150° C

-55° C to 125° C

Under Bias:

2.7 to 5.5 Volts

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss +6 V to -0.3 V

Endurance:

Data Retention:

1,000,000 Cycles/Byte (Typical)

100 Years

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operation sec-

tion of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS

Symbol

Parameter

Condition

Min

Max

Units

I

Active Vcc Current

Standby Current

READ at 100 KHZ

WRITE at 100 KHZ

Vcc = 2.7 v

0.4

1

mA

uA

V

cc1

I

3

cc2

I

0.5

2.0

3

sb

Vcc = 5.5 v

I

Input Leakage Current

Output Leakage Current

Input Low Voltage

Input High Voltage

Output Low

Vin=Vcc Max

li

I

3

lo

V

-1.0

il

V

Vcc+0.5

0.4

V

ih

V

Vcc=3.0v Iol=2.1 mA

V

ol2

V

Output Low

Vcc=2.7v Iol=-0.15 mA

0.25

V

ol1

7

Turbo IC, Inc.

24C64

BusTiming

t

HIGH

t

F

R

t

LOW

SCL

t

HD.DAT

SU.DAT

SU.STA

t

HD.STA

SU.STO

SDA IN

t

AA

BUF

DH

SDA OUT

A.C. CHARACTERISTICS

Symbol

Parameter

2.7 volt

5.5 volt

Units

Min

Max

100

Min

Max

SCL

T

SCL Clock Frequency

400

100

kHZ

ns

us

ns

us

ns

us

ns

ms

Noise Suppression Time (1)

Clock Low Period

t

4.7

4.0

0.1

4.7

4.0

4.7

0

1.2

0.6

0.1

1.2

0.6

0

LOW

t

Clock High Period

HIGH

t

SCL Low to SDA Data Out

Bus Free to New Start (1)

Start Hold Time

4.5

0.9

AA

t

BUF

t

HD.STA

t

Start Setup Time

SU.STA

t

Data-in Hold Time

HD.DAT

t

Data-in Set-up Time

SCL and SDA Rise Time (1)

SCL and SDA Fall Time (1)

Stop Setup Time

200

100

SU.DAT

t

1.0

0.3

R

t

300

F

t

4.7

0.6

50

SU.STO

t

Data-out Hold Time

Write Cycle Time

100

DH

t

10

WC

Note: 1 This parameter is characterized and not 100% tested.

Part Numbers & Order Information

TU24C64CP3

TURBO IC PRODUCTS AND DOCUMENTS

1.

2.

3.

4.

All documents are subject to change without notice. Please contact Turbo IC for the latest

revision of documents.

Turbo IC does not assume any responsibility for any damage to the user that may result from

accidents or operation under abnormal conditions.

Revision C

Turbo IC does not assume any responsibility for the use of any circuitry other than what

embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

Turbo IC products are not authorized for use in life support systems or other critical systems

where component failure may endanger life. System designers should design with error

detection and correction, redundancy and backup features.

Package

P -PDIP

S -SOIC

Voltage

3 - 2.7 to 5.5 V

2 - 2.2 to 5.5 V

8K X 8

Serial

EEPROM

Rev.5.0 - 11/27/02

Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: 408-392-0208 Fax: 408-392-0207

See us at www.turbo-ic.com


型号：	TU24C64CS2
厂家：	ETC
描述：	CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM CMOS IC 2线总线64K电可擦除可编程只读存储器8K ×8位EEPROM 存储可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总8页 (文件大小：50K)
中文：	中文翻译
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