TXC-04226AIBG [ETC]
Telecomm/Datacomm ; 电信/数据通信\n
| 型号： | TXC-04226AIBG |
| 厂家： | 
ETC |
| 描述： | Telecomm/Datacomm
|
| 文件： | 总2页 (文件大小：34K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
EtherMap -3 Device
Ethernet into STS-3/STM-1 SONET/SDH Mapper
TXC-04226
PRODUCT INFORMATION
FEATURES
DESCRIPTION
The EtherMap™-3 is a highly integrated device that provides for mapping of
10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1 Transport
payloads. The device supports connection for up to eight 10/100 Mbit/s
Ethernet ports, using SMII interfaces, or a single 1000 Mbit/s Ethernet port,
using a GMII interface. In the transmit direction, for each port, received
Ethernet frames are encapsulated using either GFP, LAPS or LAPF protocol.
The encapsulated Ethernet frames are then mapped into a configurable num-
ber of virtual concatenated low and high order payloads, such as VT1.5 SPE/
VC-12/STS-1 SPE/VC-3, or a contiguous concatenated payload such as
STS-3c SPE/VC-4. For both low and high order payloads, the required
SONET/SDH POH bytes and encapsulated Ethernet payload are generated
and output using a byte-wide parallel interface in the TranSwitch Telecom
Bus format. The EtherMap-3 supports Drop bus and Add bus timing modes.
In the receive direction, for each Ethernet port, a configurable number of low
and high order payloads are terminated, with complete POH byte processing
for virtual or contiguous concatenated payloads. Using an external SDRAM,
alignment and differential delay compensation for the received low and high
order virtual concatenated payloads is performed. The Ethernet frames are
then decapsulated using GFP, LAPS or LAPF protocol and forwarded to each
Ethernet port.
• Supports up to eight 10/100 Mbit/s Ethernet ports, each using
a SMII interface
• Supports a single 1000 Mbit/s Ethernet port, using a parallel
GMII interface (lead shared with SMII interfaces)
• Supports Ethernet Management interface for control and
configuration of externally connected PHYs.
• Supports IEEE 802.3 flow control and management statistics
(RMON) on 10/100/1000 Mbit/s Ethernet ports
• Supports Ethernet frame encapsulation/decapsulation
protocols:
• ITU-T G.7041, Generic Framing Procedure (GFP)
• ITU-T X.86/X.85, Link Access Procedure SDH (LAPS)
• ITU-T Q.922, Link Access Procedure Frame Mode (LAPF)
• Performs mapping/demapping of encapsulated Ethernet
frames into/from low order (VT1.5 SPE/VC-12) and high
order (STS-1 SPE/VC-3) virtual concatenated payloads
• Performs mapping/demapping of encapsulated Ethernet
frames into/from a single contiguous concatenated (STS-3c-
SPE/VC-4) payload
For both low and high order virtual concatenated payloads, optional stan-
dards based LCAS processing is provided to allow hitless dynamic band-
width adjustments.
In addition to support for full-rate Ethernet transfer, over-subscribed Ether-
net transfers are also supported using back pressure mechanisms in order to
prevents frame loss.
• Supports optional LCAS processing (per ITU-T G.7042) for
low and high order virtual concatenated payloads
• Glueless memory interface to external 64/128Mb SDRAMs
• Supports 84/63 VT/TU Low Order POH and
Pointer processing
APPLICATIONS
• Supports High Order POH processing for
STS-1/VC-3/STS-3c/VC-4
• SONET/SDH add/drop and terminal multiplexers
• Multi-service access platforms
• Next generation Ethernet switches
• IP DSLAMS
• Byte-wide parallel Add and Drop Telecom Bus interfaces
• Supports per-port Ethernet side and SONET/SDH system side
loopback for system level diagnostics
• 16-bit wide microprocessor interface, selectable between
Motorola or Intel
• Integrated access devices
• Boundary scan (IEEE 1149.1 standard)
• + 3.3V and +1.8V power supplies, 5V tolerant I/O leads
• 400-lead plastic ball grid array package
(27 mm x 27 mm)
CLOCKS
(SONET/SDH Ref,
System, One Sec.)
HO/LO
RING
Ports
HO/LO
POH
Ports
TELECOM BUS SIDE
Controls
ETHERNET LINE SIDE
+1.8V
+3.3V
10/100 Mbit/s SMII (Port 1)
/ 1000 Mbit/s GMII
EtherMap-3
Ethernet into STS-3/STM-1
SONET/SDH Mapper
DROP Bus
ADD Bus
10/100 Mbit/s SMII (Port 8)
TXC-04226
Ethernet
Management
Interface
Microprocessor SDRAM
Interface Interface
Boundary
Scan
U.S. and/or foreign patents issued or pending
Copyright 2002 TranSwitch Corporation
EtherMap is a trademark of TranSwitch Corporation
Document Number:
TXC-04226-MC
Ed. 3, May 2002
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation
3 Enterprise Drive
Shelton, Connecticut 06484
www.transwitch.com
USA
•
•
•
Tel: 203-929-8810
Fax: 203-926-9453
•
•
EtherMap-3, TXC-04226
APPLICATION DIAGRAM
Multi-service Ethernet Aggregation with OC-3/STM-1 Uplink
SDRAM
10/100 Mbit/s
10/100 Mbit/s
SMII interfaces
SMII interfaces
Drop Add
Bus Bus
Ethernet Switch
(24 Ports)
EtherMap-3
TXC-04226
x8
x16
OC-3/STM-1
TEMx28
TXC-04222
Up to 28xDS1 / 21xE1
Gigabit
Ethernet
PHY
EtherMap-3
TXC-04226
1000 Mbit/s
Line
1000 Mbit/s
GMII interface
SDRAM
RELATED PRODUCTS
• TXC-02030 Advanced E3/DS3 Receiver/Transmitter VLSI Device (DART)
• TXC-03003B STM-1/STS-3/STS-3c Overhead Terminator VLSI Device (SOT-3)
• TXC-03453 Triple Level 3 Mapper VLSI Device (TL3M)
• TXC-04222 21/28 Channel Dual Bus High Density Mapper VLSI Device (TEMx28)
• TXC-06103 STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator VLSI Device (PHAST-3N)
• TXC-06212 Programmable, High Performance ATM/PPP/TDM SONET/SDH
Terminator for Level 12 with Enhanced Features VLSI Device (PHAST-12E)
• TXC-06603 OC-12 SONET/SDH Path Overhead Processor, Retimer, and Cross Connect
VLSI Device (POP-12)
FURTHER INFORMATION
Contact TranSwitch for technical and ordering information on these products.
TranSwitch reserves the right to make changes to the
product(s) or circuit(s) described herein without
Document Number:
TXC-04226-MC
Ed. 3, May 2002
notice. No liability is assumed as a result of their use
or application. No rights under any patent accompany
the sale of any such product or circuit.
TranSwitch Corporation
3 Enterprise Drive
Shelton, Connecticut 06484
www.transwitch.com
USA
•
•
•
Tel: 203-929-8810
Fax: 203-926-9453
•
•
相关型号：
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TRANSWITCH
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