U62256 [ETC]
STANDARD 32K X 8 SRAM; 标准的32K ×8 SRAM
| 型号： | U62256 |
| 厂家： | 
ETC |
| 描述： | STANDARD 32K X 8 SRAM |
| 文件： | 总9页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U62256
Standard 32K x 8 SRAM
Description
Features
falling edge of W, or by the rising
edge of E, respectively.
F 32768x8 bit static CMOS RAM
F Access times 70 ns, 100 ns
F Common data inputs and
data outputs
F Three-state outputs
F Typ. operating supply current
70 ns: 50 mA
The U62256 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
MIXMOS cell.
100 ns: 40 mA
F TTL/CMOS-compatible
F Automatical reduction of power
dissipation in long Read Cycles
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
+
F Power supply voltage 5 V 10 %
F Operating temperature ranges
0 to 70 °C
-40 to 85 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity >100 mA
F Package: SOP28 (330 mil)
The Read cycle is finished by the
Pin Configuration
Pin Description
1
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
2
W
3
A13
A8
4
A6
Signal Name Signal Description
5
A9
A5
A0 - A14
Address Inputs
Data In/Out
6
A11
A4
DQ0 - DQ7
7
A3
G
Chip Enable
SOP
E
8
A10
A2
Output Enable
Write Enable
Power Supply Voltage
Ground
G
9
A1
E
W
DQ7
10
11
12
13
14
A0
VCC
VSS
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
Top View
November 01, 2001
1
U62256
A6
A7
Block Diagram
Memory Cell
Array
A8
A9
A10
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
A0
A1
A2
A3
A4
DQ0
DQ1
Sense Amplifier/
Write Control Logic
DQ2
DQ3
DQ4
A5
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
Truth Table
VCC
VSS
E
W
G
Operating Mode
E
W
G
DQ0 - DQ7
H
*
*
High-Z
Standby/not selected
Internal Read
Read
L
L
L
H
H
L
H
L
*
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
a
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.5
-0.5
-
7
VCC + 0.5
VCC + 0.5
1
V
V
b
b
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
C-Type
K-Type
0
-40
70
85
Storage Temperature
Tstg
-65
125
200
°C
Output Short-Circuit Current
at VCC = 5 V and VO = 0 V c
| IOS
|
mA
a Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b Maximum voltage is 7 V
c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
2
November 01, 2001
U62256
Recommended
Operating Conditions
Symbol
VCC
Conditions
Min.
4.5
Max.
5.5
Unit
V
Power Supply Voltage
Input Low Voltage d
VIL
-0.3
2.2
0.8
V
Input High Voltage
VIH
VCC + 0.3
V
d
-2 V at Pulse Width 30 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
VIH
tcW
tcW
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
= 100 ns
70
65
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
VE
= 5.5 V
= VCC - 0.2 V
50
10
µA
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
VCC
VE
= 5.5 V
= 2.2 V
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
= -1.0 mA
= 4.5 V
2.4
V
V
0.4
2
= 3.2 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
-2
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-1
2
mA
mA
3,2
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
Low at Three-State Outputs
-2
=
0 V
November 01, 2001
3
U62256
Symbol
Alt. IEC
07
10
Switching Characteristics
Read Cycle
Unit
Min.
Max.
Min.
Max.
Read Cycle Time
t
t
70
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
cR
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
t
t
70
70
35
25
25
100
100
45
AA
a(A)
a(E)
a(G)
t
t
ACE
t
t
OE
t
t
t
35
HZCE
HZOE
dis(E)
dis(G)
G HIGH to Output in High-Z
t
35
E LOW to Output in Low-Z
t
t
5
0
5
5
0
5
LZCE
LZOE
en(E)
en(G)
G LOW to Output in Low-Z
t
t
Output Hold Time from Address Change
t
t
v(A)
OH
Symbol
Alt. IEC
07
10
Switching Characteristics
Write Cycle
Unit
Min.
70
55
55
0
Max.
Min.
100
70
70
0
Max.
Write Cycle Time
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
cW
Write Pulse Width
t
t
t
w(W)
WP
WP
Write Pulse Width Setup Time
Address Setup Time
t
su(W)
t
t
su(A)
AS
AW
CW
CW
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
t
t
65
65
65
30
0
80
80
80
35
0
su(A-WH)
t
t
t
su(E)
t
w(E)
t
t
su(D)
DS
DH
AH
Data Hold Time
t
t
h(D)
h(A)
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
t
t
0
0
t
t
t
25
25
35
35
HZWE
dis(W)
t
t
HZOE
LZWE
dis(G)
en(W)
t
0
0
0
0
t
t
en(G)
LZOE
4
November 01, 2001
U62256
Data Retention Mode
E-Controlled
VCC
4.5 V
VCC(DR) ≥ 2 V
2.2 V
2.2 V
tDR
trec
Data Retention
E
0 V
V
- 0.2 V ≤ V
≤ V
+ 0.3 V
CC(DR)
E(DR)
CC(DR)
Data Retention
Characteristics
Symbol
Alt. IEC
Conditions
Min. Typ. Max.
Unit
Data Retention Supply Voltage
Data Retention Supply Current
V
2
5.5
30
V
CC(DR)
CC(DR)
I
V
V
= 3 V
µA
CC(DR)
E
= V
CC(DR)-0.2V
Data Retention Setup Time
Operating Recovery Time
t
t
See Data Retention
Waveforms (above)
0
ns
ns
CDR
su(DR)
t
t
t
cR
R
rec
Test Configuration for Functional Check
5 V
A0
VCC
A1
A2
A3
A4
DQ0
DQ1
DQ2
DQ3
A5
960
A6
VIH
A7
A8
A9
DQ4
DQ5
DQ6
DQ7
A10
A11
A12
A13
A14
VIL
VO
30 pF1)
E
W
G
510
VSS
1)
In measurement of t
t
, t
, t
, t
, t
the capacitance is 5 pF.
dis(E), dis(W) dis(G) en(E) en(W) en(G)
November 01, 2001
5
U62256
Capacitance
Conditions
Symbol
Min.
Max.
Unit
V
V
f
= 5.0 V
C
-
-
7
pF
CC
Input Capacitance
I
= V
I
SS
= 1 MHz
= 25 °C
Output Capacitance
C
7
pF
T
O
a
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
U62256
S
K
07
Example
Type
Package
Access Time
07 = 70 ns
10 = 100 ns
S = SOP28 (330 mil)
Operating Temperature Ranges
C = 0 to 70 °C
K = -40 to 85 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
6
November 01, 2001
U62256
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = V , W = V )
IL
IH
tcR
Ai
Address Valid
ta(A)
DQi
Output
Previous Data Valid
tv(A)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read Cycle: W = V )
IH
tcR
Ai
E
Address Valid
ta(E)
tdis(E)
tdis(G)
tsu(A)
ten(E)
ta(G)
G
ten(G)
DQi
Output
High-Z
Output Data Valid
November 01, 2001
7
U62256
Write Cycle1: W-controlled
tcW
Ai
Address Valid
tsu(E)
th(A)
E
tsu(A-WH)
tw(W)
W
tsu(A)
tsu(D)
Input Data Valid
ten(W)
th(D)
DQi
Input
tdis(W)
DQi
High-Z
Output
G
Write Cycle 2: E-controlled
tcW
Ai
E
Address Valid
tsu(A)
th(A)
tw(E)
tsu(W)
W
th(D)
tsu(D)
DQi
Input
Input Data Valid
tdis(W)
ten
(E)
High-Z
DQi
Output
tdis(G)
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
8
November 01, 2001
U62256
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the
failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikro-
elektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall
not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The infor-
mation in this document describes the type of component and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This docu-
ment does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
November 01, 2001
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de
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