UA1 [ETC]
UA1 [Updated 12/01. 8 Pages] FPGA Conversion ULC ; UA1 [ 12/01更新。 8页] FPGA转换ULC\n
| 型号： | UA1 |
| 厂家： | 
ETC |
| 描述： | UA1 [Updated 12/01. 8 Pages] FPGA Conversion ULC
|
| 文件： | 总8页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High performance ULC family suitable for large-sized CPLDs and FPGAs
• Conversion to 1,000,000 gates
• Pin counts to over 976 pins
• Any pin–out matched due to limited number of dedicated pads
• Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
• Low quiescent current: 0.3 nA/gate
• Available in commercial and industrial grades
• 0.35 µm Drawn CMOS, 3 and 4 Metal Layers
• Library Optimised for Synthesis, Floor Plan & Automatic Test Pattern
Generation (ATPG)
0.35 µm ULC
Series
• High Speed Performances:
– 150 ps Typical Gate Delay @3.3V
– Typical 600 MHz Toggle Frequency @3.3V
– Typical 360 MHz Toggle Frequency @2.5V
• High System Frequency Skew Control:
– Clock Tree Synthesis Software
UA1
• Low Power Consumption:
– 0.25 µW/Gate/ MHz @3.3V
– 0.18 µW/Gate/ MHz @2.5V
• Power on Reset
• Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
• CMOS/TTL/PCI Interface
• ESD (2 kV) and Latch-up Protected I/O
• High Noise & EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery & Core
Description
The UA1 series of ULCs is well suited for conversion of large sized CPLDs and
FPGAs. Devices are implemented in high–performance CMOS technology with
0.35µm (drawn) channel lengths, and are capable of supporting flip–flop toggle rates
of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps
at 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLD
architecture and FPGA device types with higher IO count. A compact RAM cell, along
with the large number of available gates allows the implementation of RAM in FPGA
architectures that support this feature, as well as JTAG boundary–scan and scan–
path testing.
Conversion to the UA1 series of ULC can provide a significant reduction in operating
power when compared to the original PLD or FPGA. This is especially true when
compared to many PLD and CPLD architecture devices, which typically consume
100mA or more even when not being clocked. The UA1 series has a very low
standby consumption of 0.3nA/gate typically commercial temperature, which would
yield a standby current of 42µA on a 144,000 gates design. Operating consumption is
a strict function of clock frequency, which typically results in a power reduction of 50%
to 90% depending on the device being compared.
The UA1 series provides several options for output buffers, including a variety of drive
levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques
are used for improved noise immunity and reduced EMC emissions, including: several
independent power supply busses and internal decoupling for isolation; slew rate lim-
ited outputs are also available if required. The UA1 series is designed to allow
conversion of high performance 3.3V devices as well as 2.5V devices.
Rev. B – 05-Dec-01
1
Support of mixed supply conversions is also possible, allowing optimal trade–offs
between speed and power consumption.
Array Organization
Full Programmable
Usable Pads
Equivalent FPGA
Gates
Part Number
UA1044
UA1068
UA1084
UA1100
UA1120
UA1132
UA1144
UA1160
UA1184
UA1208
UA1228
UA1256
UA1304
UA1352
UA1388
UA1432
UA1484
UA1540
UA1600
UA1700
UA1800
UA1900
UA1976
Max Pad Count
44
Routable Gates
3729
36
14916
47044
68
60
11760
84
76
19734
78936
100
120
132
144
160
184
208
228
256
304
352
388
432
484
540
600
700
800
900
976
92
29760
119040
168844
208888
253192
319464
430152
525296
640080
818208
1169152
1476656
1805076
2261724
2633256
3305412
4101840
5630544
6767624
8607060
9226436
112
124
136
152
176
200
220
240
288
336
372
416
468
516
576
676
776
876
952
42211
52222
63298
79866
107538
13124
160020
204552
292288
369164
451269
565431
658314
826353
1025460
1407636
1691906
2151765
2360609
Architecture
The basic element of the UA1 family is called a cell. One cell can typically implement
between one to four FPGA gates. Cells are located contiguously through out the core
of the device, with routing resources provided in three to four metal layers above the
cells. Some cell blockage does occur due to routing, and utilization will be significantly
greater with three metal routing than two. The sizes listed in the Product Outline are
estimated usable amounts using three metal layers. I/O cells are provided at each pad,
and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any
FPGA or PLD pinout.
In order to improve noise immunity within the device, separate VDD and VSS busses are
provided for the internal cells and the I/O cells.
2
UA1
Rev. B – 05-Dec-01
UA1
I/O buffer interfacing
I/O Flexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A
level translator could be located close to each buffer.
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull
up or pull down resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen
option. 36mA achievable, using 2 pads.
Slew Rate Controlled Output Buffer
In this mode, the p– and n–output transistors commands are delayed, so that they are
never set “ON” simultaneously, resulting in a low switching current and low noise.
These buffers are dedicated to very high load drive.
2.5V Compatibility
The UA1 series of ULC’s is fully capable of supporting high–performance operation at
2.5V or 3.3V. The performance specifications of any given ULC design however, must
be explicitly specified as 2.5V, 3.3V or both.
Power Supply and Noise The speed and density of the UA1 technology cause large switching current spikes, for
example when:
Protection
•
•
16 high current output buffers switch simultaneously, or
10% of the 700 000 gates are switching within a window of 1ns.
Sharp edges and high currents cause some parasitic elements in the packaging to
become significant. In this frequency range, the package inductance and series resis-
tance should be taken into account. It is known that an inductor slows down the setting
time of the current and causes voltage drops on the power supply lines. These drops
can affect the behavior of the circuit itself or disturb the external application (ground
bounce).
In order to improve the noise immunity of the UA1 core matrix, several mechanisms
have been implemented inside the UA1 arrays. Two types of protection have been
added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers
against the switching noise coming from the matrix.
I/O buffers switching protection
Three features are implemented to limit the noise generated by the switching current:
•
•
The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal
regulator.
•
A design rule concerning the number of buffers connected on the same power
supply line has been imposed.
Matrix switching current
protection
This noise disturbance is caused by a large number of gates switching simultaneously.
To allow this without impacting the functionality of the circuit, three new features have
been added:
•
Decoupling capacitors are integrated directly on the silicon to reduce the power
supply drop.
3
Rev. B – 05-Dec-01
•
•
A power supply network has been implemented in the matrix. This solution reduces
the number of parasitic elements such as inductance and resistance and constitutes
an artificial VDD and Ground plane. One mesh of the network supplies approximately
150 cells.
A low pass filter has been added between the matrix and the input to the output
buffer. This limits the transmission of the noise coming from the ground or the VDD
supply of the matrix to the external world via the output buffers.
Absolute Maximum
Ratings
Max Supply Core Voltage (VDD) ..............................................................3.6V
Max Supply Periphery Voltage (VDD5) .....................................................5.5V
InputVoltage (VIN)VDD .............................................................................+ 0.5V
5V Tolerant/Compliant VDD5 ...................................................................+ 0.5V
Storage Temperature ..............................................................................-65° to 150°C
Operating Ambient Temperature.............................................................-55° to 125°C
Recommended
Operating Range
VDD ....................................................................................................2.5V ± 5% or 3.3V
Operating Temperature
Commercial .............................................................................................0° to 70°C
Industrial..................................................................................................-40° to 85°C
4
UA1
Rev. B – 05-Dec-01
UA1
DC Characteristics
2.5V
Specified at VDD = +2.5V
Symbol
TA
Parameter
Buffer
All
Min
-40
2.3
Typ
Max
+85
2.7
10
Unit
°C
Conditions
Operating Temperature
SupplyVoltage
VDD
IIH
All
2.5
V
High level input current
CMOS
PCI
µA
VIN = VDD,VDD = VDD(max)
VIN = VSS,VDD = VDD (max)
10
IIL
Low Level input current
CMOS
PCI
-10
-10
µA
High-Impedance State
Output Current
VIN = VDD or VSS,
IOZ
IOS
All
10
µA
VDD = VDD (max), No Pull-up
VOUT = VDD,VDD = VDD (max)
VOUT = VSS,VDD = VDD (max)
Output short-circuit current
PO11
9
6
mA
PO11
CMOS
VIH
VIL
High-level InputVoltage
0.7VDD
0.475VDD
0.7VDD
V
V
PCI
CMOS Schmitt
CMOS
1.5
Low-Level InputVoltage
0.3VDD
0.325VDD
0.3VDD
PCI
CMOS Schmitt
CMOS Schmitt
1.0
0.5
Vhys
VOH
Hysteresis
V
V
IOH = 1.4mA,VDD = VDD (min)
IOH = -500µA
High-Level output voltage
PO11
PCI
0.7VDD
0.9VDD
IOL = 1.4mA,VDD = VDD (min)
IOL = 1.5mA
VOL
Low-Level output voltage
PO11
PCI
0.4
V
0.1VDD
5
Rev. B – 05-Dec-01
3.3V
Specified at VDD = +3.3V
Symbol
TA
Parameter
Buffer
All
Min
-40
3.0
Typ
Max
+85
3.6
10
Unit
°C
Conditions
Operating Temperature
SupplyVoltage
VDD
All
3.3
V
IIH
High level input current
CMOS
PCI
µA
VIN = VDD,VDD = VDD(max)
VIN = VSS,VDD = VDD(max)
10
IIL
Low Level input current
CMOS
PCI
-10
-10
µA
High-Impedance State
Output Current
VIN = VDD or VSS,
IOZ
IOS
All
10
µA
VDD = VDD (max), No Pull-up
VOUT = VDD,VDD = VDD (max)
VOUT = VSS,VDD = VDD (max)
Output short-circuit current
PO11
14
-9
mA
PO11
CMOS, LVTTL
PCI
VIH
VIL
High-level InputVoltage
2.0
0.475VDD
2.0
V
V
CMOS Schmitt
CMOS
1.7
Low-Level InputVoltage
0.8
PCI
0.325VDD
CMOS/TTL-level
Schmitt
1.1
0.6
0.8
Vhys
VOH
Hysteresis
TTL-level Schmitt
V
V
IOH = 2mA,VDD = VDD (min)
IOH = -500µA
High-Level output voltage
PO11
PCI
0.7VDD
0.9VDD
IOL = 2mA ,VDD = VDD (min)
IOL = 1.5mA
VOL
Low-Level output voltage
PO11
PCI
0.4
V
0.1VDD
6
UA1
Rev. B – 05-Dec-01
UA1
5V
Specified at VDD = +5V +/-10%
Symbol
Parameter
Operating Temperature
SupplyVoltage
Buffer
All
Min
-55
3.0
4.5
Typ
Max
+125
3.6
Unit
°C
V
Conditions
TA
VDD
VDD5
IIH
5V Tolerant
5V Compliant
CMOS
PCI
3.3
5.0
SupplyVoltage
5.5
V
High level input current
10
µA
VIN = VDD,VDD = VDD(max)
VIN = VSS,VDD = VDD(max)
10
IIL
Low Level input current
CMOS
PCI
-10
-10
µA
High-Impedance State
Output Current
VIN = VDD or VSS,
IOZ
IOS
All
10
µA
VDD = VDD (max), No Pull-up
VOUT = VDD,VDD = VDD (max)
VOUT = VSS,VDD = VDD (max)
Output short-circuit current
PO11V
8
mA
PO11V
PICV, PICV5
PCI
-7
VIH
VIL
High-level InputVoltage
2.0
5.0
5.0
5.5
5.5
V
V
0.475VDD
CMOS/TTL-level
Schmitt
2.0
1.7
Low-Level InputVoltage
PICV, PICV5
PCI
0.5VDD
0.8
0.325VDD
CMOS/TTL-level
Schmitt
1.1
0.6
0.8
Vhys
VOH
Hysteresis
TTL-level Schmitt
PO11V
V
V
IOH = -1.7mA
IOH = -1.7mA
High-Level output voltage
0.7VDD
PO11V5
PO11V
0.7VDD5
VOL
Low-Level output voltage
0.5
0.5
V
IOL = 1.7mA
PO11V5
I/O Buffer
Symbol
Parameter
Typ
2.4
5.6
6.6
Unit
Conditions
3.3V
C IN
C OUT
C I/O
Capacitance, Input Buffer (Die)
Capacitance, Output Buffer (Die)
Capacitance, Bidirectional
pF
pF
pF
3.3V
3.3V
7
Rev. B – 05-Dec-01
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