UC1701cGAB [ETC]
Single-Chip, Ultra-Low Power 65COM by 132SEG Passive Matrix LCD Controller-Driver;
| 型号： | UC1701cGAB |
| 厂家： | 
ETC |
| 描述： | Single-Chip, Ultra-Low Power 65COM by 132SEG Passive Matrix LCD Controller-Driver CD |
| 文件： | 总51页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H
IGH-VOLTAGE MIXED-SIGNAL IC
65x132 STN Controller-Driver
MP Specifications
Datasheet Revision: 1.0
IC Version: c_B
September 29, 2014
U
LTRA HIP
C
The Coolest LCD Driver, Ever!
S p e c i f i c a t i o n s a n d i n f o r m a t i o n h e r e i n a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e .
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
Table of Content
I
NTRODUCTION.................................................................................... 3
PPLICATIONS ......................................................................... 3
IGHLIGHTS ............................................................................. 3
NFORMATION......................................................................... 4
IAGRAM .............................................................................. 5
ESCRIPTION.................................................................................... 6
ECOMMENDED COG LAYOUT ................................................................ 8
EGISTERS ....................................................................... 9
ABLE ................................................................................. 11
ESCRIPTION ....................................................................... 12
ETTING........................................................................ 17
ERENCE ....................................................................... 18
ONTROLS...................................................................... 20
ITO LAYOUT AND LC SELECTION........................................................... 21
M
AIN
EATURE
RDERING
LOCK
IN
A
F
H
O
I
B
D
P
R
C
C
C
D
ONTROL
R
OMMAND
OMMAND
T
D
LCD VOLTAGE
UICK
LCD DISPLAY
S
VLCD
Q
R
C
H
D
R
A
OST
ISPLAY
ESET & POWER
BSOLUTE AXIMUM
I
NTERFACE .................................................................................. 24
ATA RAM (DDRAM)............................................................. 31
ANAGEMENT ............................................................ 33
ATINGS .............................................................. 38
PECIFICATIONS ................................................................................... 39
AC CHARACTERISTICS .......................................................................... 40
IMENSIONS.......................................................................... 45
NFORMATION ........................................................... 46
D
M
M
R
S
PHYSICAL
D
ALIGNMENT
MARK I
P
AD
C
OORDINATES............................................................................... 47
NFORMATION .............................................................................. 50
TRAY
I
REVISION
HISTORY................................................................................ 51
2
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
UC1701
Single-Chip, Ultra-Low Power
65COM by 132SEG
Passive Matrix LCD Controller-Driver
•
Support industry standard 8-bit parallel bus (8080 or
6800 mode), 4-wire serial bus (S8), and 2-wire I2C serial
interfaces.
I
NTRODUCTION
UC1701c is an advanced high-voltage mixed-signal CMOS IC,
especially designed for the display needs of ultra-low power
hand-held devices.
•
•
Ultra-low power consumption under all display patterns.
Selectable Mux Rate and Bias Ratio allow flexible power
management options.
In addition to low power column and row drivers, the
contains all necessary circuits for high-V LCD power sply,
bias voltage generation, timing generation and graphics data
memory.
•
•
•
Internal charge pump with on-chip pumping capacitor
requires only 1 external capacitor to operate.
Very low pin count (7~9-pin) allows exceptional image
quality in COG format on conventional ITO glass.
Advanced circuit design techniques are employed to minimize
external component counts and reduce connector size while
achieving extremely low power consuion.
Flexible data addressing/mapping schemes to support
wide ranges of software models and LCD layout
placements.
M
AIN APPLICATIONS
•
VDD range (Typ.):
VDD2/3 range(Typ.):
LCD VOP range:
2.7V ~ 3.3V
2.7V ~ 3.3V
3.85V ~ 10.0V
•
Cellular Phones, SmaPhones, PDA, and other battery
operated palm top devices or portable Instruments
•
•
Available in gold bump dies
COM/SEG bump information
F
EATURE HIGHLIGHTS
Bump pitch:
Bump gap:
27 µM
•
Single chip controller-driver supports 65x132 graphics
STN LCD panels.
12 µM ± 3 µM
Bump surface:
1500 µM2
•
Support both row ordered and column ordered display
buffer RAM access.
3
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
O
RDERING
Part Number
UC1701cGAB
I
NFORMATION
I2C
Yes
Yes
Description
Gold Bumped Die, Bump Height: 10uM
Gold Bumped Die, Bump Height: 15uM
UC1701cGBB
General Notes
APPLICATION INFORMATION
For improved readability, the specification contains many application data points. When application information is given, it is advisory and does
not form part of the specification for the device.
U
SE OF I2C
The implementation of I2C is already included and tested in all silicon.
B
ARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing. There is no post waffle saw/pack testing
performed on individual die. Although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers,
UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the
customer to test and qualify their application in which the die is to be used. UltraChip assumes no liability for device functionality or performance
of the die or systems after handling, packing or assembly of the die.
L
IFE SUPPORT APPLICATIONS
These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to
result in personal injuries. Customer using or selling these products for use in such applications do so at their own risk.
CONTENT DISCLAIMER
UltraChip believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. No
responsibility is assumed by UltraChip for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be
reproduced, or transmitted in any form or by any means without the prior consent of UltraChip Inc. UltraChip's terms and conditions of sale apply
at all times.
CONTACT DETAILS
UltraChip Inc. (Headquarter)
4F, No. 618, Recom Road,
Neihu District, Taipei 114,
Taiwan, R. O. C.
Tel: +886 (2) 8797-8947
Fax: +886 (2) 8797-8910
Sales e-mail: sales@ultrachip.com
Web site: http://www.ultrachip.com
4
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
BLOCK DIAGRAM
COM0…COM63
COMS
SEG0…SEG131
VG
VM
SEGMENT
Drivers
COMMON
Drivers
VMO
Voltage
COMMON
Output
Controller
Follower
VGin
VGout
VGs
Display Data
Latchs
XV0
Generator
XV0in
XV0out
XV0s
XV0
Timing
Generator
Display Data RAM
(DDRAM)
V0
Generator
V0in
V0out
V0s
V0
132 x 65
Oscillator
TST4
VDD2
VSS2
VDD3
Power System
Data
Register
Address
Counter
Control
Registers
VDD
VSS
Address
Counter
Reset
Circuit
MPU INTERFACE (Parallel / Serial)
5
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
P
IN DESCRIPTION
Pin (Pad) Name
Type
Pins
Description
M
AIN POWER SUPPLY
VDD supplies for Display Data RAM anital logic, VDD2 supplies for analog circuit,
VDD3 supplies for reference voltage circ
VDD
VDD2
VDD3
3
4
2
PWR
GND
VDD2/VDD3 should be connected to the same power source. But VDD can be connected
to a source voltage no higher than VDD2/VDD3
.
ITO trace resistance needs to be minimized for VDD2/VDD3.
VSS
VSS2
2
4
Ground. Connect VSS an2 to the shared GND pin. In COG applications, minimize
the ITO resistance for both VSS and VSS2.
LCD POWER
SUPPLY & VOLTAGE CONTROL
V0 is the LCD driving voltage for COM circuit at negative frame.
V0in is the nput of common circuits.
V0out is the tput of V0 regulator.
V0in
V0out
V0s
2
2
1
V0s is the feedback of V0 regulator.
PWR
PWR
Be sure that V0 ꢀ VG > VM > VSS ꢀ XV0, under operation.
These pins should be separated in ITO layout; while they should be connected
together in FPC layout.
VG is the LCD driving voltage for segment circuit.
VGout is the output of VG regulator. VGs is the feedback of VG regulator.
VGin is the VG input of segment circuits.
VGin
VGout
VGs
2
1
1
1.6V ꢁ VG < VDD2
.
These pins should be separated in ITO layout; while they should be connected
together in FPC layout.
XV0 is the LCD driving voltage for common circuit at positive frame.
XV0out is the output of XV0 regulator. XV0s is the feedback of XV0 regulator.
XV0in is the XV0 input of common circuits.
XV0in
XV0out
XV0s
2
2
1
PWR
PWR
These pins should be separated in ITO layout; while they should be connected
together in FPC layout.
VM is the LCD driving voltage for common circuits.
VMO
2
0.8V ꢁ VM < VDD2
.
NOTE
•
Recommended capacitor values:
CV0: Optional. 0.1uF/16V. Connect the capacitor of CV0 value between XV0 and V0.
HOST INTERFACE
Bus mode: The interface bus mode is determined by BM[1:0] and TST5
by the following relationship:
BM[1:0]
11
TST5
Open
Open
Open
1
Mode
6800/8-bit
BM0
BM1
TST5
1
1
1
I
10
8080/8-bit
4-wire SPI w/ 8-bit token (S8: conventional)
2-wire serial (I2C)
0x
Always connect unused pins to either Vss or VDD
.
Chip Select. Chip is selected when CS0 = “L”. When the chip is not selected, D[7:0] will
be of high impedance.
CS0
RST
I
I
1
1
It’s necessary to set pin-reset in 3 mS after VDD/2/3 stable. When RST=”L”, all control
registers are re-initialized by their default states.
An RC Filter has been included on-chip. There is no need for external RC noise filter.
6
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
Pin (Pad) Name
Type
Pins
Description
Select Control data or Display data for read/write operation.
CD
I
1
”L”: Control data
”H”: Display data
WR [1:0] controls the read/write operation oe host interface. See Host Interface
section for details.
WR0 / A3
WR1 / A2
1
1
In parallel mode, the meaning of WR[1pends on which interface it is in, 6800 or
8080 mode. In serial interface modes, these two pins are not used. Connect them to
I
I
VSS or VDD
.
In I2C mode, these two pins specifies bits 3~2 of device address (A[3:2]).
Duty selection.
DT2 DT1
Duty
1/65
1/49
1/33
1/55
DT1
DT2
1
1
0
0
1
1
0
1
0
1
Bi-drectional bus for both serial and parallel host interfaces.
In serial modes, connect D[7] to SDA, D[6] to SCK.
D7
Parallel (8-bit) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Serial (S8, I2C) SDA SCK --
-- -- -- -- --
Always connect unused pins to either VSS or VDD
D6 D5 D4 D3 D2 D1 D0
D7~D0
I/O
HV
8
.
HIGH VOLTAGE LCD DRIVER OUTPUT
SEG0 ~
SEG131
SEG (column) driver outputs. Support up to 132 pixels.
Leave unused SEG drivers open-circuit.
132
COM0 ~
COM63
COM (row) driver outputs. Support up to 64 rows.
Leave unused COM drivers open-circuit.
HV
HV
64
2
CIC
Icon driver outputs. Leave it open if not used.
M
ISC. PINS
Auxiliary VDD. This pin is connected to the main VDD bus within the IC. It’s provided to
facilitate chip configurations in COG application.
VDDX
2
There’s no need to connect VDDX to main VDD externally and it should NOT be used to
provide VDD power to the chip.
Auxiliary Vss. These pins are connected to the main Vss bus within the IC, to facilitate
chip configurations in COG application.
VSSX
2
1
There’s no need to connect VssX to main Vss externally and they should NOT be used
to provide Vss power to the chip.
Test control. There’s an on-chip pull-up resistor for TST4. Leave it open during normal
use.
TST4
I
TST2
I/O
1
8
Test I/O pins. Leave these pins open during normal use.
Dummy pins are NOT connected inside the IC.
Dummy
7
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
RECOMMENDED COG LAYOUT
CS0
RST
CD
WR0
WR1
D0
COM<53>
COM<54>
COM<55>
COM<56>
COM<57>
COM<58>
COM<59>
COM<60>
COM<61>
COM<62>
COM<63>
CIC
C
CO
COM<
COM<48>
OM<47>
6>
C
COM
COM<43>
COM<42>
COM<41>
COM<40>
COM<39>
COM<38>
COM<37>
COM<36>
COM<35>
COM<34>
COM<33>
COM<32>
D1
SEG<131>
SEG<130>
SEG<129>
SEG<128>
SEG<127>
SEG<126>
SEG<125>
SEG<124>
SEG<123>
SEG<122>
SEG<121>
SEG<120>
SEG<119>
SEG<118>
SEG<117>
SEG<116>
SEG<115>
SEG<114>
SEG<113>
SEG<112>
SEG<111>
SEG<110>
SEG<109>
SEG<108>
SEG<107>
SEG<106>
SEG<105>
SEG<104>
SEG<103>
SEG<102>
SEG<101>
SEG<100>
SEG<99>
SEG<98>
SEG<97>
SEG<96>
SEG<95>
SEG<94>
SEG<93>
SEG<92>
SEG<91>
SEG<90>
SEG<89>
SEG<88>
SEG<87>
SEG<86>
SEG<85>
SEG<84>
SEG<83>
SEG<82>
SEG<81>
SEG<80>
SEG<79>
SEG<78>
SEG<77>
SEG<76>
SEG<75>
SEG<74>
SEG<73>
SEG<72>
SEG<71>
SEG<70>
SEG<69>
SEG<68>
SEG<67>
SEG<66>
SEG<65>
SEG<64>
SEG<63>
SEG<62>
SEG<61>
SEG<60>
SEG<59>
SEG<58>
SEG<57>
SEG<56>
SEG<55>
SEG<54>
SEG<53>
SEG<52>
SEG<51>
SEG<50>
SEG<49>
SEG<48>
SEG<47>
SEG<46>
SEG<45>
SEG<44>
SEG<43>
SEG<42>
SEG<41>
SEG<40>
SEG<39>
SEG<38>
SEG<37>
SEG<36>
SEG<35>
SEG<34>
SEG<33>
SEG<32>
SEG<31>
SEG<30>
SEG<29>
SEG<28>
SEG<27>
SEG<26>
SEG<25>
SEG<24>
SEG<23>
SEG<22>
SEG<21>
SEG<20>
SEG<19>
SEG<18>
SEG<17>
SEG<16>
SEG<15>
SEG<14>
SEG<13>
SEG<12>
SEG<11>
SEG<10>
SEG<9>
D2
D3
D4
D5
D6
D7
VDD
VSS
V0
XV0
VG
TST5
BM0
BM1
DT1
DT2
SEG<8>
SEG<7>
SEG<6>
SEG<5>
SEG<4>
SEG<3>
SEG<2>
SEG<1>
SEG<0>
CIC
COM<0>
COM<1>
COM<2>
COM<3>
COM<4>
COM<5>
COM<6>
COM<7>
COM<8>
COM<9>
COM<10>
COM<11>
COM<12>
COM<13>
COM<14>
COM<15>
COM<16>
COM<17>
COM<18>
COM<19>
COM<31>
COM<30>
COM<29>
COM<28>
COM<27>
COM<26>
COM<25>
COM<24>
COM<23>
COM<22>
COM<21>
COM<20>
NOTES FOR VDD WITH COG:
The operation condition, VDD=2.7V (typical), should be satisfied under all operating conditions. UC1701c’s peak current (IDD) can
be up to ~15mA during high speed data-write to UC1701c’s on-chip SRAM. Such high pulsing current mandates very careful
design of VDD and VSS ITO trances in COG modules. When VDD and VSS trace resistance is not low enough, the pulsing IDD current
can cause the actual on-chip VDD to drop to below 2.6V and cause the IC to malfunction.
8
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
CONTROL REGISTERS
UC1701c contains registers, which control the chip operation. The following table is a summary of these control registers, a brief
description and the default values. These registers can be modified by commands, whih will be described in the next two sections,
Command Table and Command Description.
Name:
The Symbolic reference of the register. Note that, some symbol name rs to bits (flags) within another register.
Default: Numbers shown in Bold font are default values after hardware eset.
Name
Bits
Default
Description
SL
6
00H
Scroll Line. Scroll the displayed imup by SL rows. The valid SL value is between 0 (for no
scrolling) and 63. Setting SL outsithis range causes undefined effects on the displayed
image. This register does not affect icon output CIC.
CA
8
00H
Column Address of DDRAM (Display Data RAM). Value range is 0~131.
(Used in Host to access DDRAM)
PA
BR
4
1
0H
0H
Page Address of DD. Value range 0~8. (Used in Host to access DDRAM)
Bias Ratio. The ratio etween VLCD and VBIAS varies according to Duty selected:
BR=0
1/9
1/8
1/6
1/8
BR=1
1/7
1/6
1/5
1/6
Duty=1/65
Duty=1/49
Duy=1/33
D=1/55
PM
PC
6
6
20H
20H
Adjust contrast of LCD panel display.
Power Control.
PC [0]: VG pump control. (Default 0: Disable)
PC [1]: V0 pump control. (Default 0: Disable)
PC [2]: XV0 pump control. (Default 0: Disable)
PC [5:3]: Resistor Ratio for VLCD. (Default 100b)
000b~111b : Rb/Ra ratio setting
CR
8
1
0H
0H
Return Column Address. Useful for cursor implementation.
AC3
Address Control.
AC3: CUM: Cursor update mode, (Default 0: OFF)
When CUM=1, CA increment on write only, wrap around suspended
DC
LC
3
2
0H
0H
Display Control:
DC[0]: PXV: Pixels Inverse (bit-wise data inversion. Default 0: OFF)
DC[1]: APO: All Pixels ON (Default 0: OFF)
DC[2]: Display ON/OFF (Default 0: OFF)
When DC[2] is set to 0, the IC will enter Sleep Mode
LCD Control:
LC[0]: MX, Mirror X SEG/Column sequence inversion (Default: 0: OFF)
LC[1]: MY, Mirror Y COM/Row sequence inversion (Default: 0: OFF)
APC0
APC1
8
8
90H
--
Advanced Program Control.
APC0 [7] : TC, VBIAS temperature compensation coefficient (%-per-oC)
0b : TC curve definition = -0.05% / oC
1b : TC curve definition = -0.11% / oC
APC0 [6] is fixed.
APC0 [5:4] : FR, Frame Rate: (Unit: Hz)
Frame Rate FR[1:0]: 00b
FR[1:0]: 01b
FR[1:0]: 10b
FR[1:0]: 11b
115
77
136
153
76
Duty:1/65
Duty:1/55
Duty:1/49
Duty:1/33
58
102
115
57
96
170
191
94
203
229
113
APC0 [3:2] are fixed.
APC0 [1:0] : WA, automatic column/row Wrap Around.
WA[0] : 0: PA wrap around disable
1: PA wrap around enable.
WA[1] : 0: CA wrap around disable
1: CA wrap around enable.
APC1[7:0] : For UltraChip’s use only. Do NOT use.
9
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
Name
Bits
Default
Description
Status Registers
BZ,
MX,
DE,
RST
1
1
1
1
0
BZ : Set to 1 when system is busy. Commands can only be accepted when BZ=0.
MX : Mirror X-axle (i.e. SEG or column)
DE : Set to 1 when display enabled.
RST : Reset flag. RST=1 when reset is in progre.
10
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
COMMAND
TABLE
The following is a list of host commands supported by UC1701c
C/D: 0: Control, 1: Data
W/R: 0: Write Cycle, 1: Read Cycle
D7-D0: # Useful Data bits, – Don’t Care
Command
1. Write Data Byte
2. Read Data Byte
3. Get Status
C/D W/R D7 D6 D5 D4 D3 D2 D1 0
Action
Default
1
1
0
0
1
1
#
#
#
#
#
#
#
#
#
#
0
#
#
#
#
0
0
#
0
0
1
0
#
0
0
0
0
1
1
1
-
#
#
0
#
#
#
#
#
#
0
#
1
1
1
0
-
0
0
0
0
1
1
1
-
#
0
#
#
#
#
#
#
0
#
0
1
1
0
-
1
1
1
0
1
0
0
-
#
#
0
#
#
#
#
#
#
1
#
#
#
#
#
-
0
1
#
0
0
0
1
-
Write 1 byte
Read 1 byte
Get Status
Set CA [3:0]
Set CA [7:4]
Set PC[2:0]
Set SL[5:0]
Set PA[3:0]
Set PC[5:3]
N/A
N/A
--
0
0
000b
0
0
BZ MX DE RST
Set Column Address LSB
Set Column Address MSB
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
-
0
0
0
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
-
0
0
1
#
1
1
0
#
1
1
1
1
0
1
1
1
1
1
1
1
-
0
1
#
1
0
0
#
0
0
0
0
0
0
0
0
0
0
0
0
-
4.
0
0
5. Set Power Control
6. Set Scroll Line
7. Set Page Address
8. Set VLCD Resistor Ratio
0
0
0
0
0
0
0
0
100b
Set Electronic Volume
(double-byte command)
9.
0
0
Set PM[5:0]
20H
10. Set All-Pixel-ON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Set DC[1]
Set DC[0]
Set DC[2]
Set LC[0]
Set LC[1]
0b
0b
0b
0b
0b
N/A
N/A
0b
N/A
N/A
N/A
11. Set Inverse Display
12. Set Display Enable
13. Set SEG Direction
14. Set COM Direction
15. System Reset
Software Reset
No operation
Set BR
AC3=1, CR=CA
AC3=0, CA=CR.
NOP
16. NOP
17. Set LCD Bias Ratio
18. Set Cursor Update Mode
19. Reset Cursor Update Mode
20. Set Static Indicator OFF
Set Static Indicator ON
Set Static Indicator
21.
0
0
0
0
0
0
0
0
0
0
0
0
NOP
NOP
N/A
0b
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
#
Set Booster Ratio
(double-byte command)
22.
Set Power Save
23.
Display OFF &
All Pixel ON
#
#
#
#
#
#
#
#
N/A
N/A
(compound command)
1
-
1
#
1
#
1
#
1
0
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
0
1
#
1
#
0
0
0
#
TT
Set Test Control
(double-byte command)
For UCI only
Do NOT use
24.
#
1
#
1
#
#
0
#
1
#
Set Adv. Program Control 0
(double-byte command)
25.
26.
90H
N/A
Set TC, FR, WA
Set Adv. Program Control 1
(double-byte command)
For UCI only
Set APC1
* Any bit patterns other than the commands listed above, may result in NOP (No Operation).
11
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
COMMAND DESCRIPTION
1. Write Data Byte to Memory
Action
C/D W/R
D7
D7
D6
D6
D5
D5
D3
D2
D2
D1
D1
D0
D0
Write data
1
0
8-data write to SRAM
2. Read Data Byte from Memory
Action
C/D W/R
D4
D3
Read data
1
1
8-bit data read from SRAM
Write/Read Data Byte (Command 1,2) access Display Data RAM baed on Page Address (PA) register and Column Address (CA)
register. PA and CA can also be programmed directly by issuing Set Page Address and Set Column Address commands.
3. Get Status
Action
C/D W/R
7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
Get Status
0
1
BZ
MX
DE
RST
BZ: BZ=1 when busy. The system accepts commands only when BZ=0.
MX: Mirror X. Status of register LC[0]
DE: Display Enable flag. DE=1 when isplay is enabled.
RST: RST flag. RST=1 when reset is progress.
4. Set Column Address
Action
C/D W/R
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
Set Column Address LSB, CA[3:0]
Set Column Address MSB, CA[7:4]
0
0
0
0
CA3
CA7
CA2
CA6
CA1
CA5
CA0
CA4
0
0
0
1
Set the SRAM column address before Write/Read memory from host interface.
CA value range: 0~131
5. Set Power Control
Action
C/D W/R
D7
0
D6
0
D5
1
D4
0
D3
1
D2
D1
D0
Set Pump Control, PC[2:0]
0
0
PC2
PC1
PC0
Set PC[2:0] to enable the built-in charge pump.
PC[2] : XV0 pump control. 0: Disable (Default)
PC[1] : V0 pump control. 0: Disable (Default)
PC[0] : VG pump control. 0: Disable (Default)
12
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
6. Set Scroll Line
Action
C/D W/R
D7
0
D6
1
D5
D4
D3
D2
D1
D0
Set Scroll Line, SL[5:0]
0
0
SL5
S
SL3
SL2
SL1
SL0
Set the scroll line number. Range : 0~63
Scroll line setting will scroll the displayed image up by SL rows. Icon output CIC ot be affected by Set Scroll Line
command.
Image row 0
row 0
Image row N
row 0
:
:
:
:
:
Image ro
Image row 0
:
:
Image row N-1
Image row N
:
:
Image row 63
row 63
Image row N-1
row 63
SL=0
SL=N
7. Set Page Address
Action
C/D W/R
D7
1
D6
0
D5
1
D4
1
D3
D2
D1
D0
Set Page Address, PA[3:0]
0
0
PA3
PA2
PA1
PA0
Set the SRAM page address before w/read memory from host interface. Each page of SRAM corresponds to 8 COM lines on
LCD panel, except for the last page. The last page corresponds to the icon output CIC.
Possible value = 0~8.
8. Set VLCD Resistor Ratio
Action
C/D W/R
D7
0
D6
0
D5
1
D4
0
D3
0
D2
D1
D0
Set VLCD Resistor Ratio, PC[5:3]
0
0
PC5
PC4
PC3
Configure PC[5:3] to set internal Resistor Ratio, Rb/Ra, for the VLCD Voltage regulator to adjust the contrast of the display panel:
PC[5:3] : 000b~111b – 1+Rb/Ra ratio. Default : 100b. Refer to VLCD Quick Reference for “1+Rb/Ra” ratio.
VLCD=((1+Rb/Ra) x Vev) x (1+(T-25)xCT%)
Vev=(1-(63-PM)/162)xVREF
where Rb and Ra are internal resistors,
VREF is on-chip contrast voltage, and
PM is a value of electronic volume
9. Set Electronic Volume
Action
C/D W/R
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
Set Electronic Volume, PM[5:0]
0
0
0
0
PM5
PM4
PM3
PM2
PM1
PM0
Set PM[5:0] for electronic volume “PM” for VLCD voltage regulator to adjust contrast of LCD panel display
Effective range: 0~63. Default: 32 (20h)
13
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
10. Set All Pixel ON
Action
Set All Pixel ON, DC [1]
C/D W/R
D7
1
D6
0
D5
1
D4
D3
0
D2
1
D1
0
D0
0
0
DC1
Set DC[1] to force all SEG drivers to output ON signals. This function has no effecon the existing data stored in display RAM.
Default : 0
11. Set Inverse Display
Action
C/D W/R
D7
1
D6
D5
1
D4
0
D3
0
D2
1
D1
1
D0
Set Inverse Display, DC [0]
0
0
DC0
Set DC[0] to force all SEG drivers to output the inverse of he data (bit-wise) stored in display RAM. This function has no effect on
the existing data stored in display RAM.
12. Set Display Enable
Action
C/D W/R
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
Set Display Enable, DC[2]
0
0
DC2
This command is for programming register DC[2]. When DC[2] is set to 1, UC1701c will first exit from sleep mode, restore the
power and then turn on COM drivers and SEG drivers.
13. Set SEG Direction
Action
C/D W/R
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
LC0 /
MX
Set Segment Direction, LC[0]
0
0
Set LC[0] for SEG (column) mirror (MX). Default : 0
MX is implemented by reversing the mapping order between RAM and SEG (column) electrodes. The data stored in RAM is not
affected by MX command. Yet, MX has immediate effect on the display image.
14. Set COM Direction
Action
C/D W/R
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
LC1 /
MY
Set Common Direction, LC[1]
0
0
-
-
-
Set LC[1] for COM (row) mirror (MY). Default : 0b
MY is implemented by reversing the mapping between RAM and COM (row) electrodes. The data stored in RAM is not affected
by MY command. Yet, MY has immediate effect on the display image.
15. System Reset (Software Reset)
Action
C/D W/R
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
Software Reset
0
0
This command will activate the system reset.
Some control register values will be reset to their default values. Yet, data stored in RAM will not be affected. See the “Reset and
Power Management” section for more details.
16. NOP
Action
C/D W/R
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
1
No Operation
0
0
This command is used for “no operation”.
14
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
17. Set LCD Bias Ratio
Action
C/D W/R
D7
1
D6
0
D5
1
D4
D3
0
D2
0
D1
1
D0
Set Bias Ratio, BR
0
0
BR
Select voltage bias ratio required for LCD. Default : 0
The setting of Bias ratio varies according to Duty:
DUTY
1/65
1/49
1/33
1/55
BR = 0
BR = 1
1/9
1/8
1/6
1/8
1/7
1/6
1/5
1/6
18. Set Cursor Update Mode
Action
C/D W/R
7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Set Cursor Update Mode
0
0
This command is used for set cursor update mode function. When cursor update mode sets, UC1701c will update register CR
with the value of register CA. The column address CA will increment with write RAM data operation but the address wraps
around will be suspended no matter what WA setting is. However, the column address will not increment in read RAM data
operation. The set cursor update modan be used to implement “write after read RAM” function. The column address (CA) will
be restored to the value, which is before the set cursor update mode command, when reset cursor update mode.
The purpose of this pair commands and their feature is to support “write after read” function for cursor implementation.
19. Reset Cursor Update Mode
Action
C/D W/R
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Reset Cursor Update Mode
0
0
Set AC3=0 and CA=CR.
20. Set Static Indicator OFF
Action
C/D W/R
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
0
D0
0
Turn OFF Static Indicator
0
0
No Operation.
21. Set Static Indicator ON
Action
C/D W/R
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
0
D0
1
0
0
0
0
Turn ON Static Indicator
No Operation.
-
-
-
-
-
-
-
-
15
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
22. Set Booster Ratio
Action
C/D W/R
D7
1
D6
1
D5
1
D4
D3
1
D2
0
D1
0
D0
0
Set Booster Ratio
0
1
(Double-byte command)
0
0
0
0
0
-
0
0
This command is used for “No Operation”.
23. Set Power Save
Action
C/D W/R
D7
#
D6
#
D5
#
D4
#
D3
#
D2
#
D1
#
D0
#
Power Save
(Compound Command)
0
0
24. Set Test Control
Action
C/D W/R
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
#
D0
#
Set TT
TT
0
1
(Double-byte command)
-
#
#
#
#
#
This command is for UltraChip’s Test only. Do NOT use.
25. Set Advanced Program Contro
Action
C/D W/R
D7
1
D6
1
D5
1
D4
1
D3
1
D2
0
D1
1
D0
0
Set Adv. Program Control, APC0 [7:0]
(Double-byte command)
0
0
WA1,
WA0,
TC,
APC0 [7]
FR1,
APC0 [5] APC0 [4]
FR0,
0
0
0
APC0 [1] APC0 [0]
TC : APC0 [7], VBIAS temperature compensation coefficient (%-per-degree-C)
Temperature compensation curve definition:
TC : 0b = -0.05%/oC,
1b = -0.11%/oC
APC0 [6] is fixed.
APC0 [5:4] : FR, Frame Rate: (Unit: Hz)
FR[1:0] : Duty:1/65
FR[1:0] : Duty:1/55
FR[1:0] : Duty:1/49
FR[1:0] : Duty:1/33
APC0 [3:2] are fixed.
00b: 58
00b: 102
00b: 115
00b: 57
01b: 77
01b: 136
01b: 153
01b: 76
10b: 96
11b: 115
11b: 203
11b: 229
11b: 113
10b: 170
10b: 191
10b: 94
WA : APC0 [1:0], Automatic column/row wrap around.
WA[0] : 0: PA WA disable
1: PA WA enable.
WA[1] : 0: CA WA disable
1: CA WA enable.
26. Set Advanced Program Control 1
Action
C/D W/R
D7
1
D6
1
D5
1
D4
1
D3
1
D2
0
D1
1
D0
1
Set Adv. Program Control, APC1 [7:0]
(Double-byte command)
0
0
APC1 register parameter
For UltraChip only. Please Do NOT use.
16
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
LCD VOLTAGE
SETTING
M
ULTIPLEX
R
ATES
VLCD GENERATION
VLCD is supplied bnternal charge pump. The source of VLCD
is controlled bPC[2:0]. For good product reliability, it is
recommendeeep VLCD under 10.0V for all temperature
conditions.
Multiplex Rate is set by DT[2:1] :
DT2
0
DT1
0
Duty
1/65
1/49
1/33
1/55
When VLCD is generated internally, the voltage level of VLCD is
determined by three control registers: BR (Bias Ratio), PM
otentiometer), and PC[5:3] (VLCD Resistor Ratio) with the
wing relationship:
0
1
1
0
1
1
VLCD=((1+Rb/Ra) x Vev) x (1+(T-25)xCT%)
Vev=(1-(63-PM)/162)xVREF
where
B
IAS RATIO SELECTION
Bias Ratio (BR) is defined as the ratio between VLCD VBIAS
i.e.
,
Raand Rbare two design constants, whose value
depends on the setting of BR register, as illustrated in the
table on the next page,
BR = VLCD /VBIAS
,
where VBIAS = VG – VMO– = VMO
PMis value of electronic volume,
The theoretical optimum Bias Ratio can be estimated by
. BR of value 15~20% lower/her than the
Mux +1
V
REG is on-chip contrast voltage,
optimum value calculated above will not cause significant
visible change in image quality.
Tis the ambient temperature in OC, and
CT is temperature compensation coefficient.
UC1701c supports four BR as listed below. BR can be
selected by software program.
VLCD FINE TUNING
Bias Ratio
Black-and-white STN LCD is sensitive to even a 1%
mismatch between IC driving voltage and the VOP of LCD.
However, it is difficult for LCD makers to guarantee such high
precision matching of parts from different venders. It is
therefore necessary to adjust VLCD to match the actual VOP of
the LCD.
Duty
BR=0
1/9
BR=1
1/7
1/65
1/49
1/33
1/55
1/8
1/6
1/6
1/5
1/8
1/6
For the best result, software based approach for VLCD
adjustment is the recommended method for VLCD fine-tuning.
System designers should always consider the contrast fine
tuning requirement before finalizing on the LEM design
Table 1: Bias Ratios
T
EMPERATURE COMPENSATION
The temperature compensation coefficient is –0.11% / oC
(default) or –0.05% / oC.
L
OAD DRIVING STRENGTH
The power supply circuit of UC1701c is designed to handle
LCD panels with loading up to ~24nF using 20-Ω/Sq ITO
glass with VDD2/3 ꢀ 2.6V. For larger LCD panels, use lower
resistance ITO glass packaging.
17
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
VLCD
Q
UICK
REFERENCE
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60
PM
VLCD Programming Curve.
PC[5:3]
1+Rb/Ra
V
REF
PM
0
63
0
63
0
63
0
63
0
56
0
42
0
30
0
V
LCD Range (V)
3.85
000b
3.0
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
6.30
4.49
7.35
5.13
8.40
5.78
9.45
6.42
10.05
7.06
10.05
7.70
10.03
8.34
10.03
001b
010b
011b
100b
101b
110b
111b
3.5
4.0
4.5
5.0
5.5
6.0
6.5
20
Note: For good product reliability, keep VLCD under 10.0V over all temperature.
18
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
H
I
-
V
G
ENERATOR AND BIAS REFERENCE CIRCUIT
VDD
V
VDD
Cv0
XV0
VDD2/VDD3
VDD2
VDD3
VSS
VSS2
F
IGURE 1: Reference circuit using internal Hi-V generator circuit
Note
Sample component values: (The illustrated circuit and component values are for reference only. Please optimize for specific
requirements of each application.)
CV0 : Optional. 0.1 µF/16V Connect the capacitor of CV0 value between XV0 and V0.
19
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
LCD DISPLAY
CONTROLS
CLOCK & TIMING
GENERATOR
DRIVER ENABLE (DE)
UC1701c contains a built-in system clock. All required
components for the clock oscillator are built-in. No external
parts are required.
Driver Enable is controlled by the value of DC[2] via Set
Display Enable comand. When DC[2] is set to OFF (logic
“0”), both COM and SEG drivers will become idle and
UC1701c witself into Sleep Mode to conserve power.
4 different frame rates are provided based on different Mux-
Rate for system design flexibility.
When DC[2] is set to ON, the DE flag will become “1”, and
UC1701c will first exit from Sleep Mode, restore the power
(VLD, VD etc.) and then turn ON COM and SEG drivers.
DRIVER MODES
COM and SEG drivers can be in either Idle mode or Active
mode, controlled by Display Enable flag (DC[2]). When SEG
and COM drivers are in idle mode, they will be connected
together to ensure zero DC condition on the LCD.
t is the display is turned ON after setting PC[2:0]=111b
DC[2]=1.
ALL PIXELS ON (APO)
When set, this flag will force all SEG drivers to output ON
signals, disregarding the data stored in the display buffer.
D
RIVER ARRANGEMENTS
The naming conventions are: COMx, where x = 0~63, fers
to the row driver for the x-th row of pixels on the LCD panel.
This flag has no effect when Display Enable is OFF and it has
no effect on data stored in RAM.
The mapping of COM(x) to LCD pixel rows is fixed and it is
not affected by SL, MX or MY settings.
I
NVERSE (PXV)
When this flag set to ON, SEG drivers will output the inverse
of the value it received from the display buffer RAM (bit-wise
inversion). This flag has no impact on data stored in RAM.
D
ISPLAY CONTROLS
There are three groups of display control flags in the control
register DC: Driver Enable (DE), All-Pixel-ON (APO) and
Inverse (PXV). DE has the overriding effect over PXV and
APO.
20
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
ITO LAYOUT AND LC SELECTION
Since COM scanning pulses of UC1701c can be as short as
153µS, it is critical to control the RC delay of COM and SEG
signal to minimize crosstalk and maintain good mass
production consistency.
For good image quality, please minimize SEG ITO trace
resistance and limit the worst case of SEG signal RC delay as
calculated below.
(RCOL / 27 + SEG) x CCOL < 6.30µS
COM TRACES
where
Excessive COM scanning pulse RC decay can cause
fluctuation of contrast and increase COM direction crosstalk.
CCOL: LCD loading capacitance of one pixel column. It
can be calculated by CLCD / (# of column), where
CLCD is the LCD panel capacitance.
Please limit the worst case of COM signals RC delay (RCMAX
as calculated below
)
RCOL: ITO resistance over one column of pixels within the
active area
(RROW / 2.7 + RCOM) x CROW < 9.23µS
where
RSEG: SEG routing resistance from IC to the active area +
SEG driver output impedance.
CROW: LCD loading capacitance of one row of pix. It
(Use worst case values for all calculations)
can be calculated by CLCD/Mux-Rate, wheCD is
the LCD panel capacitance.
S
ELECTING LIQUID CRYSTAL
RROW: ITO resistance over one row of pixels within the
active area
The selection of LC material is crucial to achieve the optimum
image quality of finished LCM.
RCOM: COM routing resistance from IC to the active area
+ COM driver output impede.
When (V90-V10)/V10 is too large, image contrast will deteriorate,
and images will look murky and dull.
In addition, please limit the min-max spread of RC decay to
be:
When (V90-V10)/V10 is too small, image contrast will become
too strong, and crosstalk will increase.
| RCMAX – RCMIN | < 2.76µS
For the best result, it is recommended the LC material has the
following characteristics:
so that the COM distortions on the top of the screen to the
bottom of the screen are uniform.
(V90-V10)/V10 = (VON-VOFF)/VOFF x 0.72~0.80
(Use worst case values for all calculations)
where V90 and V10 are the LC characteristics, and VON and
VOFF are the ON and OFF VRMS voltage produced by LCD
driver IC at the specific Mux-rate.
SEG TRACES
Excessive SEG signal RC decay can cause image dependent
changes of medium gray shades and sharply increase the
crosstalk of SEG direction.
Example:
Duty
Bias
VON/VOFF -1 x0.80
10.6% 9.6%
x0.72
1/65
1/9
7.5%
21
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
RAM
W/R
POL
COM1
COM2
COM3
SEG1
SEG2
F
IGURE 2: COM and SEG Electrode Driving Waveform
22
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
T
HE COMMON OUTPUT STATUS SELECT CIRCUIT
In the UC1701c chips, the COM output scan direction can be selected by the common output status select command. (See the table
below for details.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized.
Duty
1/65
Direction COM[0:15] COM [16:23] COM [24:26] COM [27:36] C37:39] COM [40:47] COM[48:63]
CIC
CIC
0
1
0
1
0
1
0
1
COM [0:63]
COM 63:0]
COM[0:23]
C
NC
NC
NC
NC
NC
COM [24:47]
COM [23:0]
1/49
1/33
1/55
CIC
CIC
CIC
COM[47:24]
COM[0:15]
COM[31:16]
COM[16:31]
COM[15:0]
COM [0:26]
COM [27:53]
COM [26:0]
COM [53:27]
Table 2: Duty Layout
23
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
HOST INTERFACE
As summarized in the table below, UC1701c supports 2 8-bit parallel bus protocols and 2 erial bus protocols. Designers can
choose either the 8-bit parallel bus to achieve high data transfer rate, or use serial bus o create compact LCD modules and
minimize connector pins.
Bus T
8080
6800
S8 (4-wire)
I2C (2-wire)
Width
8-bit
8-bit
Serial
Write only
0x
Access
Read / Write
BM[1:0]
TST5
CS0
10
Op
1
Chip select
0
--
CD
Control/Data
–
Control &
___
__
_
_
WR0
WR1
–
–
A3
A2
Data Pins
WR
R/W
___ __
EN
RD
DB[5:0]
DB[7:6]
Data
Data
–
DB[6]=SCK, DB[7]=SDA
* Connect unused control pins and data bus pins to VDD or VSS
CS
CS
RESET
Disable Bus Interface
Init. Bus State
Init. Bus State
8-bit
S8
I2C
–
V
–
V
V
–
V
V
V
•
•
CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.
RESET can be pin reset / soft reset.
Table 3: Host interfaces Summary
24
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
P
ARALLEL INTERFACE
The timing relationship between UC1701c internal control
signal RD, WR and their associated bus actions are shown in
the figure below.
cycle needs to be performed before the actual data can
propagate through the pipeline and be read from data port
D[7:0].
The Display RAM read interface is implemented as a two-
stage pipeline. This architecture requires that every time
memory address is modified, either in parallel mode or serial
mode, by either Set CAor Set PAcommand, a dummy read
There is no pielinin write interface of Display RAM. Data is
transferred dy from bus buffer to internal RAM on the
rising dges oite pulses.
External
CD
___
WR
__
RD
D[7:0]
LLSB
DL
DL+
CMSB
CLSB
Dummy
DC
DC+1
MMSB
MLSB
Internal
Write
Read
Data
Latch
DL
L+K
DL+K
Dummy
DC
C+1
DC+1
C+2
DC+2
C+3
Column
Address
L
L+K+1
C
M
Figure 3: Parallel Interface & Related Internal Signals
25
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
S
ERIAL INTERFACE
UC1701c supports 2 serial modes: 4-wire SPI mode (S8). Bus interface mode is determined by the wiring of the BM[1:0] and
TST5. See table in last page for more detail.
S8 (4-WIRE) INTERFACE
Only write operations are supported in 4-wire serial mode.
Pins WR[1:0] are used for chip select and bus cycle reset. Pin
CD is used to determine the content of the data been
transferred. During each write cycle, 8 bits of data, MSB first,
are latched on eight rising SCK edges into an 8-bit data
holder.
If CD=0, the byte will be decoded as command. If CD=1,
this 8-bit will eated as data and transferred to proper
address in the Display Data RAM on the rising edge of the
last SCK pulse.
Pin CD is examined when SCK is pulled low for the LSB (D0)
ach token.
CS0
D7
D6
D4
D3
D2
D1
D0
D7
D6
D5
SDI
SCK
CD
Figure 4: 4-wire Serial Interface (S8)
26
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
I2C (2-WIRE) INTERFACE
Write Mode
MPU
⇓
MPU
⇑
MPU
⇓ ⇑ ⇓
MP
⇓ ⇑
MPU
⇑ ⇓
⇓
A A C
3 2 D
D
7
D
0
D
7
0
S 0 1 1 1
0 A
A
… ...
A P
Read Mode
MPU
MPU
MPU
MPU
MPU
⇓
⇑
⇑
⇑ ⇓
⇑
⇓
⇓
⇓
A A C
3 2 D
D
7
D
A
0
D
7
D
0
S 0 1 1 1
1 A
… ...
A
N P
When BM[1:0] is set to “LH” and TST5 is set to “H”, UC1701c
is configured as an I2C bus signaling protocol compliant slave
device. Please refer to I2C standard for details of the bus
signaling protocol, and AC Charactertic section for timing
parameters of UltraChip implementati
START
Header
In this mode, pins WR0~WR1 (WR[0] becomes A[3], WR[1]
becomes A[2]) are used to configure UC1701c’ device
address. Proper wiring to VDD or VSS is required for the IC to
operate properly for I2C mode.
Command =
System Reset
Each UC1701c I2C interface sequence starts with a “S” (Start)
from the bus master, followed by a sequence header,
containing a device address, the mode of transfer (CD,
0:Control, 1:Data), and the direction of the transfer (RW,
0:Write, 1:Read).
STOP
Since both WR and CD are expressed explicitly in the header
byte, the control pins WR[1:0] and CD are not used in I2C
mode and should be connected to VSS
.
START
The direction (read or write) and content type (command or
data) of the data bytes following each header byte are fixed
for the sequence. To change the direction (R˜W) or the
content type (C˜D), start a new sequence with a START (S)
flag, followed by a new header.
Header
After receiving the header, the UC1701c will send out an “A”
(Acknowledge signal, pull to “L”). Then, depends on the
setting of the header, the transmitting device (either the bus
master or UC1701c) will start placing data bits on SDA, MSB
to LSB, and the sequence will repeat until a STOP signal (P,
in WRITE mode), or an N (Not Acknowledged, in READ mode)
is sent by the bus master.
When using I2C serial mode, if command System Reset is
to be written, the writing sequence must be finished (STOP)
before succeeding data or commands start. The flow chart on
the right shows a writing sequence with a “System Reset”
command.
Command / Data
Command / Data
Command / Data
STOP
Note that, for data read (CD=1), the first byte of data
transmitted will be dummy.
27
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
H
OST INTERFACE REFERENCE CIRCUIT
VDD
VDD
VCC
D7~D0
D7D0
CD
WR
RD
CD
WR0(WR)
WR1(RD)
ADDRESS
IORQ
CS0
RST
MPU
UC1701c
DECODER
RST
VDD
BM1
BM0
GND
VSS
F
IGURE 5: 8080/8bit parallel mode reference circuit
VDD
VDD
VCC
D7~D0
D7~D0
CD
R/W
E
CD
WR0(R/W)
WR1(E)
ADDRESS
IORQ
CS0
RST
MPU
UC1701c
DECODER
RST
VDD
BM1
BM0
GND
VSS
F
IGURE 6: 6800/8bit parallel mode reference circuit
28
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
VDD
VDD
VCC
0
SCK
SDA
CD
SCK)
SDA(D7)
CD
WR0
WR1
ADDRESS
IORQ
CS0
RST
MPU
UC1701c
DECODER
RST
BM1
BM0
GND
VSS
F
IGURE 7: Serial-8 serial mode reference circuit
VDD
VDD
VCC
R1
R2
D5~D0
SCK
SDA
SCK(D6)
SDA(D7)
CD
WR0(A3)
WR1(A2)
CS0
MPU
UC1701c
RST
RST
VDD
TST5
BM1
BM0
GND
VSS
F
IGURE 8: I2C serial mode reference circuit
29
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
Note
•
The ID pins are for production control. The connection will affect the content of D[7] of the 1-st byte of the Get Status
command. Connect to VDD for “H” or VSS for “L”.
•
•
•
•
RST pin is optional. When the RST pin is not used, connect it to VDD.
When using I2C serial mode, WR1/0 are user configurable and affect A[3:2] vice address.
R1, R2: 2k ~ 10k Ω, use lower resistor for bus speed up to 3.6MHz, use higher resistor for lower power.
When using Read function:
(8080) Set WR1=0
(8080) Set WR1=1
(6800) Set WR1=1 ‰ data output will be enabled.
(Serial) Set SCK=0
(6800) Set WR1=0 ‰ data output will be disabled.
(Serial) Set SCK=1
•
It is REQUIRED to set MPU’s data port to 1 befoData Read or Status Read actions.
30
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
DISPLAY DATA RAM (DDRAM)
non-zero value is equialent to scrolling the LCD display up or
down (depends on MY) by SL rows.
DATA ORGANIZATION
The input display data is stored to a dual port static DDRAM
(DDRAM, for Display Data RAM) organized as 65x132.
RAM ADDRES
ENERATION
After setting CA and PA, the subsequent data write cycle will
store the data for the specified pixel to the proper memory
location.
The mapping he data stored in the display SRAM and the
scanning electrodes can be obtained by combining the fixed
Rm scanning sequence and the following RAM address
generation formula.
Please refer to the map in the following page between the
relation of COM, SEG, SRAM, and various memory control
registers.
ng the display operation, the RAM line address
neration can be mathematically represented as following:
For the 1st line period of each field
Line = SL
DISPLAY DATA RAM ACCESS
The Display RAM is a special purpose dual port RAM which
allows asynchronous access to both its column and ata.
Thus, RAM can be independently accessed both for Hst
Interface and for display operations.
Otherwise
Line = Mod (Line+1, 64)
Where Mod is the modular operator, and Line is the bit slice
line address of RAM to be outputted to column drivers. Line 0
corresponds to the first bit-slice of data in RAM.
DISPLAY DATA RAM ADDRESSING
The above Line generation formula produce the “loop around”
effect as it effectively resets Line to 0 when Line+1 reaches
64.
A Host Interface (HI) memory access oeration starts with
specifying Page Address (PA) and Con Address (CA) by
issuing Set Row Address and Set Column Address
commands.
MY IMPLEMENTATION
Row Mirroring (MY) is implemented by reversing the mapping
order between row electrodes and RAM, i.e. the mathematical
address generation formula becomes:
MX IMPLEMENTATION
Column Mirroring (MX) is implemented by selecting either (CA)
or (131–CA) as the RAM column address. Changing MX
affects the data written to the RAM.
For the 1st line period of each field
Line = Mod (SL + MR -1, 64)
Otherwise
Since MX has no effect of the data already stored in RAM,
changing MX does not have immediate effect on the
displayed pattern. To refresh the display, refresh the data
stored in RAM after setting MX.
Line = Mod (Line-1, 64)
Visually, the effect of MY is equivalent to flipping the display
upside down. The data stored in display RAM is not affected
by MY.
ROW MAPPING
COM electrode scanning orders are not affected by Start Line
(SL), or Mirror Y (MY, LC[1]). Visually, register SL having a
31
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
Line
Panel
MY=
MY=1
PA[3:0]
0000
0
AddeCss
RAM
Location SL=0 S16 SL=0 SL=0 SL=25 SL=25
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
COM1
COM2
COM3
C1
C2
C3
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
CIC
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C48
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C9
C8
C7
OM4
COM5
COM6
COM7
COM8
COM9
C4
C5
C6
C7
C8
C9
C6
C5
C4
C3
C2
C1
---
---
---
---
---
---
Page 0
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
CIC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
CIC
Page 1
P
Page 3
Page 4
Page 5
Page 6
0001
0010
0011
0100
0101
0110
---
---
---
---
---
---
---
---
---
---
C48*
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
CIC
C8
C7
C6
C5
C4
C3
C2
C1
---
---
---
---
---
---
---
---
C8
C7
C6
C5
C4
C3
C2
C1
---
---
---
---
---
---
---
---
CIC
49
C33
C32
C31
C30
C29
C28
C27
C26
CIC
65
0111
1000
Page 7
Page 8
CIC
65
49
MUX
Example for memory mapping: let MX = 0, MY = 0, SL = 0, according to the data shown in the above table:
• Page 0 SEG 1 (D7-D0) : 11100000b
• Page 0 SEG 2 (D7-D0) : 00110011b
32
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
RESET & POWER MANAGEMENT
T
YPES OF RESET
UC1701c has 2 different types of reset: Pin Reset (hardware
reset) and System Reset (Software reset). Pin Reset is
activated by connecting the RST pin to ground; while System
Reset is performed by software commands. After each power-
up, a Pin Reset, wch is in 3mS, is required. In the following
discussions, ret means Pin Reset.
The differences between pin reset (hardware reset) and system reset (softare reset) :
Pin Reset
(hardware reset)
System Reset
(software reset)
Procedure
Display OFF: DC[2]=0, all SEGs/COMs output at VSS
Normal Display: DC[0]=0, DC[1]=0
SEG Normal Direction: MX=0
Clear Serial Counter and Shift Register (if using Serial Interface)
Bias Selection: BR=0
Booster Level BL[1:0]=0
Exit Power Saving Mode
Power Control OFF: PC[2:0]=000b
Exit Cursor Update mode
Scroll Line SL[5:0]=0
Column Address CA[7:0]=0
Page Address PA[3:0]=0
COM Normal Direction: MY=0
VLCD Regulation Ratio C[5:3]=100b
PM[5:0]=10 0000b
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
Exit Test Mode
For each mode, the related statuses are as below:
RESET STATUS
Mode
OM
Reset
00
Sleep
10
Normal
11
When UC1701c enters RESET sequence:
•
•
Operation mode will be “Reset”
Host Interface
Clock
Active
OFF
OFF
OFF
ON
Active
OFF
OFF
OFF
ON
Active
ON
All control registers are reset to default values. Refer to
Control Registers for details of their default values.
LCD Drivers
Charge Pump
Draining Circuit
ON
ON
OPERATION MODES
OFF
UC1701c has three operating modes (OM):
Reset, Sleep, and Normal.
Table 4: Operating Modes
33
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
CHANGING OPERATION MODE
When entering Reset mode or Sleep mode, the display
drivers will be disabled
There are 2 commands that will initiate OM transitions:
Set Display Enable, and System Reset.
The difference beten Sleep mode and Reset mode is that,
Reset mode clearall control registers and restores them to
default valueshile Sleep mode retains all the control
registers valet by the user.
When DC[2] is modified by Set Display Enable, OM will be
updated automatically. There is no other action required to
enter sleep mode.
OM changes are synchronized with the edges of UC1701c
internal clock. To ensure consistent system states, wait at
least 10µS after Set Display Enableor System Reset
command.
It is recommended to use Sleep Mode for Display OFF
operations as UC1701c consumes very little energy in Sleep
mode (typically under 5µA).
TING SLEEP MODE
UC1701c contains internal logic to check whether VLCD and
VBIAS are ready before releasing COM and SEG drivers from
their idle states. When exiting Sleep or Reset mode, COM
and SEG drivers will not be activated until UC1701c internal
voltage sources are restored to their proper values.
Action
Mode
Reset
Sleep
OM
00
RST_ pin pulled “L”
Set Driver Enable to “0”
Set Driver Enable to “1”
10
Normal
11
Table 5: OM changes
34
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
P
OWER-UP SEQUENCE
Turn ON the Power
Wait ꢁ 3 mS er each power-up, a Pin Reset, which is set
in 3mS, is reqd.
Wait ꢁ 3 mS
Wait ꢀ1 uS :
Set RST Low
Wait ꢀ1 uS
Set RST High
Wait ꢀ5 mS
Note: If VDD and VDD2/3 are turned ON separately, each one
needs to be followed by a RST in 3mS.
Set SEG Direction (MX)
Set COM Direction (MY)
Set VLCD Resistor Ratio
Set LCD Bias Ratio (BR)
Set Electronic Volume (PM)
Wait ꢀ5 mS : System program is required to wait for only
5 mS before starting to issue commands to UC1701c. No
additional waits are required thereafter.
Set Display Enable (AFH)
Figure 9: REFERENCE
POWER-UP SEQUENCE
There’s no delay needed while turning ON VDD and VDD2/3, and either one can be turned on first:
Either VDD or VDD2/3
may be turned ON first.
VDD2/3 ≥ 2.6V
VDD ≥ 2.6V
VDD2/3 ≥ VDD
TWait > 10mS
VDD < 0.1V
Tf < 10 mS
10µS < T1< 10 mS
Figure 10: Power Off-On Sequence
35
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
E
NTER/EXIT
S
LEEP
M
ODE
S
EQUENCE
Power-Down Sequence
UC1701c enters Sleep mode from Display mode by issuing
Set Display Disable command and setting all-pixel-ON.
To prevent the charge stored in capacitor Cv0 causing
abnormal residue horizontal line on display when VDD is
switched off, use Ret mode to enable the built-in charge
draining circuit to scharge these external capacitors.
To exit Sleep mode, set All-pixel-OFF.
Display Mode
Set RST Low
Set Display OFF (AEH)
Set All-pixel-ON (A5H)
Wait ꢀ1 uS
Set RST High
Sleep Mode
Wait ꢀ5 mS
Set All-pixel-OFF (A4H)
Turn OFF the power
Set Display EnablAFH)
Display Mode
F
IGURE 12: Reference Power-Down Sequence
F
IGURE 11: Reference Enter/Exit Sleep Mode Sequence
36
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
S
AMPLE COMMAND SEQUENCES FOR POWER MANAGEMENT
The following tables are examples of command sequence for power-up, power-down and display ON/OFF operations. These are
only to demonstrate some “typical, generic” scenarios. Designers are encouraged to study related sections of the datasheet and
find out what the best parameters and control sequences are for their specific design needs.
C/D
The type of the interface cycle. It can be either Command (0) or Data (1)
The direction of data flow of the cycle. It can be either Write (0) oRead
W/R
Type
Required:
These items are required
Customized: These items are not necessary if customer parameters are the same as default
Advanced:
Optional:
We recommend new users to skip these commands and use default values.
These commands depend on what users wo do.
P
OWER-U
P
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
Turn ON VDD and VDD2/3
Wait ꢁ 3 mS
Comments
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
1
1
1
1
0
1
–
–
–
–
1
0
0
1
0
0
–
–
–
–
1
0
1
0
1
1
–
–
–
–
1
1
0
0
0
0
–
–
–
–
1
0
0
#
0
0
–
–
–
–
0
0
0
–
#
0
–
–
–
–
1
1
0
–
#
1
–
–
–
–
0
1
#
–
#
#
Wait until VDD, VDD2/3 are stable
Set RST pin Low
Set RST pin High
Wait 1 uS after RST is Low
Wait 5 mS after RST is High
O
0
0
Set Adv. Program Control 0
Set Wrap Around Enable
R
R
R
R
0
0
0
0
0
0
0
0
Set SEG Direction
Set COM Direction
Set VLCD Resistor Ratio
Set LCD Bias Ratio
Set up LCD format specific
parameters, MX, MY, etc.
LCD specific operating voltage
setting
0
0
0
0
1
0
0
0
0
#
0
#
0
#
0
#
0
#
1
#
R
Set Electronic Volume
1
.
0
.
#
.
#
.
#
.
#
.
#
.
#
.
#
.
#
.
O
Write display RAM
Set up display image
.
.
.
.
.
.
.
.
.
.
1
0
0
0
0
0
#
0
1
#
0
0
#
1
1
#
0
0
#
1
1
#
1
1
#
1
1
#
1
1
R
R
Set Power Control
Set Display Enable
P
OWER-DOWN
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
System Reset
Comments
R
R
0
–
0
–
1
–
1
–
1
–
0
–
0
–
0
–
1
–
0
–
Draining capacitor
Wait ~5mS before VDD OFF
DISPLAY-OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
Set Display Disable
Write display RAM
Comments
R
C
0
1
.
0
0
.
1
#
.
0
#
.
1
#
.
0
#
.
1
#
.
1
#
.
1
#
.
0
#
.
Set up display image (Image update
is optional. Data in the RAM is
retained through the SLEEP state.)
.
.
.
.
.
.
.
.
.
.
1
0
0
0
#
1
#
0
#
1
#
0
#
1
#
1
#
1
#
1
R
Set Display Enable
37
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
ABSOLUTE MAXIMUM RATINGS
In accordance with IEC134 - notes 1, 2 and 3.
Symbol
Parameter
Logic Supply voltage
in.
-0.3
-0.3
-0.3
--
Max.
+4.0
Unit
V
VDD
VDD2
LCD Generator Supply voltage
Analog Circuit Supply voltage
Voltage difference between VDD and VDD2/3
LCD Generated voltage
+4.0
V
VDD3
+4.0
V
VDD2/3 -VDD
VLCD
1.2
V
-0.3
-0.4
-30
-55
+11.0
VDD + 0.3
+85
V
VIN / VOUT
TOPR
Any input/output
V
Operating temperature range
Storage temperature
oC
oC
TSTR
+125
Note:
1. All voltages are based on VSS = 0V
2. Stress values listed above may cause permanent damages to the device.
38
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
S
PECIFICATIONS
DC CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
2
Typ.
Max.
3.6
Unit
V
VDD
VDD2/3
VLCD
VD
Supply for digital circuit
Supply for bias & pump
Charge pump output
LCD data voltage
2.7~3.3
2.7~3.3
2.6
3.6
V
V
V
DD2/3 ꢀ 2.6V, 25OC
DD2/3 ꢀ 2.6V, 25OC
3.85
10.0
V
0.80
1.32
V
V
VIL
Input logic LOW
0.2VDD
VIH
Input logic HIGH
0.8VDD
V
VOL
VOH
IIL
Output logic LOW
Output logic HIGH
Input leakage current
IOH = -0.5mA
IOL = mA
0.2VDD
V
0.8VDD
-50
V
VI= or VSS
1.5
50
50
uA
VDD = VDD2/3 = 3.3V,
Temp = 85oC
ISB
Standby current
uA
CIN
Input capacitance
5
5
10
10
PF
PF
Ω
COUT
Output capacitance
SEG output impedance
COM output impedance
R0(SEG)
R0(COM)
VLCD = 10V
VLCD = 10V
Duty=1/65
Duty=1/49
Duty=1/33
Duty=1/55
2000
2000
77
3000
3000
Ω
153
76
FFR
Average Frame Rate
-15%
+20%
Hz
136
P
OWER CONSUMPTION
VDD = 2.7 V,
VLCD = 8.49 V
Bias Ratio = 0b,
Frame Rate = 77Hz,
Bus mode = 6800,
PM = 32,
Cv0 = 0.1 uF,
All outputs are open circuit.
Mux Rate = 65,
Temperature = 25oC
Display Pattern
All-OFF
Conditions
Bus = idle
Typical
203
205
218
-
Maximum
Unit
µA
325
328
349
5
µA
2-pixel checker
1-pixel checker
-
Bus = idle
µA
Bus = idle
µA
Bus = idle (standby current)
39
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
AC CHARACTERISTICS
CD
tAS80
t
AH80
CS0
t
CY80
t
PWR80
WR0
WR1
t
HPW80
t
PWW80
t
DS80
t
DH80
D7~D0
(Write)
t
OD80
t
ACC80
D7~D0
(Read)
F
IGU13: Parallel Bus Timing Characteristics (for 8080 MCU)
Symbol
Signal
Description
Condition
Min.
Max.
Unit
(2.6V ꢁ VDD < 3.6V, Ta= –30 to +85oC)
(Read / Write)
tAS80
tAH80
Address setup time
Address hold time
0
10
CD
–
–
nS
nS
tCY80
Cycle time
250 / 250
140 / 140
80 / 80
WR0, WR1
tPWR80, tPWW80
tHPW80
tDS80
tDH80
tACC80
tOD80
Low Pulse width
High pulse width
D7~D0
(Write)
Data setup time
Data hold time
-- / 40
-- / 20
–
nS
nS
D7~D0
(Read)
Read access time
Output disable time
– / --
5 / --
70
50
CL= 16pF
Note: tr (rising time), tf (falling time): ꢁ 15nS
40
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
CD
WR0
t
AH68
t
AS68
CS0
t
CY68
LPW68
t
PWR68
WR1
t
t
PWW68
8
D7~D0
(Write)
t
DS68
t
OD68
t
ACC68
D7~D0
(Read)
F
IGURE 14: Parallel Bus Timing Characteristics (for 6800 MCU)
Symbol
Signal
Description
Condition
Min.
Max.
Unit
(2.6V ꢁ VDD < 3.6V, Ta= –30 to +85oC)
(Read / Write)
tAS68
tAH68
Address setup time
Address hold time
0
10
CD
–
–
nS
nS
tCY68
System cycle time
High Pulse width
Low pulse width
250 / 250
140 / 140
80 / 80
WR1
tPWR68, tPWW68
tLPW68
tDS68
tDH68
D7~D0
(Write)
Data setup time
Data hold time
-- / 40
-- / 10
–
nS
nS
tACC68
tOD68
D7~D0
(Read)
Read access time
Output disable time
– / --
5 / --
70
50
CL= 16pF
Note: tr (rising time), tf (falling time) : ꢁ 15nS
41
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
t
CSSAS
8
t
t
CSHS8
CS0
CD
AHS8
t
CYS8
SCK
t
LPWS8
t
HPWS8
SDA
(Write)
t
DSS
8
tDHS8
F
IGURE 15: Serial Bus Timing Characteristics (for S8)
Symbol
Signal
Description
Condition
Min.
Max.
Unit
(2.6V ꢁ VDD < 3.6V, Ta= –30 to +85oC)
tASS8
Address setup time
Address hold time
20
10
CD
CS0
–
–
nS
nS
tAHS8
tCSSAS8
Chip select setup time
Chip select hold time
20
40
tCSHS8
tCYS8
Cycle time
80
25
25
SCK
–
–
nS
nS
tLPWS8
tHPWS8
tDSS8
Low pulse width
High pulse width
SDA
(Write)
Data setup time
Data hold time
20
10
tDHS8
Note: tr (rising time), tf (falling time) : ꢁ 15nS
42
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
tCYI2C
tHPWI2C
START
tSSTAI2C tHSTAI2C tSDATI2C
tBUF
STOP
tLPWI2C
SCK
tHDATI2C
tSSTOI2C
SDA
F
IGURE 16: Serial bus timing characteristics (for I2C)
Symbol
Signal
Description
Condition
Min.
Max.
Unit
(2.6V ꢁ VDD ꢁ 3.6V, Ta= –30 to +85oC)
tCYI2C
SCK cycle time
305
110
165
28
SCK
–
nS
tHPWI2C
tLPWI2C
tSSTAI2C
tHSTAI2C
tSDAI2C
tHDAI2C
tSSTOI2C
High pulse width
Low pulse width
Setup time – START
Hold time – START
Setup time – Data
Hold time – Data
Setup time – STOP
55
SCK
SDA
–
–
nS
nS
40
11
28
Bus Free time between
STOP and START
tBUF
SDA
165
Note: tr (Rising time), tf (falling time): ꢁ 15nS
43
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
t
RW
RSTB
t
R
Internal
Status
During Reset…
Reset Finished
F
IGURE 17: Reset racteristics
(2.6V ꢁ VDD < 3.6V, Ta= –30 to +85oC)
Symbol
Signal
Description
Condition
Min.
Max.
Unit
tRW
RST
Reset low pulse width
1
–
µS
RST,
Reset to Internal Status
pulse delay
tR
--
1
mS
Internal Status
Note: For each mode, the signal’s rising time (tr) and falling time (tf) are stipulated to be equal to or less than 15nS each.
tr ꢁ15nS
tf ꢁ15nS
80%
20%
44
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
P
HYSICAL DIMENSIONS
Die / Bump Information:
Die Size:
(5040 µM ± 40 µM) x ( 703 µM ± 40 µM)
300 µM ± 20 µM
Die Thickness:
D
MAX - DMIN ꢁ 2 µM
Bump Height:
10 µM ± 3 µM (Part Number: UC1701cGAB)
15 µM ± 3 µM (Part Number: UC1701cGBB)
HMAX – HMIN ꢁ 2 µM
90Hv ± 25Hv
(15µM ± 2 µM) x (100µM ± 2 µM)
27 µM
Hardness:
Bump Size:
Bump Pitch:
Bump Gap:
12 µM ± 3 µM
1500uM2
Bump Area:
Coordinate origin:
Pad reference:
Chip center
Pad center
45
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
ALIGNMENT
M
ARK
I
NFORMATION
(0,0)
D-Left
Mark
D-Right
Mark
S
HAPE OF THE ALIGNMENT MARK:
1
2
NOTE:
Alignment mark is on Metal3 under Passivation.
11
10
4
5
12
3
6
The “+” mark is symmetric both horizontally and
vertically.
9
8
7
10uM 15uM 10uM
COORDINATES:
D-Left Mark
D-Right Mark
Point
X
Y
X
Y
1
2
3
4
5
6
7
8
9
-1984.5
-1969.5
-1969.5
-1959.5
-1959.5
-1969.5
-1969.5
-1984.5
-1984.5
-1994.5
-1994.5
-1984.5
-149.5
-149.5
-159.5
-159.5
-174.5
-174.5
-184.5
-184.5
-174.5
-174.5
-159.5
-159.5
1969.5
1984.5
1984.5
1994.5
1994.5
1984.5
1984.5
1969.5
1969.5
1959.5
1959.5
1969.5
-149.5
-149.5
-159.5
-159.5
-174.5
-174.5
-184.5
-184.5
-174.5
-174.5
-159.5
-159.5
10
11
12
46
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
P
AD
C
OORDINATES
#
1
2
3
4
5
6
7
Pad
COM<53>
COM<54>
COM<55>
COM<56>
COM<57>
COM<58>
COM<59>
COM<60>
COM<61>
COM<62>
COM<63>
CIC
TST4
CS0
RST
CD
WR0
WR1
VDDX
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD
VDD2
VDD2
VDD2
VDD3
VSS
X
Y
-247
-247
-247
-247
-247
-247
-247
-247
-247
-247
-247
W
15
15
15
15
15
15
15
15
15
15
15
15
50
50
5
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
45
45
45
H
100
100
100
100
100
100
100
100
100
100
100
100
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
#
59
60
61
62
63
64
65
66
67
8
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Pad
X
985
Y
W
45
45
45
45
45
45
50
50
50
50
50
50
50
50
50
50
50
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
H
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
-2363
-2336
-2309
-2282
-2255
-2228
-2201
-2174
-2147
-2120
-2093
-2066
-1970
-1905
-1840
-1775
-1710
-1645
-1580
-1515
-1450
-1385
-1320
-1255
-1190
-1125
-1060
-995
-930
-865
-800
-735
-670
-605
-540
-475
-410
-345
-280
-215
-150
-85
DUMMY
DUM
DUMY
MMY
MY
TST5
TST2
VSSX
VDDX
BM0
BM1
DT1
VSSX
DT2
VDD
VDD2
VDD3
COM<31>
COM<30>
COM<29>
COM<28>
COM<27>
COM<26>
COM<25>
COM<24>
COM<23>
COM<22>
COM<21>
COM<20>
COM<19>
COM<18>
COM<17>
COM<16>
COM<15>
COM<14>
COM<13>
COM<12>
COM<11>
COM<10>
COM<9>
COM<8>
COM<7>
COM<6>
COM<5>
COM<4>
COM<3>
COM<2>
COM<1>
COM<0>
CIC
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-247
-247
-247
-247
-247
-247
-247
-247
-247
-247
-247
-247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
1040
1095
1150
1205
1260
1320
1385
1450
1515
1580
1645
1710
1775
1840
1905
1970
2066
2093
2120
2147
2174
2201
2228
2255
2282
2309
2336
2363
2363
2336
2309
2282
2255
2228
2201
2174
2147
2120
2093
2066
2039
2012
1985
1958
1931
1904
1877
1850
1823
1768.5
1741.5
1714.5
1687.5
1660.5
1633.5
1606.5
1579.5
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
-247
-274.5
-274.5
-274.5
-274.5
-2745
-274.5
274.5
-274.5
274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
-274.5
45
45
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
90
91
92
93
94
95
96
97
VSS
VSS2
VSS2
VSS2
VSS2
V0in
98
99
V0in
V0s
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
V0out
V0out
XV0out
XV0out
XV0s
XV0in
XV0in
VMO
VMO
VGin
VGin
VGs
-20
45
110
175
240
305
370
435
500
565
630
695
760
820
875
930
247
247
247
247
247
247
247
247
247
247
247
247
SEG<0>
SEG<1>
SEG<2>
SEG<3>
SEG<4>
SEG<5>
SEG<6>
SEG<7>
45
45
45
45
VGout
DUMMY
DUMMY
DUMMY
45
47
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
#
117
118
Pad
SEG<8>
SEG<9>
X
Y
W
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
1
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
H
#
Pad
X
-67.5
-94.5
Y
W
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
H
1552.5
1525.5
1498.5
1471.5
1444.5
1417.5
1390.5
1363.5
1336.5
1309.5
1282.5
1255.5
1228.5
1201.5
1174.5
1147.5
1120.5
1093.5
1066.5
1039.5
1012.5
985.5
958.5
931.5
904.5
877.5
850.5
823.5
796.5
769.5
742.5
715.5
688.5
661.5
634.5
607.5
580.5
553.5
526.5
499.5
472.5
445.5
418.5
391.5
364.5
337.5
310.5
283.5
256.5
229.5
202.5
175.5
148.5
121.5
94.5
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
00
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
177
178
179
180
181
182
183
184
185
186
87
8
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
SEG<68>
SEG<69>
SEG<70>
SEG<>
SEG<2>
<73>
S<74>
SEG<75>
SEG<76>
SEG<77>
SEG<78>
SEG<79>
SEG<80>
SEG<81>
SEG<82>
SEG<83>
SEG<84>
SEG<85>
SEG<86>
SEG<87>
SEG<88>
SEG<89>
SEG<90>
SEG<91>
SEG<92>
SEG<93>
SEG<94>
SEG<95>
SEG<96>
SEG<97>
SEG<98>
SEG<99>
SEG<100>
SEG<101>
SEG<102>
SEG<103>
SEG<104>
SEG<105>
SEG<106>
SEG<107>
SEG<108>
SEG<109>
SEG<110>
SEG<111>
SEG<112>
SEG<113>
SEG<114>
SEG<115>
SEG<116>
SEG<117>
SEG<118>
SEG<119>
SEG<120>
SEG<121>
SEG<122>
SEG<123>
SEG<124>
SEG<125>
SEG<126>
SEG<127>
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
247
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
SEG<10>
SEG<11>
SEG<12>
SEG<13>
SEG<14>
SEG<15>
SEG<16>
SEG<17>
SEG<18>
SEG<19>
SEG<20>
SEG<21>
SEG<22>
SEG<23>
SEG<24>
SEG<25>
SEG<26>
SEG<27>
SEG<28>
SEG<29>
SEG<30>
SEG<31>
SEG<32>
SEG<33>
SEG<34>
SEG<35>
SEG<36>
SEG<37>
SEG<38>
SEG<39>
SEG<40>
SEG<41>
SEG<42>
SEG<43>
SEG<44>
SEG<45>
SEG<46>
SEG<47>
SEG<48>
SEG<49>
SEG<50>
SEG<51>
SEG<52>
SEG<53>
SEG<54>
SEG<55>
SEG<56>
SEG<57>
SEG<58>
SEG<59>
SEG<60>
SEG<61>
SEG<62>
SEG<63>
SEG<64>
SEG<65>
SEG<66>
SEG<67>
-121.5
-148.5
-175.5
-202.5
-229.5
-256.5
-283.5
-310.5
-337.5
-364.5
-391.5
-418.5
-445.5
-472.5
-499.5
-526.5
-553.5
-580.5
-607.5
-634.5
-661.5
-688.5
-715.5
-742.5
-769.5
-796.5
-823.5
-850.5
-877.5
-904.5
-931.5
-958.5
-985.5
-1012.5
-1039.5
-1066.5
-1093.5
-1120.5
-1147.5
-1174.5
-1201.5
-1228.5
-1255.5
-1282.5
-1309.5
-1336.5
-1363.5
-1390.5
-1417.5
-1444.5
-1471.5
-1498.5
-1525.5
-1552.5
-1579.5
-1606.5
-1633.5
-1660.5
67.5
40.5
13.5
-13.5
-40.5
48
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
#
Pad
X
Y
W
15
15
15
15
15
15
15
15
15
15
15
15
15
H
#
Pad
X
Y
W
15
15
15
15
15
15
15
15
15
15
15
15
H
237
238
239
240
241
242
243
244
245
246
247
248
249
SEG<128>
SEG<129>
SEG<130>
SEG<131>
COM<32>
COM<33>
COM<34>
COM<35>
COM<36>
COM<37>
COM<38>
COM<39>
COM<40>
-1687.5
-1714.5
-1741.5
-1768.5
-1823
-1850
-1877
-1904
-1931
-1958
-1985
-2012
-2039
247
247
247
247
247
247
247
247
247
247
247
247
247
100
100
100
100
100
100
100
100
100
100
100
100
100
250
251
252
253
254
255
256
257
258
259
60
1
COM<41>
COM<42>
COM<43>
COM<>
COM5>
<46>
C<47>
COM<48>
COM<49>
COM<50>
COM<51>
COM<52>
-2066
-2093
-2120
-2147
-2174
-2201
-2228
-2255
-2282
-2309
-2336
-2363
247
247
247
247
247
247
247
247
247
247
247
247
100
100
100
100
100
100
100
100
100
100
100
100
261 260 259
241 240
109 108
90 89 88
Y
U
C
1
7
0
1
c
X
(0, 0)
1
2
3
11 12
76
85 86 87
49
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
T
RAY INFORMATION
TPx
Dx
Px
Ω
W1
W2
X
W3
50
U
LTRA
©1999~2014
C
HIP
UC1701C_B1.0
65x132 STN Controller-Driver
REVISION HISTORY
Revision
Contents
Date
0.6
First Release
Jun. 17, 2014
Average Frame Rate (Min.): –10% ‰ –15%
1.0
Average Frame Rate (Max.): +10% ‰ +20%
Sep. 29, 2014
Power Consumption data are provided.
51
相关型号：
UC1701X
UC1701x is an advanced high-voltage mixed-signal CMOS IC,especially designed for the display needs of ultra-low power hand-held devices.
UTC
©2020 ICPDF网 联系我们和版权申明