UC1825BDWTR [ETC]

Current/Voltage-Mode SMPS Controller ; 电流/电压模式开关电源控制器\n


型号：	UC1825BDWTR
厂家：	ETC
描述：	Current/Voltage-Mode SMPS Controller 电流/电压模式开关电源控制器\n 开关控制器
文件：	总9页 (文件大小：488K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

High Speed PWM Controller

FEATURES

DESCRIPTION

The UC3823A & B and the UC3825A & B family of PWM control ICs are im-

proved versions of the standard UC3823 & UC3825 family. Performance en-

hancements have been made to several of the circuit blocks. Error amplifier gain

bandwidth product is 12MHz while input offset voltage is 2mV. Current limit

threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is spec-

ified at 10mA for accurate dead time control. Frequency accuracy is improved

to 6%. Startup supply current, typically 100µA, is ideal for off-line applications.

The output drivers are redesigned to actively sink current during UVLO at no

expense to the startup current specification. In addition each output is capable

of 2A peak currents during transitions.

•

Improved versions of the

UC3823/UC3825 PWMs

Compatible with Voltage or

Current-Mode Topologies

Practical Operation at Switching

Frequencies to 1MHz

•

50ns Propagation Delay to Output

High Current Dual Totem Pole

Outputs (2A Peak)

Functional improvements have also been implemented in this family. The

UC3825 shutdown comparator is now a high-speed overcurrent comparator with

a threshold of 1.2V. The overcurrent comparator sets a latch that ensures full

discharge of the soft start capacitor before allowing a restart. While the fault latch

is set, the outputs are in the low state. In the event of continuous faults, the soft

start capacitor is fully charged before discharge to insure that the fault frequency

does not exceed the designed soft start period. The UC3825 Clock pin has be-

come CLK/LEB. This pin combines the functions of clock output and leading

edge blanking adjustment and has been buffered for easier interfacing.

continued

•

Trimmed Oscillator Discharge

Current

•

Low 100µA Startup Current

Pulse-by-Pulse Current Limiting

Comparator

•

Latched Overcurrent Comparator

With Full Cycle Restart

BLOCK DIAGRAM

UDG-95101

* Note: 1823A,B Version Toggles Q and Q are always low

9/95

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

DESCRIPTION (cont.)

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VC, VCC)....................................................22V

Output Current, Source or Sink (Pins OUTA, OUTB)

DC ..................................................................................0.5A

Pulse (0.5µs)...................................................................2.2A

Power Ground (PGND) ......................................................±0.2V

Analog Inputs

(INV, NI, RAMP)...................................................−0.3V to 7V

(ILIM, SS).............................................................−0.3V to 6V

Clock Output Current (CLK/LEB) .......................................−5mA

Error Amplifier Output Current (EAOUT)..............................5mA

Soft Start Sink Current (SS)...............................................20mA

Oscillator Charging Current (RT)........................................−5mA

Power Dissipation at TA = 60°C..............................................1W

Storage Temperature Range............................−65°C to +150°C

Junction Temperature.......................................−55°C to +150°C

Lead Temperature (Soldering, 10 sec.).............................300°C

All currents are positive into, negative out of the specified terminal.

Consult Packaging Section of Databook for thermal limitations

and considerations of packages.

The UC3825A,B has dual alternating outputs and the same

pin configuration of the UC3825. The UC3823A,B outputs op-

erate in phase with duty cycles from zero to less than 100%.

The pin configuration of the UC3823A,B is the same as the

UC3823 except pin 11 is now an output pin instead of the ref-

erence pin to the current limit comparator. “A” version parts

have UVLO thresholds identical to the original UC3823/25.

The “B” versions have UVLO thresholds of 16 and 10V, in-

tended for ease of use in off-line applications.

Consult Application Note U-128 for detailed technical and ap-

plications information. Contact the factory for further pack-

aging and availability information.

Device

UVLO

DMAX

UC3823A

UC3823B

UC3825A

UC3825B

9.2V/8.4V

16V/10V

9.2V/8.4V

16V/10V

< 100%

< 50%

CONNECTION DIAGRAMS

DIL-16, SOIC-16, (Top View)

J or N Package; DW Package

PLCC-20, LCC-20, (Top View)

Q, L Packages

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = −55°C to +125°C for the

UC1823A,B and UC1825A,B; −40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and

UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.

PARAMETER

Reference Section

TEST CONDITIONS

MIN

TYP

MAX UNITS

Output Voltage

TJ = 25°C, Io = 1mA

5.05

5.1

5.15

Line Regulation

12 < VCC < 20V

Load Regulation

1mA < Io < 10mA

Total Output Variation

Temperature Stability

Output Noise Voltage

Long Term Stability

Short Circuit Current

Line, Load, Temp

5.03

5.17

TMIN < TA < TMAX (Note 1)

10Hz < f < 10kHz (Note 1)

TJ = 125°C, 1000 hours (Note 1)

VREF = 0V

0.2

0.4 mV/°C

µVRMS

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = −55°C to

+125°C for the UC1823A,B and UC1825A,B; −40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the

UC3823A,B and UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.

PARAMETER

Oscillator Section

TEST CONDITIONS

MIN

TYP

MAX UNITS

Initial Accuracy

Total Variation

TJ = 25°C (Note 1)

375

350

400

425

450

kHz

Line, Temperature (Note 1)

12V < VCC < 20V

Voltage Stability

Temperature Stability

Initial Accuracy

TMIN < TA < TMAX (Note 1)

RT = 6.6k, CT = 220pF TA = 25°C (Note 1)

RT = 6.6k, CT = 220pF (Note 1)

0.9

0.85

3.7

1.1

MHz

Total Variation

1.15

Clock Out High

Clock Out Low

0.2

Ramp Peak

2.6

0.7

1.6

2.8

Ramp Valley

1.25

Ramp Valley to Peak

Oscillator Discharge Current

Error Amplifier Section

Input Offset Voltage

Input Bias Current

Input Offset Current

Open Loop Gain

CMRR

1.8

RT = Open, VCT = 2V

0.6

0.1

µA

1V < Vo < 4V

1.5V < VCM < 5.5V

12V < VCC < 20V

VEAOUT = 1V

VEAOUT = 4V

IEAOUT = −0.5mA

IEAOUT = 1mA

F = 200kHz

PSRR

110

2.5

−1.3

4.7

0.5

Output Sink Current

Output Source Current

Output High Voltage

Output Low Voltage

Gain Bandwidth Product

Slew Rate

−0.5

4.5

MHz

V/µs

(Note 1)

PWM Comparator

RAMP Bias current

Minimum Duty Cycle

Maximum Duty Cycle

VRAMP = 0V

−1

−8

µA

Leading Edge Blanking

LEB Resistor

R = 2k, C = 470pF

VCLK/LEB = 3V

300

8.5

375

450

11.5 kohm

EAOUT Zero D.C. Threshold

VRAMP = 0V

1.1

1.25

1.4

Delay to Output

VEAOUT = 2.1V, VRAMP = 0 to 2V Step (Note 1)

Current Limit/Start Sequence/Fault Section

Soft Start Charge Current

Full Soft Start Threshold

Restart Discharge Current

Restart Threshold

VSS = 2.5V

0 < VILIM < 2V

µA

4.3

100

250

0.3

350

0.5

µA

ILIM Bias Current

µA

Current Limit Threshold

0.95

1.05

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = −55°C to

+125°C for the UC1823A,B and UC1825A,B; −40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the

UC3823A,B and UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Current Limit/Start Sequence/Fault Section (cont.)

Over Current Threshold

1.14

1.2

1.26

ILIM Delay to Output

VILIM = 0 to 2V Step (Note 1)

Output Section

Output Low Saturation

IOUT = 20mA

IOUT = 200mA

IOUT = 20mA

IOUT = 200mA

IO = 20mA

0.25

1.2

1.9

0.4

2.2

2.9

Output High Saturation

UVLO Output Low Saturation

0.8

1.2

Rise/Fall Time

CL = 1nF (Note 1)

UnderVoltage Lockout

Start Threshold

Stop Threshold

UVLO Hysteresis

Start Threshold

UCX823B and X825B only

UCX823A and X825A only

8.4

0.4

9.2

0.8

9.6

1.2

UVLO Hysteresis

Supply Current

Startup Current

Icc

VC = VCC = VTH(start) - 0.5V

100

300

µA

Note 1: Guaranteed by design. Not 100% tested in production.

APPLICATIONS INFORMATION

OSCILLATOR

Oscillator

The UC3823A,B/3825A,B oscillator is a saw tooth. The

rising edge is governed by a current controlled by the RT

pin and value of capacitance at the CT pin. The falling

edge of the sawtooth sets dead time for the outputs. Se-

lection of RT should be done first, based on desired max-

imum duty cycle. CT can then be chosen based on de-

sired frequency, RT, and DMAX. The design equations

are:

RT =

(10mA) (1 - DMAX)

(1.6 • DMAX)

CT =

(RT • F)

Recommended values for RT range from 1k to 100k.

Control of DMAX less than 70% is not recommended.

UDG-95102

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

APPLICATIONS INFORMATION (cont.)

OSCILLATOR (cont.)

Oscillator Frequency vs. RT and CT Curve

Maximum Duty Cycle vs RT Curve

UDG-95103

UDG-95104

LEADING EDGE BLANKING

The UC3823A,B/3825A,B performs fixed frequency pulse

width modulation control. The UC3823A,B outputs oper-

ate together at the switching frequency and can vary from

0 to some value less than 100%. The UC3825A,B outputs

are alternately controlled. During every other cycle, one

output will be off. Each output then, switches at one-half

the oscillator frequency, varying in duty cycle from 0 to less

than 50%.

LEB Operational Waveforms

To limit maximum duty cycle, the internal clock pulse

blanks both outputs low during the discharge time of the

oscillator. On the falling edge of the clock, the appropriate

output(s) is driven high. The end of the pulse is controlled

by the PWM comparator, current limit comparator, or the

overcurrent comparator.

Normally the PWM comparator will sense a ramp cross-

ing a control voltage (error amp output) and terminate the

pulse. Leading edge blanking (LEB) causes the PWM

comparator to be ignored for a fixed amount of time after

the start of the pulse. This allows noise inherent with

switched mode power conversion to be rejected. The

PWM ramp input may not require any filtering as result of

leading edge blanking.

UDG-95105

tLEB

= 0.5 • (R | | 10k) • C.

Values of R less than 2k should not be used

Leading edge blanking is also applied to the current limit

comparator. After LEB, if the ILIM pin exceeds the one

volt threshold, the pulse is terminated. The over current

comparator, however, is not blanked. It will catch catas-

trophic over current faults without a blanking delay. Any

time the ILIM pin exceeds 1.2V, the fault latch will be set

and the outputs driven low. For this reason, some noise

filtering may be required on the ILIM pin.

To program a Leading Edge Blanking period, connect a

capacitor, C, to CLK/LEB. The discharge time set by C and

the internal 10k resistor will determine the blanked inter-

val. The 10k resistor has a 10% tolerance. For more ac-

curacy, an external 2k 1% resistor, R, can be added, re-

sulting in an equivalent resistance of 1.66k with a tolerance

of 2.4%. The design equation is:

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

APPLICATIONS INFORMATION (cont.)

UVLO, SOFT START AND FAULT MANAGEMENT

Soft Start and Fault Waveforms

Soft start is programmed by a capacitor on the SS pin. At

power up, SS is discharged. When SS is low, the error amp

output is also forced low. As the internal 9µA source

charges the SS pin, the error amp output follows until

closed loop regulation takes over.

Anytime ILIM exceeds 1.2V, the fault latch will be set and

the output pins will be driven low. The soft start cap is then

discharged by a 250µA current sink. No more output

pulses are allowed until soft start is fully discharged, and

ILIM is below 1.2V. At this point the fault latch will be re-

set and the chip will execute a soft start.

UDG-95106

Should the fault latch be set during soft start, the outputs

will be immediately terminated, but the soft start cap will

not be discharged until it has been fully charged. This re-

sults in a controlled hiccup interval for continuous fault con-

ditions.

ACTIVE LOW OUTPUTS DURING UVLO

The UVLO function forces the outputs to be low and con-

siders both VCC and VREF before allowing the chip to

operate.

Output V and I During UVLO

Simplified Schematic

UDG-95108

UDG-95107

PWM APPLICATIONS

Current Mode

Voltage Mode

UDG-95110

UDG-95109

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

APPLICATIONS INFORMATION (cont.)

SYNCHRONIZATION

Operational Waveforms

The oscillator can be synchronized by an external pulse

inserted in series with the timing capacitor. Program the

free running frequency of the oscillator to be 10 to 15%

slower than the desired synchronous frequency. The

pulse width should be greater than 10ns and less than

half the discharge time of the oscillator. The rising edge

of the CLK/LEB pin can be used to generate a synchro-

nizing pulse for other chips. Note that, the CLK/LEB pin

will no longer accept an incoming synchronizing signal.

UDG-95112

General Oscillator Synchronization

Two Units

UDG-95111

UDG-95113

HIGH CURRENT OUTPUTS

Each totem pole output of the UC3823A,B and

UC3825A,B can deliver a 2 amp peak current into a ca-

pacitive load. The output can slew a 1000pF capacitor 15

volts in approximately 20 nanoseconds. Separate col-

lector supply (VC) and power ground (PGND) pins help

decouple the IC's analog circuitry from the high power

gate drive noise. The use of 3 Amp Schottky diodes

(1N5120, USD245 or equivalent) as shown in the figure

from each output to both VC and PGND are recom-

mended. The diodes clamp the output swing to the sup-

ply rails, necessary with any type of inductive/capacitive

load, typical of a MOSFET gate. Schottky diodes must

be used because a low forward voltage drop is required.

DO NOT USE standard silicon diodes.

Power MOSFET Drive Circuit

Although a "single ended" device, two output drivers are

available on the UC3823A,B devices. These can be “par-

alleled” by the use of a one-half ohm (noninductive) re-

sistor connected in series with each output for a com-

bined peak current of 4 Amps.

UDG-95114

UC1823A,B/1825A,B

UC2823A,B/2825A,B

UC3823A,B/3825A,B

APPLICATIONS INFORMATION (cont.)

GROUND PLANES

of the power MOSFET should connect to power ground

as should the return connection for input power to the sys-

tem and the bulk input capacitor. The output should be

clamped with a high current Schottky diode to both VCC

and PGND. Nothing else should be connected to power

ground.

Each output driver of these devices is capable of 2A peak

currents. Careful layout is essential for correct operation of

the chip. A ground plane must be employed. A unique sec-

tion of the ground plane must be designated for high di/dt

currents associated with the output stages. This point is the

power ground to which the PGND pin is connected. Power

ground can be separated from the rest of the ground plane

and connected at a single point, although this is not strictly

necessary if the high di/dt paths are well understood and

accounted for. VCC should be bypassed directly to power

ground with a good high frequency capacitor. The sources

VREF should be bypassed directly to the signal portion

of the ground plane with a good high frequency capaci-

tor. Low ESR/ESL ceramic 1µF capacitors are recom-

mended for both VCC and VREF. All analog circuitry

should likewise be bypassed to the signal ground plane.

UDG-95115

Open Loop Test Circuit

grounding and bypass procedures should be followed.

The use of a ground plane is highly recommended.

This test fixture is useful for exercising many of the

UC3823A,B, UC3825A,B functions and measuring their

specifications. As with any wideband circuit, careful

UDG-95116

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD.• MERRIMACK, NH 03054

TEL.(603) 424-2410 • FAX (603) 424-3460

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

UC1825BDWTR [ETC]

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