UC1842AL [ETC]

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型号：	UC1842AL
厂家：	ETC
描述：	开关
文件：	总8页 (文件大小：532K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

application

INFO

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

available

Current Mode PWM Controller

FEATURES

DESCRIPTION

•

Optimized for Off-line and DC to DC

The UC1842A/3A/4A/5A family of control ICs is a pin for pin compati-

ble improved version of the UC3842/3/4/5 family. Providing the nec-

essary features to control current mode switched mode power

supplies, this family has the following improved features. Start up cur-

rent is guaranteed to be less than 0.5mA. Oscillator discharge is

trimmed to 8.3mA. During under voltage lockout, the output stage

can sink at least 10mA at less than 1.2V for VCC over 5V.

Converters

•

Low Start Up Current (<0.5mA)

Trimmed Oscillator Discharge Current

Automatic Feed Forward Compensation

Pulse-by-Pulse Current Limiting

Enhanced Load Response Characteristics

Under-Voltage Lockout With Hysteresis

Double Pulse Suppression

The difference between members of this family are shown in the table

below.

Maximum Duty

Part #

UVLO On

UVLO Off

Cycle

<100%

<50%

High Current Totem Pole Output

Internally Trimmed Bandgap Reference

500kHz Operation

UC1842A

UC1843A

UC1844A

UC1845A

16.0V

8.5V

10.0V

7.9V

16.0V

8.5V

10.0V

7.9V

<50%

Low RO Error Amp

BLOCK DIAGRAM

A/B

Note 1:

A = DIL-8 Pin Number. B = SO-14 Pin Number.

Note 2: Toggle flip flop used only in 1844A and 1845A.

SLUS224A - SEPTEMBER 1994 - REVISED APRIL 2002

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS (Note 1)

PLCC-20, LCC-20

(TOP VIEW)

Q, L Packages

Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . 30V

Supply Voltage (ICC mA) . . . . . . . . . . . . . . . . . . . . Self Limiting

Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . . 5µJ

Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . -0.3V to +6.3V

Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . 1W

Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C

PACKAGE PIN FUNCTION

FUNCTION

N/C

Comp

N/C

VFB

3-4

N/C

ISENSE

N/C

RT/CT

N/C

Pwr Gnd

Gnd

N/C

Output

N/C

VCC

N/C

Note 1. All voltages are with respect to Ground, Pin 5. Currents

are positive into, negative out of the specified terminal. Consult

Packaging Section of Databook for thermal limitations and con-

siderations of packages. Pin numbers refer to DIL package only.

8-9

SOIC-14 (TOP VIEW)

D Package

VREF

DIL-8, SOIC-8 (TOP VIEW)

J or N, D8 Package

SOIC-WIDE16 (TOP VIEW)

DW Package

N/C

16 N/C

15 VREF

14 VCC

COMP

VFB

13 VCC

ISENSE

RT/CT

N/C

12 OUTPUT

11 GND

10 PWRGND

N/C

9 N/C

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –55°C ≤ TA ≤ 125°C for the

UC184xA; –40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70°C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ;

Pin numbers refer to DIL-8.

UC184xA\UC284xA

UC384xA

PARAMETER

Reference Section

TEST CONDITIONS

UNITS

MIN. TYP. MAX. MIN. TYP. MAX.

Output Voltage

TJ = 25°C, IO = 1mA

4.95

4.9

5.00

5.05

4.90

4.82

5.00

5.10

Line Regulation

12 ≤ VIN 25V

1 ≤ IO ≤ 20mA

(Note 2, Note 7)

Load Regulation

Temp. Stability

0.2

0.4

5.1

0.2

0.4

5.18

mV/°C

Total Output Variation

Output Noise Voltage

Line, Load, Temp.

10Hz ≤ f ≤ 10kHz

TJ = 25°C (Note 2)

TA = 125°C, 1000Hrs. (Note 2)

µV

Long Term Stability

Output Short Circuit

Oscillator Section

Initial Accuracy

-30

-100

-180

-30

-100

-180

TJ = 25°C (Note 6)

0.2

kHz

Voltage Stability

Temp. Stability

12 ≤ VCC ≤ 25V

TMIN ≤ TA ≤ TMAX (Note 2)

VPIN 4 peak to peak (Note 2)

TJ = 25°C, VPIN 4 = 2V (Note 8)

VPIN 4 = 2V (Note 8)

Amplitude

1.7

8.3

1.7

8.3

Discharge Current

7.8

7.5

8.8

7.8

7.6

8.8

Error Amp Section

Input Voltage

VPIN 1 = 2.5V

2.45

2.50

-0.3

2.55

-1

2.42

2.50

-0.3

2.58

-2

µA

MHz

Input Bias Current

AVOL

2 ≤ VO ≤ 4V

TJ = 25°C (Note 2)

0.7

Unity Gain Bandwidth

PSRR

12 ≤ VCC ≤ 25V

Output Sink Current

Output Source Current

VOUT High

VPIN 2 = 2.7V, VPIN 1 = 1.1V

VPIN 2 = 2.3V, VPIN 1 = 5V

VPIN 2 = 2.3V, RL = 15k to ground

VPIN 2 = 2.7V, RL = 15k to Pin 8

-0.5

-0.8

-0.5

-0.8

VOUT Low

0.7

1.1

0.7

1.1

Current Sense Section

Gain

(Note 3, Note 4)

2.85

0.9

3.15

1.1

2.85

0.9

3.15

1.1

V/V

Maximum Input Signal

PSRR

VPIN 1 = 5V (Note 3)

12 ≤ VCC ≤ 25V (Note 3)

-2

µA

Input Bias Current

Delay to Output

Output Section

Output Low Level

-10

VPIN 3 = 0 to 2V (Note 2)

150

300

150

300

ISINK = 20mA

0.1

0.4

2.2

0.1

0.4

2.2

ISINK = 200mA

Output High Level

ISOURCE = 20mA

13.5

ISOURCE = 200mA

Rise Time

TJ = 25°C, CL = 1nF (Note 2)

VCC = 5V, ISINK = 10mA

150

1.2

150

1.2

Fall Time

UVLO Saturation

0.7

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –55°C ≤ TA ≤ 125°C for the

UC184xA; –40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70°C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ;

Pin numbers refer to DIL-8.

UC184xA\UC284xA

UC384xA

PARAMETER

TEST CONDITIONS

UNITS

MIN. TYP. MAX. MIN. TYP. MAX.

Under-Voltage Lockout Section

Start Threshold

x842A/4A

7.8

8.4

9.0

14.5

7.8

8.5

7.0

8.4

17.5

9.0

x843A/5A

x842A/4A

x843A/5A

Min. Operation Voltage After

Turn On

11.5

8.2

7.0

7.6

8.2

7.6

PWM Section

Maximum Duty Cycle

x842A/3A

x844A/5A

100

Minimum Duty Cycle

Total Standby Current

Start-Up Current

0.3

0.5

0.3

0.5

Operating Supply Current

VCC Zener Voltage

VPIN 2 = VPIN 3 = 0V

ICC = 25mA

Note 2: Ensured by design, but not 100% production tested.

Note 3: Parameter measured at trip point of latch with VPIN2 = 0.

∆VPIN 1

Note 4: Gain defined as: A =

; 0 VPIN 3 0.8V.

∆VPIN 3

Note 5: Adjust VCC above the start threshold before setting at 15V.

Note 6: Output frequency equals oscillator frequency for the UC1842A and UC1843A. Output frequency is one half oscillator fre-

quency for the UC1844A and UC1845A.

Note 7: “Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

VREF (max ) −VREF (min)

Temp Stability =

.VREF (max) and VREF (min) are the maximum & minimum reference volt-

TJ (max ) −TJ (min)

age measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes

in temperature.”

Note 8: This parameter is measured with RT = 10k to VREF.This contributes approximately 300 A of current to the measurement.

The total current flowing into the RT/C pin will be approximately 300 A higher than the measured value.

Error Amp Configuration

Error Amp can Source and Sink up to 0.5mA, and Sink up to 2mA.

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

Under-Voltage Lockout

During UVLO, the Output is low.

Current Sense Circuit

Peak Current (IS) is Determined By The Formula

1.0V

ISMAX ′

A small RC filter may be required to suppress switch transients.

Output Saturation Characteristics

Error Amplifier Open-Loop Frequency Response

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

APPLICATIONS DATA (cont.)

Oscillator Section

Oscillator Frequency vs Timing Resistance

Maximum Duty Cycle vs Timing Resistor

Open-Loop Laboratory Test Fixture

High peak currents associated with capacitive loads necessi-

tate careful grounding techniques. Timing and bypass capaci-

tors should be connected close to pin 5 in a single point

ground. The transistor and 5k potentiometer are used to sam-

ple the oscillator waveform and apply an adjustable ramp to

pin 3.

Slope Compensation

A fraction of the oscillator ramp can be resistively

summed with the current sense signal to provide slope

compensation for converters requiring duty cycles over

50%.

Note that capacitor, C, forms a filter with R2 to suppress

the leading edge switch spikes.

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

APPLICATIONS DATA (cont.)

Off-line Flyback Regulator

5. Output Voltage:

Power Supply Specifications

A. +5V, 5%; 1A to 4A load

Ripple voltage: 50mV P-P Max

B. +12V, 3%; 0.1A to 0.3A load

Ripple voltage: 100mV P-P Max

C. -12V , 3%; 0.1A to 0.3A load

Ripple voltage: 100mV P-P Max

1. Input Voltage

95VAC to 130VA

(50 Hz/60Hz)

3750V

40kHz

70%

2. Line Isolation

3. Switching Frequency

4. Efficiency

Full Load

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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

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Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

UC1842AL [ETC]

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