UC2527AQTR [ETC]
Voltage-Mode SMPS Controller ; 电压型开关电源控制器\n
| 型号： | UC2527AQTR |
| 厂家： | 
ETC |
| 描述： | Voltage-Mode SMPS Controller
|
| 文件： | 总8页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1525A/27A
UC2525A/27A
UC3525A/27A
Regulating Pulse Width Modulators
FEATURES
DESCRIPTION
•
8 to 35V Operation
The UC1525A/1527A series of pulse width modulator integrated circuits are de-
signed to offer improved performance and lowered external parts count when used
in designing all types of switching power supplies. The on-chip +5.1V reference is
trimmed to ±1% and the input common-mode range of the error amplifier includes
the reference voltage, eliminating external resistors. A sync input to the oscillator
allows multiple units to be slaved or a single unit to be synchronized to an external
system clock. A single resistor between the CT and the discharge terminals pro-
vides a wide range of dead-time adjustment. These devices also feature built-in
soft-start circuitry with only an external timing capacitor required. A shutdown termi-
nal controls both the soft-start circuitry and the output stages, providing instantane-
ous turn off through the PWM latch with pulsed shutdown, as well as soft-start
recycle with longer shutdown commands. These functions are also controlled by
an undervoltage lockout which keeps the outputs off and the soft-start capacitor
discharged for sub-normal input voltages. This lockout circuitry includes approxi-
mately 500mV of hysteresis for jitter-free operation. Another feature of these PWM
circuits is a latch following the comparator. Once a PWM pulse has been termi-
nated for any reason, the outputs will remain off for the duration of the period. The
latch is reset with each clock pulse. The output stages are totem-pole designs ca-
pable of sourcing or sinking in excess of 200mA. The UC1525A output stage fea-
tures NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR
logic which results in a HIGH output level when OFF.
•
5.1V Reference Trimmed to
±1%
•
•
100Hz to 500kHz Oscillator
Range
Separate Oscillator Sync
Terminal
•
•
•
•
Adjustable Deadtime Control
Internal Soft-Start
Pulse-by-Pulse Shutdown
Input Undervoltage Lockout
with Hysteresis
•
•
Latching PWM to Prevent
Multiple Pulses
Dual Source/Sink Output
Drivers
BLOCK DIAGRAM
2/96
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UC1525A/27A
UC2525A/27A
UC3525A/27A
ABSOLUTE MAXIMUM RATINGS (Note 1)
RECOMMENDED OPERATING CONDITIONS
(Note 3)
Supply Voltage, (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Collector Supply Voltage (VC) . . . . . . . . . . . . . . . . . . . . . . +40V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN
Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA
Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . . 1000mW
Power Dissipation at TC = +25°C (Note 2). . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . . -55°C to +150°C
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 seconds). . . . . . . . . . +300°C
Note 1: Values beyond which damage may occur.
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V
Collector Supply Voltage (VC) . . . . . . . . . . . . . . +4.5V to +35V
Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA
Sink/Source Load Current (peak). . . . . . . . . . . . . . 0 to 400mA
Reference Load Current. . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range . . . . . . . . . . . . . . 100Hz to 400kHz
Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Oscillator Timing Capacitor. . . . . . . . . . . . . . . . .001µF to 0.1µF
Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . . 0 to 500Ω
Operating Ambient Temperature Range
UC1525A, UC1527A. . . . . . . . . . . . . . . . . . -55°C to +125°C
UC2525A, UC2527A. . . . . . . . . . . . . . . . . . . -25°C to +85°C
UC3525A, UC3527A. . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Note 3: Range over which the device is functional and
parameter limits are guaranteed.
Note 2: Consult packaging Section of Databook for thermal
limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-16 (TOP VIEW)
J or N Package
PLCC-20, LCC-20 (TOP VIEW)
Q, L Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
1
N/C
Inv. Input
N.I. Input
SYNC
2
3
4
OSC. output
N/C
5
6
CT
7
RT
8
Discharge
Softstart
N/C
9
10
11
12
13
14
15
16
17
18
19
20
Compensation
Shutdown
Output A
Ground
N/C
VC
Output B
+VIN
VREF
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UC1525A/27A
UC2525A/27A
UC3525A/27A
ELECTRICAL CHARACTERISTICS: +VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ
UC1525A/UC2525A
UC1527A/UC2527A
UC3525A
UC3527A
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
Reference Section
Output Voltage
TJ = 25°C
5.05
5.10
10
5.15
20
5.00
5.10
10
5.20
20
V
Line Regulation
VIN = 8 to 35V
mV
mV
Load Regulation
IL = 0 to 20mA
20
50
20
50
Temperature Stability (Note 5)
Total Output Variation (Note 5)
Shorter Circuit Current
Output Noise Voltage (Note 5)
Long Term Stability (Note 5)
Oscillator Section (Note 6)
Initial Accuracy (Notes 5 & 6)
Voltage Stability (Notes 5 & 6)
Temperature Stability (Note 5)
Minimum Frequency
Over Operating Range
Line, Load, and Temperature
VREF = 0, TJ = 25°C
10Hz ≤ 10kHz, TJ = 25°C
TJ = 125°C
20
50
20
50
5.00
5.20
100
200
50
4.95
5.25
100
V
80
40
20
80
40
20
mA
200 µVrms
50
mV
TJ = 25°C
± 2
± 0.3
± 3
± 6
± 1
± 6
120
± 2
± 1
± 3
± 6
± 2
± 6
120
%
%
VIN = 8 to 35V
Over Operating Range
RT = 200kΩ, CT = 0.1µF
RT = 2kΩ, CT = 470pF
IRT = 2mA
%
Hz
kHz
mA
V
Maximum Frequency
400
1.7
3.0
0.3
1.2
400
1.7
3.0
0.3
1.2
Current Mirror
2.0
3.5
0.5
2.0
1.0
2.2
2.0
3.5
0.5
2.0
1.0
2.2
Clock Amplitude (Notes 5 & 6)
Clock Width (Notes 5 & 6)
Sync Threshold
TJ = 25°C
1.0
2.8
2.5
1.0
2.8
2.5
µs
V
Sync Input Current
Sync Voltage = 3.5V
mA
Error Amplifier Section (VCM = 5.1V)
Input Offset Voltage
0.5
1
5
10
1
2
1
10
10
1
mV
µA
Input Bias Current
Input Offset Current
µA
DC Open Loop Gain
RL ≥ 10MΩ
60
1
75
2
60
1
75
2
dB
Gain-Bandwidth Product
(Note 5)
AV = 0dB, TJ = 25°C
MHz
DC Transconductance
(Notes 5 & 7)
TJ = 25°C, 30kΩ ≤ RL ≤ 1MΩ
1.1
1.5
1.1
1.5
mS
Output Low Level
0.2
5.6
75
0.5
0.2
5.6
75
0.5
V
V
Output High Level
3.8
60
50
3.8
60
50
Common Mode Rejection
Supply Voltage Rejection
VCM = 1.5 to 5.2V
VIN = 8 to 35V
dB
dB
60
60
Note 5: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at fOSC = 40kHz (RT = 3.6kΩ, CT = 0.01µF, RD = 0Ω). Approximate oscillator frequency is defined by:
1
f =
CT (0.7RT + 3RD)
Note 7: DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL
where RL is the resistance from pin 9 to ground..
The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded.
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UC1525A/27A
UC2525A/27A
UC3525A/27A
+VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ
ELECTRICAL CHARACTERISTICS:
UC1525A/UC2525A
UC1527A/UC2527A
UC3525A
UC3527A
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
PWM Comparator
Minimum Duty-Cycle
Maximum Duty-Cycle
0
0
%
%
V
45
49
0.9
3.3
.05
45
49
0.9
3.3
.05
Input Threshold (Note 6)
Zero Duty-Cycle
Maximum Duty-Cycle
0.7
0.7
3.6
1.0
3.6
1.0
V
Input Bias Current (Note 5)
Shutdown Section
µA
Soft Start Current
VSD = 0V, VSS = 0V
VSD = 2.5V
25
50
0.4
0.8
0.4
0.2
80
0.7
1.0
1.0
0.5
25
50
0.4
0.8
0.4
0.2
80
0.7
1.0
1.0
0.5
µA
V
Soft Start Low Level
Shutdown Threshold
Shutdown Input Current
Shutdown Delay (Note 5)
To outputs, VSS = 5.1V, TJ = 25°C
VSD = 2.5V
0.6
0.6
V
mA
µs
VSD = 2.5V, TJ = 25°C
Output Drivers (Each Output) (VC = 20V)
Output Low Level
ISINK = 20mA
0.2
1.0
19
18
7
0.4
2.0
0.2
1.0
19
18
7
0.4
2.0
V
V
ISINK = 100mA
Output High Level
ISOURCE = 20mA
ISOURCE = 100mA
VCOMP and VSS = High
VC = 35V
18
17
6
18
17
6
V
V
Under-Voltage Lockout
VC OFF Current (Note 7)
Rise Time (Note 5)
8
8
V
200
600
300
200
600
300
µA
ns
ns
CL = 1nF, TJ = 25°C
CL = 1nF, TJ = 25°C
100
50
100
50
Fall Time (Note 5)
Total Standby Current
Supply Current
VIN = 35V
14
20
14
20
mA
Note 5: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at fOSC = 40kHz (RT = 3.6kΩ, CT = 0.01µF, RD = 0Ω).
Note 7: Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.
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UC1525A/27A
UC2525A/27A
UC3525A/27A
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
UC1525A Output Circuit
UC1525A Output Saturation Characteristics
(1/2 Circuit Shown)
For single-ended supplies, the driver outputs are
grounded. The VC terminal is switched to ground by the
totem-pole source transistors on alternate oscillator cy-
cles.
In conventional push-pull bipolar designs, forward base
drive is controlled by R1-R3. Rapid turn-off times for the
power devices are achieved with speed-up capacitors
C1 and C2.
Low power transformers can be driven by the UC1525A.
Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
The low source impedance of the output drivers provides
rapid charging of power FET Input capacitance while
minimizing external components.
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UC1525A/27A
UC2525A/27A
UC3525A/27A
UC1525A Oscillator Schematic
PRINCIPLES OF OPERATION AND TYPICAL CHAR-
ACTERISTIC SHUTDOWN OPTIONS
(See Block Diagram)
a positive signal on Pin 10 performs two functions; the
PWM latch is immediately set providing the fastest turn-
off signal to the outputs; and a 150µA-current sink begins
to discharge the external soft-start capacitor. If the shut-
down command is short, the PWM signal is terminated
without significant discharge of the soft-start capacitor,
thus, allowing, for example, a convenient implementation
of pulse-by-pulse current limiting. Holding Pin 10 high for
a longer duration, however, will ultimately discharge this
external capacitor, recycling slow turn-on upon release.
Since both the compensation and soft-start terminals
(Pins 9 and 8) have current source pull-ups, either can
readily accept a pull-down signal which only has to sink a
maximum of 100µA to turn off the outputs. This is subject
to the added requirement of discharging whatever exter-
nal capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry
of Pin 10 which has been improved to enhance the avail-
able shutdown options. Activating this circuit by applying
Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation.
Oscillator Charge Time
vs RT and CT
Oscillator Discharge Time
vs RD and CT
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UC1525A/27A
UC2525A/27A
UC3525A/27A
Error Amplifier Voltage Gain
Maximum Value RD vs Minimum Value RT
and Phase vs Frequency
RL is impedance from pin 9 to ground. Values below
30kΩ will begin to limit the maximum duty cycle.
LAB TEST FIXTURE
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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相关型号：
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0.5A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO16, 0.300 INCH, PLASTIC, SOIC-16
TI
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