UC2879L [ETC]
Current/Voltage-Mode SMPS Controller ; 电流/电压模式开关电源控制器\n
| 型号： | UC2879L |
| 厂家： | 
ETC |
| 描述： | Current/Voltage-Mode SMPS Controller
|
| 文件： | 总7页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1879
UC2879
UC3879
Phase Shift Resonant Controller
FEATURES
DESCRIPTION
• Programmable Output Turn On
Delay; Zero Delay Available
The UC3879 controls a bridge power stage by phase shifting the switching
of one half-bridge with respect to the other. This allows constant frequency
pulse width modulation in combination with resonant, zero-voltage switching
for high efficiency performance. The UC3879 can be configured to provide
control in either voltage mode or current mode operation, with overcurrent
shutdown for fast fault protection.
• Compatible with Voltage Mode or
Current Mode Topologies
• Practical Operation at Switching
Frequencies to 300kHz
Independently programmable time delays provide dead-time at the turn-on
of each output stage, allowing time for each resonant switching interval.
• Four 100mA Totem Pole Outputs
• 10MHz Error Amplifier
With the oscillator capable of operating in excess of 600kHz, overall output
switching frequencies to 300kHz are practical. In addition to the standard
free running mode, with the CLKSYNC pin, the user may configure the
UC3879 to accept an external clock synchronization signal. Alternatively, up
to three units can be locked together with the operational frequency deter-
mined by the fastest device.
• Pin Programmable Undervoltage
Lockout
• Low Startup Current - 150µA
• Soft Start Control
Protective features include an undervoltage lockout and overcurrent protec-
tion. Additional features include a 10MHz error amplifier, a 5V precision ref-
erence, and soft start. The UC3879 is available in 20 pin N, J, DW, and Q
and 28 pin L packages.
• Outputs Active Low During UVLO
BLOCK DIAGRAM
UDG-94070-1
6/98
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UC1879
UC2879
UC3879
ABSOLUTE MAXIMUM RATINGS
Table I. Product Selection Guide
Supply Voltage (VC, VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Output Current, Source or Sink, DC . . . . . . . . . . . . . . . . . 20mA
Analog I/0s
TEMPERATURE
RANGE
AVAILABLE
PACKAGES
(Pins 1, 2, 3, 4, 5, 6, 14, 15, 17, 18, 19) . . . . . . −0.3 to 5.3V
(Pin 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −.03V to VIN
Storage Temperature Range . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C
UCC1879
UCC2879
UCC3879
– 55°C to +125°C
– 40°C to +85°C
0°C to +70°C
J, L
N, DW, Q, J, L
N, DW, Q
CONNECTION DIAGRAMS
Notes: Pin references are to 20 pin DIL and SOIC packages.
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
DIL-20, SOIC-20 (Top View)
J or N Package, DW Package
CLCC-28 (Top View)
L Package
PLCC-20 (Top View)
Q Package
2
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UC1879
UC2879
UC3879
ELECTRICAL CHARACTERISTICS Unless specified; VC = VIN = VUVSEL =12V, CT = 470pF, RT = 9.53k, RDELSETA-B =
RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01µF, TA = TJ.
PARAMETER
Undervoltage Lockout
TEST CONDITIONS
MIN
TYP
MAX UNITS
Start Threshold
VUVSEL = VIN
9
10.75 12.5
V
V
VUVSEL = Open
VUVSEL = VIN
12.5 15.25 16.5
UVLO Hysteresis
1.15
5.2
1.75
6
2.15
7.4
V
VUVSEL = Open
VUVSEL = VIN = 8V
V
Input Bias, UVSEL Pin
Supply Current
IVIN Startup
30
µA
VIN = VUVSEL = 8V, VC = 18V, IDELSETA-B
IDELSETC-D = 0
=
=
150
10
600
100
µA
µA
IVC Startup
VIN = VUVSEL = 8V, VC = 18V, IDELSETA-B
I
DELSETC-D = 0
IVIN Operating
UC3879, UC2879
UC1879
23
23
4
33
36
8
mA
mA
mA
IVC Operating
Voltage Reference
Output Voltage
TJ = +25°C
4.92
4.875
2.4
5
1
5
5.08
10
V
Line Regulation
11V < VIN < 18V
IVREF = –10mA
mV
mV
V
Load Regulation
20
Total Variation
Line, Load, Temperature
VREF = 0V, TJ = 25°C
5.125
–15
Short Circuit Current
Error Amplifier
–60
mA
Error Amplifier Input Voltage
Input Bias Current
AVOL
2.5
0.6
90
2.6
3
V
µA
dB
dB
mA
mA
V
1V < VCOMP < 4V
11V < VIN < 18V
VCOMP = 1V
60
85
1
PSRR
100
2.5
−1.3
4.7
0.5
11
Output Sink Current
Output Source Current
Output Voltage High
Output Voltage Low
Slew Rate
VCOMP = 4V
−0.5
5
ICOMP = –0.5mA
ICOMP = 1mA
TA = +25°C
4
0
6
1
V
V/µs
PWM Comparator
RAMP Offset Voltage
PWM Phase Shift,
TDELSETA-B, TDELSETC-D = 0, Note 1
Output Skew,
TJ = 25°C, Note 3
1.1
98
0
1.25
99.7
0.3
1.4
102
2
V
VCOMP > VRAMPpeak + VRAMPoffset
VCOMP < Zero Phase Shift Voltage
VCOMP > VRAMPpeak + VRAMPoffset
VCOMP < Zero Phase Shift Voltage
UC3879, UC2879
%
%
10
ns
ns
ns
ns
TDELSETA-B, TDELSETC-D = 0, Note 1
10
Ramp to Output Delay, TDELSETA-B = 0,
TDELSETC-D = 0
115
115
250
300
UC1879
Oscillator
Initial Accuracy
TA = 25°C
180
200
1
220
2
kHz
%
Voltage Stability
Total Variation
11V < VIN < 18V
Line, Temperature
160
2.3
2.8
0.5
200
2.5
4
240
2.7
kHz
V
CLKSYNC Threshold
Clock Out High
V
Clock Out Low
1
1.5
600
0.4
V
Clock Out Pulse Width
Ramp Valley Voltage
400
0.2
ns
V
3
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UC1879
UC2879
UC3879
ELECTRICAL CHARACTERISTICS Unless specified; VC = VIN = VUVSEL =12V, CT = 470pF, RT = 9.53k, RDELSETA-B =
RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01µF, TA = TJ.
PARAMETER
Ramp Peak Voltage
TEST CONDITIONS
MIN
TYP
MAX UNITS
2.8
2.9
3.2
V
Current Limit
Input Bias
VCS = 3.0V
VCS = 2.2V
2
10
µA
V
Threshold Voltage
Delay to OUTA, B, C, D
Cycle-by-Cycle Current Limit
Input Bias
2.35
1.85
2.5
160
2.65
300
ns
2
2
10
µA
V
Threshold Voltage
Delay to Output Zero Phase
Soft Start/Reset Delay
Charge Current
2.15
300
110
ns
VSS = 0.5V
VSS = 1V
–20
120
4.3
–9
230
4.7
–3
µA
µA
V
Discharge Current
Restart Threshold
Discharge Level
Output Drivers
300
mV
Output Low Level
Output High Level
Delay Set (Note 5)
Delay Time
IOUT = 10mA
0.3
2.2
0.4
3
V
V
IOUT = –10mA, Referenced to VC
RDELSETA-B = RDELSETC-D = 4.8k
RDELSETA-B = RDELSETC-D= 1.9k
VDELSETA-B = VDELSETC-D = 5V
300
130
430
170
5
600
250
ns
ns
ns
Delay Time
Zero Delay
Note 1. Phase shift percentage (0% = 0°, 100% = 180°) is de-
fined as θ =
Φ %
where θ is the phase shift, and Φ and T are defined in Figure 1.
At 0% phase shift, Φ is the output skew.
Note 2. Delay time is defined as:
=
•
where T is defined in Figure 1.
Note 3. Ramp offset voltage has a temperature coeffecient of
about –4mV/ °C.
Duty Cycle =
Period = T
Note 4. The zero phase shift voltage is the voltage measured
at COMP which forces zero phase shift. This condition corre-
sponds to zero effective output power. Zero phase shift voltage
has a temperature coeffecient of about –2mV/ °C.
TDHL(A to C) = TDHL(B to D) = Φ
Note 5. Delay time can be programmed via resistors from the
delay set pins to ground.
Figure 1. Phase Shift, Output Skew & Delay Time
Definitions
−
=
•
•
(
)
The recommended range for RDELAY is 1.9k to 10k.
4
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UC1879
UC2879
UC3879
PIN DESCRIPTIONS
DELSETA-B, DELSETC-D (Output Delay Control): The
user programmed currents from these pins to GND set
the turn on delay for the corresponding output pair. This
delay is introduced between the turn off of one switch
and the turn on of another in the same leg of the bridge
to allow resonant switching to take place. Separate
delays are provided for the two half-bridges to
accommodate differences in the resonant capacitor
charging currents.
CLKSYNC (Bi-directional Clock and Synchronization):
Used as an output, CLKSYNC provides a clock signal. As
an input, this pin provides a synchronization point.
Multiple UC3879s, each with their own local oscillator
frequency, may be connected together by the CLKSYNC
pin, and they will synchronize to the fastest oscillator.
This pin may also be used to synchronize the UC3879 to
an external clock, provided the frequency of the external
signal is higher than the frequency of the local oscillator.
CLKSYNC is internally connected to an emitter follower
pull-up and a current source pull-down (300µA typical).
Therefore an external resistor to GND can be used to
improve the CLKSYNC pin’s ability to drive capacitive
loads.
EA– (Error Amplifier Inverting Input): This is normally
connected to the voltage divider resistors which sense
the power supply output voltage level. The loop
compensation components are connected between this
pin and COMP.
COMP (Error Amplifier Output): This pin is the output of
the gain stage for overall feedback control. Error amplifier
output voltage levels below 0.9 volt forces zero phase
shift. Since the error amplifier has a relatively low current
drive capability, the output may be overridden by driving it
with a sufficiently low impedance source.
GND (Signal Ground): All voltages are measured with
respect to GND. The timing capacitor on CT, and bypass
capacitors on VREF and VIN should be connected
directly to the ground plane near GND.
OUTA – OUTD (Outputs A-D): The outputs are 100mA
totem pole output drivers optimized to drive FET driver
ICs. The outputs operate as pairs with a nominal 50%
duty cycle. The A-B pair is intended to drive one
half-bridge in the external power stage and is
synchronized to the clock waveform. The C-D pair drives
the other half-bridge with switching phase shifted with
respect to the A-B outputs.
CT (Oscillator Frequency Set): After choosing RT to set
the required upper end of the linear duty cycle range, the
timing capacitor (CT) value is calculated to set the
oscillator frequency as follows:
=
•
•
PWRGND (Power Ground): VC should be bypassed with
a ceramic capacitor from VC to the section of the ground
plane that is connected to PWRGND. Any required bulk
reservoir capacitor should be connected in parallel.
PWRGND and GND should be connected at a single
point near the chip to optimize noise rejection and
minimize DC voltage drops.
Connect the timing capacitor directly between CT and
GND. Use a high quality ceramic capacitor with low ESL
and ESR for best results. A minimum CT value of 200pF
insures good accuracy and less susceptibility to circuit
layout parasitics. The oscillator and PWM are designed to
provide practical operation to 600kHz.
CS (Current Sense): This pin is the non-inverting input to
the two current fault comparators whose references are
set internally to fixed values of 2.0V and 2.5V. When the
voltage at this pin exceeds 2.0V, and the error amplifier
output voltage exceeds the voltage on the ramp input, the
phase shift limiting overcurrent comparator will limit the
phase shifting on a cycle-by-cycle basis. When the
voltage at this pin exceeds 2.5V, the current fault latch is
set, the outputs are forced OFF, and a soft start cycle is
initiated. If a constant voltage above 2.5V is applied to
this pin the outputs are disabled and held low. When CS
is brought below 2.5V, the outputs will begin switching at
0 degrees phase shift before the SS pin begins to rise.
This condition will not prematurely deliver power to the
load.
RAMP (Voltage Ramp): This pin is the input to the PWM
comparator. Connect it to CT for voltage mode control.
For current mode control, connect RAMP to CS and also
to the output of the current sense transformer circuit.
Slope compensation can be achieved by injecting a
portion of the ramp voltage from CT to RAMP.
5
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UC1879
UC2879
UC3879
PIN DESCRIPTIONS (cont.)
RT (Clock/Sync Duty Cycle Set Pin): The UC3879 UVSEL: Connecting this pin to VIN sets a turn on voltage
oscillator produces a sawtooth waveform. The rising edge of 10.75V with 1.5V of UVLO hysteresis. Leaving the pin
is generated by connecting a resistor from RT to GND open-circuited programs a turn on voltage of 15.25V with
and
a capacitor from CT to GND (see CT pin 6.0V of hysteresis.
description). During the rising edge, the modulator has
linear control of the duty cycle. The duty cycle jumps to
100% when the voltage on COMP exceeds the oscillator
peak voltage. Selection of RT should be done first, based
on the required upper end of the linear duty cycle range
(Dlin) as follows:
VC (Output Switch Supply Voltage): This pin supplies
power to the output drivers and their associated bias
circuitry. The difference between the output high drive
and VC is typically 2.1V. This supply should be bypassed
directly to PWRGND with a low ESR/ESL capacitor.
VIN (Primary Chip Supply Voltage): This pin supplies
power to the logic and analog circuitry on the integrated
circuit that is not directly associated with driving the
output stages. Connect VIN to a stable source above 12V
for normal operation. To ensure proper functionality, the
UC3879 is inactive until VIN exceeds the upper
undervoltage lockout threshold. This pin should be
bypassed directly to GND with a low ESR/ESL capacitor.
=
•
(
)
Recommended values for RT range from 2.5k to 100k.
SS: Connect a capacitor between this pin and GND to
set the soft start time. The voltage at SS will remain near
zero volts as long as VIN is below the UVLO threshold.
Soft start will be pulled up to about 4.8V by an internal
9µA current source when VIN and VREF become valid
(assuming a non-fault condition). In the event of a current
fault (CS voltage exceeding 2.5V), soft start will be pulled
to GND and then ramp to 4.8V. If a fault occurs during the
soft start cycle, the outputs will be immediately disabled
and soft start must fully charge prior to resetting the fault
latch. For paralleled controllers, the soft start pins may be
paralleled to a single capacitor, but the charge currents
will be additive.
NOTE: When VIN exceeds the UVLO threshold the supply cur-
rent (IIN) jumps from about 100µA to greater than 20mA. If the
UC3879 is not connected to a well bypassed supply, it may im-
mediately enter the UVLO state again. Therefore, sufficient by-
pass capacity must be added to ensure reliable startup.
VREF: This pin provides an accurate 5V voltage
reference. It is internally short circuit current limited.
VREF is disabled while VIN is below the UVLO threshold.
The circuit is also disabled until VREF reaches
approximately 4.75V. For best results bypass VREF with
a 0.1µF, low ESR/ESL capacitor.
ADDITIONAL INFORMATION
Please refer to the following Unitrode publications for [2] Application Note U-136, Phase Shifted, Zero Voltage
additional information. The following three topics are Transition Design Considerations and the UC3875 PWM
available in the Applications Handbook.
Controller by Bill Andreycak.
[1] Application Note U-154, The New UC3879 Phase- Design Note DN-63, The Current-Doubler Rectifier: An
Shifted PWM Controller Simplifies the Design of Zero Alternative Rectification Technique for Push-Pull and
Voltage Transition Full-Bridge Converters by Laszlo Bridge Converters by Laszlo Balogh.
Balogh.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
6
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