UC62LV4008CH-55 [ETC]
Low Power CMOS SRAM; 低功耗CMOS SRAM
| 型号： | UC62LV4008CH-55 |
| 厂家： | 
ETC |
| 描述： | Low Power CMOS SRAM |
| 文件： | 总11页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀFeatures:
• Vcc operation voltage : 1.5V ~ 3.6V
• Low power consumption :
35mA (Max.) operating current
2uA (Typ.) CMOS standby current
• High Speed Access time :
ꢀDescription
The UC62LV2008 is a high performance, very low power
CMOS Static Random Access Memory organized as 524,288
words by 8 bits and operates from 1.5V to 3.6V supply
voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 2uA and maximum access
time of 70ns in 1.5V operation.
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV4008 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The UC62LV4008 is available in the JEDEC standard 32
pin 450mil Plastic SOP, 8mmx20.0mm TSOP (type I),
and 8mmx13.4mm STSOP.
ꢀPRODUCT FAMILY
Speed
(ns)
Vcc=1.5V(Max.)
Power Consumption
Package
Operating
Tempature
Product Family
Vcc Range
STANDBY
Operating
Type
Vcc=3.3V(Typ.)
Vcc=3.6V(Max.)
UC62LV4008HC
UC62LV4008FC
UC62LV4008GC
UC62LV4008AC
UC62LV4008HI
UC62LV4008FI
UC62LV4008GI
UC62LV4008AI
TSOP(I)-32
SOP-32
0℃~ 70℃
1.5V ~ 3.6V
55/70
2uA
2uA
35mA
35mA
STSOP-32
DICE
TSOP(I)-32
SOP-32
-40℃~ 85℃
1.5V ~ 3.6V
55/70
STSOP-32
DICE
ꢀPIN CONFIGURATIONS
ꢀBLOCK DIAGRAM
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VCC
A15
A18
WE
A13
A8
A9
A11
OE
ROW
Address
MEMORY ARRAY
512K X 8 Bits
COL
Address
COLUMN DECODER
CS62LV4008FI 24
CS62LV4008FC
23
A10
CE
SENSE AMPLIFIER
&
WRITE DRIVER
22
21
20
19
18
17
CE
WE
OE
DQ7
DQ6
DQ5
DQ4
DQ3
CE
X8
WE
I/O BUFFER
OE
A11
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
CS62LV4008HI
CS62LV4008HC
CS62LV4008GI
CS62LV4008GC
A6
A5
A4
A1
A2
A3
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 1
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀPIN DESCRIPTION
Name
A0 – A18
CE\
Type
Input
Input
Function
Address inputs for selecting one of the 524,288 x 8 bit words in the RAM
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip
enable is not active, the device is deselected and not in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
WE\
OE\
Input
Input
DQ0 – DQ7
Vcc
I/O
Power
Power
Ground
Gnd
ꢀTRUTH TABLE
Mode
Not Selected
Output Disabled
Read
WE\
CE\
H
OE\
X
I/O state
High Z
High Z
DOUT
Vcc Current
X
H
H
L
ISB,ISB1
ICC
L
H
L
L
ICC
Write
L
X
DIN
ICC
ꢀABSOLUTE MAXIMUM RATINGS(1) ꢀOPERATING RANGE
AMBIENT
TEMPERATURE
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
UNIT
RANGE
VCC
Terminal Voltage with
Respect to GND
-0.5 to VCC+0.5
V
0℃to 70℃
Commercial
1.5V ~ 3.6V
℃
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to 125
ꢀCAPACITANCE(1)(TA=25℃,f=1.0MHz)
℃
TSTG
-50 to 150
PARAMETER
PT
1
W
SYMBOL
CONDITIONS MAX.
UNIT
Input
IOUT
DC Output Current
20
mA
CIN
VIN=0V
VDQ
6
8
pF
Capacitance
Input/Output
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CDQ
pF
1. This parameter is guaranteed and not 100% tested.
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 2
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀDC ELECTRICAL CHARACTERISTICS (TA=0℃to 70℃)
Test Condition
Symbol
VIL
Comment
MIN.
TYP.(1)
MAX.
UNITS
V
Guaranteed Input Low
VCC=2.4V
-0.5
-
-
0.8
Voltage(2)
Guaranteed Input High
Voltage(2)
VIH
VCC=3.6V
2.0
Vcc-0.2
V
IL
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
VCC=3.6V VIN=0V to VCC
-
-
1
1
uA
uA
V
VCC=3.6V CE\=VIH or OE\=VIH
VIO=0V t VCC
IOL
-
-
VOL
VOH
ICC
VCC=3.6V, IOL=2mA
-
2.4
-
-
0.4
-
VCC=3.0V, IOH=-1mA
-
V
Operating Power Supply
Current
CE\=VIL,IDQ=0mA, F=Fmax(3)
CE\=VIH, VIN=VIH to VIL
-
35
1
mA
mA
uA
ISB1
ISB2
TTL Standby Current
-
-
CE\≧VCC-0.2V, VIN=VCC-0.2V
to 0.2V
CMOS Standby Current
-
2
10
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
ꢀDATA RETENTION CHARACTERISTICS ( TA=0℃to 70℃)
Symbol
Comment
Test Condition
MIN.
1.2
-
TYP.(1)
MAX.
UNITS
V
CE\≧VCC - 0.2V
VIN≧VCC-0.2V or VIN≦0.2V
CE\≧VCC - 0.2V
VIN≧VCC-0.2V or VIN≦0.2V
VCC to Data Retention
Data Retention Current
VDR
-
0.1
-
-
1
-
ICCDR
tDR
uA
ns
Chip Deselect to Data
Retention Time
0
See Retention Waveform
(2)
Operation Recovery Time
tR
TRC
-
-
ns
1. VCC = 1.5V, TA = 25℃.
2. tRC = Read Cycle Time
ꢀLOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled)
Data Retention Mode
VDR >= 1. 2V
Vcc
tCDR
VIH
tR
VIH
CE >= VCC - 0. 2V
CE
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 3
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀAC TEST CONDITIONS
ꢀKEY TO SWITCHING WAVEFORMS
Input Pulse Levels
VCC/0V
1V/ns
WAVEFORMS
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output Timing Reference Level
0.5VCC
MUST BE
STEADY
MUST BE
STEADY
ꢀAC TEST LOADS AND WAVEFORMS
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM H TO L
3.3V
3.3V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
WILL BE
CHANGE
FROM L TO H
MAY CHANGE
FROM L TO H
OUTPUT
OUTPUT
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
FIGURE 1A
FIGURE 1B
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
DOES NOT
APPLY
TERMINAL EQUIVALENT
667Ω
OUTPUT
1.73V
ALL INPUT PULSES
VCC
90% 90%
10%
10%
GND
FIGURE 2
1V/ns
1V/ns
ꢀAC ELECTRICAL CHARACTERISTICS (TA=0℃to 70℃, VCC=1.5V~3.6V)
READ CYCLE
JEDEC
PARAMETER
NAME
UC62LV4008-55
UC62LV4008-70
PARAMETER
NAME
DESCRIPTION
UNIT
Min
Typ
Max
Min
Typ
Max
tAVAX
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAXOX
tRC
tAA
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
-
-
-
-
-
-
-
-
-
-
55
55
30
-
-
-
-
-
-
-
-
-
-
-
70
70
35
-
tCE
Chip Select Access Time
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Address Chang to Output Change
-
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
10
5
10
5
-
-
0
20
20
-
0
20
20
-
0
0
10
10
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 4
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀSWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
ADDRESS
DOUT
tAA
tOH
tOH
READ CYCLE2 (1,3,4)
CE
tCE
(5)
(5)
tCLZ
tCHZ
DOUT
READ CYCLE3 (1,4)
tRC
ADDRESS
OE
tAA
tOH
(1,5)
tOE
tOHZ
tOLZ
CE
tCE
(5)
(5)
tCLZ
tCHZ
DOUT
NOTES:
1. WE\ is high in read cycle.
2. Device is continuously selected when CE\ = VIL
3. Address valid prior to or coincident with CE\ transition low.
4. OE\ = VIL.
5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 5
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀAC ELECTRICAL CHARACTERISTICS (TA=0℃to 70℃, VCC=1.5V~3.6V)
WRITE CYCLE
JEDEC
PARAMETER
NAME
UC62LV4008-55
UC62LV4008-70
PARAMETER
NAME
DESCRIPTION
UNIT
Min
Typ
Max
Min
Typ
Max
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tWC
tCW
tAS
Write Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to END of Write
Address Setup Time
40
0
-
-
-
-
-
-
-
-
-
-
-
-
50
0
-
-
-
-
-
-
-
-
-
-
-
-
tAW
tWP
tWR
tWHZ
tDW
tDH
Address valid to End of Write
Write Pulse Width
40
40
0
-
50
50
0
-
-
-
Write Recovery Time
-
-
Write to Output in High Z
Data to Write Time Overlap
Data Hold Time for Write End
Output Disable to Output In High Z
End of Write to Output Active
-
20
-
20
35
0
40
0
-
20
-
-
20
-
tOHZ
tOW
0
0
5
5
ꢀSWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1(1)
tWC
ADDRESS
OE
tAW
(11)
(2)
tCW
CE
tAS
(4,10)
tWP
WE
tOHZ
DOUT
tDW
tDH
DIN
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 6
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
WRITE CYCLE2(1,6)
tWC
ADDRESS
CE
tAW
(11)
(2)
tCW
tAS
tWP
WE
tWHZ
tOH
DOUT
(7)
(8)
tDW
tDH
DIN
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE\ going low to the end of write.
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 7
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀORDERING INFORMATION
UC62LV4008 AB -- YY
A => GRADE
C:COMMERCIAL; 0 ~ 70℃
I : INDUSTRIAL; -40 ~ 85℃
B => PACKAGE
H:TSOP(I)
F:SOP
G:STSOP
A:DICE
YY => SPEED
55: 55ns
70: 70ns
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 8
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
ꢀPACKAGE DIMENSIONS
Unit
Inch
mm
Symbol
0.0433±0.004
0.004±0.002
0.039±0.002
1.10±0.10
0.10±0.05
1.00±0.05
A
A1
A2
0.009±0.002
0.008±0.001
0.004~0.008
0.004~0.006
0.465±0.004
0.22±0.05
0.2±0.03
0.10~0.21
0.10~0.16
11.8±0.10
b
b1
c
c1
D
0.315±0.004
0.020±0.004
0.528±0.008
8.00±0.10
0.50±0.10
13.40±0.20
E
e
HD
0.0197+0.008
-0.004
0.5 +0.2
-0.1
L
0.0315±0.004
0.004 Max
0” ~ 8”
0.80±0.10
0.1 Max
0” ~ 8”
L1
y
θ
12°(2X)
12°(2X)
e
HD
1
32
SEATING PLANE "y"
12°(2X)
16
GAUGE PLANE
17
A
A
"A"
D
θ
0.254
12°(2X)
L
L1
"A" DETAIL VIEW
SEATING PLANE
1
32
b
W ITH PLATING
c1
BASE M ETAL
c
16
b1
17
SECTION A-A
32 - STSOP
ꢀ
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 9
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
Unit
Inch
mm
Symbol
A
A1
A2
b
0.0433±0.004
0.004±0.002
0.039±0.002
1.10±0.10
0.10±0.05
1.00±0.05
0.009±0.002
0.008±0.001
0.004~0.008
0.004~0.006
0.724±0.004
0.22±0.05
0.2±0.03
0.10~0.21
0.10~0.16
18.40±0.10
b1
c
c1
D
E
e
0.315±0.004
0.020±0.004
0.787±0.008
0.0197+0.008
-0.004
8.00±0.10
0.50±0.10
20.00±0.20
0.5 +0.2
-0.1
HD
L
L1
y
θ
0.0315±0.004
0.004 Max
0” ~ 8”
0.80±0.10
0.1 Max
0” ~ 8”
12°(2X)
12°(2X)
e
HD
1
32
SEATING PLANE "y"
12°(2X)
16
GAUGE PLANE
17
A
A
"A"
D
θ
0.254
12°(2X)
L
L1
"A" DETAIL VIEW
SEATING PLANE
1
32
b
WITH PLATING
c1
BASE METAL
c
16
b1
17
SECTION A-A
32 - TSOP
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 10
Low Power CMOS SRAM
512K X 8 Bits
UC62LV4008
-55/-70
Unit
Inch
mm
Symbol
A
A1
A2
b
0.111±0.007
0.009±0.005
0.1055±0.0055
2.821±0.176
0.229±0.127
2.680±0.140
0.014 ~ 0.020
0.014 ~ 0.018
0.006 ~ 0.012
0.006 ~ 0.011
0.805±0.005
0.35 ~ 0.50
0.35~0.46
0.15 ~ 0.32
0.15 ~ 0.28
20.447±0.127
b1
c
c1
D
E
E1
e
0.445±0.005
0.555±0.012
0.050±0.006
0.033±0.010
11.303±0.127
14.097±0.305
1.270±0.152
0.834±0.25
L
L1
y
θ
0.055±0.008
0.004 Max
0” ~ 10”
1.397±0.203
0.1 Max
0” ~ 10”
17
32
"A"
1
16
b
e
A
D
θ
A
L
10°(4X)
L1
DETAIL "A" (2:1)
b
WITH PLATING
c1
BASE METAL
Seating Plane "y"
c
b1
SOP - 32
SECTION A-A
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 11
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