UCC3911DPTR-3 [ETC]
Analog IC ; 模拟IC\n
| 型号： | UCC3911DPTR-3 |
| 厂家： | 
ETC |
| 描述： | Analog IC
|
| 文件： | 总11页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢁ ꢂ ꢃꢄꢄ ꢅꢄ ꢆ ꢀꢁꢁ ꢂꢃ ꢄꢄꢅ ꢇ
ꢀꢁꢁ ꢂ ꢃꢄꢄ ꢅꢂ ꢆ ꢀꢁ ꢁꢂ ꢃꢄꢄꢅ ꢈ
SLUS429A – AUGUST 2001
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FEATURES
DESCRIPTION
The UCC3911 is a two-cell lithium-ion (Li-Ion) and
lithium-polymer (Li-Pol) battery pack protector
device that incorporates an on-chip series FET
switch thus reducing manufacturing costs and
increasing reliability. The device’s primary
function is to protect both Li-Ion and Li-Pol cells in
a two-cell battery pack from being either
overcharged (overvoltage) or overdischarged
(undervoltage). It employs a precision bandgap
voltage reference that is used to detect when
either cell is approaching an overvoltage or
undervoltage state. When on-board logic detects
either condition, the series FET switch opens to
protect the cells.
D
Protects Sensitive Lithium-Ion and
Lithium-Polymer Cells from Overcharging
and Overdischarging
D
D
D
D
Used for Two-Cell Battery Packs
No External FETs Required
Provides Protection Against Battery Pack
Output Short Circuit
Extremely Low Power Drain on Batteries of
About 20 µA
D
Low Internal FET Switch Voltage Drop
D
User Controllable Delay for Tripping Short
Circuit Current Protector
D
3-A Current Capacity
A negative feedback loop controls the FET switch
when the battery pack is in either the overvoltage
or undervoltage state. In the overvoltage state the
action of the feedback loop is to allow only
discharge current to pass through the FET switch.
In the undervoltage state, only charging current is
allowed to flow. The operational amplifier that
drives the loop is powered only when in one of
these two states. In the undervoltage state the
chip enters sleep mode until it senses that the
pack is being charged.
APPLICATIONS
D
PDA, Camcorder, Digital Camera, Private
Mobile Radio
SIMPLIFIED APPLICATION DIAGRAM
UCC3911
B2 16
The FET switch is driven by a charge pump when
the battery pack is in a normally charged state to
1
2
3
4
5
6
7
8
NC
achieve the lowest possible R
. In this state
+
+
DS(on)
CDLY 15
B1 14
OV
UV
the negative feedback loop’s operational amplifier
is powered down to conserve battery power. Short
circuit protection for the battery pack is provided
and has a nominal delay of 100 µs before tripping.
An external capacitor may be connected between
CDLY and B0 to increase this delay time to allow
longer overcurrent transients.
ISOLATED
COPPER
PAD
ISOLATED
COPPER
PAD
SUBS SUBS 13
SUBS SUBS 12
GND
GND
B0 11
B0 10
A chip enable (CE) pin is provided that when held
low, inhibits normal operation of the device to
facilitate assembly of the battery pack.
LPWARN CE
9
UDG–01075
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Copyright 2001, Texas Instruments Incorporated
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1
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SLUS429A – AUGUST 2001
description (continued)
The UCC3911 is specified for operation over the temperature range of –20°C to 70°C, the typical operating and
storage temperature range of Li-Ion and Li-Pol batteries.
}w
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Maximum input voltage (B2, GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V
Minimum input voltage (B0, GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –9 V
Maximum charge current (B0, GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 A
Minimum discharge current (B0, GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 A
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
J
Storage temperature range T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
§
All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals.
AVAILABLE OPTIONS
PACKAGES
SOIC–16 (DW)
UCC3911DP–1
UCC3911DP–2
OVERVOLTAGE THRESHOLD
T
A
MIN
TYP
MAX
4.15
4.20
4.25
4.30
4.20
4.25
4.30
4.35
4.40
4.25
4.30
4.35
–20°C to 70 °C
UCC3911DP–3
UCC3911DP–4
†
The DP package is available taped and reeled. Add TR suffix to device type (e.g. UCC3911DPTR–1)
to order quantities of 3000 devices per reel.
DP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
OV
UV
B2
CDLY
B1
SUBS
SUBS
B0
SUBS
SUBS
GND
GND
LPWARN
B0
CE
2
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SLUS429A – AUGUST 2001
electrical characteristics –20°C < T = 70°C, all voltages are referenced to B0, V = 7.2 V, T = T
A
B2
A
J
(unless otherwise noted)
state transition threshold
PARAMETER
TEST CONDITIONS
MIN
4.15
TYP
4.20
MAX
UNITS
V
V
V
V
V
V
V
V
V
V
Overvoltage threshold
4.25
3.80
4.30
3.85
4.35
3.90
4.40
3.95
2.58
3.10
OV
UCC3911–1
Overvoltage threshold recovery
Overvoltage threshold
3.60
4.20
3.65
4.25
3.70
4.30
3.75
2.42
2.90
3.70
4.25
3.75
4.30
3.80
4.35
3.85
2.50
3.00
OVR
OV
UCC3911–2
UCC3911–3
UCC3911–4
Overvoltage threshold recovery
Overvoltage threshold
OVR
OV
V
Overvoltage threshold recovery
Overvoltage threshold
OVR
OV
Overvoltage threshold recovery
Undervoltage threshold
OVR
UV
Undervoltage threshold recovery
UVR
B0-to-GND switch
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
(Normal) I
(Normal) I
= 2 A
–320
–160
160
GND
= –2 A
320
GND
(Overcharge) I
(Overcharge) I
= 1 mA
–300
–500
–150
–250
150
GND
V
to V
GND
mV
B0
= 2 A
GND
(Undercharge) I
= –1 mA
= –2 A
300
500
GND
GND
GND
(Undercharge) I
250
(Overcharge) V
= –5 V
–5
I
µA
GND
(Undercharge) V
GND
= 5 V
0
30
input bias current
PARAMETER
TEST CONDITIONS
MIN
TYP
18
MAX
UNITS
Nominal
25
I
I
B2
In sleep mode
3.5
0
µA
–1
1
B1
short circuit protection
PARAMETER
TEST CONDITIONS
MIN
TYP
5.25
100
MAX
UNITS
A
I
t
Current threshold
Delay time
3.5
7
SC
CDLY = OPEN,
See Note 1
µs
DLY
timing delays
PARAMETER
TEST CONDITIONS
MIN
TYP
7.5
2.0
1.0
MAX
UNITS
F
Internal clock frequency
See Note 2
kHz
INTERNAL
t
t
– OV Delay time to register overcharge
– UV Delay time to register undercharge
0.6
0.3
5.0
3.5
DLY
ms
DLY
3
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SLUS429A – AUGUST 2001
electrical characteristics –20°C < T = 70°C, all voltages are referenced to B0, V = 7.2 V, T = T
A
B2
A
J
(unless otherwise noted) (continued)
drives
PARAMETER
TEST CONDITIONS
= –100 µA
MIN
TYP
0.15
MAX
UNITS
V
–V
I
I
I
I
0.89
0.75
0.75
0.75
B2 HIGH
PIN
OV and UV output
LPWARN output
V
V
= 100 µA
0.05
0.05
0.04
LOW
–V
PIN
V
= –0.1 mA
B2 HIGH
LPWARN
LPWARN
V
V
LOW
= 0.1 mA
other thresholds
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7
UNITS
V
V
= 8.5 V
= 5 V,
5
6
2.45
165
B2
V
CE
Chip enable threshold voltage
Thermal shutdown
V
See Note 3
2.05
4.05
B2
T
SD
See Note 1
°C
NOTE: 1. Ensured by design. Not production tested.
NOTE: 2. Tested at functional probe only.
NOTE: 3. V is the voltage at the B2 pin relative to the B0 pin.
B2
Terminal Functions
TERMINAL
PACKAGE
NAME
I/O
DESCRIPTION
DP
10, 11
14
B0
B1
I
I
Connects to the negative teminal of the lower cell in the battery pack.
Connects to the junction of the positive terminal of the lower cell and the negative terminal of the upper
cell in the battery pack.
B2
16
I
Connects to the positive terminal of the upper cell in the battery pack. This pin also connects to the
positive of the two terminals that are presented to the user of the battery pack.
CDLY
CE
15
9
I
Delay control pin for the short circuit protection feature.
O
Chip enable. The internal FET is disabled when CE is connected to B0. With the CE pin connected to
B0, the supply current drain is only about 4 µA.
GND
6,7
–
The second of two terminals that are presented to the user of the battery pack. The internal FET switch
connects this terminal to the B0 terminal to give the battery pack user appropriate access to the batter-
ies. In an overcharged state, current is allowed to flow only into this terminal. Similarly, in an over-dis-
charged state, current is allowed to flow only out of this terminal.
LPWARN
OV
8
2
O
O
This active–high signal is the low Power Warning. The voltage on this pin goes high (to B2 potential) as
soon as either of the battery’s cells voltage falls below 3.0 V. Once the UV state is entered, this output
goes back to low.
This active–low signal indicates the state of the state machine’s OV bit. When low, it indicates that one
or both cells are overvoltage. Further charging is inhibited by the opening of the FET switch. The out-
put buffer for this pin is sized to drive a very light load.
SUBS
UV
4,5,12,13
3
I
The substrate connections connect these points to a heat sink which is electrically isolated from all
other device pins.
O
This active–low signal indicates the state of the state machine’s undervoltage bit. When low, it indi-
cates that one or both cells are under voltage. Further discharging is inhibited by the opening of the
FET switch.
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SLUS429A – AUGUST 2001
detailed pin descriptions
CDLY: Delay control pin for the short circuit protection feature. A capacitor connected between this pin and the
B0 pin lengthens the time delay from when an overcurrent situation is detected to when the protection circuitry
is activated. This control will be useful for those applications where high-peak load currents may momentarily
exceed the protection circuit’s threshold current and interruption of the battery current is undesirable. The
nominal delay time is internally set at 100 µs. The equation for determining this delay is:
(
) ( )
ms + 25 ) 25 ) CDLY (pF) 0.4 V
B2
t
(1)
DLY
To recover from an overcurrent shutdown the load must be removed momentarily from the pack.
CE: While the chip enable signal is held low, the internal FET is held off. CE is pulled high by a 2-µA current
source. This function was included to facilitate construction of the battery pack. The last step in the electrical
assembly of the pack is to cut a link grounding B0. With the CE pin connected to B0, the supply current drain
is only about 4 µA.
GND: The second of the two terminals that are presented to the user of the battery pack. The internal FET switch
connects this terminal to the B0 terminal to give the battery pack user appropriate access to the cells. In an
overvoltage state, current is allowed to flow only into this terminal. Similarly, in an undervoltage state, current
is allowed to flow only out of this terminal.
OV: This active-low signal indicates the state of the state machine’s overvoltage bit. When low, it indicates that
one or both cells are overvoltage. Further charging is inhibited by the opening of the FET switch. The output
buffer for this pin is sized to drive a very light load.
UV: This active-low signal indicates the state of the state machine’s undervoltage bit. When low, it indicates that
one or both cells are undervoltage. Further discharging is inhibited by the opening of the FET switch. The chip
enters the sleep mode when UV goes low and waits in this state until the device detects that the battery pack
has been placed in a charging circuit. The output buffer for this pin is sized to drive a very light load.
5
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SLUS429A – AUGUST 2001
functional block diagram
B2 16
B1 14
8
3
2
LPWARN
UV
REFERENCE
VOLTAGE
SELECT
AND
COMPARE
CELL
VOLTAGE
INPUT
STATE
MACHINE
B0 10
B0 11
SELECT
OV
4
9
1
CE
NC
CLOCK
REFERENCE
AND
THERMAL
SHUTDOWN
TS
CE
S
R
Q
SCP
CDLY 15
CLOCK
R
SHORT CIRCUIT
PROTECTION
SENSE
CHARGE
PUMP
UV
OV
EN
GND
GND
6
7
4
5
CE
SCP
OV
UV
UV
OV
ENABLE
LOGIC
OV
UV
SUBS
SUBS
+
SUBS 12
SUBS 13
100 mV
TS
SLP
SLEEP
MODE
CONTROLLER
CLOCK
UV
50 mV
UDG–99173
6
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SLUS429A – AUGUST 2001
APPLICATION INFORMATION
Figure 1 shows a typical application for the UCC3911 Li-Ion and Li-Pol battery protector. All of the functions
required to protect two series cells from overvoltage and undervoltage conditions, as well as provide short circuit
protection for the complete battery pack, are included in a single chip. An internal state machine controls an
internal power FET which allows either bi-directional or uni-directional battery current. An optional time delay
capacitor can be included to slow the reaction time of the short circuit protection circuitry if desired.
While the device is capable of providing overload and over/undervoltage protection of both cells with virtually
no external parts, the demands of true short circuit protection require some passive external components.
Ω
UCC3911
R1 220
B2 16
1
2
3
4
5
6
7
8
NC
µ
C1 10
10 V
F
C
330 pF
DLY
+
+
CELL 2
CELL 1
µ
C3 0.1
25 V
F
CDLY
15
OV
UV
R2 10 kΩ
C4
B1 14
(OPTIONAL)
SUBS
SUBS
GND
SUBS
SUBS
13
12
ISOLATED COPPER PAD
FOR HEAT SINKING AT
HIGH LOAD CURRENTS
ISOLATED COPPER PAD
FOR HEAT SINKING AT
HIGH LOAD CURRENTS
C2
0.22
µ
F
B0 11
B0 10
GND
J1
LPWARN
CE
9
ENABLE (OPEN)
UDG–99173
Figure 1. Application Circuit Including Components for Short-Circuit Protection
state machine operation
The internal state machine constantly monitors the two cells for both overvoltage and undervoltage conditions.
Figure 2 shows a state diagram which describes the operation of the protection circuitry for the UCC3911–2
version. In the normal mode, both the external overvoltage and undervoltage status bits are held high and full
battery current is allowed through the internal power FET in either the charge or discharge direction.
If the voltage across one or both cells exceeds the overvoltage (V ) threshold, the external overvoltage signal
OV
goes low, and further charge current is not allowed. An internal feedback loop controls the power FET to allow
only discharge current, allowing for battery recovery. The state machine will not reenter normal mode until the
voltage across both cells decays to less than the overvoltage recovery (V
important to prevent circuit oscillation due to battery ESR when the circuitry transitions between states.
) threshold. This feature is
OVR
If the voltage across one or both battery cells falls below 3 V, the LPWARN signal goes high indicating a low
power condition. This signal can be used to signal the user that the battery pack is in need of charge.
If the voltage across one or both cells falls below 2.5 V, the UV signal goes low, and the feedback loop allows
only charge current. The LPWARN signal goes low and the UCC3911 enters sleep mode which consumes only
3 µA, limiting self discharge to a minimum. The circuit remains in this state until the voltage across both cells
exceeds 3 V. The battery pack can still be charged, unless the sum of the two cells voltages falls below 3.7 V,
which is the minimum guaranteed operating voltage for the device.
7
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SLUS429A – AUGUST 2001
APPLICATION INFORMATION
If the battery cells become so poorly matched that the voltage across one cell exceeds 4.25 V and the voltage
across the other cell falls below 2.5 V, the power FET does not pass either charge or discharge current, and
both the OV and UV signals will be set low.
The normal high current path for battery current is through the B0 (10, 11) and GND (6, 7) pins of the UCC3911.
The GND pins are intended to be connected to system ground for either the charger or the load. The SUBS pins
(4, 5, 12, 13) are internally connected to the substrate of the UCC3911, which is internally referenced to B0 or
GND depending on the direction of pack current. If high battery currents are anticipated, the SUBS pins can be
thermally connected to a heat sink to control the device temperature. However, this heat sink must be electrically
isolated from all other device pins including ground. This is a critically important point, as heat sinking to the
system ground is not possible.
The CE pin is used to initialize the state of the battery pack during assembly. Holding this pin low forces the state
machine to hold the FET off. The last step in the assembly process would be to cut the trace between this pin
and B0 which allows the internal pull up to start the state machine. While CE is low, the device’s current
consumption is approximately 4 µA. This is a useful feature for battery packs that may experience a long period
of storage while waiting to be sold.
The one cell over and one cell under state (see Figure 2) is entered whenever one cell is overcharged and the
other cell is simultaneously overdischarged. When in this state, the series FET switch is turned off inhibiting both
charging and discharging of the battery pack. If the battery pack ever gets into this condition, it should be
discarded.
short-circuit protection
The demands of true short-circuit protection require that careful attention be paid to the selection of a few
external components.
In the application circuit shown in Figure 1, C3 protects the battery pack output terminals from inductive kick
when the pack current is shut off due to an overcurrent or overvoltage/undervoltage condition. (It also increases
the ESD protection level.)
To prevent a momentary cell voltage drop, caused by large capacitive loads, from causing an erroneous
undervoltage shutdown, an RC filter is required in series with the two battery sense inputs, B1 and B2. The
resistors (R1 and R2) are sized to have a negligible impact on voltage sensing accuracy. The capacitors (C1
and C2) should be sized to provide a time constant longer than the overcurrent delay time. In the example of
Figure 1, they are sized for a nominal 2.2 ms time constant. They do not need to be low ESR style capacitors,
as they see no ripple current. A larger resistor value and smaller capacitor value can be used on the B1 input
due to the extremely low input current on this pin.
The overcurrent delay capacitor, CDLY, sets the time delay, after the overcurrent threshold is exceeded, before
turning off the UCC3911’s internal FET. If no capacitor is used, the nominal delay is 100 µs. To charge large
capacitive loads without tripping the overcurrent circuit, a small capacitor (typically less than 1000 pF) is used
to extend the delay time. The approximate delay time is given below and shown graphically in Figure 3.
(
) ( )
ms + 25 ) 25 ) CDLY(pF) 0.4 V
B2
t
(2)
DLY
8
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ꢀꢁꢁ ꢂ ꢃꢄꢄ ꢅꢄ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄꢅ ꢇ
ꢀꢁꢁ ꢂ ꢃꢄꢄ ꢅꢂ ꢆ ꢀꢁ ꢁꢂ ꢃꢄꢄꢅ ꢈ
SLUS429A – AUGUST 2001
APPLICATION INFORMATION
UCC3911–2 STATE DIAGRAM
NOMINAL OVERCURRENT DELAY TIME
vs
DELAY CAPACITANCE AND B2 VOLTAGE
3500
3000
2500
2000
1500
1000
500
V
B2
= 7
V
B2
= 8
V
B2
= 5
V
B2
= 6
0
0
200
400
600
800
1000
Delay Capacitance (pF)
Figure 2
Figure 3
The amount of time required will be a function of the load capacitance, battery voltage, and the total circuit
impedance, including the internal resistance of the cells, the UCC3911’s on resistance, and the load capacitor
ESR. The required delay time can be calculated from:
ǒI RǓ
V
t + * R C ln
(3)
In this equation, R is the total circuit resistance, C is the capacitor being charged, I is the overcurrent trip current
(5.25 A nominal), and V is the battery voltage. Using the minimum trip current of 3.5 A and the maximum battery
voltage of 8.4 V, the worst case maximum delay time required is defined as:
ǒ R Ǔ
(ms) + * R C (mF) ln
t
MAX
2.4
(4)
In the example of Figure 1, CDLY, C1 and C2 are sized to drive a 1500-µF load capacitor.
If large capacitive loads (or other loads with surge currents above the overcurrent trip threshold) are not being
applied to the pack terminals, the overcurrent delay time can be short. In this case, it may be possible to eliminate
CDLY, as well as R2 and C2 altogether (replacing R2 with a short). In addition, the time constant of R1 and C1
can be made much shorter. R1 and C2 are still necessary, however, to assure proper operation under short
circuit conditions. It is important to maintain a minimum R1/C1 time constant of 100 µs. (For example, R1 and
C1 could be reduced to 100 Ω and 1 µF.)
Capacitor C4 is recommended, in case the wires connecting to the top and bottom of the cell stack are more
than an inch long (not likely in a small battery pack). In this case, a 10-µF, low ESR capacitor is recommended
to prevent excessive overshoot at turn-off due to wiring inductance.
9
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ꢀ ꢁꢁꢂ ꢃ ꢄꢄ ꢅꢄ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄꢄ ꢅꢇ
ꢀ ꢁꢁꢂ ꢃ ꢄꢄ ꢅꢂ ꢆ ꢀ ꢁꢁ ꢂ ꢃꢄꢄ ꢅꢈ
SLUS429A – AUGUST 2001
PLASTIC SMALL-OUTLINE PACKAGE (DP)
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/D 01/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
10
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