UCC3941J-ADJ [ETC]
Analog IC ; 模拟IC\n
| 型号： | UCC3941J-ADJ |
| 厂家： | 
ETC |
| 描述： | Analog IC
|
| 文件： | 总11页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
available
1V Synchronous Boost Converter
FEATURES
DESCRIPTION
• 1V Input Voltage Operation Startup
Guaranteed Under Full Load on Main
Output With Operation Down to 0.4V
The UCC3941 family of low input voltage single inductor boost converters
are optimized to operate from a single or dual alkaline cell, and step up to
a 3.3V, 5V, or an adjustable output at 500mW. The UCC3941 family also
provides an auxiliary 9V 100mW output, primarily for the gate drive supply,
which can be used for applications requiring an auxiliary output such as a
5V supply by linear regulating. The primary output will start up under full
load at input voltages typically as low as 0.8V, with a guaranteed maximum
of 1V, and will operate down to 0.4V once the converter is operating, maxi-
mizing battery utilization.
• Input Voltage Range of 1V to VOUT
+
0.5V
• 500mW Output Power at Battery
Voltages as Low as 0.8V
• Secondary 9V Supply From a Single
Inductor
Demanding applications such as Pagers and PDA’s require high efficiency
from several milli-watts to several hundred milli-watts, and the UCC3941
family accommodates these applications with >80% typical efficiencies
over the wide range of operation. The high efficiency at low output current
is achieved by optimizing switching and conduction losses along with low
quiescent current. At higher output current the 0.25Ω switch, and 0.4Ω syn-
chronous rectifier, along with continuous mode conduction, provide high ef-
ficiency. The wide input voltage range on the UCC3941 family can
accommodate other power sources such as NiCd and NiMH.
• Adjustable Output Power Limit Control
• Output Fully Disconnected in
Shutdown
• Adaptive Current Mode Control for
Optimum Efficiency
• 8µA Shutdown Supply Current
Other features include maximum power control and shutdown control.
Packages available are the 8-pin SOIC (D) and 8-pin DIP (N or J).
SIMPLIFIED BLOCK DIAGRAM AND APPLICATION CIRCUIT
+
10µF
0.8V TO VOUT +0.5V
22µH
VIN
3
SW
UCC3941-3 = 3.3V
UCC3941-5 = 5.0V
UCC3941-ADJ = 1.30V TO 6V
VOUT
8
8V
VGD
0.4Ω
STARTUP
2
1
CIRCUITRY
10µF
0.25Ω
100µF
MODULATOR CONTROL CIRCUIT
SYNCHRONOUS RECTIFICATION CIRCUITRY
ANTI-CROSS CONDUCTION
STARTUP
MULTIPLEXING LOGIC
MAXIMUM INPUT POWER CONTROL
ADAPTIVE CURRENT CONTROL
PLIM
5
SD
4
*SGND/FB
6
OPEN=SD
UCC3941-ADJ
1.25V
–
+
PGND
7
*FOR UCC3941-ADJ ONLY:
PIN 7 = SGND & PGND, PIN 6 = OUTPUT SENSE FEEDBACK, FB.
UDG-98147
SLUS242 - JULY 1999
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
DIL-8, SOIC-8 (Top View)
N or J Package, D Package
VIN Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V
SD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VIN
PLIM Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V
VGD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V
SW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V
VOUT Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
Pin 6 is FB for UCC3941-ADJ.
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, for UCC3941, TA = 0°C to 70°C; for UCC2941, TA = –40°C
to 85°C; VIN = 1.25V, TA = TJ.
PARAMETER
VIN Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Minimum Startup Voltage
Minimum Start Voltage
No External VGD Load, TJ = 25°C, IOUT = 100mA (Note 1)
0.8
0.9
1.0
1.1
V
V
No External VGD Load, IOUT = 100mA, TJ = 0°C to 85°C
(Note 1)
Minimum Startup Voltage
Minimum Dropout Voltage
No External VGD Load, TJ = –40°C to 0°C
0.9
1.5
0.5
V
V
No External VGD Load, IOUT = 100mA, VGD = 6.3V
(Note 1)
Input Voltage Range
1
VOUT
+0.5
V
Quiescent Supply Current
Supply Current at Shutdown
Output Section
(Note 2)
13
8
25
20
µA
µA
SD = Open
Quiescent Supply Current
Supply Current at Shutdown
(Note 2)
32
6
80
15
µA
µA
V
SD = Open
Regulation Voltage (UCC3941-3) 1V < VIN < 3V
1V < VIN < 3V, 0mA < IOUT < 150mA (Note 1)
Regulation Voltage (UCC3941-5) 1V < VIN < 5V
1V < VIN < 5V, 0mA < IOUT 100mA (Note 1)
1V < VIN < 3V
3.18
3.17
4.85
4.8
3.25
3.30
5.00
5.0
3.37
3.43
5.15
5.2
V
V
V
FB Voltage (UCC3941-ADJ)
VGD Output Section
1.212 1.250 1.288
V
Quiescent Supply Current
Supply Current at Shutdown
Regulation Voltage
(Note 2)
25
8
60
20
µA
µA
V
SD = Open
1V < VIN < 3V
7.5
7.4
8.7
8.7
9.2
9.3
1V < VIN < 3V, 0mA < IOUT < 10mA (Note 1)
V
Inductor Charging Section (L = 22µH)
Peak Discontinuous Current
Over Operating Range
0.50
0.8
0.85
1.1
A
A
A
Peak Continuous Current
RPLIM = 6.2Ω, UCC3941-3 and UCC3941-5
UCC3941-ADJ
0.5
0.6
0.9
1.3
2
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, for UCC3941, TA = 0°C to 70°C; for UCC2941, TA = –40°C
to 85°C; VIN = 1.25V, TA = TJ.
PARAMETER
Inductor Charging Section
Charge Switch RDS(on)
Current Limit Delay
TEST CONDITIONS
MIN
TYP
MAX UNITS
N and D Package, I = 200mA
0.25
50
0.4
Ω
(Note 1)
ns
Synchronous Rectifier Section
Rectifier RDS(on)
N and D Package, I = 200mA, UCC3941-ADJ VOUT = 3.3V
and UCC3941–3
0.35
0.5
0.6
0.8
Ω
Ω
N and D Package, I = 200mA, UCC3941-5
Shutdown Section
Shutdown Bias Current
–10
–7
µA
Note 1: Performance from application circuit shown in Figures 3 - 5 guaranteed by design and alternate testing methods, but not
100% tested as shown in production.
Note 2: For the UCC3941-3, VOUT = 3.47V and VGD = 9.3V. For the UCC3941-5, VOUT = 5.25V, VGD = 9.3V. For the UCC3941-
ADJ, FB = 1.315V, VGD = 9.3V.
PIN DESCRIPTIONS
FB: Feedback control pin used in the UCC3941-ADJ SGND: Signal ground of the IC. For the UCC3941-ADJ
version only. The internal reference for this comparator is signal ground and power ground lines are tied to a
1.25V and external resistors provide the gain to the common pin.
output voltage.
SW: An inductor is connected between this node and
PGND: Power ground of the IC. The inductor charging VIN. The VGD (Gate Drive Supply) flyback diode is also
current flows through this pin. For the UCC3941-ADJ connected to this pin. When servicing the 3.3V supply,
signal ground and power ground lines are tied to a this pin will go low charging the inductor, then shut off,
common pin.
dumping the energy through the synchronous rectifier to
the output. When servicing the VGD supply, the internal
synchronous rectifier stays off, and the energy is diverted
to VGD through the flyback diode. During discontinuous
portions of the inductor current a MOSFET resistively
connects VIN to SW damping excess circulating energy
to eliminate undesired high frequency ringing.
PLIM: This pin is programmed to set the maximum input
power for the converter. For example a 1A current limit at
1V would have a 333mA limit at 3V input keeping the
input power constant at 1W. The peak current at VIN =
1V is programmed to 1.5A (1.5W) when this pin is
grounded. The power limit is given by:
VGD: The VGD pin which is coarsely regulated around
9V and is primarily used for the gate drive supply for the
power switches in the IC. This pin can be loaded with up
11.8 • n
PL(W)
=
+VIN (0.26)
RPL +6.7
where RPL is equal to the external resistor from the PLIM to 10mA as long as it does not present a load at voltages
pin to ground and n is the expected efficiency of the below 2V. This ensures proper startup of the IC. The
converter. The peak current limit is given by:
VGD supply can go as low as 7.5V without interfering
with the servicing of the 3.3V output. Below 7.5V, VGD
will have the highest priority, although practically the
voltage should not decay to that level if the output
capacitor is sized properly.
11.8 • n
IPK
=
+0.26
(A)
VIN • R +6.7
(
)
PL
Constant power gives several advantages over constant
current such as lower output ripple.
VIN: Input voltage to supply the IC during startup. After
the output is running the IC draws power from VOUT or
VGD.
SD: When this pin is open, the built in 7µA current source
pulls up on the pin and programs the IC to go into
shutdown mode. This pin requires an open circuit for
shutdown and will not operate correctly when driven to a
logic level high with TTL or CMOS logic. When this pin is
connected to ground, (either directly or with a transistor)
the IC is enabled and both output voltages will regulate.
VOUT: Main output voltage (3.3V, 5V or adjustable)
which has highest priority in the multiplexing scheme, as
long as VGD is above the critical level of 7.5V. Loads
over 150mA are achievable at 1V input voltage. This
output will startup with 1V input at full load.
3
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION
A detailed block diagram of the UCC3941 is shown in waveforms for the application circuit shown in Fig. 3. A
Fig. 1. Unique control circuitry provides high efficiency
power conversion for both light and heavy loads by tran-
sitioning between discontinuous and continuous conduc-
tion based on load conditions. Fig. 2 depicts converter
single 22µH inductor provides the energy pulses required
for a highly efficient 3.3V converter at up to 500mW out-
put power.
VIN
3
SW
8
ANTI-RINGING
SWITCH
VOUT
1
VGD ZERO
DETECT
VOUT ZERO
DETECT
200kHz
STARTUP
OSCILATOR
AND CONTROL
VGD
VGD
2
VGD
+
–
–
+
1.7µS
OFF TIME
CONTROLLER
+
–
5V
VGD
FROM
SD
RECTIFIER
CONTROL
FROM SD
1.4A
MAX
5Ω
PLIM
5
CLK
CURRENT
LIMIT
D
Q
L1
+
–
50mV
MAXIMUM
R
Q
VSAT
SD
VIN
ON TIME
CONTROLLER
11µSEC
50mV
VIN
SD
4
SD
BOOST
LATCH
T
=
ON
VIN
FB FOR
UCC3941-ADJ
ONLY
6
–
+
*
Q
R
–
+
VGD
VGD
SD
SGND FOR
UCC3941-3/-5
6
7
**
***
THERMAL
SHUTDOWN
–
+
PGND
* 3.3V FOR UCC3941-3
5.0V FOR UCC3941-5
1.25V FOR UCC3941-ADJ
** 8.7V FOR UCC3941-3
9.6V FOR UCC3941-5/-ADJ
*** 7.7V FOR UCC3941-3
8.8V FOR UCC3941-5/-ADJ
UDG-98146
Note: Switches are shown in the logic low state.
Figure 1. 1V Synchronous boost.
4
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION (cont.)
UDG-96117
Figure 2. Inductor current and output ripple waveforms.
At time t1, the 3.3V output drops below its lower thresh- Time t6, represents a transition between light and heavy
old, and the inductor is charged with an on time deter- load. A single energy pulse is not sufficient to force the
mined by:
output voltage above its upper threshold before the mini-
mum off time has expired, and a second charge cycle is
commanded. Since the inductor current does not reach
zero in this case, the peak current is greater than 0.5A at
the end of the next charge on time. The result is a
ratcheting of inductor current until either the output volt-
age is satisfied, or the converter reaches its programmed
current limit. At time t7, the gate drive voltage has
dropped below its threshold but the converter continues
to service the output because it has highest priority, un-
less VGD drops below 7.5V.
12µ s
TON
=
VIN
For a 1.25V input, and a 22µH inductor, the resulting
peak current is approximately 500mA. At time t2, the in-
ductor begins to discharge with a minimum off time of
1.7µs. Under lightly loaded conditions, the amount of en-
ergy delivered in this single pulse would satisfy the volt-
age control loop, and the converter would not command
any more energy pulses until the output again drops be-
low the lower voltage threshold.
Between t7 and t8, the converter reaches its peak current
limit which is determined by RPL and VIN. Once the limit
is reached, the converter operates in continuous mode
with approximately 200mA of ripple current. At time t8,
the output voltage is satisfied, and the converter can ser-
vice VGD, which occurs at t9.
At time t3, the VGD supply has dropped below its lower
threshold, but the output voltage is still above its thresh-
old point. This results in an energy pulse to the gate drive
supply at t4. However, while the gate drive is being serv-
iced, the output voltage has dropped below its lower
threshold, so the state machine commands an energy
pulse to the output as soon as the gate drive pulse is
completed.
5
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION (cont.)
Programming the Power Limit
delivered to the load will be less than the peak current
set by the power limit function due to current ripple. How-
ever, if the ripple component of the current is kept low,
the power limit equation can be used as an adequate es-
timate of input power. Furthermore, since an initial effi-
ciency estimate was required, sufficient margin can be
built into this estimate to insure proper converter opera-
tion. The 6.2Ω external power limit resister in Fig. 3-5 will
result in approximately 700mW of power capability with a
The UCC3941 incorporates an adaptive power limit con-
trol which modifies the converter current limit as a func-
tion of input voltage. In order to program the function, the
user simply determines the output power requirements
and makes an initial converter efficiency estimate. The
programming resistor is chosen by:
11.8 • n
RPL
=
– 6.7
POUT – 0.26 • n • VBAT
1V TO 5.5V
+
Where n is the initial efficiency estimate. For 500mW of
output power, with a 1.0V input, and an efficiency esti-
mate of 0.75:
DT3316P-223
22µH
10µF
MMSZ5240BT1
11.8 0.75
(
)
3
8
RPL
=
– 6.7 = 22Ω
VIN
SW
0.5 – 0.26 0.75 1.0
(
)( )
5.0V AT 500mW
8V
2
4
VGD
VOUT
1
For decreasing values of RPL, the power limit increases.
Therefore, to insure that the converter can supply
500mW of output power, a power limiting resistor of less
than 22Ω must be chosen.
10SN100M
100µF
10µF
UCC3941-5
PLIM
ADJ
5
6
7
SD
11.8
PL =VBAT • IL =
+1.0 0.26 =0.67W
(
)
R
6.2Ω
WCR0805-6R207
PL
22 +6.7
OPEN =
SD
This power limiting setting will support 0.5W of output
power. It should be noted that the power limit equation
contains an approximation which results in slightly less
actual input power than the equation predicts. This dis-
PGND
UDG-98159
crepancy results from the fact that the average current Figure 4. Dual output synchronous boost 5V version.
1V TO VOUT + 0.5V
1V TO 3.5V
+
+
DT3316P-223
22µH
DT3316P-223
22µH
10µF
MMSZ5240BT1
10µF
MMSZ5240BT1
3
8
R1
R2
VOUT=1.25(1+
3.3V AT 500mW
)
3
8
VIN
SW
VIN
SW
3.3V AT 500mW
10V
2
4
VGD
VOUT
1
8V
10SN100M
2
4
VGD
VOUT
1
5
100µF
10SN100M
100µF
10µF
UCC3941-3
R1
R2
10µF
UCC3941-3
SD
SGND
PLIM
6
5
PLIM
SD
R
PL
OPEN =
SD
R
6.2Ω
WCR0805-6R207
PL
6.2Ω
OPEN =
SD
WCR0805-6R207
SGND
PGND
6
7
PGND
7
UDG-98163
UDG-98164
Figure 5. Dual output synchronous boost ADJ
version.
Figure 3. Dual output synchronous boost 3.3V
version.
6
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION (cont.)
1.0V input.
2
I
• L
(CL )
∆V =
+ICL • CESR where
Inductor Section
2• C • V −V
(
)
O
I
An inductor value of 22µH will work well in most applica-
tions, but values between 10µH and 100µH are also ac-
ceptable. Lower value inductors typically offer lower ESR
and smaller physical size. Due to the nature of the
“bang-bang” controllers, larger inductor values will typi-
cally result in larger overall voltage ripple, because once
the output voltage level is satisfied the converter goes
discontinuous, resulting in the residual energy of inductor
causing overshoot.
Power Limit
VIN
ICL = the peak inductor current ICL
=
∆V = output ripple
VO = output voltage
VI = input voltage
CESR = ESR of the output capacitor
A Sanyo OS-CON series surface mount capacitor
(10SN100M) is one recommendation. This part has an
ESR rating of 90mΩ at 100µF. Other potential capacitor
sources are shown in Table 2.
It is recommended to keep the ESR of the inductor below
0.15Ω for 500mW applications. A Coilcraft DT3316P-223
surface mount inductor is one choice since it has a cur-
rent rating of 1.5A and an ESR of 84mΩ. Other choices
Table 2. Capacitor Suppliers
MANUFACTURER
PART NUMBER
Table 1. Inductor Suppliers
Sanyo Video
Components
MANUFACTURER
Coilcraft
PART NUMBERS
San Diego, California
Tel: 619-661-6322
Fax: 619-661-1055
AVX
OS-CON Series
Cary, Illinois
DT Series
Tel: 708-639-2361
Fax: 708-639-1469
Coiltronics
Sanford, Maine
TPS Series
695D Series
Tel: 207-282-5111
Fax: 207-283-1941
Sprague
Boca Raton, Florida
Tel: 407-241-7876
CTX Series
Concord, New Hampshire
Tel: 603-224-1961
for surface mount inductors are shown in Table 1.
Output Capacitor Selection
Input Capacitor Selection
Once the inductor value is selected the capacitor value
will determine the ripple of the converter. The worst case
peak to peak ripple of a cycle is determined by two com-
ponents, one is due to the charge storage characteristic,
and the other is the ESR of the capacitor. The worst case
ripple occurs when the inductor is operating at maximum
current and is expressed as follows:
Since the UCC3941 family does not require a large de-
coupling capacitor on the input voltage to operate prop-
erly, a 10µF capacitor is sufficient for most applications.
Optimum efficiency will occur when the capacitor value is
large enough to decouple the source impedance. This
usually occurs for capacitor values in excess of 100µF.
7
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
VIN = 1V
VIN = 1.25V
VIN = 1.5V
VIN= 2V VIN= 2.5V VIN= 3V
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.1
1
10
100
0.1
1
10
100
IOUT (mA)
IOUT (mA)
Figure 6. UCC3941 Efficiency vs. IOUT, VOUT = 3.3V.
Figure 7. UCC3941 Efficiency vs. IOUT, VOUT = 3.3V.
T0:
T1:
T2:
T3:
T4:
200kHz startup oscillator starts VGD rising.
VGD gets to a sufficient voltage (5V) to run IC in normal operating mode.
VGD has reached a sufficient voltage (7.5V) to get VOUT started.
VOUT is serviced and starting up.
VOUT has reached a sufficient voltage and VGD is serviced until it reaches = 8.5V.
Figure 8. Startup characteristics.
8
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION (cont.)
T1:
T2:
T3:
T4:
T5:
VOUT is service and inductor current goes continuous.
VGD is serviced with discontinuous operation and reaches 1st threshold (7.5V).
VOUT requires servicing so since VGD has at least reached its first threshold of 7.5V the VOUT has priority.
VOUT is satisfied and VGD is serviced until 2nd threshold is reached.
Both outputs are satisfied.
Figure 9. Dual output example.
VOUT RIPPLE
20mV/DIV
IINDUCTOR CURRENT
0.2A/DIV
L = 22 H
C = 100 F
20 s/DIV
R
PL = 6
VIN = 1.25
OUT = 100mA
CVGD = 22 H
I
Figure 10. Pseudo continuous mode operation.
9
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UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION (cont.)
1.2
1.1
1
1.2
1.16
1.12
1.08
1.04
1
0.96
0.92
0.88
0.84
0.8
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
50
100
150
0
50
100
150
IOUT (mA)
IOUT (mA)
Figure 11. UCC3941-3 Dropout vs. IOUT
.
Figure 12. Minimum start voltage vs. IOUT.
1V
2.100
1.25V
1.5V
1.75V
2V
3V
1V
2.100
1.25V
1.5V
1.75V
2V
3V
1.900
1.700
1.500
1.300
1.100
0.900
0.700
0.500
0.300
1.900
1.700
1.500
1.300
1.100
0.900
0.700
0.500
0.300
0
2
4
6
8
10 12 14 16 18 20
RP(Ω)
0
2
4
6
8
10 12 14 16 18 20
RP(Ω)
11.8
6.7 +R • V
11.5
6.1+R • V
IL
=
)
+0.26
IL
=
)
+0.2
(
Rp
(
Rp
((
)
)
((
)
)
P
BAT
P
BAT
Figure 13. UCC3941-ADJ ILIM vs. RP (J package only).
Figure 14. UCC3941-ADJ ILIM vs. RP (all other
packages).
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
Figure 15. VIN startup vs. temp.
10
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