UP7706U8 [ETC]

3A Ultra Low Dropout Linear Regulator;
UP7706U8
型号: UP7706U8
厂家: ETC    ETC
描述:

3A Ultra Low Dropout Linear Regulator

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uP7706  
3A Ultra Low Dropout Linear Regulator  
Features  
General Description  
The uP7706 is a 3A ultra low dropout linear regulator † Works with 1.2~5.5V VIN  
specifically designed for motherboard and notebook  
„ Adjustable Output Voltage, Down to 0.8V  
„ 1.5% Initial Accuracy  
„ Excellent Line and Load Regulation  
† 3A Guaranteed Output Current  
„ 200mV @ 2A Dropout Voltage  
† Very Low On-Resistance  
applications. This device works with dual supplies, a control  
input for the control circuitry and a power input as low as  
1.2V for providing current to output. The uP7706 delivers  
high-current and ultra-low-drop output voltage as low as  
0.8V for applications where VOUT is very close to VIN.  
The uP7706 features comprehensive control and protection  
functions: a power on reset (POR) circuit for monitoring  
both control and power inputs for proper operation; an EN  
input for enabling or disabling the device, a power OK with  
time delay for indicating the output voltage status, a  
foldback current limit function, and a thermal shutdown  
function.  
„ 100mtypical  
† VOUT Pull Low Resistance when Disabled  
† Low Reverse Leakage (Output to Input )  
† VOUT Power OK Signal  
† Fast Transient Response  
† Low External Component Count  
† Low Cost and Easy to Use  
The uP7706 is available in PSOP-8 or VDFN6x5-8L  
packages with very low thermal resistance.  
Applications  
† Desktop PCs, Notebooks, and Workstations  
† Graphic Cards  
† Enable Pin  
† Over Current and Over Temperature Protection  
Ordering Information  
† Low Voltage Logic Supplies  
† Microprocessor and Chipset Supplies  
† Split Plane Microprocessor Supplies  
† Advanced Graphics Cards Supplies  
† SoundCards and Auxiliary Power Supplies  
† SMPS Post Regulators  
Order Number  
uP7706U8  
Package Type  
Remark  
PSOP-8  
uP7706ADC8 VDFN6x5 - 8L  
Note: uPI products are compatible with the current IPC/  
JEDEC J-STD-020 and RoHS requirements. They are  
100% matte tin (Sn) plating and suitable for use in SnPb  
or Pb-free soldering processes.  
Pin Configuration & Typical Application Circuit  
5VCC  
POK  
EN  
1
2
3
4
8
7
6
5
GND  
FB  
CNTL  
4
GND  
C1  
EN  
POK  
VOUT  
FB  
VIN  
VOUT  
NC  
0.1uF  
2
1
6
7
CNTL  
R3  
10K  
VOUT  
VIN  
VIN  
PSOP-8  
3
R2  
12.5K  
C2  
22uF  
C4  
option  
POK  
EN  
1
2
3
4
8
7
6
5
GND  
FB  
GND  
C3  
100uF  
R1  
10K  
VIN  
VOUT  
NC  
8
CNTL  
GND  
DFN6x5-8L  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
1
uP7706  
Functional Pin Description  
Pin No. Name Pin Function  
Power OK Indication. This pin is an open-drain output and is set high impedance once VOUT  
1
2
POK  
EN  
reaches 92% of its rating voltage.  
Enable Input. Pulling this pin below 0.8V turns the regulator off, reducing the quiescent current  
to a fraction of its operating value.  
Input Voltage. This is the drain input to the power device that supply current to the output pin.  
Large bulk capacitors with low ESR should be placed physically close to this pin o prevent the  
input rail from dropping during large load transient. A 10uF ceramic capacitor is recommended  
at this pin.  
3
VIN  
Supply Input for Control Circuit. This pin provides bias voltage to the control circuitry and  
driver for the pass transistor.The driving capability of output current is proportioned to the VCNTL  
.
4
5
6
CNTL  
NC  
For the device to regulate, the voltage on this pin must be at least 1.5V greater than the output  
voltage, and no less than VCNTL_MIN.  
Not Internally Connected.  
Output Voltage. This pin is power output of the device. A pull low resistance exists when the  
device is disabled by pulling low the EN pin. To maintain adequate transient response to large  
load change, typical value of 1000uF Al electrolytic capacitor with 10uF ceramic capacitors are  
recommended to reduce the effects of current transients on VOUT.  
VOUT  
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from  
7
8
FB  
the output to GND is used to set the regulation voltage as VOUT = 0.8x(R1+R2)/R1 (V)  
Ground.  
GND  
GND  
Exposed  
Pad  
Ground. The exposed pad acts the dominant power dissipation path and should be soldered  
to well design PCB pads as described in the Application Informations Chapter.  
Functional Block Diagram  
EN  
2
CNTL  
4
VIN  
3
Power On  
Reset  
Thermal Limit  
0.3V  
Softstart &  
Control Logic  
Current Limit  
7
FB  
0.8V VREF  
6
Delay  
92% VREF  
8
1
POK  
GND  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
2
uP7706  
Functional Description  
Definitions  
It’s recommended to maintain 50-100uA through the output  
divider network for a tight load and line regulation. The  
internal voltage reference is VREF = 0.8V with 1.5%  
accuracy over full temperature range. This commands the  
use of 0.5% or better accuracy resistors to build a precision  
power supply.  
Some important terminologies for LDO are specified below.  
Dropout Voltage  
The input/output voltage differential at which the regulator  
output no longer maintains regulation against further  
reductions in input voltage. Measured when the output drops  
2% below its nominal value.Dropout voltage is affected by  
junction temperature, load current and minimum input  
supply requirements.  
5VCC  
CNTL  
4
C1  
0.1uF  
EN  
POK  
VOUT  
FB  
2
1
6
7
R3  
10K  
Line Regulation  
VOUT  
VIN  
VIN  
3
R2  
The change in output voltage for a change in input voltage.  
The measurement is made under conditions of low  
dissipation or by using pulse techniques such that average  
chip temperature is not significantly affected.  
C2  
C4  
12.5K  
22uF  
option  
C3  
100uF  
R1  
10K  
8
GND  
Load Regulation  
The change in output voltage for a change in load current  
at constant chip temperature. The measurement is made  
under conditions of low dissipation or by using pulse  
techniques such that average chip temperature is not  
significantly affected.  
Figure 1. Typical application of 2.5V to 1.8V conversion  
with a 5.0V control supply  
Over Current Protection  
The uP7706 features a foldback over current protection  
function as shown in Figure 2. The current limit threshold  
level is proportional to VOUT/VNOM and is typically 4A when  
Maximum Power Dissipation  
The maximum total device dissipation for which the  
regulator will operate within specifications.  
V
OUT = VNOM, where VNOM is the target output voltage. If the  
output continuously demands more current than the  
maximum current, output voltage will eventually drops below  
its nominal value. This, in turns, will lower its OCP threshold  
level. This will limit power dissipation in the device when  
over current limit happens. The power dissipation is near  
zero when the output is short circuited to ground.  
Initialization  
The uP7706 automatically initiates upon the receipt of  
supply voltage and power voltage.Apower on reset circuit  
continuously monitors VIN and CNTL pins voltages with  
rising threshold levels of 1.0V and 2.7V respectively.  
Chip Enable and Soft Start  
The uP7706 features an enable pin for enable/disable  
control of the chip. Pulling VEN lower than 0.8V disables  
the chip and reduces its quiescent current down to 1uA.  
When disabled, an internal MOSFET of 90RDS(ON) turns  
on to pull output voltage to ground. Pulling VEN higher than  
2.0V enables the output voltage, providing POR is  
recognized. The uP7706 features soft start function that  
limits inrush current for charging the output capacitors. The  
soft start time is typically 2.5ms.  
VOUT  
3V  
2A  
1V  
Output Voltage Programming  
IOUT  
0A  
1A  
2A  
3A  
4A  
Figure 1 shows a typical application of 2.5V to 1.8V  
conversion with a 5.0V control supply. The output voltage  
is sensed through a voltage divider and regulated to internal  
reference voltage VREF. The output voltage is programmed  
as:  
Figure 2. Current Limit Behavior  
VOUT = VREF x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
3
uP7706  
Absolute Maximum Rating  
Control Input VoltageVCNTL (Note 1) -------------------------------------------------------------------------------------------------- -0.3V to +6V  
Power Input VoltageVIN --------------------------------------------------------------------------------------------------------------------- -0.3V to +6V  
Other Pins --------------------------------------------------------------------------------------------------------------- 0.3V to (VCNTL + 0.3V)  
StorageTemperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC  
JunctionTemperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC  
LeadTemperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC  
ESD Rating (Note 2)  
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV  
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V  
Thermal Information  
Package Thermal Resistance (Note 3)  
PSOP-8 θJA ---------------------------------------------------------------------------------------------------------------------------------- 52°C/W  
PSOP-8 θJA ------------------------------------------------------------------------------------------------------------------------------------- 5°C/W  
VDFN6x5-8LθJA ----------------------------------------------------------------------------------------------------------------------------- 45°C/W  
VDFN6x5-8L θJC ------------------------------------------------------------------------------------------------------------------------------ C/W  
PowerDissipation, PD @ TA = 25°C  
PSOP-8 ------------------------------------------------------------------------------------------------------------------------------------------- 1.9W  
VDFN6x5-8L------------------------------------------------------------------------------------------------------------------------------------ 2.2W  
Recommended Operation Conditions  
Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C  
OperatingAmbient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C  
Supply InputVoltage, VCNTL ------------------------------------------------------------------------------------------------------------ +4.5Vto +5.5V  
Electrical Characteristics  
(VCNTL = 5V, TA = 25OC, unless otherwise specified)  
Parameter  
Symbol Test Conditions  
Min  
Typ  
Max  
Units  
Supply Input Voltage  
Control Input Voltage  
POR Threshold  
VCNTL  
VCNTLRTH  
VCNTLHYS  
VIN  
VOUT = VREF  
3.0  
--  
2.7  
0.2  
--  
5.5  
--  
V
V
V
V
--  
--  
POR Hysteresis  
--  
Power Input Voltage  
VOUT = VREF  
1.0  
5.5  
Control Input Current in  
Shutdown  
ICNTL_SD VCNTL = VIN = 5.0V, IOUT = 0A, VEN = 0V  
--  
20  
30  
uA  
Control Input Current  
Quiescent Current  
ICNTL  
IQ  
VCNTL = VIN = VEN = 5.0V, IOUT = 0A, VOUT = VREF  
VCNTL = VIN = VEN = 5.0V, IOUT = 0A, VOUT = VREF  
--  
--  
1.0  
1.0  
1.5  
1.5  
mA  
mA  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
4
uP7706  
Electrical Characteristics  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Units  
Feedback Voltage  
Reference Voltage  
Feedback Input Current  
VREF  
IFB  
VCNTL = VIN = VEN = 5.0V, IOUT = 0A. VOUT = VREF  
0.788 0.8  
0.812  
--  
V
--  
20  
nA  
1.2V < VIN < 5.0V, VCNTL = VEN = 5.0V, IOUT = 0A. VOUT  
VREF  
=
VIN Line Regulation  
VREF(LINE)  
--  
0.01  
0.1  
%/V  
VCNTL Line Regulation  
Load Regulation  
VREF(CNTL) VIN = 3.3V, IOUT = 0A. VOUT = VREF  
--  
--  
0.01  
0.8  
0.1  
1.5  
%/V  
%/A  
VREF(LOAD) 10mA < IOUT < 3A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
Load Regulation over  
Temperature  
10mA < IOUT < 3A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF,  
VREF(LOAD)  
--  
--  
1.4  
3
%
-40OC < TJ < 125OC  
IOUT = 2A, VCNTL = VEN = 5.0V, VOUT = VREF  
VDROP  
200  
300  
240  
360  
Dropout Voltage  
mV  
I OUT = 3A, VCNTL = VEN = 5.0V, VOUT = VREF  
VOUT Pull Low Resistance  
VCNTL = VIN = 5.0V, VEN = 0V,  
--  
90  
--  
Enable  
Enable High Level  
Disable Low Level  
EN Input Current  
EN Input Impedance  
PWROK  
VEN  
VSD  
--  
0.8  
--  
--  
--  
1.4  
--  
V
V
IEN  
VEN = VCNTL = 5.0V  
12  
65  
20  
--  
uA  
KΩ  
ZEN  
--  
FB Power OK Threshold VPOKTH  
IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
--  
--  
92  
8
--  
--  
%
%
Power OK Hysteresis  
Overcurrent Protection  
OCP Threshold Level  
VPOKHYS  
IOCP  
ISC  
VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
--  
--  
4
--  
--  
A
Output Short Circuit  
Current  
100  
mA  
Thermal Protection  
Thermal Shutdown  
Temperature  
TSD  
IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF  
--  
--  
170  
30  
--  
--  
OC  
OC  
Thermal Shutdown  
Hysteresis  
TSDHYS  
Note 1. Stresses listed as the above Absolute Maximum Ratingsmay cause permanent damage to the device.  
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those  
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may remain possibility to affect device reliability.  
Note 2. Devices are ESDsensitive. Handling precaution recommended.  
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of  
JEDEC 51-3 thermal measurement standard.  
Note 4. The device is not guaranteed to function outside its operating conditions.  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
5
uP7706  
Typical Operation Characteristics  
Power On from VIN  
Power On from VCNTL  
VCNTL (5V/Div)  
VOUT (1V/Div)  
VIN (2V/Div)  
VOUT (1V/Div)  
POK (5V/Div)  
POK (5V/Div)  
IIN (1A/Div)  
IIN (1A/Div)  
1ms/Div  
1ms/Div  
VCNTL =5V, VIN = 3.3V, COUT = 1000uF, No Load.  
VCNTL =5V, VIN = 3.3V, COUT = 1000uF, No Load.  
Turn On from EN  
Dropout Voltage vs. Output Current  
VEN (5V/Div)  
VOUT (1V/Div)  
300mV  
200mV  
POK (5V/Div)  
100mV  
0mV  
IIN (1A/Div)  
3A  
0A  
1A  
2A  
1ms/Div  
Output Current (A)  
VCNTL =5V, VIN = 3.3V, COUT = 1000uF, No Load.  
Output Short Circuit  
Ouput Voltage vs. Ouptut Current  
2V  
1.5V  
1V  
0A  
1A  
2A  
3A  
0mV  
2mV  
4mV  
0.5V  
0V  
0A  
1A  
2A  
3A  
4A  
5A  
Output Current (A)  
Output Current (A)  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
6
uP7706  
Typical Operation Characteristics  
Load Transient Response  
Quiescent Current vs. Input Voltage  
1200  
1000  
800  
600  
400  
200  
0
VOUT  
(5mV/Div)  
IOUT  
(1A/Div)  
2.5  
3
3.5  
4
4.5  
5
5.5  
6
25us/Div  
C
OUT = 22uF/X5R  
Input Voltage VCNTL = VIN (V)  
Shutdown Current vs. Input Voltage  
Line Regulation  
0.81  
80  
70  
60  
50  
40  
30  
20  
10  
0
0.808  
0.806  
0.804  
0.802  
0.8  
0.798  
0.796  
0.794  
0.792  
0.79  
2.5  
3
3.5  
4
4.5  
5
5.5  
6
2.5  
3
3.5  
4
4.5  
5
5.5  
6
Input Voltage VCNTL = VIN (V)  
Input Voltage VCNTL = VIN (V)  
Quiescent Current vs. Temperature  
Shutdown Current vs. Temperature  
1400  
1200  
1000  
800  
600  
400  
200  
0
25  
20  
15  
10  
5
0
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Junction Temperature (OC)  
VCNTL = VIN = 5V  
Junction Temperature (OC)  
VCNTL = 5V  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
7
uP7706  
Typical Operation Characteristics  
FB Voltage vs. Temperature  
On Resistance vs. Temperature  
140  
0.81  
0.808  
0.806  
0.804  
0.802  
0.8  
120  
100  
80  
60  
40  
20  
0
0.798  
0.796  
0.794  
0.792  
0.79  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Junction Temperature (OC)  
VCNTL = 5V, VIN = VOUT + 1V  
Junction Temperature (OC)  
VCNTL = 5V, VOUT = 1.6V  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
8
uP7706  
Application Information  
The uP7706 is a high performance linear regulator This allows for the device being some distance from any  
specifically designed to deliver up to 3A output current with bulk capacitance on the rail.Additionally, bulk capacitance  
very low input voltage and ultra low dropout voltage. With may be added closely to the input supply pin of the uP7706  
dual-supply configuration, the uP7706 operates with a wide to ensure that VIN does not sag, improving load transient  
input voltage VIN range from 1.0V to 5.5V and is ideal for response.  
applications where VOUT is very close to VIN .  
Output capacitor: A minimum bulk capacitance of 33uF,  
Supply Voltage for Control Circuit VCNTL  
along with a 0.1uF ceramic decoupling capacitor is  
recommended. Increasing the bulk capacitance will improve  
the overall transient response. The use of multiple lower  
value ceramic capacitors in parallel to achieve the desired  
bulk capacitance will not cause stability issues. Although  
designed for use with ceramic output capacitors, the uP7706  
is extremely tolerant of output capacitor ESR values and  
thus will also work comfortably with tantalum output  
capacitors.  
Unlike other linear regulators that use a P-Channel  
MOSFET as the pass transistor, the uP7706 uses an N-  
Channel as the pass transistor. N-Channel MOSFET  
provides lower on-resistance and better stability meeting  
stringent requirements of current generation  
microprocessors and other sensitive electronic devices.  
The drain ofN-Channel MOSFET is connected to VINand  
the source is connected to VOUT. This requires that the  
supply voltage VCNTL for control circuit is at least 1.5V higher Thermal Consideration  
than the output voltage to provide enough overdrive capability  
for the pass transistor thus to achieve low dropout and fast  
transient response. It is highly recommended to bias the  
device with 5V voltage source if available.  
The uP7706 integrates internal thermal limiting function to  
protect the device from damage during fault conditions.  
However, continuously keeping the junction near the thermal  
shutdown temperature may remain possibility to affect  
Use a minimum 0.1uF ceramic capacitor plus a 10device reliability. It is highly recommended to keep the  
resistor to locally bypass the control voltage.  
Input/Output Capacitor Selection  
The uP7706 has a fast transient response that allows it to  
handle large load changes associated with high current PD = (VIN - VOUT) x IOUT + VCNTL x ICNTL  
applications. Proper selection of the of the output capacitor  
and it’s ESR value determines stable operation and  
optimizes performance. The typical application circuit  
shown in Figure 1 was tested with a wide range of different  
capacitors. The circuit was found to be unconditionally  
stable with capacitor values from 10ìF to 2200ìF and ESR  
ranging from 0.5mto greater then 75m.  
junction temperature below the recommended operation  
condition 125OC for maximum reliability.  
Power dissipation in the device is calculated as:  
It is adequate to neglect power loss with respective to  
control circuit VCNTL x ICNTL when considering thermal  
management in uP7706 Take the following moderate  
operation condition as an example: VIN = 2.5V, VOUT = 1.5V,  
I
OUT = 2A, the power dissipation is:  
PD = (1.8V- 1.2V) x 2A = 2.0W  
This power dissipation is conducted through the package  
into the ambient environment, and, in the process, the  
temperature of the die (TJ) rises above ambient. Large power  
dissipation may cause considerable temperature raise in  
the regulator in large dropout applications. The geometry  
of the package and of the printed circuit board (PCB) greatly  
influence how quickly the heat is transferred to the PCB  
and away from the chip. The most commonly used thermal  
metrics for IC packages are thermal resistance from the  
chip junction to the ambient air surrounding the package  
(θJA):  
5VCC  
CNTL  
4
C1  
0.1uF  
EN  
POK  
VOUT  
FB  
2
1
6
7
R3  
10K  
VOUT  
VIN  
VIN  
3
R2  
C2  
C4  
12.5K  
22uF  
option  
C3  
100uF  
R1  
10K  
8
GND  
θJA = ( TJ -TA ) / PD  
θJA specified in the Thermal Information section is measured  
in the natural convection at TA = 25OC on a high effective  
thermal conductivity test board (4 Layers, 2S2P) of JEDEC  
51-7 thermal measurement standard. The case point of  
Figure 1. TypicalApplication Circuit  
Input capacitor:Aminimum of 10uF ceramic capacitor is  
recommended to be placed directly next to the VIN pin.  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
9
uP7706  
Application Information  
θJC is on the exposed pad for PSOP-8 package.  
Given power dissipation PD, ambient temperature and  
thermal resistance θJA, the junction temperature is  
calculated as:  
TJ = TA + TJA = TA + PD x θJA  
To limit the junction temperature within its maximum rating,  
the allowable maximum power dissipation is calculated  
as:  
PD(MAX) = ( TJ(MAX) -TA ) /θJA  
where TJ(MAX) is the maximum operation junction  
temperature 125OC, TA is the ambient temperature and the  
θJA is the junction to ambient thermal resistance. θJA of  
PSOP-8 packages is 75OC/W on JEDEC 51-7 (4 layers,  
2S2P) thermal test board with minimum copper area. The  
maximum power dissipation at TA = 25¢XC can be calculated  
as:  
Figure 4. Recommended PCB Layout.  
Layout Consideration  
1. Place a local bypass capacitor as closed as possible  
to the VIN pin. Use short and wide traces to minimize  
parasitic resistance and inductance.  
PD(MAX) = (125OC - 25OC) / 75OC/W = 1.33W  
The thermal resistance θJA highly depends on the PCB  
design. Copper plane under the exposed pad is an effective  
heatsink and is useful for improving thermal conductivity.  
Figure 3 show the relationship between thermal resistance  
θJA vs. copper area on a standard JEDEC 51-7 (4 layers,  
2S2P) thermal test board at TA = 25OC. A 50mm2 copper  
plane reduces θJA from 75OC/W to 50OC/W and increases  
maximum power dissipation from 1.33W to 2W.  
2. The exposed pad should be soldered on GND plane  
with maximum area and with multiple vias to inner layer  
of ground place for improved thermal performance.  
3. Connect voltage divider directly to the point where  
regulation is required. Place voltage divider close to  
the device.  
100  
90  
80  
70  
60  
50  
40  
30  
0
10  
20  
30  
40  
50  
60  
70  
2
Copper Area (mm)  
Figure 3. Thermal Resistance èJA vs. CopperArea  
Figure 4 illustrated the recommended PCB layout for best  
thermal performance.  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
10  
uP7706  
Application Information  
PSOP-8 Package  
0.76 REF  
1.27 REF  
4.80 - 5.00  
2.29 BSC  
2.39 REF  
0.32 - 0.52  
1.27 BSC  
Recommended Solder Pad Layout  
1.45 - 1.60  
0.20 BSC  
0.18 - 0.25  
0.10 - 0.25  
3.81 BSC  
1.75 MAX  
0.41 - 0.89  
Note  
1.Package Outline UnitDescription:  
BSC: Basic. Represents theoretical exact dimension or dimension target  
MIN: Minimum dimension specified.  
MAX: Maximum dimension specified.  
REF: Reference. Represents dimension for reference use only. This value is not a device specification.  
TYP. Typical. Provided as a general value. This value is not a device specification.  
2.Dimensions in Millimeters.  
3.Drawing not to scale.  
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
11  
uP7706  
Application Information  
VDFN6x5-8LPackage  
3.90 - 4.10  
4.90 - 5.10  
0.50 - 0.75  
5
8
4
1
1.27 BSC  
0.35 - 0.48  
3.90 - 4.10  
0.20 REF  
0.00 - 0.05  
1.27 BSC  
0.40 - 0.50  
Recommended Solder Pitch and Dimensions  
Note  
1.Package Outline UnitDescription:  
BSC: Basic. Represents theoretical exact dimension or dimension target  
MIN: Minimum dimension specified.  
MAX: Maximum dimension specified.  
REF: Reference. Represents dimension for reference use only. This value is not a device specification.  
TYP. Typical. Provided as a general value. This value is not a device specification.  
2.Dimensions in Millimeters.  
3.Drawing not to scale.  
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.  
uPI Semiconductor Corp., http://www.upi-semi.com  
Rev. F00, File Name: uP7706-DS-F0000  
12  

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