UPA1742 [ETC]
UPA1742TP Data Sheet | Data Sheet[04/2003] ; UPA1742TP数据表|数据表[ 04/2003 ]\n
| 型号： | UPA1742 |
| 厂家： | 
ETC |
| 描述： | UPA1742TP Data Sheet | Data Sheet[04/2003]
|
| 文件： | 总7页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1742TP
SWITCHING
N-CHANNEL POWER MOS FET
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µPA1742TP is N-channel MOS FET device that
features a low on-state resistance and excellent switching
characteristics, and designed for high voltage applications
such as DC/DC converter.
8
5
1, 2, 3
4
5, 6, 7, 8, 9 ; Drain
; Source
; Gate
FEATURES
• High voltage: VDSS = 250 V
• Gate voltage rating: ±30 V
6.0 ±0.3
1
4
0.8 ±0.2
4.4 ±0.15
+0.17
–0.2
5.2
• Low on-state resistance
S
RDS(on) = 0.55 Ω MAX. (VGS = 10 V, ID = 3.5 A)
• Low input capacitance
0.10
S
1.27 TYP.
Ciss = 460 pF TYP. (VDS = 10 V, VGS = 0 V)
• Built-in gate protection diode
• Small and surface mount package (Power HSOP8)
+0.10
0.40
0.12 M
–0.05
1
4
2.0 ±0.2
9
ORDERING INFORMATION
4.1 MAX.
PART NUMBER
PACKAGE
8
5
µPA1742TP
Power HSOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise noted. All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
250
±30
±7.0
±21
24
V
V
EQUIVALENT CIRCUIT
A
Drain
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C) Note2
Channel Temperature
W
W
°C
Body
Diode
Gate
PT2
1.0
Tch
150
Gate
Storage Temperature
Tstg
−55 to +150 °C
Protection
Diode
Single Avalanche Current Note3
Single Avalanche Energy Note3
Repetitive Avalanche Current Note4
Source
IAS
7.0
4.9
7.0
4.9
A
mJ
A
EAS
IAR
Repetitive Pulse Avalanche Energy Note4
EAR
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm
3. Starting Tch = 25°C, VDD = 125 V, RG = 25 Ω, L = 100 µH, VGS = 20 → 0 V
4. Tch(peak) ≤ 150°C, L = 100 µH
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16325EJ1V0DS00 (1st edition)
Date Published April 2003 NS CP(K)
Printed in Japan
2002
µ PA1742TP
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted. All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = 250 V, VGS = 0 V
MIN.
TYP.
MAX.
10
UNIT
µA
µA
V
IGSS
VGS(off)
| yfs |
RDS(on)
Ciss
VGS = ±30 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 3.5 A
VGS = 10 V, ID = 3.5 A
VDS = 10 V
±10
4.5
Gate Cut-off Voltage
2.5
2.5
3.5
5
Note
Forward Transfer Admittance
Drain to Source On-state Resistance
Input Capacitance
S
Note
0.41
460
100
45
11
9
0.55
Ω
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V
f = 1 MHz
td(on)
tr
td(off)
tf
VDD = 125 V, ID = 3.5 A
VGS = 10 V
Turn-off Delay Time
Fall Time
RG = 10 Ω
24
8
Total Gate Charge
QG
VDD = 200 V
14
3
Gate to Source Charge
Gate to Drain Charge
QGS
QGD
VF(S-D)
trr
VGS = 10 V
ID = 7.0 A
7
Note
Body Diode Forward Voltage
IF = 7.0 A, VGS = 0 V
IF = 7.0 A, VGS = 0 V
di/dt = 100 A/µs
0.9
140
560
1.5
Reverse Recovery Time
Reverse Recovery Charge
ns
nC
Qrr
Note Pulsed: PW ≤ 800 µs, Duty Cycle ≤ 2%
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
V
GS
R
L
RG
= 25 Ω
90%
90%
V
GS
Wave Form
V
GS
10%
0
R
G
PG.
GS = 20 → 0 V
PG.
50 Ω
V
DD
V
DD
V
DS
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
t
d(on)
t
r
t
d(off)
tf
V
DD
t
on
toff
µ
τ = 1
s
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
RL
PG.
50 Ω
V
DD
2
Data Sheet G16325EJ1V0DS
µ PA1742TP
TYPICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted. All terminals are connected.)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
100
80
60
40
20
0
25
20
15
10
5
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
175
TC - Case Temperature - °C
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
10
µ
s
PW = 100
ID(pulse) = 21 A
10 ms
ID(DC) = 7.0 A
1 ms
DC
1
RDS(on) Limited
(at VGS = 10 V)
0.1
0.01
TC = 25°C
Single pulse
Power Dissipation Limited
0.1
1
10
100
1000
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
th(ch-A)
R
= 125°C/W
= 5.2°C/W
th(ch-C)
R
1
Single pulse
0.1
th(ch-A)
R
:Mounted on glass epoxy board
(1 inch x 1inch x 0.8 mm), TA = 25°C
th(ch-C)
C
R
:T = 25°C
0.01
100 µ
1 m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
3
Data Sheet G16325EJ1V0DS
µ PA1742TP
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
30
25
20
15
10
5
100
Pulsed
VDS = 10 V
Pulsed
VGS = 10 V
10
1
TA = 150°C
125°C
0.1
75°C
25°C
−
25°C
0.01
0.001
0.0001
0
0
5
10
15
20
25
30
0
5
10
15
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
4.5
4
100
10
VDS = 10 V
Pulsed
VDS = 10 V
ID = 1 mA
−
TA = 25°C
25°C
75°C
125°C
150°C
3.5
3
1
0.1
0.01
2.5
2
-50
-25
0
25
50
75
100
125
150
0.01
0.1
1
10
100
Tch - Channel Temperature - °C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
1.3
1.3
Pulsed
VGS = 10 V
Pulsed
1.2
1.2
1.1
1
1.1
1
ID = 7.0 A
3.5 A
1.4 A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.1
1
10
100
0
2
4
6
8
10 12 14 16 18 20
ID - Drain Current - A
VGS - Gate to Source Voltage - V
4
Data Sheet G16325EJ1V0DS
µ PA1742TP
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
1.5
1000
100
10
VGS = 10 V
Pulsed
1.25
iss
C
ID = 7.0 A
1
0.75
oss
rss
C
3.5 A
0.5
0.25
0
C
GS
V
= 0 V
f = 1 MHz
1
0.1
1
10
100
1000
-50 -25
0
25
50
75 100 125 150 175
VDS - Drain to Source Voltage - V
Tch - Channel Temperature - °C
SWITCHING CHARACTERISTICS
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
100
10
1
250
15
12
9
VDD = 125 V
VGS = 10 V
RG = 0 Ω
ID = 7.0 A
200
150
100
50
td(off)
VDD = 200 V
125 V
tf
62.5 V
td(on)
tr
6
GS
V
3
DS
V
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0.1
1
10
100
QG - Gate Charge - nC
ID - Drain Current - A
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
100
1000
100
10
Pulsed
µ
s
di/dt = 100 A/
GS
V
= 0 V
GS
V
= 0 V
10
1
0.1
0.01
1
0.1
1
10
100
0
0.25
0.5
0.75
1
1.25
1.5
IF - Diode Forward Current - A
VF(S-D) - Source to Drain Voltage - V
5
Data Sheet G16325EJ1V0DS
µ PA1742TP
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
100
80
60
40
20
0
10
DD
V
= 125 V
VDD = 125 V
G
R
Ω
= 25
AS
I
Ω
= 7.0 A
R
G
= 25
GS
V
→
= 20 0 V
VGS = 20 → 0 V
≤
IAS 7.0 A
AS
E
= 4.9 mJ
1
0.1
25
50
75
100
125
150
0.001
0.01
0.1
1
10
L - Inductive Load - mH
Starting Tch - Starting Channel Temperature - °C
6
Data Sheet G16325EJ1V0DS
µ PA1742TP
•
The information in this document is current as of April, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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•
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M8E 02. 11-1
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