UPA2701 [ETC]
UPA2701GR Data Sheet | Data Sheet[05/2002] ; UPA2701GR数据表|数据表[ 05/2002 ]\n
| 型号： | UPA2701 |
| 厂家： | 
ETC |
| 描述： | UPA2701GR Data Sheet | Data Sheet[05/2002]
|
| 文件： | 总8页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA2701GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
PACKAGE DRAWING (Unit: mm)
The µPA2701GR is N-Channel MOS Field Effect Transistor
designed for DC/DC converters and power management
applications of notebook computers.
8
5
1, 2, 3
4
; Source
; Gate
5, 6, 7, 8 ; Drain
FEATURES
• Low on-state resistance
RDS(on)1 = 7.5 mΩ MAX. (VGS = 10 V, ID = 7.0 A)
RDS(on)2 = 11.6 mΩ MAX. (VGS = 4.5 V, ID = 7.0 A)
• Low Ciss: Ciss = 1200 pF TYP. (VDS = 10 V, VGS = 0 V)
• Small and surface mount package (Power SOP8)
6.0 ±0.3
4.4
1
4
5.37 MAX.
0.8
0.5 ±0.2
ORDERING INFORMATION
0.10
1.27 0.78 MAX.
PART NUMBER
PACKAGE
+0.10
0.40
0.12 M
–0.05
µPA2701GR
Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC)
VDSS
VGSS
ID(DC)
ID(pulse)
PT
30
V
EQUIVALENT CIRCUIT
±20
V
±14
A
Drain
Drain Current (pulse) Note1
±56
A
Total Power Dissipation (TA = 25°C) Note2
Body
2.0
W
°C
°C
A
Diode
Gate
Channel Temperature
Tch
150
Storage Temperature
Tstg
–55 to +150
14
Gate
Protection
Diode
Single Avalanche Current Note3
Single Avalanche Energy Note3
Source
IAS
EAS
19.6
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, L = 100 µH, VGS = 20 → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is extemally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.G15714EJ2V0DS00 (2nd edition)
Date Published May 2002 NS CP(K)
Printed in Japan
2002
©
The mark ! shows major revised points.
µPA2701GR
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
VDS = 30 V, VGS = 0 V
MIN. TYP. MAX. UNIT
Zero Gate Voltage Drain Current
Gate Leakage Current
IDSS
IGSS
10
±10
2.5
µA
µA
V
VGS = ±20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 7.0 A
VGS = 10 V, ID = 7.0 A
VGS = 4.5 V, ID = 7.0 A
VGS = 4.0 V, ID = 7.0 A
VDS = 10 V
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
1.5
7
2.0
14
Forward Transfer Admittance
Drain to Source On-state Resistance
S
6.2
8.7
10.3
1200
500
160
10
7.5
mΩ
mΩ
mΩ
pF
pF
pF
ns
11.6
13.7
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V
f = 1 MHz
td(on)
tr
td(off)
tf
VDD = 15 V, ID = 7.0 A
VGS = 10 V
13
ns
Turn-off Delay Time
Fall Time
RG = 10 Ω
44
ns
11
ns
Total Gate Charge
QG
VDD = 15 V
12
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
QGD
VF(S-D)
trr
VGS = 5 V
4
ID = 14 A
6
IF = 14 A, VGS = 0 V
IF = 14 A, VGS = 0 V
di/dt = 100 A/ µs
0.8
32
1.2
ns
Qrr
27
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
GS
R
L
RG
= 25 Ω
90%
V
GS
Wave Form
VGS
10%
0
R
G
PG.
PG.
50 Ω
V
DD
V
DD
V
GS = 20 → 0 V
V
DS
90%
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
t
d(on)
t
r
t
d(off)
tf
V
DD
t
on
toff
τ
= 1
µ
s
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
RL
PG.
50 Ω
V
DD
2
Data Sheet G15714EJ2V0DS
µPA2701GR
TYPICAL CHARACTERISTICS (TA = 25°C)
!
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
120
100
80
Mounted on ceramic
substrate of
1200 mm2 ×2.2 mm
60
40
20
0
20
40 60
80 100 120 140 160
0
20 40
60
80 100 120 140 160
T
A
- Ambient Temperature - ˚C
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
I
D(pulse) = 56 A
I
D(DC) = 14 A
Limited
= 10 V)
10
1
RDS(on)
(VGS
100 ms
Remark Mounted on ceramicsubstrate of
1200 mm2 x 2.2 mm
0.1
T = 25˚C
A
Single Pulse
0.01
0.01
0.1
1
10
100
V
DS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
10
1
Rth(ch-A) = 62.5˚C/W
Mounted on ceramic substrate of
1200 mm2 × 2.2 mm
Single Pulse
Channel to Ambient
0.1
0.001
0.01
0.1
1
10
100
1000
PW - Pulse Width - s
3
Data Sheet G15714EJ2V0DS
µPA2701GR
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
Pulsed
100
10
80
70
60
50
40
30
20
10
0
V
GS = 10 V
4.5 V
T
A
= 150˚C
75˚C
1
0.1
4.0 V
25˚C
−25˚C
Pulsed
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DS - Drain to Source Voltage - V
V
DS = 10 V
4
0.01
0
1
2
3
5
0
VGS - Gate to Source Voltage - V
V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100
10
1
20
V
DS = 10 V
Pulsed
Pulsed
18
16
14
12
10
8
T
A
= 150˚C
75˚C
I = 7.0 A
D
25˚C
6
−25˚C
4
2
0.1
0.01
0
0.1
0
2
4
6
8
10 12 14 16 18 20
1
10
100
V
GS - Gate to Source Voltage - V
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
30
15
10
5
3
2
1
0
Pulsed
V
DS = 10 V
I
D = 1 mA
V
GS = 4.0 V
4.5 V
10 V
0
0.1
1
10
100
−50 −25
0
25
50
75 100 125 150
I
D - Drain Current - A
T
ch - Channel Temperature - ˚C
4
Data Sheet G15714EJ2V0DS
µPA2701GR
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
20
15
10
5
100
10
1
Pulsed
Pulsed
V
GS = 0 V
VGS = 4 V
4.5 V
10 V
0.1
0
0.01
0
0.2
0.4
0.6
0.8
1.0
1.2
−50 −25
0
25 50 75 100 125 150 175
V
SD - Source to Drain Voltage - V
T
ch - Channel Temperature - ˚C
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
100
10
1
10000
1000
t
d(off)
t
f
C
iss
t
r
C
oss
rss
t
d(on)
C
100
10
V
DD = 15 V
V
GS = 10 V
V
GS = 0 V
R = 10 Ω
G
f = 1 MHz
0.1
1
10
100
0.1
1
10
100
V
DS - Drain to Source Voltage - V
I
D
- Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
1000
100
40
35
30
25
20
15
10
5
8
7
6
5
4
3
2
1
0
µ
di/dt = 100 A/
GS = 0 V
s
V
V
DD = 24 V
15 V
6 V
VGS
10
1
V
DS
I
D
= 14 A
0
0.1
1
10
100
0
2
4
6
8
10 12 14 16 18 20
I
F
- Drain Current - A
Q
G
- Gate Charge - nC
5
Data Sheet G15714EJ2V0DS
µPA2701GR
[MEMO]
6
Data Sheet G15714EJ2V0DS
µPA2701GR
[MEMO]
7
Data Sheet G15714EJ2V0DS
µPA2701GR
•
The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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•
•
•
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M8E 00. 4
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