UPD432937GF-A33 [ETC]
x36 Synchronous SRAM ; X36同步SRAM\n
| 型号： | UPD432937GF-A33 |
| 厂家： | 
ETC |
| 描述： | x36 Synchronous SRAM
|
| 文件： | 总24页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD432937
2M-BIT CMOS SYNCHRONOUS FAST SRAM
64K-WORD BY 36-BIT
PIPELINED OPERATION / HSTL INTERFACE
Description
The µPD432937 is a 65,536-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology
using N-channel four-transistor memory cell.
The µPD432937 integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as
SRAM core. All input registers are controlled by a positive edge of the single clock input (K).
The µPD432937 is suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration, such as cache and buffer memory.
The µPD432937GF is packaged in 100-pin plastic LQFP for high density and low capacitive loading.
Features
• 3.3 V (Chip) / 1.6 V (I/O) Supply
• Synchronous operation
• Internally self-timed write control
• Burst read / write : Interleaved burst sequence
• Fully registered inputs and outputs for 4-1-1-1 pipelined burst operation
• All registers triggered off positive clock edge
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
• Internally controlled burst advance
• Free running active high and active low echo clock outputs
• AND tree testability
• Power down mode :
ZZ pin used to place SRAM in power down mode. Stop clock method for power down mode.
Part number
Class
Clock
frequency
MHz
Maximum supply current
Supply voltage
Active
mA
Standby
mA
Chip
I/O
V
V
•
µPD432937
A28
A29
A31
A33
A36
A40
360
350
325
300
275
250
420
400
60
3.3 ± 0.2
1.6 + 0.1/
− 0.15
350
50
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14018EJ3V0DS00 (3rd edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark shows major revised points.
★
1999
©
µPD432937
Ordering Information
Part number
Clock frequency
MHz
Package
•
µPD432937GF-A28
µPD432937GF-A29
µPD432937GF-A31
µPD432937GF-A33
µPD432937GF-A36
µPD432937GF-A40
360
350
325
300
275
250
100-PIN PLASTIC LQFP (14 x 20)
2
Data Sheet M14018EJ3V0DS00
µPD432937
•
Pin Configuration (Marking Side)
/××× indicates active low signal.
100-PIN PLASTIC LQFP (14 x 20)
[ µPD432937GF ]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP2
I/O16
I/O15
I/OP3
I/O17
I/O18
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
V
DDQ
V
DD
Q
Q
4
VSSQ
V
SS
5
I/O14
I/O13
I/O12
I/O11
I/O19
I/O20
I/O21
I/O22
6
7
8
9
V
V
SS
Q
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DD
Q
V
DD
I/O10
I/O9
I/O23
I/O24
/KQA
VSS
/KQB
V
DD
V
DD
KQA
KQB
I/O8
I/O7
V
SS
I/O25
I/O26
V
DDQ
V
DD
Q
Q
VSSQ
V
SS
I/O6
I/O5
I/O4
I/O3
I/O27
I/O28
I/O29
I/O30
V
V
SS
Q
V
SS
Q
Q
DD
Q
V
DD
I/O2
I/O31
I/O32
I/OP4
I/O1
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for 1-pin index mark.
3
Data Sheet M14018EJ3V0DS00
µPD432937
Pin Identification
Symbol
Pin number
Description
A0 - A15
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 Synchronous Address Input
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, Synchronous Data In,
I/O1 - I/O32
2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
Synchronous Data Out
I/OP1 - I/OP4
Synchronous Data In (Parity),
Synchronous Data Out (Parity)
Echo Clock Output
KQA, /KQA,
KQB, /KQB
/AC
16, 14, 64, 66
85
Synchronous Address Status Input
Synchronous Chip Enable Input
Synchronous Global Write Input
Differential Input Clock Pair
/CE, CE2, /CE2 98, 97, 92
/GW
88
K, /K
89, 93
84
/RESET
Asynchronous Input
Initialize internal state at power up
Asynchronous Power Down State Input
ZZ
95
/TE
39
Test Enable Input
Test Output
TO
50
VREF
VDD
38, 43
Input Reference Voltage
Power Supply
15, 41, 65, 91
VSS
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77, 87, 94
5, 10, 21, 26, 55, 60, 71, 76
31, 42, 83, 86
Output Buffer Power Supply
Output Buffer Ground
No Connection
RES
96
Reserved
It must be tied LOW during normal operation
4
Data Sheet M14018EJ3V0DS00
µPD432937
Block Diagram
16
14
16
Address
register
A0 - A15
K
A0, A1
Q1
Binary
A1’
A0’
counter
and logic
Row and column
decoders
CLR
Q0
/AC
Advance
control
/RESET
Memory matrix
1,024 rows
Write driver
Write
controller
64 × 36 columns
(2,359,296 bits)
/GW
/CE
CE2
/CE2
/OE
36
36
Data output enable,
Data output strobe
Output
registers
Output
buffers
Strobe_Out
Input
registers
36
I/O1 - I/O32
I/OP1 - I/OP4
Echo clock
registers
Echo clock
buffers
/K
4
KQA, /KQA
KQB, /KQB
ZZ
Power down control
Burst Sequence
Interleaved Burst Sequence Table
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A15 - A2, A1, A0
A15 - A2, A1, /A0
A15 - A2, /A1, A0
A15 - A2, /A1, /A0
5
Data Sheet M14018EJ3V0DS00
µPD432937
Synchronous Truth Table
Operation
Deselected Note
/CE
H
L
CE2
×
/CE2
×
/AC
L
/GW
×
I/O
Hi-Z
Address
None
Deselected Note
L
×
L
×
Hi-Z
None
Deselected Note
L
×
H
L
L
×
Hi-Z
None
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
L
H
×
L
H
×
Hi-Z
External
Current
Current
Next
×
×
H
H
H
H
H
H
L
Hi-Z
×
×
×
×
Hi-Z
×
×
×
×
Data-out
Data-out
Data-out
Data-out
Hi-Z
×
×
×
×
Next
×
×
×
×
Next
×
×
×
×
None
L
H
×
L
L
External
Current
Current
Next
×
×
H
H
H
H
H
L
Data-in
Data-in
Data-in
Data-in
Hi-Z
×
×
×
L
×
×
×
L
×
×
×
×
Next
×
×
×
×
Next
Note Deselect status is held until new “Begin Burst” entry.
Remark × : don’t care
Asynchronous Truth Table
ZZ
H
×
/RESET
/TE
H
I/O
Operation
Sleep Mode
Reset
H
L
Hi-Z
Hi-Z
H
×
×
L
Hi-Z
Test Mode
Read
L
H
H
H
Data-out
Data-in
L
H
Write
Remark × : don’t care
6
Data Sheet M14018EJ3V0DS00
µPD432937
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
+4.0
Unit
V
Note
Output supply voltage
Input voltage
VDDQ
VIN
VDD
V
VDDQ + 0.5
VDDQ + 0.5
70
V
1
1
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
V
TA
°C
°C
Tstg
–55
+125
Note 1. –1.0 V (MIN.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
3.1
TYP.
3.3
MAX.
3.5
Unit
V
Note
•
•
Output supply voltage
High level input voltage
Low level input voltage
Input reference voltage
VDDQ
VIH
1.45
1.6
1.7
V
VREF + 0.1
–0.3
VDDQ + 0.3
VREF – 0.1
0.85
V
VIL
V
1
VREF
0.725
VDDQ / 2
V
Note 1. –1.0 V (MIN.) (Pulse width : 2 ns)
Recommended AC Operating Conditions (TA = 0 to 70 °C)
Parameter
Input reference voltage
Low level input voltage
High level input voltage
Symbol
VREF(RMS)
VIL
Conditions
MIN.
–5 %
TYP.
MAX.
+5 %
Unit
V
Note
–0.3
VREF – 0.2
VDDQ + 0.3
V
VIH
VREF + 0.2
V
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CIN
Test condition
MIN.
TYP.
MAX.
Unit
pF
Note
VIN = 0 V
7
7
7
Input / Output capacitance
Clock input capacitance
CI/O
VI/O = 0 V
Vclk = 0 V
pF
Cclk
pF
1
Note1. Cclk is for both K and /K.
Remark These parameters are periodically sampled and not 100% tested.
7
Data Sheet M14018EJ3V0DS00
µPD432937
•
DC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.2 V)
Parameter
Input leakage current
I/O leakage current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit Note
VIN = 0 V to VDD
µA
µA
ILO
VI/O = 0 V to VDD, Output disabled.
Device selected, Cycle = MAX.,
VIN ≤ 0.2 V or VIN ≥ VDDQ – 0.2 V
–2
+2
Operating supply current
IDD
-A28
-A29
-A31
-A33
-A36
-A40
-A28
-A29
-A31
-A33
-A36
-A40
-A28
-A29
-A31
-A33
-A36
-A40
-A28
-A29
-A31
-A33
-A36
-A40
420
400
400
350
350
350
450
437
406
374
343
311
150
150
150
110
110
110
60
mA
Operating VDDQ supply
current
IDDQ
All outputs toggling, Cycle = MAX.,
CL = 20 pF
mA
mA
mA
1
Standby supply current
ISB
Device deselected, Cycle = MAX.,
VIN ≤ 0.2 V or VIN ≥ VDDQ – 0.2 V,
All inputs are static.
ISB1
Device deselected,
Cycle = 0 MHz,
60
VIN ≤ 0.2 V or VIN ≥ VDDQ – 0.2 V,
All inputs are static.
60
50
50
50
ISB2
VOH
VOL
Sleep Mode (ZZ = VIH), All inputs are static.
VDDQ = 1.45 to 1.7 V, IOH = –1 mA
VDDQ = 1.45 to 1.7 V, IOL = +1 mA
5.0
mA
V
High level output voltage
VDDQ – 0.4
Low level output voltage
0.4
V
Note 1. See next page.
8
Data Sheet M14018EJ3V0DS00
µPD432937
•
AC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.2 V, VDDQ = 1.45 to 1.7 V)
AC Test Conditions
Input waveform (Rise / Fall time : 1.0 V / ns)
VDDQ
V
DDQ/2
V
DDQ/2
Test points
0 V
Output waveform
V
DDQ/2
V
DDQ/2
Test points
Output load condition
V
REF = VDDQ / 2
V
REF = VDDQ / 2
V
REF
50 Ω
µ
PD432937
OUT
ZO = 50 Ω
Test point
: 20 pF
CL
Remark CL includes capacitances of the probe and jig, and stray capacitances.
9
Data Sheet M14018EJ3V0DS00
µPD432937
•
Read and Write Cycle
Parameter
Symbol
-A28
-A29
-A31
-A33
-A36
-A40
Unit Note
(360 MHz) (350 MHz) (325 MHz) (300 MHz) (275 MHz) (250 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time
2.77
1.03
1.03
2.85
1.06
1.06
3.07
1.15
1.15
3.3
3.6
4.0
ns
ns
ns
ns
ns
TKHKH
TKHKL
TKLKH
TKHKB
TKHKE
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Clock high pulse width
Clock low pulse width
Clock (K) to clock (/K)
1.24
1.24
1.36
1.36
1.49
1.49
1.28 1.55 1.33 1.60 1.43 1.72 1.55 1.86 1.69 2.04 1.87 2.24
1.1 2.0 1.1 2.1 1.1 2.3 1.1 2.6 1.1 2.9 1.1 3.2
Clock to echo clock (/KQ)
low
Output setup to echo clock
(/KQ)
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
ns
ns
TQVKE
TKEQX
−
−
−
−
−
−
−
−
−
−
−
−
Output hold from echo clock
(/KQ)
Setup time Address
0.75
0.75
0.85
0.75
0.75
2.65
0.40
0.30
0.40
2.65
2
0.8
0.8
0.9
0.8
0.8
2.8
0.45
0.35
0.45
2.8
2
0.9
0.9
1.0
0.9
0.9
3.1
0.55
0.45
0.55
3.1
2
1.0
1.0
1.1
1.0
1.0
3.4
0.65
0.55
0.65
3.4
2
1.1
1.1
1.2
1.1
1.1
3.8
0.8
0.7
0.8
3.8
2
1.3
1.3
1.4
1.3
1.3
4.2
0.9
0.85
0.9
4.2
2
ns
ns
TAVKH
TADSVKH
TDVKH
TWVKH
TCVKH
TKHAX
TKHADSX
TKHDX
TKHWX
TKHCX
TZZR
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Address status
Data-in
ns
Global write
Chip enable
ns
ns
Hold time
Address
ns
Address status
Data-in
ns
ns
Global write
Chip enable
ns
ns
ZZ recovery time
clocks
10
Data Sheet M14018EJ3V0DS00
µPD432937
READ - READ - WRITE
K
/K
/AC
A3
Address
A1
A2
/GW
/CEs Note
D1(A3) D2(A3) D3(A3) D4(A3)
Data In
Q1(A1) Q2(A1)
Q4(A1)
Q3(A1)
Q1(A2) Q2(A2) Q3(A2) Q4(A2)
Data Out
KQ
/KQ
Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
READ - DESELECT (standby) - READ
K
/K
/AC
A3
Address
A2
A1
/GW
/CEs Note
Data In
Q1(A1) Q2(A1) Q3(A1) Q4(A1)
Q1(A3) Q2(A3) Q3(A3) Q4(A3)
Data Out
KQ
/KQ
Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Remark Qn(A1) refers to output from address A1. Q1-Q4 refer to outputs according to burst sequence.
11
Data Sheet M14018EJ3V0DS00
µPD432937
WRITE - WRITE - READ
K
/K
/AC
A3
Address
A1
A2
/GW
/CEs Note
D1(A1) D2(A1)
D4(A1)
D3(A1)
D1(A2) D2(A2) D3(A2) D4(A2)
Data In
Q1(A3) Q2(A3) Q3(A3) Q4(A3)
Data Out
KQ
/KQ
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
Qn(A3) refers to output from address A3. Q1-Q4 refer to outputs according to burst sequence.
Remark
DUAL BANK READ
K
/K
/AC
A3
Address
A2
A1
/GW
/CE
Data Out
Bank 1
Q1(A1) Q2(A1)
Q4(A1)
Q3(A1)
Q1(A3) Q2(A3) Q3(A3) Q4(A3)
Data Out
Bank 2
Q1(A2) Q2(A2) Q3(A2) Q4(A2)
/KQ
Bank 1
/KQ
Bank 2
CE2,
/CE2
Bank 1
Bank 2
Bank 1
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
12
Data Sheet M14018EJ3V0DS00
µPD432937
STOP CLOCK OPERATION (READ)
K
/K
/AC
Address
/GW
A2
A1
/CEs Note
Data In
Q1(A1) Q2(A1)
Q4(A1)
Q3(A1)
Q1(A2) Q2(A2) Q3(A2) Q4(A2)
Data Out
KQ
/KQ
Invalid
clocks
Power down state
(ISB1)
Wakeup
cycles
Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
STOP CLOCK OPERATION (WRITE)
K
/K
/AC
Address
/GW
A2
A1
/CEs Note
Data In
D1(A1) D2(A1) D3(A1) D4(A1)
D1(A2) D2(A2) D3(A2) D4(A2)
Data Out
KQ
/KQ
Invalid
clocks
Wakeup
cycles
Power down state
(ISB1)
Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
13
Data Sheet M14018EJ3V0DS00
µPD432937
STOP CLOCK OPERATION (DESELECT)
K
/K
/AC
A2
Address
/GW
/CEs Note
Data In
Q1(A1) Q2(A1)
Q4(A1)
Q3(A1)
Q1(A2) Q2(A2) Q3(A2) Q4(A2)
Data Out
KQ
/KQ
Invalid
clocks
Power down state
(ISB1)
Wakeup
cycles
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
Remark
POWER DOWN CYCLE (using ZZ)
K
/K
A1
A2
Address
/AC
/GW
/CE1
CE2
/CE2
KQ
/KQ
Q1(A1)
Q2(A1) Q3(A1) Q4(A1)
Data Out
TZZR
ZZ
Remark
Qn(A1) refers to output from address A1. Q1-Q4 refer to outputs according to burst sequence.
14
Data Sheet M14018EJ3V0DS00
µPD432937
POWER DOWN CYCLE (using STOP CLOCK Method)
K
A2
A1
Address
/AC
/GW
/CE1
CE2
/CE2
KQ
Q1(A1)
Q2(A1) Q3(A1) Q4(A1)
Data Out
Qn(A1) refers to output from address A1. Q1-Q4 refer to outputs according to burst sequence.
Remark
15
Data Sheet M14018EJ3V0DS00
µPD432937
READ CYCLE
TKHKL
TKHKH
V
IH
K
/K
V
IL
TKHKB
TKLKH
TADSVKH
TKHADSX
/AC
TKHAX
TAVKH
A1
A2
Address
/GW
TWVKH
TKHWX
TCVKH TKHCX
/CEs Note
Data In
Q1(A1)
Q2(A1) Q3(A1) Q4(A1)
Q1(A2)
TQVKE
Q2(A2) Q3(A2) Q4(A2)
TKEQX
Data Out
KQ
/KQ
TKHKE
Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
16
Data Sheet M14018EJ3V0DS00
µPD432937
WRITE CYCLE
TKHKL
TKHKH
V
IH
K
/K
V
IL
TKHKB
TKLKH
TADSVKH
TKHADSX
/AC
TKHAX
TAVKH
A1
A2
Address
/GW
TWVKH
TKHWX
TCVKH
TKHCX
/CEs Note
TDVKH
D1(A1)
TKHDX
D2(A1) D3(A1) D4(A1)
D1(A2)
D2(A2) D3(A2) D4(A2)
Data In
Data Out
KQ
/KQ
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
17
Data Sheet M14018EJ3V0DS00
µPD432937
TIMING DIAGRAM REFERENCE for CENTERED ECHO CLOCK
TKHKH
K
TKHKB
/K
Data[18:1]
D1
D2
D3
D1
D2
D3
D1
D2
D3
Latest data
/KQ
KQ
Earliest echo clock
Earliest data
Latest echo clock
RESET OPERATION
K
/AC
/RESET
8 cycles
4 cycles
First cycle from /RESET de-asserted
Power-On
/RESET de-asserts
Remark This device needs this RESET OPERATION after power-up.
18
Data Sheet M14018EJ3V0DS00
µPD432937
Testability
Testability in this device is achieved by the use of a cascaded AND tree structure. Test mode is selected by asserting
the Test Enable pin (/TE) low. When in Test Mode, the all of the pins of this device that make an actual connection
with the die, with the exception of /TE, Test Out (TO), VDD, VDDQ, VREF, VSS and all clock pins, act as inputs to a large,
cascaded AND tree structure to produce a single output on the Test Out (TO) pin. Input voltages during test mode are
operated off VDDQ. During test mode, VREF will operate as normal within the range specified in the DC Characteristic
section earlier in this document. A simplified illustration of this AND tree is shown below. By walking specific values
around the pins of this device, open connections between the circuit board and this device can be detected on the TO
pin. When /TE is deasserted, the device operates in a normal manner.
AND TREE STRUCTURE EXAMPLE
I/O
pad
I/O
pad
I/O
pad
Test out
/TE
I/O
pad
I/O
pad
I/O
pad
Truth Table for /TE and TO Pins
/TE
TO
Mode
0
1
AND of all listed inputs
Hi-Z
Test Mode
Normal Mode
19
Data Sheet M14018EJ3V0DS00
µPD432937
Test input assignments for µPD432937 (64 K words x 36 bits), 100 pin plastic LQFP
Signal
I/OP3
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
Pin
1
Signal
I/O31
A7
Pin
28
99
100
29
30
32
98
92
95
33
34
35
97
88
85
Signal
A10
A11
A12
A1
Pin
44
45
46
36
37
96
84
47
48
49
81
82
51
52
53
Signal
I/O3
Pin
56
57
58
59
62
63
68
69
72
73
74
75
78
79
80
2
I/O4
3
A6
I/O5
6
I/O32
I/OP4
A5
I/O6
7
A0
I/O7
8
RES
/RESET
A13
A14
A15
A9
I/O8
9
/CE
/CE2
ZZ
I/O9
12
13
18
19
22
23
24
25
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/OP2
A4
A3
A2
A8
CE2
/GW
/AC
I/OP1
I/O1
I/O2
20
Data Sheet M14018EJ3V0DS00
µPD432937
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0±0.2
20.0±0.2
14.0±0.2
16.0±0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0±0.2
0.5±0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125±0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
21
Data Sheet M14018EJ3V0DS00
µPD432937
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD432937.
Type of Surface Mount Devices
µPD432937GF : 100-PIN PLASTIC LQFP (14 x 20)
22
Data Sheet M14018EJ3V0DS00
µPD432937
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Data Sheet M14018EJ3V0DS00
µPD432937
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
相关型号：
©2020 ICPDF网 联系我们和版权申明