UPD4382181GF-A10 [ETC]
x18 Fast Synchronous SRAM ; X18高速同步SRAM\n型号: | UPD4382181GF-A10 |
厂家: | ETC |
描述: | x18 Fast Synchronous SRAM
|
文件: | 总24页 (文件大小:195K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
PD4382161, 4382181, 4382321, 4382361
µ
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The µPD4382161 is a 524,288-word by 16-bit, the µPD4382181 is a 524,288-word by 18-bit, the µPD4382321 is a
262,144-word by 32-bit and the µPD4382361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using N-channel four-transistor memory cell.
The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 are packaged in 100-pin plastic LQFP with a 1.4 mm
package thickness for high density and low capacitive loading.
Features
• Single 3.3 V power supply
• Synchronous operation
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs for flow through operation
• All registers triggered off positive clock edge
• LVTTL Compatible : All inputs and outputs
• Fast clock access time : 8.5 ns (100 MHz), 9 ns (90 MHz) (µPD4382321, µPD4382361)
9 ns (90 MHz), 10 ns (83 MHz) (µPD4382161, µPD4382181)
• Asynchronous output enable : /G
★
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable :
/BW1 - /BW4 (µPD4382321, µPD4382361), /BW1 - /BW2 (µPD4382161, µPD4382181), /BWE
Global write enable : /GW
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14019EJ5V0DS00 (5th edition)
Date Published June 2000 NS CP(K)
Printed in Japan
The mark shows major revised points.
★
1999
©
µPD4382161, 4382181, 4382321, 4382361
Ordering Information
Part number
Access
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O
Interface
V
Package
Notes
Time
ns
µPD4382161GF-A90
µPD4382161GF-A10
µPD4382181GF-A90
µPD4382181GF-A10
µPD4382321GF-A85
µPD4382321GF-A90
µPD4382361GF-A85
µPD4382361GF-A90
9.0
10.0
9.0
90
83
3.3 ± 0.165
3.3 LVTTL
100-pin Plastic LQFP (14 x 20)
1
★
★
90
10.0
8.5
83
100
90
2
9.0
8.5
100
90
9.0
and A10 are
the
Notes 1. Grade A90
available in
µPD4382161GF and µPD4382181GF
µPD4382321GF and µPD4382361GF
2. Grade A85 and A90 are available in the
Data Sheet M14019EJ5V0DS00
2
µPD4382161, 4382181, 4382321, 4382361
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin Plastic LQFP (14 x 20)
[µPD4382161GF, µPD4382181GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
2
NC
NC
3
NC
VDDQ
VSSQ
NC
4
VDDQ
VSSQ
NC
5
6
NC
7
I/OP1, NC
I/O8
I/O7
VSSQ
VDDQ
I/O6
I/O5
VSS
I/O9
8
I/O10
VSSQ
VDDQ
I/O11
I/O12
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
NC
VDD
VSS
ZZ
I/O13
I/O14
VDDQ
VSSQ
I/O15
I/O16
I/OP2, NC
NC
I/O4
I/O3
VDDQ
VSSQ
I/O2
I/O1
NC
NC
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for 1-pin index mark.
Data Sheet M14019EJ5V0DS00
3
µPD4382161, 4382181, 4382321, 4382361
Pin Identification (µPD4382161GF, µPD4382181GF)
Symbol
Pin No.
Description
Synchronous Address Input
A0 - A18
37, 36, 35, 34, 33, 32, 100, 99, 82,
81, 44, 45, 46, 47, 48, 49, 50, 43, 80
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9,
Synchronous Data In,
12, 13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
I/OP1, NCNote
74
I/OP2, NCNote
24
/ADV
83
/AP
84
/AC
85
/CE, CE2, /CE2
98, 97, 92
/BW1, /BW2, /BWE
93, 94, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,
38, 39, 42, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4382161GF.
I/OP1 - I/OP2 is used in the µPD4382181GF.
Data Sheet M14019EJ5V0DS00
4
µPD4382161, 4382181, 4382321, 4382361
100-pin Plastic LQFP (14 x 20)
[µPD4382321GF, µPD4382361GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP2, NC
I/O16
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
I/O15
I/O18
3
VDDQ
V
DD
Q
Q
4
V
SS
Q
V
SS
5
I/O14
I/O13
I/O12
I/O11
I/O19
I/O20
I/O21
I/O22
6
7
8
9
VSS
Q
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
V
DD
I/O10
I/O9
I/O23
I/O24
NC
V
SS
NC
VDD
VDD
NC
ZZ
V
SS
I/O25
I/O26
I/O8
I/O7
VDDQ
V
DD
Q
Q
V
SS
Q
V
SS
I/O6
I/O5
I/O4
I/O3
I/O27
I/O28
I/O29
I/O30
VSS
Q
V
SS
Q
Q
VDDQ
V
DD
I/O2
I/O31
I/O32
I/O1
I/OP1, NC
I/OP4, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for 1-pin index mark.
Data Sheet M14019EJ5V0DS00
5
µPD4382161, 4382181, 4382321, 4382361
Pin Identification (µPD4382321GF, µPD4382361GF)
Symbol Pin No.
A0 - A17
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 43
I/O1 - I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1, NC Note
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
/ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
83
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
/AP
84
/AC
85
/CE, CE2, /CE2
/BW1 - /BW4, /BWE
/GW
98, 97, 92
93, 94, 95, 96, 87
88
86
89
31
/G
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
14, 16, 38, 39, 42, 66
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4382321GF.
I/OP1 - I/OP4 is used in the µPD4382361GF.
Data Sheet M14019EJ5V0DS00
6
µPD4382161, 4382181, 4382321, 4382361
Block Diagrams
[µPD4382161, µPD4382181]
19
19
17
19
Address
register
A0 - A18
A0, A1
MODE
/ADV
CLK
Q1
Binary
A1’
A0’
counter
and logic
/AC
/AP
Row and column
decoders
CLR
Q0
8/9
8/9
Memory cell array
1,024 rows
Byte 1
Byte 1
/BW1
/BW2
Write register
Write driver
Byte 2
Write register
Byte 2
Write driver
512 × 16 columns
(8,388,608 bits)
512 × 18 columns
(9,437,184 bits)
/BWE
16/18
16/18
Input
register
Output
buffer
/GW
/CE
Enable
register
CE2
/CE2
/G
2
16/18
I/O1 - I/O16
I/OP1 - I/OP2
Power down control
ZZ
Burst Sequence
[µPD4382161, µPD4382181]
Interleaved Burst Sequence Table (MODE = Open or VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 - A2, A1, A0
A18 - A2, A1, /A0
A18 - A2, /A1, A0
A18 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 0
Data Sheet M14019EJ5V0DS00
7
µPD4382161, 4382181, 4382321, 4382361
[µPD4382321, µPD4382361]
18
18
16
18
Address
register
A0 - A17
A0, A1
MODE
/ADV
CLK
Q1
Binary
A1’
A0’
counter
and logic
/AC
/AP
Row and column
decoders
CLR
Q0
8/9
8/9
8/9
8/9
Byte 1
Byte 1
Memory cell array
1,024 rows
/BW1
/BW2
/BW3
Write register
Write driver
Byte 2
Write register
Byte 2
Write driver
256 × 32 columns
(8,388,608 bits)
256 × 36 columns
(9,437,184 bits)
Byte 3
Write register
Byte 3
Write driver
Byte 4
Write register
Byte 4
Write driver
/BW4
/BWE
32/36
32/36
Input
register
Output
buffer
/GW
/CE
Enable
register
CE2
/CE2
/G
4
32/36
I/O1 - I/O32
I/OP1 - I/OP4
Power down control
ZZ
Burst Sequence
[µPD4382321, µPD4382361]
Interleaved Burst Sequence Table (MODE = Open or VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 - A2, A1, A0
A17 - A2, A1, /A0
A17 - A2, /A1, A0
A17 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
Data Sheet M14019EJ5V0DS00
8
µPD4382161, 4382181, 4382321, 4382361
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
/G
L
I/O
Dout
H
×
Hi-Z
Hi-Z, Din
Hi-Z
×
Remark × : don’t care
Synchronous Truth Table
Operation
/CE
H
L
CE2
×
/CE2
×
/AP
×
/AC
L
/ADV
×
/WRITE
CLK
Address
None
Deselected Note
×
×
×
×
×
×
H
×
×
×
×
L
×
×
×
×
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
Deselected Note
L
×
L
×
×
None
Deselected Note
L
×
H
×
L
×
×
None
Deselected Note
L
L
H
H
L
L
×
None
Deselected Note
L
×
H
L
L
×
None
Read Cycle / Begin Burst
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Suspend Burst
Read Cycle / Suspend Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Suspend Burst
Write Cycle / Suspend Burst
L
H
H
×
×
×
External
External
Next
L
L
H
H
×
L
×
×
×
H
H
H
H
L
L
H
×
×
×
L
Next
×
×
H
×
H
H
×
Current
Current
External
Next
H
L
×
×
H
×
L
H
H
×
×
×
H
H
H
H
L
H
×
×
×
L
Next
×
×
H
×
H
H
Current
Current
H
×
×
Note Deselect status is held until new “Begin Burst” entry.
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW
or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW.
Data Sheet M14019EJ5V0DS00
9
µPD4382161, 4382181, 4382321, 4382361
Partial Truth Table for Write Enables
[µPD4382161, µPD4382181]
Operation
/GW
/BWE
/BW1
/BW2
Read Cycle
Read Cycle
H
H
H
H
L
H
L
L
L
×
×
H
L
L
×
×
H
H
L
Write Cycle / Byte 1 Only
Write Cycle / All Bytes
Write Cycle / All Bytes
×
Remark × : don’t care
[µPD4382321, µPD4382361]
Operation
/GW
H
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
L
L
L
×
×
H
L
L
×
×
H
H
L
×
H
H
L
×
H
H
L
Read Cycle
H
Write Cycle / Byte 1 Only
Write Cycle / All Bytes
Write Cycle / All Bytes
H
H
L
×
×
×
Remark × : don’t care
ZZ (Sleep) Truth Table
ZZ
Chip Status
Active
≤ 0.2 V
Open
Active
≥ VDD − 0.2 V
Sleep
Data Sheet M14019EJ5V0DS00
10
µPD4382161, 4382181, 4382321, 4382361
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
VDDQ
VIN
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
+4.0
Unit
V
Note
Supply voltage
Output supply voltage
Input voltage
VDD
V
VDD + 0.5
VDDQ + 0.5
70
V
1, 2
1, 2
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
V
TA
°C
°C
Tstg
–55
+125
Notes 1. –2.0 V (MIN.)(Pulse width : 2 ns)
DD
2. V Q + 2.3 V (MAX.)(Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
3.135
3.135
2.0
TYP.
3.3
MAX.
3.465
Unit
V
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
3.3
3.465
V
VDDQ + 0.3
+0.8
V
VIL
–0.3 Note
V
Note –0.8 V (MIN.)(Pulse width : 2 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
pF
CIN
CI/O
Cclk
VIN = 0 V
4
7
4
Input / Output capacitance
Clock input capacitance
VI/O = 0 V
Vclk = 0 V
pF
pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M14019EJ5V0DS00
11
µPD4382161, 4382181, 4382321, 4382361
DC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.165 V)
Parameter
Input leakage current
I/O leakage current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit Note
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled.
µA
µA
ILO
–2
+2
Operating supply current
IDD
Device selected,
Cycle = MAX.
µPD4382161-A90
250
mA
µPD4382181-A90
µPD4382161-A10
µPD4382181-A10
µPD4382321-A85
µPD4382361-A85
µPD4382321-A90
µPD4382361-A90
VIN ≤ VIL or VIN ≥ VIH,
II/O = 0 mA
240
350
330
120
★
★
IDD1
Suspend cycle, Cycle = MAX.
/AC, /AP, /ADV, /GW, /BWEs ≥ VIH
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
Device deselected, Cycle = 0 MHz
VIN ≤ VIL or VIN ≥ VIH, All inputs are static.
Device deselected, Cycle = 0 MHz
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V
VI/O ≤ 0.2 V, All inputs are static.
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
Standby supply current
ISB
30
10
mA
ISB1
ISB2
150
10
Power down supply current
High level output voltage
Low level output voltage
ISBZZ
VOH
VOL
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
IOH = –4.0 mA
mA
V
2.4
IOL = +8.0 mA
0.4
V
Data Sheet M14019EJ5V0DS00
12
µPD4382161, 4382181, 4382321, 4382361
AC Characteristics (TA = 0 to 70 °C, VDD = 3.3 V ± 0.165 V)
AC Test Conditions
Input waveform (Rise / Fall time ≤ 3.0 ns)
3.0 V
1.5 V
Test points
Test points
1.5 V
1.5 V
V
SS
Output waveform
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
VT = +1.5 V
50 Ω
ZO = 50 Ω
I/O (Output)
CL
Remark CL includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M14019EJ5V0DS00
13
µPD4382161, 4382181, 4382321, 4382361
Read and Write Cycle
★
Parameter
Symbol
-A85
-A90
-A10
Unit
Note
(100 MHz)
(90 MHz)
(83 MHz)
Standard
Alias
TCYC
TCD
TOE
TDC1
TDC2
TOLZ
TOHZ
TCZ
TCH
TCL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
–
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
10
–
–
8.5
3.5
–
11
–
–
9
12
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
10
4.8
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output high-Z
Clock high to output high-Z
Clock high pulse width
Clock low pulse width
Setup times Address
Address status
–
–
3.5
–
–
2
2
2
3
–
3
–
3
–
0
–
0
–
0
–
0
3.5
4
0
3.5
4
0
3.5
4
2
2
2
2.5
2.5
2
–
2.5
2.5
2
–
2.5
2.5
2.5
–
TKLKH
–
–
–
TAVKH
TADSVKH
TDVKH
TWVKH
TAS
TSS
TDS
TWS
–
–
–
–
Data in
Write enable
Address advance TADVVKH
Chip enable
Hold times Address
TEVKH
TKHAX
–
TAH
TSH
TDH
TWH
–
0.5
–
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX
TKHDX
Write enable
TKHWX
Address advance TKHADVX
Chip enable
Power down entry setup
Power down entry hold
TKHEX
TZZES
TZZEH
TZZRS
TZZRH
–
TZZES
TZZEH
TZZRS
TZZRH
5
1
6
0
–
–
–
–
5
1
6
0
–
–
–
–
5
1
6
0
–
–
–
–
ns
ns
ns
ns
1
1
1
1
Power down recovery setup
Power down recovery hold
Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be
recognized.
Data Sheet M14019EJ5V0DS00
14
READ CYCLE
TKHKH
CLK
/AP
/AC
TKHKL
TKLKH
TADSVKH
TKHADSX
TADSVKH
TKHADSX
TAVKH
TKHAX
A1
A2
TADVVKH
Address
/ADV
A3
TKHADVX
µ
TWVKH
TKHWX
TKHWX
/BWE
/BWs
TWVKH
/GW
TEVKH
TKHEX
/CEsNote
/G
TGLQV
TGHQZ
Data In
TKHQV
Q2(A2)
TKHQZ
Q1(A3)
TGLQX
Hi-Z
TKHQX2
Q1(A1)
Q1(A2)
Q3(A2)
Q4(A2)
Q1(A2)
Data Out
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
Remark
WRITE CYCLE
TKHKH
CLK
/AP
TADSVKH TKHADSX
TKHKL
TKLKH
TADSVKH TKHADSX
/AC
Address
/ADV
TAVKH
TKHAX
A1
A2
A3
TADVVKH
TKHADVX
µ
TWVKH
TKHWX
/BWENote1
/BWs
TWVKH
TEVKH
TKHWX
TKHEX
/GWNote1
/CEsNote2
/G
TDVKH
TKHDX
Data In
D1(A1)
D2(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
TGHQZ
Hi-Z
Data Out
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
TADSVKH
/AP
/AC
TKHADSX
TAVKH
TKHAX
A1
A2
A3
TADVVKH
Address
/ADV
TKHADVX
µ
TWVKH
TWVKH
TKHWX
/BWENote1
/BWs
TKHWX
/GWNote1
TEVKH
TKHEX
/CEsNote2
/G
TDVKH
TKHDX
D1(A2)
Data In
TGHQZ
TKHQV
TKHQX1
TGLQX
Q1(A3) Q2(A3)
Hi-Z
Q1(A1)
Data Out
Q3(A3)
Q4(A3)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
POWER DOWN (ZZ) CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
µ
/ADV
/BWE
/BWs
/GW
/CEs
/G
Hi-Z
Q1(A1)
Q1(A2)
Q2(A2)
Data Out
TZZEH TZZES
TZZRH TZZRS
ZZ
Power Down (ISBZZ) State
STOP CLOCK CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
/ADV
µ
/BWE
/BWs
/GW
/CEs
/G
Data In
Hi-Z
Q1(A1)
Q1(A2)
Data Out
Note
Power Down State (ISB1
)
Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V
µPD4382161, 4382181, 4382321, 4382361
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0±0.2
20.0±0.2
14.0±0.2
16.0±0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0±0.2
0.5±0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125±0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
Data Sheet M14019EJ5V0DS00
20
µPD4382161, 4382181, 4382321, 4382361
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4382161, 4382181, 4382321 and 4382361.
Types of Surface Mount Devices
µPD4382161GF : 100-pin Plastic LQFP (14 x 20)
µPD4382181GF : 100-pin Plastic LQFP (14 x 20)
µPD4382321GF : 100-pin Plastic LQFP (14 x 20)
µPD4382361GF : 100-pin Plastic LQFP (14 x 20)
Data Sheet M14019EJ5V0DS00
21
µPD4382161, 4382181, 4382321, 4382361
[MEMO]
Data Sheet M14019EJ5V0DS00
22
µPD4382161, 4382181, 4382321, 4382361
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14019EJ5V0DS00
23
µPD4382161, 4382181, 4382321, 4382361
•
The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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